Adaptive Resolution Management Prediction Rescaling

Abstract

The method includes receiving a reference frame, determining a scaling constant for a current block, determining a scaled reference block using the reference frame and the scaling constant, determining a scaled predictive block using the scaled reference block, and reconstructing pixel data for the current block using the rescaled predictive block. Related apparatus, systems, techniques, and articles are also described.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of priority of U.S. Provisional Patent Application No. 62 / 883,454, filed on Aug. 6, 2019, entitled "ADAPTIVE RESOLUTION MANAGEMENT PREDICTION RESCALING", which is incorporated herein by reference in its entirety.

[0002] The present invention generally relates to the field of video compression. In particular, the present invention is directed to adaptive resolution management prediction rescaling.

Background Art

[0003] A video codec may include an electronic circuit or software that compresses or decompresses digital video. This may convert uncompressed video to a compressed format and vice versa. In the context of video compression, a device that compresses video and / or performs certain functions thereof may typically be called an encoder, and a device that decompresses video and / or performs certain functions thereof may be called a decoder.

[0004] The format of the compressed data may conform to standard video compression specifications. Compression may be lossy in that the compressed video may lack certain information present in the original video. This may include the result that the decompressed video may have lower quality than the original uncompressed video because there may be insufficient information to accurately reconstruct the original video.

[0005] There may be a complex relationship between video quality and the amount of data used to represent the video, such as determined by, for example, the bitrate, the complexity of the encoding and decoding algorithms, the sensitivity to data loss and errors, the ease of editing, random access, and end - to - end delays such as, but not limited to, latency, and the like.

[0006] Motion compensation may include an approach for predicting a video frame or a portion thereof, based on a reference frame such as a previous and / or future frame, by taking into account the motion of a camera and / or an object in the video. This may be employed in the encoding and decoding of video data for video compression, for example, in the encoding and decoding using the Advanced Video Coding (AVC) standard of the Moving Picture Experts Group (MPEG) (also referred to as H.264). Motion compensation may describe a picture from the perspective of the transformation of a reference picture to the current picture. The reference picture may be the one immediately preceding in time and / or the one from the future when compared to the current picture. Summary of the Invention Means for Solving the Problems

[0007] In one aspect, a decoder is configured to include a network of circuits that receives a reference frame, determines a scaling constant for a current block, determines a scaled reference block using the reference frame and the scaling constant, determines a scaled prediction block using the scaled reference block, and reconstructs pixel data of the current block using the re-scaled prediction block.

[0008] In another aspect, a method includes receiving a reference frame, determining a scaling constant for a current block, determining a scaled reference block using the reference frame and the scaling constant, determining a scaled prediction block using the scaled reference block, and reconstructing pixel data of the current block using the re-scaled prediction block.

[0009] Details of one or more variations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described in this specification will be apparent from the description, the drawings, and the claims. The present invention provides, for example, the following. (Item 1) A decoder, wherein the decoder is a circuit network, receives a reference frame, determines a scaling constant for a current block, uses the reference frame and the scaling constant to determine a scaled reference block, uses the scaled reference block to determine a scaled prediction block, uses the re-scaled prediction block to reconstruct pixel data of the current block is a circuit network configured to perform and includes a decoder. (Item 2) The decoder according to Item 1, further configured to determine the scaled prediction block by determining scaled motion information. (Item 3) The decoder according to Item 2, wherein the scaled motion information is determined by multiplying at least a horizontal component of a motion vector by the scaling constant and multiplying a vertical component of the motion vector by the scaling constant. (Item 4) The decoder according to Item 1, further configured to determine the scaled reference block by determining a position of the scaled reference block. (Item 5) The decoder according to Item 4, wherein the position is determined by multiplying a horizontal component of a position of a reference block by a scaling ratio and multiplying a vertical component of the position of the reference block by the scaling ratio. (Item 6) receives a bitstream, determines the scaling constant from the bitstream, wherein the scaling constant is signaled within the bitstream, and is the decoder according to Item 1, further configured to perform. (Item 7) The decoder according to Item 6, wherein the bitstream includes an index for a predetermined scaling constant. (Item 8) The decoder according to Item 1, further configured to receive the reference frame by accessing the reference frame from a memory. (Item 9) An entropy decoder processor, wherein the entropy decoder processor is configured to receive a bitstream and decode the bitstream into quantized coefficients, and an entropy decoder processor An inverse quantization and inverse transform processor, wherein the inverse quantization and inverse transform processor is configured to process the quantized coefficients including performing an inverse discrete cosine, an inverse quantization and inverse transform processor; A deblocking filter; A frame buffer; An intra prediction processor The decoder according to item 1, further comprising. (Item 10) The decoder according to item 1, wherein the current block is a coding tree unit. (Item 11) The decoder according to item 1, wherein the current block is a coding unit. (Item 12) The decoder according to item 1, wherein the current block is a prediction unit. (Item 13) A method, Receiving a reference frame; Determining a scaling constant for a current block; Using the reference frame and the scaling constant to determine a scaled reference block; Using the scaled reference block to determine a scaled prediction block; Reconstructing pixel data of the current block using the rescaled prediction block A method including. (Item 14) The method according to item 13, wherein determining the scaled prediction block includes determining scaled motion information. (Item 15) The method according to item 14, wherein the scaled motion information is determined by multiplying a horizontal component of a motion vector by the scaling constant and multiplying a vertical component of the motion vector by the scaling constant. (Item 16) The method according to item 13, wherein determining the scaled reference block includes determining a position of the scaled reference block. (Item 17) The method according to item 16, wherein the position is determined by multiplying a horizontal component of a position of a reference block by a scaling ratio and multiplying a vertical component of the position of the reference block by the scaling ratio. (Item 18) Receiving a bitstream; Determining the scaling constant from the bitstream, wherein the scaling constant is signaled within the bitstream; The method according to item 13, further comprising. (Item 19) The method according to item 18, wherein the bitstream includes an index for a predetermined scaling constant. (Item 20) The method according to item 13, wherein receiving the reference frame includes accessing the reference frame from a memory. (Item 21) At least one of the receiving, the determining, and the reconstructing is performed by a decoder, and the decoder is an entropy decoder processor configured to receive a bitstream and decode the bitstream into quantized coefficients, an entropy decoder processor; is an inverse quantization and inverse transform processor configured to process the quantized coefficients including performing an inverse discrete cosine transform, an inverse quantization and inverse transform processor; a deblocking filter; a frame buffer; and an intra prediction processor The method according to item 13, comprising. (Item 22) The method according to item 13, wherein the current block is a coding tree unit. (Item 23) The method according to item 13, wherein the current block is a coding unit. (Item 24) The method according to item 13, wherein the current block is a prediction unit.

Brief Description of the Drawings

[0010] For the purpose of illustrating the present invention, the drawings show aspects of one or more embodiments of the present invention. However, it should be understood that the present invention is not limited to the precise arrangements and means shown in the drawings.

[0011]

Figure 1

[0012]

Figure 2

[0013]

Figure 3

[0014]

Figure 4

[0015]

Figure 5

[0016]

Figure 6

[0017]

Figure 7

[0018]

Figure 8

[0019]

Figure 9

[0020] The drawings are not necessarily to scale and may be illustrated by imaginary lines, diagrammatic representations, and fragmentary views. In some instances, details that are not necessary for an understanding of the embodiments or that render other details difficult to perceive may be omitted. Like reference numerals in the various drawings indicate like elements. DETAILED DESCRIPTION

[0021] Detailed Description In many current state-of-the-art encoders, resolution is managed by recoding and retransmitting the entire portion of the video known as a group of pictures (GOP). This requires transmitting an intra-frame (I-frame) since those frames account for most of the bits within the GOP, which can incur additional cost.

[0022] The embodiments described in this disclosure relate to Adaptive Resolution Management (ARM), a technique that enables additional flexibility for video encoders / decoders, allowing for bitrate savings in various use cases. Generally, ARM involves performing predictions using a reference frame with a different resolution than the current frame. In current coding standards, the reference frame has the same resolution as the predicted frame. In ARM, the reference frame can be of lower or higher resolution than the frame being predicted. This approach can be used to downscale the video resolution and thus reduce the bitrate, or to upscale the video resolution and thus enhance the display characteristics of video playback.

[0023] Alternatively, or equivalently for the purposes of this disclosure, ARM may be referred to as Reference Picture Resampling (RPR), and RPR and ARM may be used synonymously.

[0024] Some implementations of this subject matter may involve using ARM for any number of frames at any position within a GOP, and thus may include removing the requirements related to re-coding of I-frames.

[0025] FIG. 1 is a diagram of reference frames and prediction frames at various resolution scales. Frame 1 is smaller than (has a lower resolution than) the reference frame, Frame 2 is the same size (the same resolution), while Frame 3 is larger (has a higher resolution). "Resolution" as used in the present disclosure is the number of pixels within a picture, frame, sub-frame, and / or other displayed area or portion thereof used in video playback, compression, or the like, with a higher number of pixels corresponding to a higher resolution and a lower number of pixels corresponding to a lower resolution. Resolution may be measured from an area perspective, for example, but not limited to, using one or more dimensions of length measured in pixel units that define an area. For example, a circular sub-frame or other region may have a resolution defined according to a radius. Alternatively, or in addition, resolution may be defined by the total number of pixels.

[0026] As an example, continuing to refer to FIG. 1, when the reference frame and / or sub-frame has a geometric form whose area over it can be completely defined from the perspective of two length parameters in the form of, but not limited to, a triangle, a parallelogram, and / or a rectangle, etc., the reference frame and / or sub-frame may have a resolution W×H (where W and H may respectively indicate the number of pixels describing the width (or base) dimension and the height dimension of the reference frame and / or sub-frame). Each prediction frame may also have a resolution that can be determined similarly to the resolution of the reference frame. For example, frame 1 may have a lower resolution WS×HS, frame 2 may have the same resolution as the reference frame W×H, and frame 3 may have a higher resolution WL×HL. The widths and heights of the smaller and larger frames can be obtained by multiplying the reference width and height by an arbitrary rescaling constant (Rc), also referred to as a scaling rate and / or a constant. In the case of a smaller frame, Rc may have a value between 0 and 1. In the case of a larger frame, Rc may have a value greater than 1. For example, Rc may have a value between 1 and 4. Other values are also conceivable. The rescaling constant may be different for one resolution dimension than for another. For example, a rescaling constant Rch may be used to rescale the height, while another rescaling constant Rcw may be used to rescale the width.

[0027] Still referring to FIG. 1, the ARM may be implemented as a mode. In the case of activating the ARM mode at a certain point during decoding, the decoder may already have received the reference frame at the resolution W×H, and may scale the predicted frame using the scaling constant. In some implementations, the encoder may signal the decoder with the scaling constant to be used. The signaling may be performed within the sequence parameter set (SPS) corresponding to the GOP containing the current picture, and / or the picture parameter set (PPS) corresponding to the current picture. For example, but not limited to, the encoder may use fields such as pps_pic_width_in_luma_samples, pps_pic_height_in_luma_samples, pps_scaling_win_left_offset, pps_scaling_win_right_offset, pps_scaling_win_top_offset, pps_scaling_win_bottom_offset, and / or sps_num_subpics_minus1 to signal the scaled parameters.

[0028] Still referring to FIG. 1, the W parameter and the H parameter as described above may be represented, for example but not limited to, using the variables CurrPicScalWinWidthL and CurrPicScalWinHeightL, respectively, and these variables may be derived from the signaled parameters as described above using one or more mathematical relationships between the signaled parameters and the variables. For example, but not limited to, CurrPicScalWinWidthL may be derived according to the following equation. CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset) As a further non-limiting example, CurrPicScalWinHeightL can be derived according to the following equation. CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset)

[0029] One of ordinary skill in the art will recognize various alternative calculations that can be used to derive the variables described above in light of the overall review of the present disclosure. The encoder may alternatively or additionally signal directly, for example, but not limited to, one or more such variables Rc, Rch, and / or Rcw within the PPS and / or SPS.

[0030] Alternatively or additionally, still referring to FIG. 1, the rescaling constant and / or set of rescaling constants as described above may be signaled in the bitstream using references to stored scaling constants and / or a plurality of scaling constants, and / or the index of the frame and / or block signaled and / or utilized immediately prior, where the reference to the index of the stored scaling constant may be explicitly signaled and / or determined from one or more additional parameters signaled within the bitstream. For example, but not limited to, the decoder may identify the group of pictures containing the reference frame and / or the current frame, and if the rescaling constant is signaled and / or used immediately prior within such a group of pictures with respect to the reference frame such that it is applicable to the current frame and / or the current group of pictures, or the equivalent, the decoder may identify such rescaling constant for use as the rescaling constant with respect to the current frame.

[0031] In some implementations, referring continuously to FIG. 1, the ARM operations may be executed according to the block level of the encoded frame. For example, the reference frame may first be rescaled, and subsequently, the prediction may be performed as depicted in FIG. 2. FIG. 2 is a diagram depicting a reference frame, a rescaled reference frame, and a subsequent block prediction process. The block prediction process may be performed on the rescaled reference frame (having a scaled resolution) rather than the original reference frame. Rescaling the reference frame may include rescaling according to any parameter signaled by the encoder as described above. For example, but not limited to, if the reference frame to be used with the current picture is signaled via a reference to an index value associated with the reference frame or equivalent, the signaled reference frame may be rescaled according to any of the rescaling methods described above prior to prediction. The rescaled reference frame may be stored in memory and / or a buffer that may include, but is not limited to, a buffer that identifies the frames contained therein by an index according to the frame readout that may be performed. The buffer may include a decoded picture buffer (DCB) as well as / or one or more additional buffers implemented by the decoder. The prediction process may include, for example, inter-picture prediction, including motion compensation.

[0032] Some implementations of block-based ARM may allow the flexibility of applying an optimal filter for each block instead of applying the same filter across the entire frame. In some implementations, skip ARM mode may be considered possible so that some blocks (e.g., based on the uniformity of pixels and bitrate cost) may be in skip ARM mode such that resizing will not change the bitrate. The skip ARM mode may be signaled within the bitstream. For example, but not limited to, the skip ARM mode may be signaled within the PPS parameter. Alternatively, or in addition, the decoder may determine that the skip ARM mode is active based on one or more parameters set by the decoder and / or signaled within the bitstream. The spatial filters used within block-based ARM may include, but are not limited to, a bicubic spatial filter that applies bicubic interpolation, a bilinear spatial filter that applies bilinear interpolation, a Lanczos filter that uses Lanczos filtering, and / or a sinc filter, sinc function interpolation, and / or Lanczos resampling that uses a combination of signal reconstruction techniques, or equivalents, and those skilled in the art will recognize various filters that may be consistently used in the present disclosure for interpolation in light of the overall review of the present disclosure.

[0033] Continuing to refer to FIG. 2, if a sequence of frames has already been encoded, post-encoding ARM may allow for rapid resizing and transmission of the predicted coding unit (block or frame). This may eliminate the need to re-encode video frames at different resolutions. Some implementations of the present subject matter may reduce computational complexity at a relatively minor cost in rate-distortion performance.

[0034] Referring further to FIG. 2, depending on the use case, resizing may be performed on the encoder side (to downscale the reduced bandwidth) or on the decoder side (to upscale the bandwidth required for video transmission and then downscale again) in the encoding and decoding processes that the encoder transmits to the decoder. In some implementations, resizing may be performed using an interpolation filter such as a sub-pixel prediction filter. The interpolation filter may, by way of non-limiting example and without limitation, use an upsampling process in which pixels between the pixels of the block and / or frame immediately preceding the resizing are initialized to zero and then the output of a low-pass filter is taken in, and may include any of the filters described above such as a low-pass filter. Alternatively, or in addition, any luminance sample interpolation filtering process may be used. Luminance sample interpolation may include calculating an interpolation value at a half-sample interpolation filter index corresponding between two consecutive sample values of the unscaled sample array. The calculation of the interpolation value may, without limitation, be performed by reading coefficients and / or weights from a look-up table, and the selection of the look-up table may be performed as a function of the coding unit and / or the motion model of the scaling ratio, such as determined using a scaling constant as described above. The calculation may, without limitation, include performing a weighted sum of adjacent pixel values when the weights are read from a look-up table. The calculated value may alternatively or in addition be offset, for example, without limitation, the value may be offset by only the minimum value (4, i.e., bit depth - 8), 6, the maximum value (2, i.e., 14 - bit depth), or the equivalent. Those skilled in the art will recognize various alternative or additional implementations that may be used for the interpolation filter in light of the overall review of the present disclosure.

[0035] In such an approach, still referring to FIG. 2, the predicted elements may be re-scaled by a rate Rc (scaling constant or rate), which may be signaled to the decoder, for example, as described above. For example, but not limited to, pps_scaling_window_explicit_signalling_flag equal to 1 may indicate that the scaling window offset parameter is present within the PPS, while pps_scaling_window_explicit_signalling_flag equal to 0 may indicate that the scaling window offset parameter is not present within the PPS. When sps_ref_pic_resampling_enabled_flag is equal to 0, pps_scaling_window_explicit_signalling_flag may be equal to 0.

[0036] The scaled elements may include intra-coding units and inter-coding units (e.g., blocks) that may be re-scaled using the scaling rate depicted in FIG. 3 and the like. FIG. 3 is a diagram depicting the reference block positions before and after the scaling process.

[0037] The scaled elements may include motion vectors. FIG. 4 is a diagram depicting motion vector scaling including a reference block, a predicted block, a scaled reference block, and a scaled predicted block. FIG. 4 illustrates motion-compensated prediction with respect to the reference frame of the original size (top) and the scaled reference frame (bottom).

[0038] FIG. 5 is a process flow diagram illustrating an exemplary embodiment of a process 500 for adaptive resolution management that may enable additional flexibility for a video encoder / decoder, allowing for bitrate savings in various use cases.

[0039] In step 505, still referring to FIG. 5, a reference frame is received. The reference frame may be received (and for example, accessed thereafter) by a memory. The reference frame may have been just decoded from a bitstream. The bitstream may be received by a decoder. The bitstream may include the current block. The current block may be contained within the bitstream received by the decoder. The bitstream may include data found within a stream of bits, which is for example an input to a decoder when using data compression. The bitstream may include information necessary to decode video. Receiving may include extracting and / or parsing blocks and associated signaling information from the bitstream. In some implementations, the current block may include a coding tree unit (CTU), a coding unit (CU), and / or a prediction unit (PU).

[0040] In step 510, still referring to FIG. 5, a scaling constant is determined for the current block. In some implementations, the scaling constant may be determined from the bitstream. For example, the scaling constant may be signaled within the bitstream. The bitstream may include an index for one of several predetermined scaling constants or the like.

[0041] In step 515, still referring to FIG. 5, a scaled reference block may be determined using the reference frame and the scaling constant. Determining the scaled reference block may include determining the position of the scaled reference block. In some implementations, the position may be determined by multiplying at least one dimension of the reference block or more than one dimension thereof by a scaling rate or more than one scaling rate. For example, the horizontal component of the position of the reference block may be multiplied by the scaling rate, and the vertical component of the position of the reference block may be multiplied by the scaling rate.

[0042] In step 520, continuing to refer to FIG. 5, the scaled prediction block may be determined using the scaled reference block. In some implementations, determining the scaled prediction block may include determining scaled motion information. The scaled motion information may be determined by multiplying at least the horizontal component of the motion vector by a scaling constant and multiplying the vertical component of the motion vector by the scaling constant.

[0043] In step 525, still referring to FIG. 5, the pixel data of the current block may be reconstructed using the rescaled prediction block.

[0044] FIG. 6 is a system block diagram illustrating an exemplary decoder 600 capable of adaptive resolution management prediction rescaling as described in the present disclosure. The decoder 600 may include an entropy decoder processor 604, an inverse quantization and inverse transform processor 608, a deblocking filter 612, a frame buffer 616, a motion compensation processor 620, and / or an intra prediction processor 624.

[0045] In operation, still referring to FIG. 6, a bitstream 628 may be received by the decoder 600 and input to the entropy decoder processor 604, which may entropy decode a portion of the bitstream into quantized coefficients. The quantized coefficients may be provided to the inverse quantization and inverse transform processor 608, which may perform inverse quantization and inverse transform to generate a residual signal, which may be added to the output of the motion compensation processor 620 or the intra prediction processor 624 according to the processing mode. The outputs of the motion compensation processor 620 and the intra prediction processor 624 may include a block prediction based on the previously decoded block. The sum of the prediction and the residual may be processed by the deblocking filter 612 and stored in the frame buffer 616.

[0046] Figure 7 is a process flow diagram illustrating an exemplary embodiment of a process 700 for encoding video using adaptive resolution management that can enable additional flexibility for a video encoder and / or decoder that allows for bitrate savings in various use cases. At step 705, a video frame may undergo an initial block segmentation using a tree-structured macroblock partitioning scheme that may include, for example, partitioning a picture frame into coding tree units (CTUs) and coding units (CUs).

[0047] At step 710, still referring to FIG. 7, block-based adaptive resolution management may be performed, including resolution scaling of a frame or a portion thereof.

[0048] At step 715, still referring to FIG. 7, the blocks may be encoded and included in a bitstream. Encoding may include, for example, utilizing inter prediction modes and intra prediction modes.

[0049] Figure 8 is a system block diagram illustrating an exemplary video encoder 800 capable of adaptive resolution management prediction rescaling as described in the present disclosure. The exemplary video encoder 800 may receive an input video 804, which may first be segmented or split according to a processing scheme such as a tree-structured macroblock partitioning scheme (e.g., quadtree + binary tree). An example of a tree-structured macroblock partitioning scheme may include partitioning a picture frame into large block elements called coding tree units (CTUs). In some implementations, each CTU may be further partitioned one or more times into several sub-blocks called coding units (CUs). The final result of this partitioning may include a group of sub-blocks that may be referred to as prediction units (PUs). Transformation units (TUs) may also be utilized.

[0050] Still referring to FIG. 8, the exemplary video encoder 800 may include an intra prediction processor 808, a motion estimation / compensation processor 812, also referred to as an inter prediction processor, which can construct a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list, a transform / quantization processor 816, an inverse quantization / inverse transform processor 820, a loop filter 824, a decoded picture buffer 828, and / or an entropy coding processor 832. Bitstream parameters may be input to the entropy coding processor 832 for inclusion in the output bitstream 836.

[0051] During operation, still referring to FIG. 8, for each block of a frame of the input video 804, it may be determined whether to process the block via intra picture prediction or using motion estimation / compensation. The block may be provided to the intra prediction processor 808 or the motion estimation / compensation processor 812. If the block is to be processed via intra prediction, the intra prediction processor 808 may perform the processing and output a predictor. If the block is to be processed via motion estimation / compensation, the motion estimation / compensation processor 812 may perform the processing, including constructing a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list if applicable.

[0052] Referring further to FIG. 8, the residual may be formed by subtracting the predictor from the input video. The residual may be received by the transform / quantization processor 816, which may perform a transform process (e.g., discrete cosine transform (DCT)) and produce coefficients that may be quantized. The quantized coefficients and any associated signaling information may be provided to the entropy coding processor 832 for entropy coding and inclusion within the output bitstream 836. The entropy coding processor 832 may assist in encoding the signaling information associated with encoding the current block. Additionally, the quantized coefficients may be provided to the inverse quantization / inverse transform processor 820, which may reproduce pixels that may be processed by the in-loop filter 824 in combination with the predictor, and the output thereof may be stored in the decoded picture buffer 828 for use by the motion estimation / compensation processor 812, which may be capable of constructing a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list.

[0053] Continuing to refer to FIG. 8, several variations have been described in detail above, but other modifications or additions are also conceivable as possibilities. For example, in some implementations, the current block may include any symmetric block (8×8, 16×16, 32×32, 64×64, 128×128, and equivalents) as well as any asymmetric block (8×4, 16×8, and equivalents).

[0054] In some implementations, still referring to Figure 8, a quadtree + binary decision tree (QTBT) may be implemented. In the QTBT, at the coding tree unit level, the partition parameter of the QTBT may be dynamically derived to conform to local characteristics without transmitting any overhead. Subsequently, at the coding unit level, the joint classifier decision tree structure may eliminate unnecessary repetitions and control the risk of incorrect predictions. In some implementations, an LTR frame block update mode may be available as an additional option for each leaf node of the QTBT.

[0055] In some implementations, still referring to Figure 8, additional syntax elements may be signaled at different hierarchical levels of the bitstream. For example, a flag may be enabled for the entire sequence by including a flag coded within a sequence parameter set (SPS). Further, a CTU flag may be coded at the coding tree unit (CTU) level.

[0056] Some embodiments may include a non-transitory computer program product (i.e., a physically embodied computer program product) that stores instructions for causing at least one data processor to perform the operations herein when executed by one or more data processors of one or more computing systems.

[0057] Embodiments disclosed herein may include a decoder having a network of circuits configured to receive a reference frame, determine a scaling constant for a current block, use the reference frame and the scaling constant to determine a scaled reference block, use the scaled reference block to determine a scaled prediction block, and use the rescaled prediction block to reconstruct pixel data for the current block.

[0058] In some embodiments, the decoder may further be configured to determine a scaled prediction block by determining scaled motion information. The scaled motion information may be determined by multiplying at least the horizontal component of the motion vector by a scaling constant and multiplying the vertical component of the motion vector by the scaling constant. The decoder may further be configured to determine a scaled reference block by determining the position of the scaled reference block. The position may be determined by multiplying the horizontal component of the position of the reference block by a scaling factor and multiplying the vertical component of the position of the reference block by the scaling factor. The decoder may further be configured to receive a bitstream and determine, from the bitstream, a scaling constant that is signaled within the bitstream. The bitstream may include an index for a predetermined scaling constant. The decoder may further be configured to receive a reference frame by accessing the reference frame from memory. The decoder may include an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients including performing an inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor. The current block may include a coding tree unit. The current block may include a coding unit. The current block may include a prediction unit.

[0059] Embodiments disclosed in this specification may include a method. The method may include receiving a reference frame, determining a scaling constant for a current block, using the reference frame and the scaling constant to determine a scaled reference block, using the scaled reference block to determine a scaled prediction block, and using the rescaled prediction block to reconstruct pixel data of the current block.

[0060] In some embodiments, determining a scaled prediction block may include determining scaled motion information. The scaled motion information may be determined by multiplying a horizontal component of a motion vector by a scaling constant and multiplying a vertical component of the motion vector by the scaling constant. Determining a scaled reference block may include determining a position of the scaled reference block. The position may be determined by multiplying a horizontal component of the position of the reference block by a scaling ratio and multiplying a vertical component of the position of the reference block by the scaling ratio. The method may include receiving a bitstream and determining from the bitstream a scaling constant, where the scaling constant is signaled within the bitstream. The bitstream may include an index for a predetermined scaling constant. Receiving a reference frame may include accessing the reference frame from memory. At least one of receiving, determining, and reconstructing may be performed by a decoder including an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients including performing an inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor. The current block may include a coding tree unit. The current block may include a coding unit. The current block may include a prediction unit.

[0061] One or more of the aspects and embodiments described herein, as would be apparent to one of ordinary skill in the computer technology art, may be implemented and / or realized within one or more machines (e.g., one or more computing devices utilized as a user computing device for electronic documents, one or more server devices such as a document server, etc.) programmed in accordance with the teachings herein, using digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof. It should be noted that these various aspects or features may be implemented in one or more computer programs and / or software that are executable and / or interpretable on a programmable system including at least one programmable processor coupled to receive and transmit data and instructions from and to a storage system, at least one input device, and at least one output device, which may be of special purpose or general purpose. Appropriate software coding can be readily prepared by a skilled programmer based on the teachings of the present disclosure, as would be apparent to one of ordinary skill in the software art. The aspects and implementations discussed above that employ software and / or software modules may also include appropriate hardware to assist in the implementation of machine-executable instructions of the software and / or software modules.

[0062] Such software may be a computer program product that employs a machine-readable storage medium. The machine-readable storage medium can store and / or encode a sequence of instructions for execution by a machine (e.g., a computing device), and can be any medium that causes the machine to perform any one of the methodologies and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CD, CD-R, DVD, DVD-R, etc.), magneto-optical disks, read-only memory "ROM" devices, random access memory "RAM" devices, magnetic cards, optical cards, solid state memory devices, EPROM, EEPROM, programmable logic devices (PLD), and / or any combination thereof. As used herein, a machine-readable medium includes both a single medium and a collection of physically distinct media such as, for example, a collection of compact disks or one or more hard disk drives in combination with computer memory. As used herein, a machine-readable storage medium does not include transitory forms of signal transmissions.

[0063] Such software may also include information (e.g., data) carried as a data signal on a data carrier such as a carrier wave. For example, machine-executable information can include a data carrier signal embodied in a data carrier that encodes a sequence of instructions or a portion thereof for execution by a machine (e.g., a computing device), and any associated information (e.g., data structures and data) that causes the machine to perform any one of the methodologies and / or embodiments described herein.

[0064] Examples of computing devices include, but are not limited to, e - book reading devices, computer workstations, desktop computers, server computers, handheld devices (such as tablet computers, smartphones, etc.), web devices, network routers, network switches, network bridges, and any machine capable of executing a sequence of instructions that prescribe actions to be taken by those machines and any combination thereof. In one embodiment, the computing device may include and / or be included within a kiosk.

[0065] FIG. 9 shows a graphical representation of one embodiment of a computing device in an exemplary form of a computer system 900 in which a set of instructions for causing the control system to implement any one or more than one of the aspects and / or methodologies of the present disclosure may be executed. It is also envisioned that multiple computing devices may be utilized to implement a specially configured set of instructions for causing one or more than one of those devices to implement any one or more than one of the aspects and / or methodologies of the present disclosure. The computer system 900 includes a processor 904 and a memory 908 that communicate with each other and other components via a bus 912. The bus 912 may include any of several types of bus structures, including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combination thereof, using any of various bus architectures.

[0066] Memory 908 may include various components (e.g., machine-readable media), including but not limited to random access memory components, read-only components, and any combination thereof. In one embodiment, a basic input / output system 916 (BIOS) that includes basic routines that help transfer information between elements within computer system 900 during startup and the like may be stored in memory 908. Memory 908 may also include instructions (e.g., software) 920 that embody any one or more than one of the aspects and / or methodologies of the present disclosure (e.g., stored on one or more than one machine-readable medium). In another embodiment, memory 908 may further include any number of program modules, including but not limited to an operating system, one or more application programs, other program modules, program data, and any combination thereof.

[0067] Computer system 900 may also include a memory device 924. Examples of memory devices (e.g., memory device 924) include, but are not limited to, hard disk drives, magnetic disk drives, optical disk drives in combination with optical media, solid state memory devices, and any combination thereof. Memory device 924 may be connected to bus 912 by an appropriate interface (not shown). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FIREWIRE (registered trademark)), and any combination thereof. In one embodiment, memory device 924 (or one or more of its components) may be removably interfaced with computer system 900 (e.g., via an external port connector (not shown)). In particular, memory device 924 and associated machine-readable medium 928 may provide non-volatile and / or volatile storage for machine-readable instructions, data structures, program modules, and / or other data for computer system 900. In one embodiment, software 920 may reside, in whole or in part, within machine-readable medium 928. In another embodiment, software 920 may reside, in whole or in part, within processor 904.

[0068] Computer system 900 may also include an input device 932. In one embodiment, a user of computer system 900 may enter commands and / or other information into computer system 900 via input device 932. Examples of input device 932 include, but are not limited to, alphanumeric input devices (e.g., keyboards), pointing devices, joysticks, game pads, audio input devices (e.g., microphones, voice response systems, etc.), cursor control devices (e.g., mice), touch pads, optical scanners, video capture devices (e.g., still cameras, video cameras), touch screens, and any combination thereof. Input device 932 may interface with bus 912 via any of a variety of interfaces (not shown), including, but not limited to, serial interfaces, parallel interfaces, game ports, USB interfaces, FIREWIRE (registered trademark) interfaces, direct interfaces to bus 912, and any combination thereof. Input device 932 may further include a touch screen interface that is part of, or separate from, display 936, which is discussed further below. Input device 932 may be utilized as a user selection device for selecting one or more graphical representations within a graphical interface as described above.

[0069] The user may also input commands and / or other information into computer system 900 via a memory device 924 (e.g., a removable disk drive, a flash drive, etc.) and / or a network interface device 940. A network interface device such as network interface device 940 may be utilized to connect computer system 900 to one or more of various networks such as network 944 and one or more remote devices 948 connected thereto. Examples of network interface devices include, but are not limited to, network interface cards (e.g., mobile network interface cards, LAN cards), modems, and any combination thereof. Examples of networks include, but are not limited to, wide area networks (e.g., the Internet, corporate networks), local area networks (e.g., networks associated with offices, buildings, campuses, or other relatively small geographical spaces), telephone networks, data networks associated with telephone / voice providers (e.g., data and / or voice networks of mobile communication providers), direct connections between two computing devices, and any combination thereof. Networks such as network 944 may employ wired and / or wireless modes of communication. Generally, any network topology may be used. Information (e.g., data, software 920, etc.) may be communicated to and / or from computer system 900 via network interface device 940.

[0070] The computer system 900 may further include a video display adapter 952 for communicating an image viewable on a display device, such as the display device 936. Examples of display devices include, but are not limited to, liquid crystal displays (LCDs), cathode ray tubes (CRTs), plasma displays, light emitting diode (LED) displays, and any combination thereof. The display adapter 952 and the display device 936 may be utilized in combination with the processor 904 to provide a graphical representation of aspects of the present disclosure. In addition to the display device, the computer system 900 may include one or more other peripheral output devices including, but not limited to, audio speakers, printers, and any combination thereof. Such peripheral output devices may be connected to the bus 912 via a peripheral interface 956. Examples of peripheral interfaces include, but are not limited to, serial ports, USB connections, FIREWIRE®, parallel connections, and any combination thereof.

[0071] The foregoing is a detailed description of illustrative embodiments of the invention. Various modifications and additions can be made without departing from the spirit and scope of the invention. Each feature of the various embodiments described above can be combined, as appropriate, with features of other described embodiments to provide combinations of multiple features in associated new embodiments. Further, while the foregoing describes several separate embodiments, what is described herein is merely illustrative of the application of the principles of the invention. Additionally, specific methods described herein may be illustrated and / or described as being performed in a particular order, but the order is highly variable among those skilled in the art for achieving embodiments as disclosed herein. Accordingly, this description is intended to be regarded only as examples, and is not intended to limit the scope of the invention otherwise.

[0072] In the above description, and in the claims, phrases such as "at least one of ~" or "one or more of ~" may occur, followed by a connective listing of elements or features. The term "and / or" may also occur within a listing of two or more elements or features. Unless otherwise implicitly or explicitly contradicted by the context in which such phrases are used, this is intended to mean any of the individually listed elements or features, or any of the elements or features cited in combination with any of the other cited elements or features. For example, the phrases "at least one of A and B", "one or more of A and B", and "A and / or B" are each intended to mean "A alone, B alone, or A and B together". Similar interpretations are also intended for listings containing three or more items. For example, the phrases "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, and / or C" are each intended to mean "A alone, B alone, C alone, A and B together, A and C together, B and C together, or A and B and C together". In addition, the use of the term "based on ~" in the above and in the claims is intended to mean "at least, based on ~" so that features or elements not cited are also acceptable.

[0073] The subject matter described in this specification can be embodied in a system, apparatus, method, and / or article, depending on the desired configuration. The implementations described in the foregoing description do not represent all implementations consistent with the subject matter described in this specification. Instead, they are merely some examples consistent with aspects related to the described subject matter. Some variations have been described in detail above, but other modifications or additions are also conceivable. In particular, additional features and / or variations can be provided in addition to those described herein. For example, the implementations described above can be directed to various combinations and sub-combinations of the disclosed features and / or combinations and sub-combinations of some additional features disclosed above. Additionally, the logical flows depicted in the accompanying figures and / or described herein do not necessarily require the particular order or sequential order shown to achieve the desired result. Other implementations can also be within the scope of the following claims.

Claims

1. A decoder, the decoder comprising: receiving a bitstream comprising a reference picture, a current picture having a resolution different from that of the reference picture and including a first block and a second block, and information useful for determining a scaling constant; determining a scaling constant using the information in the bitstream; determining the location of a scaled prediction block by scaling motion vector components using the scaling constant; scaling the resolution of blocks of the reference picture using the scaling constant and applying a filter determined for the scaled prediction block and not determined for the entire reference picture; thereby determining the scaled prediction block from the reference picture; reconstructing the first block using the scaled prediction block; reconstructing the second block without using the scaled prediction block; A decoder configured to perform the above.

2. The information in the bitstream useful for determining a scaling constant includes an index for a set of predetermined values, the index being utilized to determine the scaling constant, the decoder according to claim 1.

3. A decoder, the decoder comprising: receiving a bitstream including a current coded picture including a first plurality of coded blocks and a second plurality of coded blocks; determining a scaling constant using the information in the bitstream; determining a scaled prediction block from a reference picture having a resolution different from that of the current coded picture, by scaling motion vector components to determine the location of the scaled prediction block, scaling blocks from the reference picture using the scaling constant, and applying a filter determined individually for the scaled prediction block; thereby decoding each block of the first plurality of coded blocks; decoding each of the first plurality of coded blocks using its scaled prediction block; decoding each of the second plurality of coded blocks without using a scaled prediction block of a reference picture and without applying a resolution change filter determined for a block of the reference picture; A decoder configured to perform the above.

4. The decoder according to claim 3, wherein the information in the bitstream includes an index for a set of predetermined values, and the index is utilized to determine the scaling constant.

Images