Digital Oscilloscope

Abstract

To improve a technique of displaying information on a bus.SOLUTION: A digital oscilloscope 1 according to the present disclosure can acquire a plurality of logic signals and display a logic waveform. The digital oscilloscope 1 includes: a display unit 27 that can display a logic waveform; and a bus processing circuit 10 for generating, by hardware processing, display data of a bus waveform and display data of a bus value to display on a display unit 27 on the basis of a plurality of logic signals.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a digital oscilloscope.

Background Art

[0002] There are measuring devices such as a digital oscilloscope equipped with a logic input and capable of displaying a plurality of logic signals, such as a logic analyzer.

[0003] Some digital oscilloscopes and logic analyzers can display not only the logic waveforms of individual logic signals but also bus waveforms based on a plurality of logic signals. For example, Patent Document 1 discloses a logic analyzer capable of displaying a bus waveform.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The device described in Patent Document 1 generates a bus waveform by software processing. However, when generating a bus waveform by software processing, it takes time to generate the bus waveform. Therefore, for example, in the roll mode where the waveform is displayed so as to flow from the right to the left of the screen, only the logic waveforms of individual logic signals generated by hardware processing smoothly flow from the right to the left, and the bus waveform may not be able to follow the display format of flowing from the right to the left.

[0006] Therefore, an object of the present disclosure is to provide a digital oscilloscope capable of improving the technology for displaying information related to a bus.

Means for Solving the Problems

[0007] Digital oscilloscopes according to some embodiments are digital oscilloscopes capable of acquiring a plurality of logic signals and displaying logic waveforms, and include a display capable of displaying the logic waveforms, and a bus processing circuit that generates display data of a bus waveform and display data of a bus value for display on the display by hardware processing based on the plurality of logic signals. According to such a digital oscilloscope, it is possible to display the bus waveform and the bus value on the display at high speed. Therefore, according to such a digital oscilloscope, it is possible to improve the technology for displaying information related to the bus.

[0008] In a digital oscilloscope according to an embodiment, a synthesis circuit may be further provided, and the synthesis circuit may synthesize the display data of the bus waveform and the display data of the bus value so that the bus value is displayed between change points of the bus waveform. Thereby, the user can recognize the bus waveform and the bus value as a whole.

[0009] In a digital oscilloscope according to an embodiment, the synthesis circuit may synthesize the logic waveform, the display data of the bus waveform, and the display data of the bus value. Thereby, the user can recognize the logic waveform and the information related to the bus in association with each other.

[0010] In a digital oscilloscope according to an embodiment, the bus processing circuit may generate display data of the bus waveform so that change points of the bus waveform are displayed as diagonal lines. Thereby, it is possible to make it easier for the user to see the change points of the bus.

[0011] In a digital oscilloscope according to an embodiment, the bus processing circuit may generate a bus code indicating a change state of the bus value for each minimum unit of the horizontal resolution of the display, and generate the diagonal lines by combining the bus code and the bus codes shifted before and after it. Thereby, the bus processing circuit can generate diagonal lines with a simple configuration.

[0012] In a digital oscilloscope according to an embodiment, when the period between change points of the bus waveform is equal to or greater than a predetermined threshold, the bus processing circuit may generate display data of the bus value to be displayed between the change points of the bus waveform. Thereby, the process of generating display data of bus values that cannot be displayed can be omitted, and the processing load on the bus processing circuit can be reduced.

[0013] A digital oscilloscope according to an embodiment further includes an acquisition memory that stores the plurality of logic signals, and a logic waveform drawing circuit that generates the logic waveform, and the bus processing circuit may read the plurality of logic signals from the acquisition memory at the same timing as the timing at which the logic waveform drawing circuit reads the plurality of logic signals from the acquisition memory. Thereby, the read process of the logic signals can be executed at once, and the processing time can be reduced.

Advantages of the Invention

[0014] According to the present disclosure, it is possible to provide a digital oscilloscope capable of improving the technology for displaying information related to a bus.

Brief Description of the Drawings

[0015]

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Mode for Carrying Out the Invention

[0016] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings.

[0017] FIG. 1 is a diagram showing a schematic configuration of a digital oscilloscope 1 according to an embodiment. The digital oscilloscope 1 can acquire a plurality of logic signals and display a logic waveform. Further, the digital oscilloscope 1 can display a bus waveform and a bus value generated based on a plurality of logic signals.

[0018] The digital oscilloscope 1 includes a bus processing circuit 10, an AD converter (hereinafter sometimes referred to as "ADC") 11, a sampler 12, a trigger circuit 13, a data capture processing circuit 14, an acquisition memory (hereinafter sometimes referred to as "ACQ memory") 15, an analog waveform drawing circuit 16, a logic waveform drawing circuit 17, a waveform memory 18, a display timing generation circuit 25, a synthesis circuit 26, and a display 27.

[0019] The bus processing circuit 10 includes a bus code generation circuit 19, a bus code memory 20, a bus waveform generation circuit 21, a bus value information generation circuit 22, a bus value information memory 23, and a display bus value generation circuit 24.

[0020] The ADC 11 receives an analog signal, converts the received analog signal into a digital signal, and outputs it to the data capture processing circuit 14. The ADC 11 may receive the analog signal in a state normalized with respect to the full scale of the ADC 11 via an analog front end such as an attenuator or an amplifier. The digital oscilloscope 1 may include any number of one or more ADCs 11.

[0021] The sampler 12 receives the binary digital signal. Hereinafter, the binary digital signal is also referred to as a "logic signal". The sampler 12 may receive the logic signal via a logic probe. The sampler 12 samples the received logic signal and outputs it to the data capture processing circuit 14. The digital oscilloscope 1 may include any number of two or more samplers 12.

[0022] The trigger circuit 13 is a circuit using a digital trigger method. The trigger circuit 13 receives a digital signal from the ADC 11 and a logic signal from the sampler 12. Based on the digital signal received from the ADC 11 and the logic signal received from the sampler 12, the trigger circuit 13 generates a trigger signal under predetermined conditions and outputs the trigger signal to the data acquisition processing circuit 14. The predetermined conditions for generating the trigger signal may be arbitrarily set by the user of the digital oscilloscope 1.

[0023] Based on the trigger signal received from the trigger circuit 13, the data acquisition processing circuit 14 stores the digital signal received from the ADC 11 and the logic signal received from the sampler 12 in the ACQ memory 15.

[0024] The ACQ memory 15 stores the digital signal and the logic signal received from the data acquisition processing circuit 14.

[0025] The analog waveform drawing circuit 16 reads out a digital signal from the ACQ memory 15, performs bitmap conversion, and generates an analog waveform for display on the display 27. The digital signal read out by the analog waveform drawing circuit 16 from the ACQ memory 15 is the digital signal output by the ADC 11 or a digitally processed signal based on it.

[0026] The logic waveform drawing circuit 17 reads out a logic signal from the ACQ memory 15, performs bitmap conversion, and generates a logic waveform for display on the display 27. The logic waveform is a waveform showing the state (logical value 0, logical value 1) of each logic signal and the state of its change. The logic waveform drawing circuit 17 reads out a plurality of logic signals from the ACQ memory 15 and generates a logic waveform for each individual logic signal.

[0027] The waveform memory 18 stores the analog waveform generated by the analog waveform drawing circuit 16 and the logic waveform generated by the logic waveform drawing circuit 17. The waveform memory 18 may store not only one screen's worth of analog waveforms and logic waveforms for display on the display 27, but also multiple screens' worth, such as two or three screens. Thereby, the waveform memory 18 can perform writing to the synthesis circuit 26 and reading from the analog waveform drawing circuit 16 and the logic waveform drawing circuit 17 simultaneously.

[0028] The bus processing circuit 10 reads a plurality of logic signals from the ACQ memory 15 and, based on the read plurality of logic signals, generates display data for the bus waveform and display data for the bus value for display on the display 27 by hardware processing. Here, generating by hardware processing means not generating by software processing using a processor or the like. Since the bus processing circuit 10 generates the display data for the bus waveform and the display data for the bus value by hardware processing, it can generate the display data for the bus waveform and the display data for the bus value at high speed compared to the case of generating by software processing. Details of the processing by the bus processing circuit 10 will be described later.

[0029] The display timing generation circuit 25 generates a timing signal for controlling the display on the display 27. The display timing generation circuit 25 outputs the generated timing signal to the bus processing circuit 10, the synthesis circuit 26, and the display 27. When the display 27 performs display, the display timing generation circuit 25 generates a timing signal at a predetermined time interval and outputs it to the bus processing circuit 10, the synthesis circuit 26, and the display 27.

[0030] The display timing generation circuit 25 generates a dot clock, a horizontal synchronization signal, a vertical synchronization signal, etc. as timing signals for controlling the display on the display 27. The display timing generation circuit 25 has a dot counter that counts the dot clock and a line counter that counts the horizontal synchronization signal. The dot counter indicates the horizontal position on the screen of the display 27. The line counter indicates the vertical position on the screen of the display 27.

[0031] The synthesis circuit 26 reads out an analog waveform and a logic waveform from the waveform memory 18 according to the timing signal received from the display timing generation circuit 25. Also, the synthesis circuit 26 receives the display data of the bus waveform and the display data of the bus value generated by the bus processing circuit 10 according to the timing signal received from the display timing generation circuit 25. The synthesis circuit 26 synthesizes the analog waveform and the logic waveform read out from the waveform memory 18 and the display data of the bus waveform and the display data of the bus value input from the bus processing circuit 10, generates synthesis display data for display on the display 27, and outputs it to the display 27. The synthesis circuit 26 synthesizes the display data of the bus waveform and the display data of the bus value so that the bus value is displayed between the change points of the bus waveform.

[0032] The display 27 displays the synthesis display data according to the timing signal received from the display timing generation circuit 25. The display 27 may include a display device such as a liquid crystal display or an organic EL display, for example.

[0033] In the following description, as an example, it will be described that the number of pixels displayed by the display 27 is 1024×768 pixels. Also, as an example, it will be described that 1000 pixels in the horizontal direction of the display area of the display 27 are allocated to the waveform display area. In this case, when 10000 data are displayed in the waveform display area, 10 data per pixel in the horizontal direction will be displayed.

[0034] Subsequently, the details of the processing by the bus processing circuit 10 will be described.

[0035] The bus processing circuit 10 generates display data of a bus waveform and display data of a bus value for display on the display 27. The bus waveform is a waveform showing the state of change of a bus configured based on a plurality of logic signals. The bus value is the value of a bus configured based on a plurality of logic signals. The bus value is represented, for example, by hexadecimal or binary numbers. The bus value is not limited to hexadecimal and binary numbers and may be represented in any format.

[0036] FIG. 2 shows an example of a bus waveform and a bus value. The bus waveform is a waveform as indicated by reference numeral 301 in FIG. 2. Reference numerals 302 and 303 indicate change points of the bus waveform. That is, reference numerals 302 and 303 are waveforms indicating that there has been a change in the bus value. Reference numeral 304 represents the bus value. As shown in FIG. 2, the bus value 304 is displayed between change points. In the example shown in FIG. 2, the bus value is represented in hexadecimal.

[0037] In the example shown in FIG. 2, at the change point 302, the bus value 304 changes from "1" to "8". Also, at the change point 303, the bus value 304 changes from "8" to "F".

[0038] In the example shown in FIG. 2, the change point 302 is represented by intersecting diagonal lines. This represents that the bus value 304 has changed once at the change point 302. That is, it represents that the bus value 304 has changed from "1" to "8" at the change point 302. By representing the change point with diagonal lines in this way, the user can easily visually recognize the change point of the bus waveform.

[0039] In the example shown in FIG. 2, the change point 303 is represented by intersecting diagonal lines and a vertical line that intersects the intersection of the diagonal lines. This indicates that at the change point 303, the bus value 304 has changed multiple times. That is, at the change point 303, the bus value 304 has changed from "8" to "F", but it indicates that during the change from "8" to "F", it has changed from "8" to "F" via at least one or more other bus values.

[0040] The bus code generation circuit 19 reads a plurality of logic signals from the ACQ memory 15, and extracts information on bits constituting the bus based on the read logic signals. The bus code generation circuit 19 generates a bus code based on the extracted bit information. Here, the "bus code" is a code indicating the state of change of the bus value. Details of the bus code will be described later.

[0041] The bus code memory 20 stores the bus code generated by the bus code generation circuit 19. The bus code memory 20 may store not only one screen's worth of bus codes when displaying on the display 27, but may be able to store multiple screens' worth, such as two screens or three screens. Thereby, the bus code memory 20 can perform writing to the bus waveform generation circuit 21 and reading from the bus code generation circuit 19 simultaneously.

[0042] The bus waveform generation circuit 21 reads a bus code from the bus code memory 20 in response to the timing signal received from the display timing generation circuit 25. The bus waveform generation circuit 21 generates display data for the bus waveform based on the bus code read from the bus code memory 20 and outputs it to the synthesis circuit 26.

[0043] The bus value information generation circuit 22 reads a plurality of logic signals from the ACQ memory 15, and extracts information on bits constituting the bus based on the read logic signals. The bus value information generation circuit 22 generates a bus value based on the extracted bit information.

[0044] The bus value information memory 23 stores the bus values generated by the bus value information generation circuit 22. The bus value information memory 23 may store not only the bus values for one screen when displaying on the display 27, but also multiple screens such as two screens or three screens. Thereby, the bus value information memory 23 can perform writing to the display bus value generation circuit 24 and reading by the bus value information generation circuit 22 and the like simultaneously.

[0045] The display bus value generation circuit 24 reads the bus value from the bus value information memory 23 according to the timing signal received from the display timing generation circuit 25. The display bus value generation circuit 24 generates display data of the bus value based on the bus value read from the bus value information memory 23 and outputs it to the synthesis circuit 26.

[0046] The bus code generation circuit 19 and the bus value information generation circuit 22 read the same plurality of logic signals from the ACQ memory 15 at the same timing as the timing when the logic waveform drawing circuit 17 reads a plurality of logic signals from the ACQ memory 15. Thereby, in one read process, the logic waveform drawing circuit 17, the bus code generation circuit 19, and the bus value information generation circuit 22 can read the same plurality of logic signals.

[0047] Subsequently, with reference to FIGS. 3 to 6, the details of the bus code generation circuit 19, the bus value information generation circuit 22, the bus waveform generation circuit 21, and the display bus value generation circuit 24 will be described.

[0048] First, with reference to FIG. 3, the details of the bus code generation circuit 19 will be described. The bus code generation circuit 19 includes a change point detection unit 191, an acquisition memory read control circuit (hereinafter, may be referred to as an "ACQ memory read control circuit") 192, a bus code generation unit 193, a bus code memory write control circuit 194, and a horizontal position counter 195.

[0049] The change point detection unit 191 always detects whether there is a change from the previous data for the logic signal read from the ACQ memory 15. Here, the "previous data" means the data that is one before in terms of time. For example, when the logic signal read from the ACQ memory 15 contains 10,000 data, the change point detection unit 191 detects whether there is a change from the 99th data for the 100th data.

[0050] The change point detection unit 191 determines the change between the data for one pixel, which is the minimum unit of the horizontal resolution of the display 27, and outputs the determination result to the bus code generation unit 193. When the logic signal read by the change point detection unit 191 from the ACQ memory 15 contains 10,000 data, one pixel contains 10 data. In this case, the change point detection unit 191 determines whether there is a change from the previous data for the 10 data within one pixel. If there is no change from the previous data for the 10 data within one pixel, the change point detection unit 191 determines that there is no change. If there is only one change from the previous data for the 10 data within one pixel, the change point detection unit 191 determines that there is one change. If there are multiple changes from the previous data for the 10 data within one pixel, the change point detection unit 191 determines that there are multiple changes.

[0051] The ACQ memory read control circuit 192 controls the process of the change point detection unit 191 reading the logic signal from the ACQ memory 15.

[0052] The bus code generation unit 193 generates a bus code for each pixel based on the determination result of the change between the data for one pixel obtained from the change point detection unit 191. The bus code is a code indicating the state of the change of the bus value between one pixel. The bus code may indicate four states by four codes from 0 to 3, for example, as follows. 0: Non-display (no display data) 1: No change 2: One change 3: Multiple changes

[0053] When the bus code indicates four states as described above, the bus code can be represented by 2 bits. In the above example of the bus code, "0" of the bus code indicates non-display, and this "non-display" means that there is no display data in the corresponding pixel. For example, when performing roll mode display on the display 27, when the waveform flows and is displayed from the right to the left in the waveform display area, the left side of the head of the waveform becomes non-display. Also, for example, when performing zoom display of a waveform on the display 27, when the zoom position includes the left end of the waveform, the left side of the left end of the waveform becomes non-display, and when the zoom position includes the right end of the waveform, the right side of the right end of the waveform becomes non-display.

[0054] The bus code generation unit 193 may determine whether the bus code is "0" based on the address read from the ACQ memory read control circuit 192.

[0055] The bus code generation unit 193 generates bus codes for 1000 pixels in the horizontal direction and stores them in the bus code memory 20.

[0056] The bus code memory write control circuit 194 controls the writing from the bus code generation unit 193 to the bus code memory 20.

[0057] When reading a logic signal from the ACQ memory 15, the horizontal position counter 195 counts up every time it reads data for 1 pixel, which is the minimum unit of the horizontal resolution of the display 27. For example, if the horizontal direction of the waveform display area of the display 27 is 1000 pixels and a logic signal for 10000 data is read, the horizontal position counter 195 counts up every time it reads a logic signal for 10 data.

[0058] Next, with reference to FIG. 4, the details of the bus value information generation circuit 22 will be described. The bus value information generation circuit 22 includes a bus value generation unit 221, a buffer memory 222, an acquisition memory read control circuit (hereinafter sometimes referred to as the "ACQ memory read control circuit") 223, a horizontal position counter 224, a change point interval detection circuit 225, a buffer memory control circuit 226, a character code generation unit 227, a character left end position generation unit 228, an end determination circuit 229, a character count counter 230, a total character count counter 231, and a bus value information memory write control circuit 232.

[0059] For each character of the bus value to be displayed on the display 27, the bus value information generation circuit 22 generates information on the horizontal position of the left end of the character and a character code, and stores them in the bus value information memory 23. Hereinafter, the horizontal position of the left end of the character is also referred to as the "character left end position". Further, hereinafter, the information combining the bus value, the information on the character left end position, and the information on the character code is also referred to as the "bus value information".

[0060] On the display 27, the bus value is displayed between change points of the bus waveform. Therefore, if the interval between change points is not large enough to display the bus value, the bus value information generation circuit 22 does not need to generate bus value information. Accordingly, the bus value information generation circuit 22 does not need to store a bus value that changes within 1 pixel, which is the minimum unit of the horizontal resolution of the display 27. Therefore, the bus value information generation circuit 22 targets only the last bus value within 1 pixel for the process of generating bus value information.

[0061] The bus value generation unit 221 reads a plurality of logic signals from the ACQ memory 15 and generates a bus value. The bus value generation unit 221 stores the generated bus value in the buffer memory 222.

[0062] The buffer memory 222 stores the bus value received from the bus value generation unit 221. The buffer memory 222 also stores the data received from the change point interval detection circuit 225. Details of the data received by the buffer memory 222 from the change point interval detection circuit 225 will be described later.

[0063] The ACQ memory read control circuit 223 controls the process in which the bus value generation unit 221 reads a logic signal from the ACQ memory 15.

[0064] When reading a logic signal from the ACQ memory 15, the horizontal position counter 224 counts up every time it reads data for one pixel, which is the minimum unit of the horizontal resolution of the display 27.

[0065] The change point interval detection circuit 225 receives a bus code from the bus code generation circuit 19. The change point interval detection circuit 225 detects the interval of the bus code indicating the state of "no change" in the received bus code.

[0066] The details of the process in which the change point interval detection circuit 225 detects the interval of the bus code indicating the state of "no change" will be described.

[0067] The change point interval detection circuit 225 includes a counter. The counter included in the change point interval detection circuit 225 resets the counter when the bus code received from the bus code generation circuit 19 is "non-display", "one change", or "multiple changes". The counter included in the change point interval detection circuit 225 counts up the counter when the bus code received from the bus code generation circuit 19 is "no change".

[0068] Thereby, the change point interval detection circuit 225 can count the number of consecutive pixels with "no change". The change point interval detection circuit 225 holds the value of the horizontal position at the timing when the counter is reset as the start position of the area for displaying the bus value. Hereinafter, the area for displaying the bus value is also referred to as the "bus value display area".

[0069] When the change-point interval detection circuit 225 resets the counter and, if the counter value at that time is equal to or greater than a predetermined threshold, determines that the bus value is to be displayed between change points, it stores the bus value at this time, the counter value indicating the interval between change points, and the head position of the bus value display area in the buffer memory 222. Hereinafter, the interval between change points is also referred to as the "change-point interval".

[0070] For example, when the size of the font to be displayed on the display 27 is 8 pixels horizontally × 16 pixels vertically, the predetermined threshold may be (the number of characters of the bus value to be displayed × 8 pixels + α). Here, α is a numerical value determined by a margin for preventing the diagonal line of the bus waveform from overlapping the bus value, and may be set in advance as an initial value.

[0071] Since the head position of the bus value display area is a value between 0 and 999, 10 bits may be allocated to the head position of the bus value display area. Here, the value of the data of the head position of the bus value display area pre-stored in the buffer memory 222 may be 1000 or more. For example, all bits of the value of the data of the head position of the bus value display area pre-stored may be set to 1. By doing so, when the circuit subsequent to the buffer memory 222 sequentially reads out the bus value, the counter value indicating the change-point interval, and the head position of the bus value display area from the buffer memory 222, if it determines that the value of the data of the head position of the bus value display area is 1000 or more, it can determine that it is not necessary to display the subsequent bus values on the display 27.

[0072] For example, when the number of characters to be displayed as the bus value is 1 and the width of one character is 8 pixels, up to 125 characters can be displayed in the waveform display area of the display 27. Therefore, the buffer memory 222 may have an address for 7 bits as an address for storing the bus value.

[0073] As described above, 10 bits may be allocated to the head position of the bus value display area. Also, since the counter value indicating the change point interval is also a value between 0 and 999, 10 bits may be allocated to the counter value indicating the change point interval. Further, for example, assuming that the maximum width of the bus is 32 bits, 32 bits may be allocated to the bus value. Then, for the data that sets the head position of the bus value display area, the counter value indicating the change point interval, and the bus value, 10 + 10 + 32 = 52 bits may be allocated.

[0074] Therefore, the buffer memory 222 may have an area of 125 × 52 bits as an area for storing data that sets the head position of the bus value display area, the counter value indicating the change point interval, and the bus value.

[0075] The buffer memory 222 may store the data of the bus value of the configured bits selected by the user in descending order from the LSB in the order selected by the user. For the 32 bits allocated to the bus value, the unused bits in the buffer memory 222 may be stored with the upper bits filled with 0.

[0076] The buffer memory control circuit 226 controls the buffer memory 222.

[0077] The character code generation unit 227 generates a character code for each character of the bus value to be displayed on the display 27, and stores the generated character code in the bus value information memory 23. In the present embodiment, it is described assuming that the number of bits of the character code is 4 bits.

[0078] For example, when the bus value is displayed in hexadecimal, the character code generation unit 227 divides the bits into groups of 4 bits from the LSB, and generates a character code for every 4 bits. At this time, the character code generated for the 4 bits including the bit corresponding to the MSB among the bits constituting the bus becomes the character code of the leading character.

[0079] FIG. 7 shows an example in which the number of bits constituting the bus is at most 32 bits and the bus is composed of 9 bits. FIG. 7(a) is an example when the bus value is displayed in hexadecimal. FIG. 7(b) is an example when the bus value is displayed in binary.

[0080] Referring to FIG. 7(a), nine bits are allocated from bit 8 (MSB) to bit 0 (LSB). Here, bits 11 to 8 correspond to the first character, bits 7 to 4 correspond to the second character, and bits 3 to 0 correspond to the third character. Note that bits 31 to 9 may be filled with "0" in the preprocessing. In the case of hexadecimal, the character code is either 0 to F.

[0081] Referring to FIG. 7(b), bits 8 (MSB) to bit 0 (LSB) are divided by 1 bit for each character. When one character is represented by 4 bits, the upper 3 bits are filled with "0", and one of the values from bit 8 to bit 0 is put in the least significant bit. In the case of binary, the character code is either 0 or 1.

[0082] The character code generation unit 227 stores the calculated character code in the bus value information memory 23 by the number of characters of the bus value. When the character code generation unit 227 stores the character code for the number of characters of the bus value in the bus value information memory 23, it reads the next bus value from the buffer memory 222 and executes the same process for the next bus value.

[0083] The character left end position generation unit 228 generates information on the character left end position for each character of the bus value to be displayed on the display 27, and stores the generated information on the character left end position in the bus value information memory 23.

[0084] The left - end position generator 228 reads the start position and the change - point interval from the buffer memory 222. The left - end position generator 228 calculates the central position based on the start position and the change - point interval. The left - end position generator 228 calculates the left - end position of the first character of the bus value by subtracting (the number of characters of the bus value × the width of the font / 2) from the central position. By displaying the left - end of the first character of the bus value at the left - end position calculated in this way, the bus value is displayed near the center between the change - points of the bus waveform.

[0085] For the left - end positions of the characters after the first character, the left - end position generator 228 calculates them by adding the character width of the font to the left - end position of the previous character.

[0086] The left - end position generator 228 stores the calculated left - end positions in the bus - value information memory 23 for the number of characters of the bus value. When the left - end position generator 228 stores the left - end positions for the number of characters of the bus value in the bus - value information memory 23, it reads the next bus value from the buffer memory 222 and executes the same process for the next bus value.

[0087] The end - determination circuit 229 determines whether the data of the start position sequentially read by the left - end position generator 228 from the buffer memory 222 is 1000 or more. When the end - determination circuit 229 determines that the data of the start position is 1000 or more, it outputs a signal instructing to end the reading from the buffer memory 222 to the buffer - memory control circuit 226 and the character - count counter 230.

[0088] The character count 230 counts the number of characters of the bus value for each bus value displayed between the change points of the bus waveform. The number of characters of the bus value displayed between the change points of the bus waveform is determined by the number of bits constituting the bus and the format in which the bus value is displayed. The number of bits constituting the bus and the format in which the bus value is displayed may be set by the user. For example, when the number of bits constituting the bus is 9 bits and the bus value is displayed in hexadecimal, the number of characters is 3 characters. Also, for example, when the number of bits constituting the bus is 9 bits and the bus value is displayed in binary, the number of characters is 9 characters.

[0089] The total character count 231 receives the counter value from the character count and counts up. That is, the total character count 231 counts the total number of characters of the displayed bus value. For example, when the number of displayed bus values is 10 and the number of characters of the bus value is 3 characters, the total character count 231 counts up from 0 to 29.

[0090] The bus value information memory write control circuit 232 controls the writing to the bus value information memory 23.

[0091] The bus value information memory 23 stores the character code and the character left end position for all characters of the displayed bus value. Since the maximum number of characters of the bus value that can be displayed on the display 27 is 125 characters, the bus value information memory 23 only needs to have 125 addresses for storing the character code and the character left end position. The bus value information memory 23 uses the value counted by the total character count 231 as the address for storing the character code and the character left end position.

[0092] Also, since the character code is 4 bits and the character left end position can be stored in 10 bits, the bus value information memory 23 only needs to have a 14-bit area for storing the character code and the character left end position at each address.

[0093] The bus value information memory 23 may set the data of the left end position of the character stored in advance to 1000 or more. For example, the bus value information memory 23 may set all bits of the value of the data of the left end position of the character stored in advance to 1. Thereby, when the circuit subsequent to the bus value information memory 23 sequentially reads the character code and the left end position of the character from the bus value information memory 23, if it determines that the value of the data of the left end position of the character is 1000 or more, it can determine that it is not necessary to read the character code and the left end position of the character thereafter.

[0094] Note that the bus value information generation circuit 22 shown in FIG. 4 includes an ACQ memory read control circuit 223 and a horizontal position counter 224, but the ACQ memory read control circuit 223 and the horizontal position counter 224 may be circuits common to the ACQ memory read control circuit 192 and the horizontal position counter 195 shown in FIG. 3, respectively.

[0095] Subsequently, with reference to FIG. 5, the details of the bus waveform generation circuit 21 will be described. The bus waveform generation circuit 21 includes delay circuits 211-1 to 211-4, a combinational circuit 212, a bus code memory read control circuit 213, and a bus waveform part selection circuit 214. Hereinafter, when the delay circuits 211-1 to 211-4 are not particularly distinguished, they may be simply described as the delay circuit 211.

[0096] The bus waveform generation circuit 21 receives the value of the dot counter and the value of the line counter from the display timing generation circuit 25. The value of the dot counter is received by the bus code memory read control circuit 213. The value of the line counter is received by the bus waveform part selection circuit 214.

[0097] The bus waveform generation circuit 21 reads the bus code from the bus code memory 20 with reference to the value of the dot counter and the value of the line counter. The bus waveform generation circuit 21 generates display data of the bus waveform based on the bus code read from the bus code memory 20.

[0098] FIG. 8 shows an example of display data of a change point of a bus waveform. Note that FIG. 8 shows display data of a change point of a bus waveform in the case of a single change. The horizontal line 401 is a horizontal line displayed at the top when there is no change in the bus value. The horizontal line 402 is a horizontal line displayed at the bottom when there is no change in the bus value. The reference numeral 403 indicates a change point.

[0099] In the example shown in FIG. 8, the change point 403 is represented by two intersecting diagonal lines. The change point 403 is represented using 5 pixels in the horizontal direction. The change point 403 is represented by a first portion 404, a second portion 405, and a third portion 406. The first portion 404 is located at the horizontal position where the bus value has changed and has a height of 6 lines. The second portion 405 is arranged 1 pixel before and after the first portion 404 and has a height of 6 lines. The third portion 406 is arranged 2 pixels before and after the first portion 404 and has a height of 3 lines.

[0100] The delay circuit 211 shifts the bus code received from the bus code memory 20. In the example shown in FIG. 5, the bus waveform generation circuit 21 includes four delay circuits 211 connected in series. This is because the change point 403 is represented using 5 pixels in the horizontal direction. The number of delay circuits 211 connected in series may be (the number of pixels used by the change point in the horizontal direction - 1).

[0101] The combinational circuit 212 receives five bus codes with shifted timings. The combinational circuit 212 reads out the unshifted bus code from the bus code memory 20. The combinational circuit 212 receives the bus code shifted by 1 clock from the delay circuit 211-1. The combinational circuit 212 receives the bus code shifted by 2 clocks from the delay circuit 211-2. The combinational circuit 212 receives the bus code shifted by 3 clocks from the delay circuit 211-3. The combinational circuit 212 receives the bus code shifted by 4 clocks from the delay circuit 211-4.

[0102] The combinational circuit 212 generates display data of the bus waveform represented by diagonal lines by combining the five received bus codes. At this time, the combinational circuit 212 receives information from the bus waveform part selection circuit 214 about which part in the vertical direction of the bus waveform the display data is being generated for.

[0103] Fig. 9 shows an example in which the combinational circuit 212 generates display data of the bus waveform based on five bus codes. In Fig. 9, the change point 403 shows the display of the bus waveform in the case of a single change. Also, the change point 407 shows the display of the bus waveform in the case of multiple changes.

[0104] In Fig. 9, the read data indicates the bus code read by the combinational circuit 212 from the bus code memory 20. The 1-clock shift data to 4-clock shift data respectively indicate the bus codes received by the combinational circuit 212 from the delay circuits 211-1 to 211-4.

[0105] As in the example shown in Fig. 9, when representing the change point 403 or the change point 407 using 5 pixels in the horizontal direction, the middle data, that is, the 2-clock shift data, is the data at the timing that coincides with the timing of the actual bus value. Therefore, when the bus code is "0 (non-display)" in the 2-clock shift data, the combinational circuit 212 does not display the line indicating the bus waveform.

[0106] The bus code memory read control circuit 213 receives the value of the dot counter from the display timing generation circuit 25. The bus code memory read control circuit 213 controls the reading of the bus code from the bus code memory 20.

[0107] The bus waveform part selection circuit 214 receives the value of the line counter from the display timing generation circuit 25, compares the value of the line counter with the preset display position of the bus waveform, and calculates which part of the bus waveform the value of the line counter is.

[0108] Next, referring to FIG. 6, the details of the display bus value generation circuit 24 will be described. The display bus value generation circuit 24 includes a latch circuit 241, a bus value information memory read control circuit 242, a font memory 243, a parallel-serial conversion circuit 244, and a font memory read control circuit 245.

[0109] The display bus value generation circuit 24 receives the value of the dot counter and the value of the line counter from the display timing generation circuit 25. The value of the dot counter is received by the bus value information memory read control circuit 242. The value of the line counter is received by the bus value information memory read control circuit 242 and the font memory read control circuit 245.

[0110] The display bus value generation circuit 24 reads bus value information from the bus value information memory 23 with reference to the value of the dot counter and the value of the line counter. The bus value information includes a bus value, information on the left end position of the character, and information on the character code. The display bus value generation circuit 24 generates display data of the bus value based on the bus value information read from the bus value information memory 23.

[0111] FIG. 10 shows an example of displaying a bus value in a bus waveform. In the example shown in FIG. 10, "8" is displayed as the bus value. As shown in FIG. 10, the bus value is displayed at a position offset from the horizontal line 401 of the bus waveform. The display bus value generation circuit 24 calculates a line for generating display data of the bus value based on the offset.

[0112] In the example shown in FIG. 10, a font with a size of 8 pixels wide × 16 pixels high is used. Therefore, the display bus value generation circuit 24 generates display data of the bus value over 16 lines.

[0113] The latch circuit 241 reads and latches the bus value information from the bus value information memory 23.

[0114] The bus value information memory read control circuit 242 receives the values of the dot counter and the line counter from the display timing generation circuit 25. The bus value information memory read control circuit 242 controls the reading of the bus value from the bus value information memory 23.

[0115] The font memory 243 stores a font for displaying the bus value. The font may be, for example, a fixed-width font. The size of the font to be displayed on the display 27 may be, for example, 8 pixels wide × 16 pixels high. In this case, assuming that the horizontal width of the waveform display area of the display 27 is 1000 pixels, the maximum number of characters of the bus value that can be displayed is 125 characters.

[0116] FIG. 11 shows an example of a font for displaying the bus value. The font memory 243 has an 8-bit address. The 8-bit address of the font memory 243 may indicate the display line with the lower 4 bits and the character code with the upper 4 bits. For example, in FIG. 11, when referring to the address of the character "0", 0 to F of the lower 4 bits indicate the display line, and the upper 4-bit "0" indicates that the character is "0".

[0117] The parallel-serial conversion circuit 244 reads the font data from the font memory 243 and generates the display data of the bus value by parallel-serial converting the read font data.

[0118] When the parallel-serial conversion circuit 244 reads the font data from the font memory 243, it designates the lower 4 bits based on the value of the line counter and the upper 4 bits based on the character code.

[0119] The font memory read control circuit 245 receives the value of the line counter from the display timing generation circuit 25. The font memory read control circuit 245 controls the reading of the font from the font memory 243.

[0120] Subsequently, the operation of the display bus value generation circuit 24 will be described.

[0121] The latch circuit 241 reads the first bus value information from the bus value information memory 23 near the start of the horizontal synchronization signal. The latch circuit 241 latches the read bus value information.

[0122] Based on the information on the leftmost position of the character and the character code information included in the bus value information latched by the latch circuit 241, the parallel-serial conversion circuit 244 reads a font from the font memory 243. At this time, the parallel-serial conversion circuit 244 may read the font from the font memory 243 earlier by the amount of latency in consideration of the latency in the subsequent circuit.

[0123] The parallel-serial conversion circuit 244 performs parallel-serial conversion on the read font to generate display data for the bus value.

[0124] When the process of the parallel-serial conversion circuit 244 reading the font from the font memory 243 is completed, the latch circuit 241 reads the next bus value information from the bus value information memory 23. The display bus value generation circuit 24 repeats this process.

[0125] When the display bus value generation circuit 24 determines that the value of the leftmost position of the character included in the bus value information read from the bus value information memory 23 is 1000 or more, it ends the process of generating the display data for the bus value for that line.

[0126] By synthesizing the display data of the bus value generated by the display bus value generation circuit 24 and the display data of the bus waveform generated by the bus waveform generation circuit 21 by the synthesis circuit 26, as shown in FIG. 10, the bus value and the bus waveform can be superimposed and displayed on the display 27.

[0127] As described above, in the digital oscilloscope 1 according to the present embodiment, the bus processing circuit 10 generates display data of the bus waveform and display data of the bus value by hardware processing. As a result, it becomes possible to display the bus waveform and the bus value on the display 27 at high speed. Therefore, for example, even when displaying in roll mode or auto-scroll mode, the bus waveform and the bus value can be displayed so as to flow smoothly. In particular, when analog waveforms and logic waveforms are also generated by hardware processing, the bus waveform and the bus value can be displayed so as to flow at exactly the same timing as these waveforms. Here, the auto-scroll display is a display method in which, in a zoom display in which a part of the captured waveform is enlarged and displayed in the time axis direction, the position of the time axis to be enlarged is automatically changed so that the waveform appears to scroll at a constant speed in the time axis direction. Also, for example, even when the display position is changed by a drag operation using a touch screen or the like, the bus waveform and the bus value can be smoothly moved and displayed. Therefore, according to the digital oscilloscope 1 according to the present embodiment, the technology for displaying information related to the bus such as the bus waveform and the bus value can be improved.

[0128] (First Modified Example) FIG. 12 shows a schematic configuration of a digital oscilloscope 2 according to the first modified example. Regarding the digital oscilloscope 2 according to the first modified example, the differences from the digital oscilloscope 1 described with reference to FIG. 1 will be mainly described, and the description of similar contents will be omitted as appropriate.

[0129] The digital oscilloscope 2 according to the first modified example is different from the digital oscilloscope 1 shown in FIG. 1 in that the trigger circuit 13 is an analog trigger type circuit.

[0130] Also, the digital oscilloscope 2 according to the first modified example further includes a comparator 28, unlike the digital oscilloscope 1 shown in FIG. 1. The comparator 28 binarizes the analog signal before it is input to the ADC 11 and outputs it to the trigger circuit 13.

[0131] In the digital oscilloscope 2 according to the first modification example, the trigger circuit 13 receives the binary signal from the comparator 28. The trigger circuit 13 also receives the logic signal before it is input to the sampler 12.

[0132] Based on the binary signal received from the comparator 28 and the logic signal before it is input to the sampler 12, the trigger circuit 13 generates a trigger signal under a predetermined condition and outputs the trigger signal to the data capture processing circuit 14. The predetermined condition for generating the trigger signal may be arbitrarily set by the user of the digital oscilloscope 2.

[0133] (Second Modification Example) FIG. 13 shows a schematic configuration of a digital oscilloscope 3 according to the second modification example. Regarding the digital oscilloscope 3 according to the second modification example, the differences from the digital oscilloscope 1 described with reference to FIG. 1 will be mainly described, and the description of similar contents will be omitted as appropriate.

[0134] The digital oscilloscope 3 according to the second modification example includes a bus processing circuit 10A, an ADC 11, a sampler 12, a trigger circuit 13, a data capture processing circuit 14, an ACQ memory 15, an analog waveform drawing circuit 16, a logic waveform drawing circuit 17, a waveform memory 18, a display timing generation circuit 25, a synthesis circuit 26, and a display 27.

[0135] The bus processing circuit 10A included in the digital oscilloscope 3 according to the second modification example includes a bus code generation circuit 19, a bus code memory 20A, a bus code memory 20B, a bus waveform generation circuit 21, a bus value information generation circuit 22, a bus value information memory 23A, a bus value information memory 23B, and a display bus value generation circuit 24.

[0136] Thus, the bus processing circuit 10A is different from the bus processing circuit 10 shown in FIG. 1 in that it includes two bus code memories, namely, the bus code memory 20A and the bus code memory 20B. Further, the bus processing circuit 10A is different from the bus processing circuit 10 shown in FIG. 1 in that it includes two bus value information memories, namely, the bus value information memory 23A and the bus value information memory 23B.

[0137] The digital oscilloscope 3 can vary the update rate of the bus waveform and the bus value displayed on the display 27 by virtue of the bus processing circuit 10A including two bus code memories, namely, the bus code memory 20A and the bus code memory 20B, and two bus value information memories, namely, the bus value information memory 23A and the bus value information memory 23B.

[0138] For example, when the frequency of the vertical synchronization signal is 60 Hz, it may be difficult to view the bus waveform and the bus value being updated at 60 Hz. In particular, for the bus value, it is difficult to distinguish the value when it is updated at 60 Hz. In such a case, the update rate of the bus waveform and the bus value can be decreased to make them easier to view, and in some cases, the amount of information that the user can obtain can be increased compared to the case where the update rate is not decreased.

[0139] The bus waveform generation circuit 21 shown in FIG. 1 directly read the bus code from the bus code memory 20 based on the values of the dot counter and the line counter received from the display timing generation circuit 25. Further, the display bus value generation circuit 24 shown in FIG. 1 directly read the bus value information from the bus value information memory 23 based on the values of the dot counter and the line counter received from the display timing generation circuit 25.

[0140] In contrast, in the bus processing circuit 10A shown in FIG. 13, the bus code memory 20B directly reads the bus code from the bus code memory 20A based on the values of the dot counter and the line counter received from the display timing generation circuit 25, and updates the content of the bus code memory 20B. At this time, the bus code memory 20B reads from the bus code memory 20A every time in units of vertical synchronization signals, but the update of the bus code memory 20B can be thinned out to once every several times in units of vertical synchronization signals. For example, the update of the bus code memory 20B can be thinned out to once every two times of the vertical synchronization signal. After that, the bus waveform generation circuit 21 reads the bus code from the bus code memory 20B every time in units of vertical synchronization signals for display on the display 27, and outputs the generated bus waveform to the synthesis circuit 26. However, since the bus code memory 20B is updated only once every two times of the vertical synchronization signal, the update rate of the bus waveform can be reduced from 60 Hz to 30 Hz.

[0141] Also, in the bus processing circuit 10A shown in FIG. 13, the bus value information memory 23B directly reads the bus value information from the bus value information memory 23A based on the values of the dot counter and the line counter received from the display timing generation circuit 25, and updates the content of the bus value information memory 23B. At this time, the bus value information memory 23B reads from the bus value information memory 23A every time in units of vertical synchronization signals, but the update of the bus value information memory 23B can be thinned out to once every several times in units of vertical synchronization signals. For example, the update of the bus value information memory 23B can be thinned out to once every two times of the vertical synchronization signal. After that, the display bus value generation circuit 24 reads the bus value information from the bus value information memory 23B every time in units of vertical synchronization signals for display on the display 27, and outputs the generated display bus value to the synthesis circuit 26. However, since the bus value information memory 23B is updated only once every two times of the vertical synchronization signal, the update rate of the display bus value can be reduced from 60 Hz to 30 Hz.

[0142] Since the bus code is read from the bus code memory 20A by the bus code memory 20B every time according to the vertical synchronization signal, no matter at what timing the update of the bus code memory 20A stops, the display 27 can display the bus waveform based on the information of the last bus code.

[0143] Also, since the bus value information is read from the bus value information memory 23A by the bus value information memory 23B every time according to the vertical synchronization signal, no matter at what timing the update of the bus value information memory 23A stops, the display 27 can display the bus value based on the last bus value information.

[0144] Also, when the display 27 is performing roll mode display, or auto-scroll display of the zoom waveform, etc., by displaying at the highest update rate without reducing the update rate, the display of the bus waveform and the bus value can be made to flow smoothly.

[0145] Note that in the digital oscilloscope 3 according to the second modification example, like the digital oscilloscope 2 according to the first modification example shown in FIG. 12, the trigger circuit 13 may be a circuit of an analog trigger method.

[0146] (Third Modification Example) FIG. 14 shows a schematic configuration of a digital oscilloscope 4 according to the third modification example. Regarding the digital oscilloscope 4 according to the third modification example, the differences from the digital oscilloscope 3 according to the second modification example described with reference to FIG. 13 will be mainly described, and the description of similar contents will be omitted as appropriate.

[0147] The digital oscilloscope 4 according to the third modification example includes a bus processing circuit 10A, an ADC 11, a sampler 12, a trigger circuit 13, a data capture processing circuit 14, an ACQ memory 15, an analog waveform drawing circuit 16, a logic waveform drawing circuit 17A, a waveform memory 18A, a display timing generation circuit 25, a synthesis circuit 26, and a display 27.

[0148] The digital oscilloscope 4 according to the third modification example is different from the digital oscilloscope 3 according to the second modification example in that it is possible to superimpose and draw the waveforms captured a plurality of times for the logic waveform.

[0149] Note that it is easier to view without superimposing and drawing the bus waveform and bus value. Therefore, the digital oscilloscope 4 does not perform superimposing and drawing for the bus waveform and bus value, and performs superimposing and drawing only for the logic waveform.

[0150] The logic waveform drawing circuit 17A generates a single logic waveform and a superimposed logic waveform. The waveform memory 18A stores the single logic waveform and the superimposed logic waveform generated by the logic waveform drawing circuit 17A.

[0151] The single logic waveform generated by the logic waveform drawing circuit 17A is a logic waveform generated based on the logic signal read at the same timing as the logic signal read by the bus processing circuit 10A to generate the bus waveform and bus value.

[0152] The logic waveform drawing circuit 17A may generate the single logic waveform as a waveform in a mode different from the superimposed logic waveform. For example, the logic waveform drawing circuit 17A may draw the single logic waveform in a color different from the superimposed logic waveform. Alternatively, the logic waveform drawing circuit 17A may draw the single logic waveform with a thicker line than the superimposed logic waveform. By thus drawing the single logic waveform as a waveform in a mode different from the superimposed logic waveform, the user can easily recognize the logic waveform at the same timing as the bus waveform and bus value.

[0153] For comparison, an example of the timing chart of the drawing process when superimposing and drawing is not performed is shown in FIG. 15.

[0154] In FIG. 15, the top line represents the vertical synchronization signal output by the display timing generation circuit 25. The second line from the top represents the memory access of the ACQ memory 15. The third line from the top represents the memory access of the bus code memory 20A or the bus value information memory 23A. In the third line from the top, "transfer" represents the data transfer to the bus code memory 20B or the bus value information memory 23B. The bottom line represents the display timing of the display 27. In the example shown in FIG. 15, when the logic waveform drawing circuit 17A fetches a logic signal from the ACQ memory 15, it performs the drawing process of the logic waveform. Also, the bus processing circuit 10A performs bus processing based on the logic signal at the same timing as the logic signal fetched by the logic waveform drawing circuit 17A, and transfers the data processed by the bus near the start of the vertical synchronization signal.

[0155] Subsequently, an example of the time chart of the drawing process in the case of performing over-drawing is shown in FIG. 16.

[0156] In the example shown in FIG. 16, when the logic waveform drawing circuit 17A fetches six logic signals from the ACQ memory 15, it performs the drawing process of overlapping six logic waveforms. At this time, for the logic signal fetched at the sixth time, the logic waveform drawing circuit 17A performs the drawing process as a waveform in a different mode from other logic waveforms.

[0157] Also, the bus processing circuit 10A performs bus processing such as bus code generation and bus value information generation based on the logic signal at the same timing as the logic signal fetched by the logic waveform drawing circuit 17A at the sixth time. The bus processing circuit 10A may perform data transfer from the bus code memory 20A to the bus code memory 20B and data transfer from the bus value information memory 23A to the bus value information memory 23B near the start of the vertical synchronization signal.

[0158] Although the digital oscilloscope 4 according to the third modification has been described as performing over-drawing for logic waveforms, over-drawing may further be performed for analog waveforms.

[0159] Further, the digital oscilloscope 4 according to the third modification example may have a trigger circuit 13 that is a circuit of an analog trigger method, like the digital oscilloscope 2 according to the first modification example shown in FIG. 12.

[0160] It is obvious to those skilled in the art that the present disclosure can be realized in other predetermined forms other than the above-described embodiments without departing from its spirit or its essential features. Therefore, the foregoing description is illustrative and not restrictive. The scope of the disclosure is defined not by the foregoing description but by the appended claims. Some changes within the equivalent scope of any change are included therein.

[0161] For example, the arrangement and number of each of the above-described components are not limited to the content shown in the above description and the drawings. The arrangement and number of each component may be arbitrarily configured as long as its function can be realized.

[0162] Also, in the present disclosure, although the description has been centered on the device, the present disclosure can also be realized as a method including steps executed by each component of the device, a method executed by a processor included in the device, a program, or a storage medium storing the program, and it should be understood that these are also included in the scope of the present disclosure.

Explanation of Signs

[0163] 1, 2, 3, 4 Digital oscilloscope 10, 10A Bus processing circuit 11 ADC (AD converter) 12 Sampler 13 Trigger circuit 14 Data capture processing circuit 15 ACQ memory (Acquisition memory) 16 Analog waveform drawing circuit 17, 17A Logic waveform drawing circuit 18, 18A Waveform memory 19 Bus code generation circuit 20 Bus code memory 20A and 20B Bus Code Memory 21 Bus Waveform Generation Circuit 22 Bus Value Information Generation Circuit 23 Bus Value Information Memory 23A and 23B Bus Value Information Memory 24 Display Bus Value Generation Circuit 25 Display Timing Generation Circuit 26 Synthesis Circuit 27 Display 28 Comparator 191 Change Point Detection Unit 192 ACQ Memory Read Control Circuit (Acquisition Memory Read Control Circuit) 193 Bus Code Generation Unit 194 Bus Code Memory Write Control Circuit 195 Horizontal Position Counter 211 Delay Circuit 212 Combinational Circuit 213 Bus Code Memory Read Control Circuit 214 Bus Waveform Part Selection Circuit 221 Bus Value Generation Unit 222 Buffer Memory 223 ACQ Memory Read Control Circuit (Acquisition Memory Read Control Circuit) 224 Horizontal Position Counter 225 Change Point Interval Detection Circuit 226 Buffer Memory Control Circuit 227 Character Code Generation Unit 228 Character Left End Position Generation Unit 229 End Judgment Circuit 230 Character Count Counter 231 Total Character Count Counter 232 Bus Value Information Memory Write Control Circuit 241 Latch Circuit 242 Bus Value Information Memory Read Control Circuit 243 Font Memory 244 Parallel-Serial Conversion Circuit 245 Font Memory Read Control Circuit

Claims

1. A digital oscilloscope capable of acquiring a plurality of logic signals and displaying a logic waveform, comprising: a display capable of displaying the logic waveform; a bus processing circuit that generates display data for a bus waveform and display data for a bus value to be displayed on the display by hardware processing based on the plurality of logic signals; the bus processing circuit generates the display data for the bus waveform such that a change point of the bus waveform is displayed as a diagonal line; the bus processing circuit generates a bus code indicating a change state of the bus value for each pixel, which is the minimum unit of the horizontal resolution of the display; generates combined data by combining the generated bus code with a bus code shifted one pixel forward, a bus code shifted two pixels forward, a bus code shifted one pixel backward, and a bus code shifted two pixels backward; A digital oscilloscope that generates the diagonal line by drawing a vertical line at a horizontal pixel where the combined data includes a bus code indicating that the bus value has changed.

2. The digital oscilloscope according to claim 1, further comprising: a synthesis circuit; The synthesis circuit synthesizes the display data for the bus waveform and the display data for the bus value such that the bus value is displayed between change points of the bus waveform.

3. The digital oscilloscope according to claim 2, wherein the synthesis circuit synthesizes the logic waveform, the display data for the bus waveform, and the display data for the bus value.

4. In the digital oscilloscope according to any one of claims 1 to 3, the bus processing circuit generates the display data for the bus value to be displayed between change points of the bus waveform when the interval between the change points of the bus waveform is equal to or greater than a predetermined threshold.

5. In the digital oscilloscope according to any one of claims 1 to 4, an acquisition memory for storing the plurality of logic signals; a logic waveform drawing circuit for generating the logic waveform; The bus processing circuit is a digital oscilloscope that reads the plurality of logic signals from the acquisition memory at the same timing as the timing at which the logic waveform drawing circuit reads the plurality of logic signals from the acquisition memory.

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