Time synchronization method between a host device and a storage device and its system

Abstract

To provide a method for efficient time synchronization between a host device and a storage device, and a system for performing the same.SOLUTION: A time synchronization method according to the present invention is a method for time synchronization between a host device and a storage device and includes the steps of: in the storage device, determining a time synchronization section requiring time information on the host device; notifying the time synchronization section to the host device from the storage device; in the time synchronization section, providing the time information on the host device to the storage device from the host device; and in the storage device, based on the time information on the host device, synchronizing time information on the storage device with the time information on the host device.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and more particularly, to a method for time synchronization between a host device and a storage device and a system for performing the same.

Background Art

[0002] In recent years, storage devices such as SSDs (solid state drives) that utilize memory devices have been widely used. Since the storage device as described above has no mechanical drive unit, it has advantages of excellent stability and durability, a very high information access speed, and low power consumption. Recently, as electronic circuits are applied to various types of systems such as not only electronic systems such as notebook personal computers but also automobiles, airplanes, drones, etc., storage devices are also used in various types of systems.

[0003] On the other hand, in order to improve the performance and / or lifespan of storage devices, various methods for managing the time information of storage devices have been studied.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the problems in the above-described conventional storage devices, and an object of the present invention is to provide an efficient time synchronization method between a host device and a storage device. Another object of the present invention is to provide a system for performing an efficient time synchronization method between a host device and a storage device.

Means for Solving the Problem

[0006] The time synchronization method according to the present invention made to achieve the above object is a time synchronization method between a host device and a storage device. In the storage device, it includes steps of determining a time synchronization interval in which time information of the host device is required, notifying the host device from the storage device of the time synchronization interval, providing the time information of the host device from the host device to the storage device during the time synchronization interval, and in the storage device, synchronizing the time information of the storage device with the time information of the host device based on the time information of the host device. It is characterized by having these steps.

[0007] The system according to the present invention made to achieve the above object includes a storage device including a plurality of non-volatile memory devices and a host device for controlling the storage device. In the storage device, it determines a time synchronization interval in which time information of the host device is required, notifies the host device from the storage device of the time synchronization interval, and provides the time information of the host device from the host device to the storage device during the time synchronization interval. It is characterized by this.

[0008] Further, the time synchronization method according to the present invention made to achieve the above object is a time synchronization method between a host device and a storage device that communicate according to the UFS standard. In the storage device, the method includes: determining a time synchronization interval in which time information of the host device is required; notifying the host device from the storage device of the start of the time synchronization interval; providing the time information of the host device from the host device to the storage device during the time synchronization interval based on the notification of the start of the time synchronization interval; notifying the host device from the storage device of the end of the time synchronization interval; and stopping providing the time information of the host device in the host device based on the notification of the end of the time synchronization interval. The start and end of the time synchronization interval are notified and the time information of the host device is provided by using a UFS protocol information unit (UPIU) according to the UFS standard or a unipro attribute of the host device or the storage device according to the UFS standard.

Advantages of the Invention

[0009] According to the time synchronization method and its system according to the present invention, by providing time information from the host device to the storage device only during a time synchronization interval determined by the storage device, the overhead of time information transfer can be reduced, and the performance of the storage device and the system including the same can be improved. In addition, without using another signal for transferring time information, by expanding an existing signal to transfer time information, the overhead of time information transfer can be further reduced.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Next, a specific example of an embodiment for implementing a time synchronization method and its system between a host device and a storage device according to the present invention will be described with reference to the drawings. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. For the same components on the drawings, the same drawing numbers are assigned, and duplicate explanations for the same components are omitted.

[0012] FIG. 1 is a flowchart for explaining a time synchronization method according to an embodiment of the present invention. As shown in FIG. 1, the time synchronization method according to an embodiment of the present invention is performed by a system including a host device and a storage device. The storage device operates based on commands received from the host device. The structure of the system including the host device and the storage device will be described later with reference to FIG. 2 and the like.

[0013] According to the time synchronization method according to an embodiment of the present invention, in the storage device, a time synchronization interval in which the time information of the host device is required is determined (step S100). The storage device includes a timer and manages the time information of the storage device based on the local time provided by the timer. However, in the power cycle or hibernation interval, the operation of the timer is unavailable, and it is necessary to provide the time information of the host device for time synchronization with the host device. The storage device determines the time synchronization interval periodically or aperiodically.

[0014] The storage device notifies the host device of the time synchronization interval (step S200). During the time synchronization interval, the host device provides the time information of the host device to the storage device (step S300).

[0015] The storage device notifies the host device of the start and end of the time synchronization interval. Based on the notification of the start of the time synchronization interval, the host device provides the time information of the host device to the storage device during the time synchronization interval, and based on the notification of the end of the time synchronization interval, the host device stops providing the time information.

[0016] In one embodiment, as described later with reference to FIGS. 8 to 19, the time synchronization interval can be notified from the storage device to the host device and the time information of the host device can be provided from the host device to the storage device by using a Universal Flash Storage (UFS) Protocol Information Unit (UPIU) according to the UFS standard. In other embodiments, as will be described later with reference to FIGS. 20 and 21, the UniPro attribute of the host device or the storage device according to the UFS standard can be used to notify the host device from the storage device of the time synchronization interval and provide the time information of the host device from the host device to the storage device.

[0017] In the storage device, based on the time information of the host device, the time information of the storage device is synchronized with the time information of the host device (step S400). In one embodiment, the storage device corrects the time information of the host device provided from the host device based on the local time provided from the built-in timer, and manages the time information of the storage device based on the corrected time information of the host device.

[0018] As will be described later with reference to FIG. 23, various operations for improving the performance of the system can be performed using the time information of the storage device synchronized with the time information of the host device. Conventionally, the host device has previously set a time providing period, and during the operation of the storage device, the time information of the host device has been transferred to the storage device periodically using another command. In this case, overhead occurs in the interface between the host device and the storage device due to the transfer of another command for providing time information.

[0019] The time synchronization method according to the embodiment of the present invention and the system performing the time synchronization method can reduce the overhead of time information transfer and improve the performance of the storage device and the system including the same by providing the time information from the host device to the storage device only during the time synchronization interval determined by the storage device. Further, the time synchronization method according to the embodiment of the present invention and the system performing the time synchronization method can further reduce the overhead of time information transfer by extending the existing signal to transfer the time information without using another signal for transferring the time information.

[0020] Figure 2 is a block diagram showing a schematic configuration of a storage device and a storage system including the same according to an embodiment of the present invention. As shown in FIG. 2, the storage system 100 includes a host device 200 and a storage device 300.

[0021] The host device 200 controls the overall operation of the storage system 100. The host device 200 includes a host processor 210 and a host memory 220. The host processor 210 controls the operation of the host device 200. For example, the host processor 210 executes an operating system (OS). For example, the operating system includes a file system for file management and a device driver for controlling peripheral devices including the storage device 300 at the operating system level. For example, the host processor 210 may include any processor such as a CPU. The host memory 220 stores commands and data executed and processed by the host processor 210. For example, the host memory 220 includes a volatile memory such as DRAM.

[0022] The storage device 300 is accessed by the host device 200. The storage device 300 includes a storage controller 310, a plurality of non-volatile memories (320a, 320b, 320c), and a buffer memory 330. The storage controller 310 controls the operation of the storage device 300. For example, the storage controller 310 controls the operation of the plurality of non-volatile memories (320a, 320b, 320c) based on commands and data received from the host device 200.

[0023] The host processor 210 and the storage controller 310 are embodied to perform the time synchronization method according to the embodiment of the present invention as described in FIG. 1. For example, the host processor 210 includes a time information generator 212 that generates time information (TI) of the host device 200, and the storage controller 310 receives the time information (TI) from the host device 200 and includes a time information manager 312 that manages the time information of the storage device 300 based on this. The time information manager 312 of the storage device 300 determines a time synchronization interval in which the time information (TI) of the host device 200 is required, and notifies the host device 200 of the time synchronization interval. The host device 200 provides the time information (TI) generated by the time information generator 212 to the storage device 300, and the time information manager 312 of the storage device 300 synchronizes the time information of the storage device 300 with the time information (TI) of the host device 200 based on the time information (TI) of the host device 200.

[0024] The plurality of non-volatile memories (320a, 320b, 320c) store a plurality of data. For example, the plurality of non-volatile memories (320a, 320b, 320c) store metadata and other user data. In one embodiment, each of the plurality of non-volatile memories (320a, 320b, 320c) includes a NAND flash memory.

[0025] In other embodiments, each of the plurality of non-volatile memories (320a, 320b, 320c) includes an EEPROM (Electrically Erasable Programmable Read-Only Memory), a PRAM (Phase Change Random Access Memory), an RRAM (Resistance Random Access Memory), an NFGM (Nano Floating Gate Memory), a PoRAM (Polymer Random Access Memory), an MRAM (Magnetic Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), or a memory similar thereto.

[0026] The buffer memory 330 stores commands and data to be executed and processed by the storage controller 310, and can temporarily store data that is or is to be stored in the plurality of non-volatile memories (320a, 320b, 320c). For example, the buffer memory 330 includes a volatile memory such as an SRAM (Static Random Access Memory) or a DRAM.

[0027] In one embodiment, the storage device 300 is a UFS (Universal Flash Storage). In other embodiments, the storage device 300 is an SSD (Solid State Drive), an MMC (Multi Media Card), or an eMMC (embedded MMC). In other embodiments, it is embodied in the form of an SD (Secure Digital) card, a micro SD card, a memory stick (registered trademark), a chip card, a USB (Universal Serial Bus) card, a smart card, a CF (Compact Flash) card, or the like.

[0028] In one embodiment, the storage device 300 is connected to the host device 200 via a block accessible interface including buses such as SATA (Serial Advanced Technology Attachment) bus, SCSI (Small Computer Small Interface) bus, NVMe (Non-Volatile Memory Express) bus, SAS (Serial Attached SCSI) bus, UFS, eMMC, etc., and is accessed by the host device 200 in block units via the block accessible interface.

[0029] In one embodiment, the storage system 100 is any computer system such as a PC, a server computer, a data center, a workstation, a digital TV, a set-top box, etc. In other embodiments, the storage system 100 is any mobile system such as a mobile phone, a smartphone, a tablet PC, a laptop computer, a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a digital camera, a camcorder, a portable game console, a music player, a video player, a navigation device, a wearable device, an IoT (Internet of Things) device, an e-book, a VR (Virtual Reality) device, an AR (Augmented Reality) device, a drone, etc.

[0030] FIG. 3 is a diagram for explaining the operation of the storage system according to an embodiment of the present invention. FIG. 3 conceptually shows the software hierarchical structure of the host device 200 and the storage device 300 in FIG. 2. As shown in FIG. 3, the host device 200 includes a device driver 251, a time information generator 252, a command generator 253, a response analyzer 254, a data transfer manager 256, a link layer 257, and a PHY (physical layer) 258.

[0031] The device driver 251 controls the general operations for controlling the storage device 300. The time information generator 252 generates the time information of the host device 200. In one embodiment, the time information generator 252 generates an RTC (real time clock) as the time information. The command generator 253 generates commands to be transferred to the storage device 300. The response analyzer 254 analyzes the command word request response received from the storage device 300. The data transfer manager 256 generates packets for the data to be transmitted to the storage device 300. The link layer 257 controls the data flow transmitted to the PHY 258 and performs recovery for data transfer errors. The PHY 258 manages the physical data communication with the storage device 300.

[0032] On the other hand, although not shown in FIG. 3, the host device 200 can further include an application and a file system. The application, also referred to as an application program, is software that runs on the operating system. For example, the application is programmed to assist in file generation, copying, and deletion operations. For example, the application can provide various services such as videos, games, web browsers, and the like.

[0033] The file system manages the files used in the host device 200. For example, upon a request from an application, a file system manages a file name, an extension, file attributes, a file size, cluster information, etc. for a file to be accessed. Also, the file system generates, deletes, and manages data in file units. For example, the file system is F2FS (Flash-Friendly File System) or the like. An application, a file system, etc. are called high level, and a data transfer manager 256, a link layer 257, a PHY 258, etc. are called low level.

[0034] The storage device 300 includes a device controller 351, a time information manager 352, a response generator 353, a command analyzer 354, a data transfer manager 356, a link layer 357, and a PHY 358.

[0035] The device controller 351 controls the overall operation of the storage device 300. The time information manager 352 manages the time information transmitted from the host device 200. The response generator 353 generates a response to be transferred to the host device 200. The command analyzer 354 analyzes the command transferred from the host device 200. The data transfer manager 356 generates packets for data to be transmitted to the host device 200. The link layer 357 controls the data flow to be transmitted to the PHY 358 and performs recovery for data transfer errors. The PHY 358 manages the physical data communication with the host device 200.

[0036] On the other hand, although not shown in FIG. 3, the storage device 300 can further include an FTL (Flash Translation Layer). The FTL can perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation that replaces the logical address received from the host device 200 with the physical address used to actually store data in the non-volatile memory (e.g., 320a, 320b, 320c in FIG. 2).

[0037] Wear-leveling is a technique for preventing excessive degradation of a specific block by ensuring that the memory blocks in the non-volatile memory (320a, 320b, 320c) are uniformly used, and can be implemented, for example, by a firmware technique that balances the erase counts of physical blocks. Garbage collection is a technique for securing the available capacity in the non-volatile memory (320a, 320b, 320c) by copying the valid data of a memory block to a new memory block and then erasing the existing memory block.

[0038] In one embodiment, the link layer 257 of the host device 200 and the link layer 357 of the storage device 300 are implemented according to the UniPro protocol proposed by the MIPI Alliance. In this case, the link layer 257 includes a register (HREG) that stores the UniPro attributes of the host device 200, and the link layer 357 includes a register (SREG) that stores the UniPro attributes of the storage device 300.

[0039] FIG. 4 is a block diagram showing a schematic configuration of an example of a storage controller included in a storage device according to an embodiment of the present invention. As shown in FIG. 4, the storage controller 400 includes a processor 410, a memory 420, a time information manager 430, a host interface 440, an ECC (Error Correction Code) engine 450, a memory interface 460, and an AES (Advanced Encryption Standard) engine 470.

[0040] The processor 410 controls the operation of the storage controller 400 in response to commands received from a host device (e.g., 200 in FIG. 2) via the host interface 440. For example, the processor 410 controls the operation of the storage device (e.g., 300 in FIG. 2) and employs firmware for driving the storage device 300 to control each configuration. The memory 420 stores instruction words and data to be executed and processed by the processor 410. For example, the memory 420 can be implemented as a volatile memory such as SRAM, DRAM, etc.

[0041] The time information manager 430 for performing the time synchronization method according to an embodiment of the present invention determines a time synchronization interval in which the time information of the host device 200 is required, and synchronizes the time information of the storage device 300 with the time information of the host device 200 based on the time information of the host device 200 provided from the host device 200. The time information manager 430 can correct an error in the time information provided from the host device 200 based on the local time provided from the built-in timer 432.

[0042] The ECC engine 450 for error correction can perform ECC encoding and ECC decoding using coded modulation such as BCH (Bose-Chaudhuri-Hocquenghem) code, LDPC (Low Density Parity Check) code, Turbo code, Reed-Solomon code, Convolution Code, RSC (Recursive Systematic Code), TCM (Trellis-Coded Modulation), BCM (Block Coded Modulation), or other error correction codes.

[0043] The host interface 440 provides a physical connection between the host device 200 and the storage device 300. That is, the host interface 440 provides an interface with the storage device 300 corresponding to the bus format of the host device 200. In one embodiment, the bus format of the host device 200 is SCSI or SAS. In other examples, the bus format of the host device 200 is USB, PCIe (peripheral component interconnect express), ATA, PATA, SATA, NVMe.

[0044] The memory interface 460 exchanges data with non-volatile memory (e.g., (320a, 320b, 320c) in FIG. 2). The memory interface 460 transfers data to the non-volatile memory (320a, 320b, 320c) and receives the data read from the non-volatile memory (320a, 320b, 320c). For example, the memory interface 460 is implemented to comply with a standard convention such as Toggle or ONFI.

[0045] The AES engine 470 performs at least one of an encryption operation and a decryption operation on data input to the storage controller 400 using a symmetric-key algorithm. Although not shown in detail in the figures, the AES engine 470 includes an encryption module and a decryption module. According to an embodiment, the encryption module and the decryption module can be implemented as separate modules from each other or as one module.

[0046] FIG. 5 is a block diagram showing a schematic configuration of an example of a non-volatile memory included in a storage device according to an embodiment of the present invention. As shown in FIG. 5, the non-volatile memory 500 includes a memory cell array 510, an address decoder 520, a page buffer circuit 530, a data input / output circuit 540, a voltage generator 550, and a control circuit 560.

[0047] The memory cell array 510 is connected to the address decoder 520 via a plurality of string selection lines (SSLs), a plurality of word lines (WLs), and a plurality of ground selection lines (GSLs). Also, the memory cell array 510 is connected to the page buffer circuit 530 via a plurality of bit lines (BLs). The memory cell array 510 includes a plurality of memory cells connected to a plurality of word lines (WLs) and a plurality of bit lines (BLs). The memory cell array 510 is divided into a plurality of memory blocks (BLK1, BLK2,..., BLKz) each including memory cells. Also, each of the memory blocks (BLK1 to BLKz) is divided into a plurality of pages. According to an embodiment, the memory cell array 510 is formed in a two-dimensional array structure or a three-dimensional vertical array structure. The vertical (or three-dimensional) memory cell array will be described later with reference to FIG. 24.

[0048] The control circuit 560 receives a command (CMD) and an address (ADDR) from an external device (e.g., the storage controller 310 in FIG. 2), and controls the erase loop, program loop, and read operation of the non-volatile memory 500 based on the command (CMD) and the address (ADDR). Here, the program loop includes a program operation and a program verification operation, and the erase loop includes an erase operation and an erase verification operation. Here, the read operation includes a normal read operation and a data recovery read operation.

[0049] For example, the control circuit 560 generates a control signal (CON) for controlling the voltage generator 550 and a control signal (PBC) for controlling the page buffer circuit 530 based on the command (CMD), and generates a row address (R_ADDR) and a column address (C_ADDR) based on the address (ADDR). The control circuit 560 provides the row address (R_ADDR) to the address decoder 520 and provides the column address (C_ADDR) to the data input / output circuit 540.

[0050] The address decoder 520 is connected to the memory cell array 510 via a plurality of string selection lines (SSLs), a plurality of word lines (WLs), and a plurality of ground selection lines (GSLs). For example, during an erase / program / read operation, the address decoder 520 determines at least one of the plurality of word lines (WLs) as a selected word line in response to the row address (R_ADDR), and determines the remaining word lines among the plurality of word lines (WLs) except the selected word line as non-selected word lines.

[0051] Also, during an erase / program / read operation, the address decoder 520 determines at least one of the plurality of string selection lines (SSLs) as a selected string selection line in response to the row address (R_ADDR), and determines the remaining string selection lines as non-selected string selection lines. Also, during the erase / program / read operations, the address decoder 520 determines at least one of the plurality of ground selection lines (GSLs) as the selected ground selection line and the remaining ground selection lines as non-selected ground selection lines in response to the row address (R_ADDR).

[0052] The voltage generator 550 generates a voltage (VS) necessary for the operation of the non-volatile memory 500 based on the power supply voltage (PWR) and the control signal (CON). The voltage (VS) is supplied to the plurality of string selection lines (SSLs), the plurality of word lines (WLs), and the plurality of ground selection lines (GSLs) via the address decoder 520. Also, the voltage generator 550 generates an erase voltage (VERS) necessary for the erase operation based on the power supply voltage (PWR) and the control signal (CON).

[0053] For example, during the erase operation, the voltage generator 550 supplies the erase voltage (VERS) to the common source line and / or the bit line (BL) of the memory blocks (BLK1~BLKz), and supplies an erase allowable voltage (e.g., ground voltage) to all the word lines of one memory block via the address decoder 520. During the erase verification operation, the voltage generator 550 simultaneously supplies the erase verification voltage to all the word lines of one memory block or sequentially supplies it word line by word line via the address decoder 520.

[0054] For example, during the program operation, the voltage generator 550 supplies a program voltage to the selected word line and a program inhibit voltage to the non-selected word lines via the address decoder 520. During the program verification operation, the voltage generator 550 supplies a program verification voltage to the selected word line and a verification pass voltage to the non-selected word lines via the address decoder 520. Also, during the normal read operation, the voltage generator 550 supplies a read voltage to the selected word line and a read pass voltage to the non-selected word lines via the address decoder 520. Also, during the data recovery read operation, the voltage generator 550 applies a read voltage to the word lines adjacent to the selected word line via the address decoder 520, and applies a recovery read voltage to the selected word line.

[0055] The page buffer circuit 530 is connected to the memory cell array 510 via a plurality of bit lines (BL). The page buffer circuit 530 includes a plurality of page buffers. In one embodiment, one bit line is connected to one page buffer. In other examples, two or more bit lines are connected to one page buffer. The page buffer circuit 530 stores the write data (DAT) programmed into the memory cell array 510 or stores the read data (DAT) sensed from the memory cell array 510. That is, the page buffer circuit 530 operates as a write driver or a sense amplifier according to the operation mode of the non-volatile memory 500.

[0056] The data input / output circuit 540 is connected to the page buffer circuit 530 via a data line (DL). The data input / output circuit 540 provides data (DAT) to the memory cell array 510 via the page buffer circuit 530 in response to a column address (C_ADDR), or provides the data (DAT) output from the memory cell array 510 via the page buffer circuit 530 to the outside.

[0057] On the other hand, although the non-volatile memory according to the embodiment of the present invention has been described based on a NAND flash memory, the non-volatile memory according to the embodiment of the present invention can be any non-volatile memory such as PRAM, RRAM, NFGM (Nano Floating Gate Memory), PoRAM, MRAM, FeRAM, etc.

[0058] FIG. 6 is a block diagram showing a schematic configuration of a non-volatile memory according to an embodiment of the present invention and a memory system including the same. As shown in FIG. 6, the memory system 600 includes a memory device 610 and a memory controller 620.

[0059] The memory system 600 supports a plurality of channels (CH1, CH2, …, CHm), and the memory device 610 and the memory controller 620 are connected via the plurality of channels (CH1~CHm). For example, the memory system 600 is implemented as a storage device such as UFS or SSD, and corresponds to the storage device 300 in FIG. 2.

[0060] The memory device 610 includes a plurality of non-volatile memories (NVM11, NVM12, …, NVM1n, NVM21, NVM22, …, NVM2n, NVMm1, NVMm2, …, NVMmn). For example, the non-volatile memories (NVM11~NVMmn) correspond to the non-volatile memories (320a, 320b, 320c) in FIG. 2. Each of the non-volatile memories (NVM11~NVMmn) is connected to one of the plurality of channels (CH1~CHm) via a corresponding way.

[0061] For example, the non-volatile memories (NVM11~NVM1n) are connected to the first channel (CH1) via ways (W11, W12, …, W1n), the non-volatile memories (NVM21~NVM2n) are connected to the second channel (CH2) via ways (W21, W22, …, W2n), and the non-volatile memories (NVMm1~NVMmn) are connected to the mth channel (CHm) via ways (Wm1, Wm2, …, Wmn). In an exemplary embodiment, each of the non-volatile memories (NVM11~NVMmn) is implemented as any memory unit operable by an individual command from the memory controller 620. For example, each of the non-volatile memories (NVM11~NVMmn) can be implemented as a chip or a die, but is not limited thereto.

[0062] The memory controller 620 transmits and receives signals to and from the memory device 610 via a plurality of channels (CH1 to CHm). For example, the memory controller 620 corresponds to the storage controller 310 in FIG. 2. For example, the memory controller 620 transfers commands (CMDa, CMDb, …, CMDm), addresses (ADDRa, ADDRb, …, ADDRm), and data (DATAa, DATAb, …, DATAm) to the memory device 610 via channels (CH1 to CHm), or receives data (DATAa to DATAm) from the memory device 610.

[0063] The memory controller 620 selects one of the non-volatile memories connected to the corresponding channel via each channel, and transmits and receives signals to and from the selected non-volatile memory. For example, the memory controller 620 selects the non-volatile memory (NVM11) from among the non-volatile memories (NVM11 to NVM1n) connected to the first channel (CH1). The memory controller 620 transfers a command (CMDa), an address (ADDRa), and data (DATAa) to the selected non-volatile memory (NVM11) via the first channel (CH1), or receives data (DATAa) from the selected non-volatile memory (NVM11).

[0064] The memory controller 620 transmits and receives signals to and from the memory device 610 in parallel via different channels. For example, while the memory controller 620 transfers a command (CMDa) to the memory device 610 via the first channel (CH1), it can transfer a command (CMDb) to the memory device 610 via the second channel (CH2).[[ID=!9]] For example, while the memory controller 620 receives data (DATAa) from the memory device 610 via the first channel (CH1), it can receive data (DATAb) from the memory device 610 via the second channel (CH2).

[0065] The memory controller 620 controls the overall operation of the memory device 610. The memory controller 620 transfers signals to channels (CH1 to CHm) to control each of the non-volatile memories (NVM11 to NVMmn) connected to the channels (CH1 to CHm). For example, the memory controller 620 transfers a command (CMDa) and an address (ADDRa) to the first channel (CH1) to control one selected from the non-volatile memories (NVM11 to NVM1n).

[0066] Each of the non-volatile memories (NVM11 to NVMmn) operates under the control of the memory controller 620. For example, the non-volatile memory (NVM11) programs data (DATAa) with the command (CMDa), address (ADDRa), and data (DATAa) provided to the first channel (CH1). For example, the non-volatile memory (NVM21) reads data (DATAb) with the command (CMDb) and address (ADDRb) provided to the second channel (CH2) and transfers the read data (DATAb) to the memory controller 620.

[0067] In FIG. 6, it is shown that the memory device 610 communicates with the memory controller 620 via "m" channels and the memory device 610 includes "n" non-volatile memories corresponding to each channel, but the number of channels and the number of non-volatile memories connected to one channel can be variously changed.

[0068] Hereinafter, embodiments of the present invention will be described in detail based on the case where the storage device is UFS. However, the present invention is not limited thereto, and the storage device can be embodied in various other forms such as an SSD.

[0069] FIG. 7 is a flowchart for explaining a time synchronization method according to an embodiment of the present invention. As shown in FIGS. 2 to 7, the storage device 300 notifies the host device 200 of the start of the time synchronization interval (step S210). Based on the notification of the start of the time synchronization interval, during the time synchronization interval, the host device 200 provides the time information of the host device 200 to the storage device 300 (step S310).

[0070] On the other hand, the storage device 300 notifies the host device 200 of the end of the time synchronization interval (step S220). On the other hand, based on the notification of the end of the time synchronization interval, in the host device 200, the provision of the time information of the host device 200 is stopped (step S320).

[0071] In one embodiment, as will be described later with reference to FIGS. 8 to 19, using a UFS protocol information unit (UPIU) according to the UFS standard, the storage device notifies the host device of the time synchronization interval, and the host device provides the time information of the host device to the storage device.

[0072] In other embodiments, as will be described later with reference to FIGS. 20 and 21, using the unipro attribute of the host device or the storage device according to the UFS standard, the storage device notifies the host device of the time synchronization interval, and the host device provides the time information of the host device to the storage device.

[0073] FIG. 8 is a diagram for explaining an example of a sequence of a time synchronization method according to an embodiment of the present invention. FIG. 8 shows first to sixth request UPIUs (REQ1 to REQ6) and first to sixth response UPIUs (RSP1 to RSP6) transferred between the host device 200 and the storage device 300 during the runtime interval of the storage device 300. Regarding the UFS protocol information unit (UPIU) according to the UFS standard, it will be described later with reference to FIG. 9 and the like.

[0074] As shown in FIG. 8, in step S11, the host device 200 transfers a first request UPIU (REQ1) to the storage device 300, In step S21, the storage device 300 transfers a first response UPIU (RSP1) corresponding to the first request UPIU (REQ1) to the host device 200.

[0075] In step S31, the storage device 300 determines the start (enter) of a time synchronization interval (TSI) that requires the time information of the host device 200.

[0076] In step S12, the host device 200 transfers a second request UPIU (REQ2) to the storage device 300, In step S22, the storage device 300 transfers a second response UPIU (RSP2) corresponding to the second request UPIU (REQ2) to the host device 200. Here, the storage device 300 sets the synchronization setting bit (SSB) included in the second response UPIU (RSP2) to a first value (for example, a value of "1") and notifies the host device from the storage device 300 of the start of the time synchronization interval (TSI).

[0077] In step S13, the host device 200 transfers a third request UPIU (REQ3) to the storage device 300, In step S23, the storage device 300 transfers a third response UPIU (RSP3) corresponding to the third request UPIU (REQ3) to the storage device 300. Here, based on the notification of the start of the time synchronization interval (TSI) by the second response UPIU (RSP2), the host device 200 transfers a third request UPIU (REQ3) including the time information (TI) of the host device 200 to the storage device 300. The storage device 300 sets the synchronization setting bit (SSB) included in the third response UPIU (RSP3) to the first value and notifies the host device that the time synchronization interval (TSI) is maintained.

[0078] In step S14, the host device 200 transfers a fourth request UPIU (REQ4) to the storage device 300, In step S24, the storage device 300 transfers a fourth response UPIU (RSP4) corresponding to the fourth request UPIU (REQ4) to the host device 200. Here, based on the notification of the maintenance of the time synchronization interval (TSI) by the third response UPIU (RSP3), the host device 200 transfers a fourth request UPIU (REQ4) including the time information (TI) of the host device 200 to the storage device 300. The storage device 300 sets the synchronization setting bit (SSB) included in the fourth response UPIU (RSP4) to a first value and notifies the host device 200 that the time synchronization interval (TSI) is maintained.

[0079] In step S32, the storage device 300 determines the end (exit) of the time synchronization interval (TSI) that requires the time information of the host device 200.

[0080] In step S15, the host device 200 transfers a fifth request UPIU (REQ5) to the storage device 300, In step S25, the storage device 300 transfers a fifth response UPIU (RSP5) corresponding to the fifth request UPIU (REQ5) to the host device 200. Here, the storage device 300 sets the synchronization setting bit (SSB) included in the fifth response UPIU (RSP2) to a second value (for example, a value of "0") and notifies the host device from the storage device 300 of the end of the time synchronization interval (TSI).

[0081] In step S16, the host device 200 transfers a sixth request UPIU (REQ6) to the storage device 300, In step S26, the storage device 300 transfers a sixth response UPIU (RSP6) corresponding to the sixth request UPIU (REQ6) to the host device 200. Here, based on the notification of the end of the time synchronization interval (TSI) by the fifth response UPIU (RSP3), the host device 200 transfers a sixth request UPIU (REQ6) that does not include the time information (TI) of the host device 200 to the storage device 300. The storage device 300 sets the synchronization setting bit (SSB) included in the sixth response UPIU (RSP6) to a second value and notifies the host device 200 that it is not the time synchronization interval (TSI).

[0082] In this way, the storage device 300 notifies the host device 200 of the time synchronization interval (TSI) by the start notification by the second response UPIU (RSP2) and the end notification by the fifth response UPIU (RSP5). The host device 200 provides the time information (TI) to the storage device 300 only during the time synchronization interval (TSI) determined by the storage device 300, thereby reducing the overhead of time information transfer and improving the performance of the storage device 300 and the system 100 including the same.

[0083] Hereinafter, embodiments of the present invention will be described centering on a system 100 in which the host device 200 and the storage device 300 communicate according to the USF standard. Matters not explicitly described in this specification comply with the USF standard, and the USF standard is incorporated by reference in its entirety or in part.

[0084] FIG. 9 is a diagram showing a UFS protocol information unit (hereinafter, UPIU) used in a time synchronization method according to an embodiment of the present invention. FIG. 9 shows a general format of the UPIU according to the UFS standard. The UPIU includes a plurality of fields, and FIG. 9 describes the byte numbers (0 to j + 3) and names for each field.

[0085] For example, the UPIU includes fields such as Transaction Type, Flags, LUN, Task Tag, IID, Command Set Type, Query Function / Task Manag.Function, Response, Total EHS Length(00h), Device Information, Data Segment Length, Transaction Specific Fields, Extra Header Segment(EHS)1 to Extra Header Segment(EHS)N, Header E2ECRC, Data Segment, and Data E2ECRC. For the description of each field, refer to the description published in the UFS standard.

[0086] Using the UPIU according to the UFS standard as shown in FIG. 9, the storage device 300 notifies the host device 200 of the Time Synchronization Interval (TSI), and the host device 200 provides the time information (TI) of the host device 200 to the storage device 300.

[0087] FIGS. 10 and 11 are diagrams showing an example of notification of the time synchronization interval of the time synchronization method according to an embodiment of the present invention. FIG. 10 shows the header portion of the response UPIU, and FIG. 11 shows an example of the format of the device information field (FLD1) included in the response UPIU of FIG. 10.

[0088] As shown in FIGS. 10 and 11, the first bit (B[0]) of the device information field (FLD1) has already been used in the USF standard for the purpose of the storage device 300 notifying the host device 200 that a specific event has occurred ("EVENT_ALERT"). When the first bit (B[0]) of the device information field (FLD1) has a value of "1", the host device 200 transfers the UPIU to the storage device 300 again for confirmation of the occurred event.

[0089] The second to eighth bits (B[1:7]) of the device information field (FLD1) are bits reserved by the USF standard. According to an embodiment of the present invention, one of the bits reserved by the UFS standard is used as a bit for notifying a time synchronization interval (TSI), that is, a synchronization setting bit (SSB) in FIG. 8. FIG. 11 shows an example in which the second bit (B[1]) is used as the synchronization setting bit (SSB). For example, when the second bit (B[1]) has a first value (for example, a value of "1"), it indicates the start of the time synchronization interval (TSI), and when the second bit (B[1]) has a second value (for example, a value of "0"), it indicates the end of the time synchronization interval (TSI).

[0090] As described with reference to FIGS. 8 to 11, among the bits included in the device information field (FLD1) of the response UPIU transferred from the storage device 300 to the host device 200, the synchronization setting bit (SSB) is set to the first value to notify the host device 200 from the storage device 300 of the start of the time synchronization interval (TSI). Also, the synchronization setting bit (SSB) included in the device information field (FLD1) of the response UPIU is set to the second value to notify the host device 200 from the storage device 300 of the end of the time synchronization interval (TSI).

[0091] FIGS. 12, 13a, and 13b are diagrams showing an example of providing time information of a time synchronization method according to an embodiment of the present invention. FIGS. 12, 13a, and 13b show a command UPIU as an example of a request UPIU transferred from the host device 200 to the storage device 300, but the embodiments of the present invention are not limited only to time information transfer using the command UPIU. The time information (TI) of the host device 200 can be transferred using a UPIU transferred from the host device 200 to the storage device 300, such as "DATA OUT UPIU" defined by the UFS standard.

[0092] FIG. 12 shows the format of a command UPIU that does not include the time information (TI) of the host device 200. That is, the command UPIU in FIG. 12 corresponds to the first request UPIU (REQ1), the second request UPIU (REQ2), and the sixth request UPIU (REQ6) in FIG. 8. As shown in FIG. 12, the request UPIU that does not include the time information (TI) does not include an extra header segment (EHS), and the value of the overall EHS length field (FLD2) is set to "00h".

[0093] FIG. 13a shows a command UPIU that includes the time information (TI) of the host device 200. That is, the command UPIU in FIG. 13a corresponds to the third request UPIU (REQ3), the fourth request UPIU (REQ4), and the fifth request UPIU (REQ5) in FIG. 8. As shown in FIG. 13a, the request UPIU that includes the time information (TI) includes an extra header segment (FLD3), and the value of the overall EHS length field (FLD2) indicates the length of the extra header segment (FLD3). FIG. 13a exemplifies that the extra header segment (FLD3) is 8 bytes, and the value of the overall EHS length field (FLD2) is set to "02h". The value of the overall EHS length field (FLD2) sets the data size transferred to the extra header segment (FLD3) in units of 4 bytes.

[0094] As shown in FIG. 13b, the extra header segment (FLD3) of the request UPIU, that is, bytes 32 to 39 of the request UPIU, includes the time information (TI) of the host device 200 corresponding to a predetermined time resolution. That is, the time information (TI) of the host device 200 is added to the extra header segment (EHS) of the request UPIU transferred from the host device 200 to the storage device 300, and the host device 200 can provide the time information (TI) to the storage device 300.

[0095] In this way, the time synchronization method according to the embodiment of the present invention and the system for performing the time synchronization method can further reduce the overhead of time information transfer by expanding the existing signal to transfer time information without using another signal for the transfer of time information.

[0096] FIG. 14 is a flowchart for explaining the time synchronization method according to the embodiment of the present invention. As shown in FIG. 14, set the time resolution of the time information (TI) of the host device 200 provided from the host device 200 to the storage device 300 (step S500). During the time synchronization interval (TSI), provide the time information (TI) of the host device 200 corresponding to the time resolution from the host device 200 to the storage device 300 (step S600).

[0097] In one embodiment, as described later with reference to FIGS. 15 to 19, the time resolution can be set using the UPIU according to the UFS standard. In other embodiments, as described later with reference to FIGS. 20 and 21, the time resolution can be set using the unipro attribute according to the UFS standard.

[0098] FIG. 15 is a diagram for explaining an example of the sequence of the time synchronization method according to the embodiment of the present invention, and FIGS. 16a, 16b, and 17 are diagrams showing an example of setting the time resolution of the time synchronization method according to the embodiment of the present invention. Steps S11, S21, S31, S12, S22, S13, and S23 performed during the runtime interval in FIG. 15 are the same as those described in FIG. 8 above, so duplicate explanations are omitted.

[0099] FIG. 15 shows a query request UPIU (QREQ) transferred from the host device 200 to the storage device 300 and a query response UPIU (QRSP) transferred from the storage device 300 to the host device 200 during an initialization interval or an idle interval of the storage device 300.

[0100] In step S10, the host device 200 transfers a query request UPIU (QREQ) to the storage device 300. In step S20, the storage device 300 transfers a query response UPIU (QRSP) corresponding to the query request UPIU (QREQ) to the host device 200. Here, the host device 200 includes the time resolution (HRSL) implemented in the host device 200 in the query request UPIU (QREQ), and the storage device 300 includes the time resolution (SRSL) supported by the storage device 300 in the query response UPIU (QRSP).

[0101] In this way, the time resolution of the time information (TI) of the host device 200 provided from the host device 200 to the storage device 300 can be set through the query request UPIU (QREQ) transferred from the host device 200 to the storage device 300 and the query response UPIU (QRSP) transferred from the storage device 300 to the host device 200.

[0102] FIGS. 16A, 16B, and 17 are diagrams showing an example of setting the time resolution of the time synchronization method according to an embodiment of the present invention. FIG. 16A shows the format of the query request UPIU transferred from the host device 200 to the storage device 300, and FIG. 16B shows the format of the query response UPIU transferred from the storage device 300 to the host device 200. FIG. 17 shows an example of the UFS attribute indicating the time resolution.

[0103] The UFS attribute indicating time resolution can be defined using the identification number (IDN) reserved in the UFS standard. For example, as shown in FIG. 17, the device time resolution attribute (bDeviceTimeResolution) is defined for the identification number (IDN) of 20h, and the host time resolution attribute (bHostTimeResolution) is defined for the identification number (IDN) of 21h.

[0104] Each of the device time resolution attribute (bDeviceTimeResolution) and the host time resolution attribute (bHostTimeResolution) has a size of 1 byte. The device time resolution attribute (bDeviceTimeResolution) can only be read from the storage device 300 to the host device 200 (Read Only), and the host time resolution attribute (bHostTimeResolution) can be read from the storage device 300 to the host device 200 and can also be written from the host device 200 to the storage device 300 (Read / Write).

[0105] Each of the device time resolution attribute (bDeviceTimeResolution) and the host time resolution attribute (bHostTimeResolution) includes bits (B[0] to B[3]) indicating the enable / disable of various time resolutions. By setting each bit value of the bits (B[0] to B[3]), time resolutions such as nanoseconds (ns), microseconds (us), milliseconds (ms), and seconds (s) are set.

[0106] Such device time resolution attribute (bDeviceTimeResolution) and host time resolution attribute (bHostTimeResolution) are included in the "Transaction Specific Fields" of the query request UPIU and the query response UPIU in FIGS. 16a and 16b according to the USF standard, and thus are transferred between the host device 200 and the storage device 300.

[0107] FIG. 18 is a diagram for explaining an example of a sequence of a time synchronization method according to an embodiment of the present invention. Steps S11, S21, S31, S12, S22, S13, and S23 performed during the runtime interval of FIG. 18 are the same as those described in FIG. 8 above, except for matters related to the transfer of time resolution, and thus redundant explanations are omitted.

[0108] As shown in FIG. 18, the second response UPIU (REQ2) and the third response UPIU (REQ3) include not only the aforementioned synchronization setting bit (SSB) but also the time resolution (SRSL) supported by the storage device 300. In the examples of FIGS. 15 to 17, the time resolution is set during the initialization interval or the idle interval of the storage device 300, whereas in the examples of FIGS. 18 and 19, the time resolution is set during the runtime interval of the storage device 300.

[0109] FIG. 19 is a diagram showing an example of setting the time resolution of the time synchronization method according to an embodiment of the present invention. FIG. 19 shows an example of the format of the device information field (FLD1) included in the response UPIU of FIG. 10.

[0110] As shown in FIGS. 10 and 19, the first bit (B[0]) of the device information field (FLD1) has already been used in the USF standard for the purpose of the storage device 300 notifying the host device 200 that a specific event has occurred (“EVENT_ALERT”). When the first bit (B[0]) of the device information field (FLD1) has a value of “1”, the host device 200 transfers the UPIU to the storage device 300 again for event confirmation.

[0111] The second to eighth bits (B[1:7]) of the device information field (FLD1) are bits reserved according to the USF standard. According to an embodiment of the present invention, among the bits reserved in the UFS standard, one bit can be used as a bit for notifying a time synchronization interval (TSI), that is, a synchronization setting bit (SSB) in FIG. 8. In addition, among the reserved bits, one or more bits can be used as bits for time resolution. FIG. 19 shows an example in which the second bit (B[1]) is used as the synchronization setting bit (SSB), and the third to sixth bits (B[2:5]) are used as bits for time resolution as described with reference to FIG. 17.

[0112] FIGS. 20 and 21 are diagrams for explaining an example of a sequence of a time synchronization method according to an embodiment of the present invention. FIGS. 20 and 21 show service primitives transferred between the host device 200 and the storage device 300 during the link layer idle interval of the storage device 300.

[0113] As shown in FIGS. 20 and 21, among the UniPro attributes of the host device 200 or the storage device 300 according to the UFS standard, the time information configuration attribute (TICNF), the time information enable attribute (TIEN), and the time information attribute (TIVL) can be set. The UniPro attribute of the host device 200 or the storage device 300 is stored in the registers (HREG, SREG) in FIG. 3.

[0114] The time information configuration attribute (TICNF) indicates the time resolution (RSL) and the update period (UPR) of the time information (TI) of the host device 200 provided from the host device 200 to the storage device 300. The time information enable attribute (TIEN) indicates the above-described time synchronization interval (TLI). The time information attribute (TIVL) indicates the time information (TI) of the host device 200.

[0115] FIG. 20 shows an example of performing a time synchronization method using the unipro attribute of the host device 200. As shown in FIG. 20, in step S51, the storage device 300 determines the start of a time synchronization interval (TSI) that requires the time information of the host device 200. In step S52, the storage device 300 transfers a first setting request service primitive (DME_PEER_SET.req1) indicating the start of the time synchronization interval (TSI) to the host device 200. The first setting request service primitive (DME_PEER_SET.req1) includes the time resolution (RSL) and update period (UPR) of the time information (TI), and a first value (ENABLE) indicating the start notification of the time synchronization interval (TSI).

[0116] In step S53, based on the first setting request service primitive (DME_PEER_SET.req1), the host device 200 sets the time information enable attribute to the first value. Also, based on the first setting request service primitive (DME_PEER_SET.req1), the host device 200 sets the time information configuration attribute (TICNF) to the time resolution (RSL) and update period (UPR) of the time information (TI).

[0117] The host device 200 refers to the value of the time information configuration attribute (TICNF) and stores the time information (TI) corresponding to the time resolution (RSL) in the time information attribute (TIVL). While the time information enable attribute (TIEN) has the first value (ENABLE), the host device 200 refers to the value of the time information configuration attribute (TICNF) and periodically updates the time information (TI) of the time information attribute (TIVL) according to the update period (UPR).

[0118] In step S54, the storage device 300 transfers an inquiry request service primitive (DME_PEER_GET.req) to request the time information (TI) of the host device 200, that is, the value of the time information attribute (TIVL), to the host device 200. In step S55, based on the query request service primitive (DME_PEER_GET.req), the host device 200 transfers a query response service primitive (DME_PEER_GET_cnf) including the value of the time information attribute (TIVL), that is, the time information (TI) of the host device 200, to the storage device 300.

[0119] In step S56, the storage device 300 determines the end (exit) of the time synchronization interval (TSI) that requires the time information of the host device 200. In step S57, the storage device 300 transfers a second setting request service primitive (DME_PEER_SET.req2) indicating the end of the time synchronization interval (TSI) to the host device 200. The second setting request service primitive (DME_PEER_SET.req2) includes a second value (DISABLE) indicating the end notification of the time synchronization interval (TSI).

[0120] In step S58, based on the second setting request service primitive (DME_PEER_SET.req2), the host device 200 sets the time information enable attribute (TIEN) to the second value (DISABLE). While the time information enable attribute (TIEN) is set to the second value (DISABLE), the host device 200 suspends the update of the time information (TI) of the time information attribute (TIVL).

[0121] FIG. 21 shows an example of performing a time synchronization method using the unipro attribute of the storage device 300. As shown in FIG. 21, in step S61, the storage device 300 determines the start (enter) of the time synchronization interval (TSI) that requires the time information of the host device 200.

[0122] In step S62, the storage device 300 sets the time information enable attribute (TIEN) to the first value (ENABLE). Also, the storage device 300 sets the time information configuration attribute (TICNF) to the time resolution (RSL) and update period (UPR) of the time information (TI).

[0123] In step S63, the host device 200 transfers a first query request service primitive (DME_PEER_GET.req1) for requesting the value of the time information enable attribute (TIEN) to the storage device 300. Also, the host device 200 requests the value of the time information configuration attribute (TICNF) by the first query request service primitive (DME_PEER_GET.req1).

[0124] In step S64, based on the first query request service primitive (DME_PEER_GET.req1), the storage device 300 transfers a first query response service primitive (DME_PEER_GET.cnf1) including the first value (ENABLE) of the time information enable attribute (TIEN) to the host device 200. Also, the storage device 300 transfers the value of the time information configuration attribute (TICNF), that is, the time resolution (RSL) and update period (UPR) of the time information (TI) by the first query response service primitive (DME_PEER_GET.cnf1).

[0125] In step S65, when the time information enable attribute (TIEN) included in the first query response service primitive (DME_PEER_GET.cnf1) has the first value (ENABLE), the host device 200 transfers a setting request service primitive (DME_PEER_SET.req) including the time information (TI) of the host device 200 to the storage device 300. The storage device 300 updates the value of the time information attribute (TIVL) to the time information (TI) of the host device 200 included in the setting request service primitive (DME_PEER_SET.req).

[0126] Steps S63, S64, and S65 are periodically repeated by an update period (UPR) during a time synchronization interval (TSI). In step S66, the storage device 300 determines the end of a time synchronization interval (TSI) when the time information of the host device 200 is required. In step S67, the storage device 300 sets a time information enable attribute (TIEN) to a second value (DISABLE).

[0127] In step S68, the host device 200 transfers a second query request service primitive (DME_PEER_GET.req2) to the storage device 300 to request a value of the time information enable attribute (TIEN). Also, the host device 200 requests a value of a time information configuration attribute (TICNF) via the second query request service primitive (DME_PEER_GET.req2).

[0128] In step S69, based on the second query request service primitive (DME_PEER_GET.req2), the storage device 300 transfers a second query response service primitive (DME_PEER_GET.cnf2) including the second value (DISABLE) of the time information enable attribute (TIEN) to the host device 200. When the time information enable attribute (TIEN) included in the second query response service primitive (DME_PEER_GET.cnf2) has the second value (DISABLE), the host device 200 aborts the transfer of the time information (TI) of the host device 200.

[0129] In this way, the storage device 300 sets the time information enable attribute (TIEN) to the first value (ENABLE) during the time synchronization interval (TSI) and to the second value (DISABLE) during intervals other than the time synchronization interval (TSI).

[0130] FIG. 22 is a diagram showing a time synchronization method according to an embodiment of the present invention. As shown in FIG. 22, the setting of synchronization conditions including synchronization enable / disable, time resolution, and update period, and the transfer of time information (TI) can be performed using various combinations of UPIU and unipro attributes.

[0131] In one embodiment, as described with reference to FIGS. 15 to 19, both the setting of synchronization conditions and the transfer of time information (TI) are performed using UPIU. In other embodiments, the setting of synchronization conditions is performed using UPIU, and the transfer of time information (TI) is performed using unipro attributes. Also, in other embodiments, as described with reference to FIGS. 21 and 22, both the setting of synchronization conditions and the transfer of time information (TI) are performed using unipro attributes.

[0132] FIG. 23 is a diagram for explaining an example of using time information by the time synchronization method according to an embodiment of the present invention. FIG. 23 shows an example of a host system log (Log) managed by the host device 200 and a ring buffer or device input / output (I / O) log managed by the storage device 300.

[0133] The host device 200 manages the time of operations or events (evt1 to evt9) of the host device 200 based on the time information (TI) of the host device 200. The storage device 300 manages the time and status (Status), i.e., success (Success) or failure (Fail), of commands (CMD) transferred from the host device 200 based on the time information of the storage synchronized with the time information (TI) of the host device 200 by the time synchronization method described above. The host device 200 queries the device input / output (I / O) log of the storage device 300 to obtain accurate time information at the time of error occurrence.

[0134] On the other hand, the storage device 300 efficiently performs various functions using the time synchronized with the time information (TI) of the host device 200. In one embodiment, when implementing an on-board debugging function that automatically stores and extracts information of the storage device 300 upon occurrence of a fatal error, the information storage time or dump time is stored in synchronization with the time information of the host device 200.

[0135] In one embodiment, the synchronized time information is efficiently used for operations related to the lifespan and reliability of the non-volatile memory device, such as retention monitoring enhancement by temperature monitoring, countermeasures for EPI (Erase to Program Interval), PTS (Program Time Stamp), and the like.

[0136] In one embodiment, the synchronized time information is efficiently used for operations related to performance, such as setting the data validity period, setting the background operation time, HID (Host Initiated Defrag), purge, and the like. Also, the synchronized time information is efficiently used as an input for machine running for pattern analysis, such as Scheduling, "Throttling Turbo Write", "Host-aware Performance Booster", and the like.

[0137] FIG. 24 is a circuit diagram showing an equivalent circuit of a memory block of a non-volatile memory device included in a storage device according to an embodiment of the present invention. As shown in FIG. 24, the memory block (BLKi) represents a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block (BLKi) are formed in a direction (D3) perpendicular to the substrate.

[0138] The memory block (BLKi) is connected between bit lines (BL1, BL2, BL3) and a common source line (CSL), and includes a plurality of cell strings, that is, a plurality of memory NAND strings (NS11 to NS33), which are repeatedly arranged in a first horizontal direction (D1) and a second horizontal direction (D2). Each of the plurality of memory NAND strings (NS11 to NS33) includes a string select transistor (SST), a plurality of memory cells (MC1, MC2,..., MC8), and a ground select transistor (GST). FIG. 24 shows that each of the plurality of memory NAND strings (NS11 to NS33) includes eight memory cells (MC2, MC2,..., MC8), but embodiments of the present invention are not limited thereto.

[0139] The string select transistor (SST) is connected to a corresponding string select line (SSL1, SSL2, SSL3). The plurality of memory cells (MC1, MC2,..., MC8) are respectively connected to corresponding gate lines (GTL1, GTL2,..., GTL8). The gate lines (GTL1, GTL2,..., GTL8) correspond to word lines, and a part of the gate lines (GTL1, GTL2,..., GTL8) corresponds to dummy word lines. The ground select transistor (GST) is connected to a corresponding ground select line (GSL1, GSL2, GSL3). The string select transistor (SST) is connected to a corresponding bit line (BL1, BL2, BL3), and the ground select transistor (GST) is connected to the common source line (CSL).

[0140] Word lines at the same height (for example, GTL1) are commonly connected, and the ground select lines (GSL1, GSL2, GSL3) and the string select lines (SSL1, SSL2, SSL3) are separable respectively. FIG. 24 shows a memory block (BLK) connected to eight gate lines (GTL1, GTL2,..., GTL8) and three bit lines (BL1, BL2, BL3), but embodiments of the present invention are not limited thereto.

[0141] FIG. 25 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention. As shown in FIG. 25, the electronic device 4000 includes an application processor 4100, a communication module 4200, a display / touch module 4300, a storage device 4400, and a buffer RAM 4500.

[0142] The application processor 4100 controls the overall operation of the electronic device 4000. The application processor 4100 executes applications that provide an Internet browser, games, videos, and the like. The communication module 4200 is embodied to control wired communication and / or wireless communication with the outside. The display / touch module 4300 is embodied to display data processed by the application processor 4100 or to receive data from a touch panel. The storage device 4400 is embodied to store user data. The storage device 4400 can be an eMMC, an SSD, or a UFS device.

[0143] The buffer RAM 4500 is embodied to temporarily store necessary data during the processing operation of the electronic device 4000. For example, the buffer RAM 4500 is a dynamic random access memory such as DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, or RDRAM.

[0144] The application processor 4100 includes a time information generator (TIGEN) that generates time information of the electronic device 4000. The storage device 4400 includes a time information manager (TIMNG) that synchronizes the time information of the storage device 4400 with the received time information based on the time information provided from the application processor 4100 corresponding to the host device 200 described above according to an embodiment of the present invention.

[0145] As described above, the time synchronization method according to the embodiment of the present invention and the system performing the time synchronization method can reduce the overhead of time information transfer and improve the performance of the storage device and the system including the same by providing time information from the host device to the storage device only during a time synchronization interval determined by the storage device. Also, the time synchronization method according to the embodiment of the present invention and the system performing the time synchronization method can further reduce the overhead of time information transfer by expanding an existing signal to transfer time information without using another signal for the transfer of time information.

[0146] Note that the present invention is not limited to the above-described embodiments. Various modifications can be made within the scope without departing from the technical scope of the present invention.

Industrial Applicability

[0147] The storage device and the system including the same according to the embodiment of the present invention can be suitably used for electronic devices such as, for example, memory cards, SSDs, eMMCs, UFSs, computers, laptop computers, mobile phones, smartphones, MP3 players, PDAs (Personal Digital Assistants), PMPs (Portable Multimedia Players), digital TVs, digital cameras, portable game consoles, navigation devices, wearable devices, IoT (internet of things) devices, IoE (internet of everything) devices, e-books, VR (virtual reality) devices, AR (augmented reality) devices, server systems, autonomous driving devices, and the like.

Explanation of Signs

[0148] 100 Storage system 200 Host device 210 Host processor 212, 252 Time information generator 220 Host memory 251 Device driver 253 Command generator 254 Response analyzer 256, 356 Data transfer manager 257, 357 Link layer 258, 358 PHY (physical layer) 300, 4400 Storage device 310 Storage controller 312 Time information manager 320a, 320b, 320c Non-volatile memory 330 Buffer memory 351 Device controller 352, 430 Time information manager 353 Response generator 354 Command analyzer 400 Storage controller 410 Processor 420 Memory 432 Timer 440 Host Interface 450 ECC Engine 460 Memory Interface 470 AES Engine 500 Non-volatile Memory 510 Memory Cell Array 520 Address Decoder 530 Page Buffer Circuit 540 Data Input / Output Circuit 550 Voltage Generator 560 Control Circuit 600 Memory System 610 Memory Device 620 Memory Controller 4000 Electronic Device 4100 Application Processor 4200 Communication Module 4300 Display / Touch Module 4500 Buffer RAM

Claims

1. A method for time synchronization between a host device and a storage device, comprising: in the storage device, determining a time synchronization interval that requires time information of the host device; notifying the host device from the storage device of the time synchronization interval; during the time synchronization interval, providing the time information of the host device from the host device to the storage device; in the storage device, synchronizing the time information of the storage device with the time information of the host device based on the time information of the host device. A time synchronization method characterized by comprising the above steps.

2. The step of notifying the time synchronization interval includes notifying the start of the time synchronization interval from the storage device to the host device, and notifying the end of the time synchronization interval from the storage device to the host device. The time synchronization method according to claim 1, characterized by including the above steps.

3. The step of providing the time information of the host device includes, based on the notification of the start of the time synchronization interval, during the time synchronization interval, providing the time information of the host device from the host device to the storage device, and based on the notification of the end of the time synchronization interval, in the host device, stopping the provision of the time information of the host device. The time synchronization method according to claim 2, characterized by including the above steps.

4. The host device and the storage device communicate according to the UFS (Universal Flash Storage) standard. The time synchronization method according to claim 1, characterized by this.

5. Using the UFS protocol information unit according to the UFS standard, notifying the host device from the storage device of the time synchronization interval, and providing the time information of the host device from the host device to the storage device. The time synchronization method according to claim 4, characterized by this.

6. Using the UniPro attribute of the host device or the storage device according to the UFS standard, notifying the host device from the storage device of the time synchronization interval, and providing the time information of the host device from the host device to the storage device. The time synchronization method according to claim 4, characterized by this.

7. The step of notifying the time synchronization interval includes setting a synchronization setting bit among the bits included in the device information field of a response UPIU (UFS Protocol Information Unit) transferred from the storage device to the host device to a first value, and notifying the host device from the storage device of the start of the time synchronization interval; The time synchronization method according to claim 4, further comprising setting the synchronization setting bit included in the device information field of the response UPIU to a second value, and notifying the host device from the storage device of the end of the time synchronization interval.

8. The step of providing the time information of the host device includes adding the time information of the host device to an extra header segment of a request UPIU transferred from the host device to the storage device, the time synchronization method according to claim 4.

9. The time synchronization method according to claim 4, further comprising setting a time resolution of the time information of the host device provided from the host device to the storage device via a query request UPIU transferred from the host device to the storage device and a query response UPIU transferred from the storage device to the host device.

10. The time synchronization method according to claim 4, further comprising setting a time information enable attribute indicating the time synchronization interval and a time information attribute indicating the time information of the host device among the uni-pro attributes of the host device according to the UFS standard.

11. The step of notifying the time synchronization interval includes transferring a first set request service primitive indicating the start of the time synchronization interval from the storage device to the host device; in the host device, setting the time information enable attribute to a first value based on the first set request service primitive; transferring a second set request service primitive indicating the end of the time synchronization interval from the storage device to the host device; In the host device, a step of setting the time information enable attribute to a second value based on the second setting request service primitive, the time synchronization method according to claim 10, characterized in that it includes this.

12. The time synchronization method according to claim 11, further characterized in that it further includes a step of periodically updating the value of the time information attribute while the time information enable attribute in the host device has the first value.

13. The step of providing the time information of the host device includes transferring an inquiry request service primitive for requesting the time information of the host device from the storage device to the host device, Based on the inquiry request service primitive, transferring an inquiry response service primitive including the value of the time information attribute from the host device to the storage device, the time synchronization method according to claim 11, characterized in that it includes this.

14. The time synchronization method according to claim 4, further characterized in that it further includes a step of setting a time information enable attribute indicating the time synchronization interval and a time information attribute indicating the time information of the host device among the uni-pro attributes of the storage device according to the UFS standard.

15. The step of notifying the time synchronization interval includes, in the storage device, setting the time information enable attribute to a first value during the time synchronization interval and to a second value during intervals other than the time synchronization interval, Transferring an inquiry request service primitive for requesting the value of the time information enable attribute from the host device to the storage device, Based on the inquiry request service primitive, transferring an inquiry response service primitive including the value of the time information enable attribute from the storage device to the host device, the time synchronization method according to claim 14, characterized in that it includes this.

16. The step of providing the time information of the host device includes, when the time information enable attribute included in the inquiry response service primitive has the first value, transferring a setting request service primitive including the time information of the host device from the host device to the storage device, In the storage device, a step of updating a value of the time information attribute with respect to time information of the host device included in the setting request service primitive, the time synchronization method according to claim 15, characterized by including this.

17. The time synchronization method according to claim 4, further including a step of setting a time information configuration attribute indicating a time resolution and an update period of time information of the host device provided from the host device to the storage device among unipro attributes of the host device or the storage device according to the UFS standard.

18. The time synchronization method according to claim 17, characterized by setting a value of the time information configuration attribute using a UPIU according to the UFS standard or a service primitive according to the UFS standard.

19. A storage device including a plurality of non-volatile memory devices, A host device for controlling the storage device, having In the storage device, determining a time synchronization interval in which time information of the host device is required, Notifying the host device from the storage device of the time synchronization interval, A system characterized by providing time information of the host device from the host device to the storage device during the time synchronization interval.

20. A time synchronization method between a host device and a storage device that communicate according to the UFS standard, In the storage device, a step of determining a time synchronization interval in which time information of the host device is required, Notifying the host device from the storage device of the start of the time synchronization interval, Based on the notification of the start of the time synchronization interval, during the time synchronization interval, a step of providing time information of the host device from the host device to the storage device, Notifying the host device from the storage device of the end of the time synchronization interval, Based on the notification of the end of the time synchronization interval, in the host device, a step of stopping the provision of time information of the host device, having Notifying the start and end of the time synchronization interval and providing time information of the host device using a UFS protocol information unit (UPIU) according to the UFS standard or unipro attributes of the host device or the storage device according to the UFS standard, the time synchronization method characterized by this.

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