Information processing device, packet control method, and packet control program

Abstract

To improve the performance of a packet routing.SOLUTION: Memories 11a, 11b, 11c distribute and store a plurality of pieces of routing information that respectively include a destination address range regulated by using a prefix length. Retrieval parts 12a, 12b designate a memory of an access destination on the basis of correspondence information 15 showing correspondence between a plurality of prefix lengths and the memories 11a, 11b, 11c, and respectively retrieve routing information corresponding to a destination address of a packet and an allocated prefix length. A switch 13 connects the memories 11a, 11b, 11c and the retrieval parts 12a, 12b, and accesses the different memories in parallel on the basis of access destinations designated by the retrieval parts 12a, 12b. A determination part 14 determines routing information having the maximum prefix length among pieces of routing information to be retrieved from the packet by using the retrieval parts 12a, 12b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing device, a packet control method, and a packet control program. [Background technology]

[0002] Routers perform routing by referencing a routing table to determine the output destination of packets. The routing table stores routing information that associates destination address ranges with packet output destinations. Destination address ranges are sometimes expressed using prefix lengths. The portion of the bit string indicating the destination address that corresponds to the prefix length from the beginning is interpreted as the prefix that identifies the network. The portion after the prefix is the host portion that is assigned to nodes that belong to that network.

[0003] For example, 192.168.1.0 / 24 indicates that the first 24 bits of the 32-bit destination address are a prefix, representing the destination address range of 192.168.1.0 to 192.168.1.255. The router searches its routing table for routing information that has the destination address range to which the packet's destination address belongs. The router then forwards the packet according to the packet output destination indicated by the routing information found.

[0004] A routing table may contain multiple pieces of routing information with destination address ranges that are in an inclusive relationship. For example, a routing table may contain the routing information 192.168.1.0 / 24 and the routing information 192.168.1.128 / 26. The former indicates a destination address range of 192.168.1.0 to 192.168.1.255, while the latter indicates a destination address range of 192.168.1.128 to 192.168.1.191. Therefore, the former destination address range encompasses the latter destination address range.

[0005] In this case, the router may select routing information based on the Longest Prefix Match (LPM) rule, which selects the routing information with the longest prefix length when there is more than one routing information that matches the packet's destination address.

[0006] An address search system has been proposed that stores multiple address tables corresponding to multiple packet types in multiple memories and accesses the address table corresponding to the packet type of the received packet.An address search device has also been proposed that has multiple search units that perform longest match searches for IP (Internet Protocol) addresses.A router has also been proposed that stores destination addresses with different prefix lengths in different Content Addressable Memories (CAMs) and accesses multiple CAMs in parallel. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-151709 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-60970 [Patent Document 3] Japanese Patent Application Laid-Open No. 2002-330163 Summary of the Invention [Problem to be solved by the invention]

[0008] Under the longest prefix match rule, a router may retrieve multiple routing information with different prefix lengths from the same packet, so the implementation method of longest prefix match affects packet routing performance.

[0009] Storing all routing information in a single memory can cause memory access bottlenecks, delaying routing information lookups and reducing packet routing performance. One of the proposed techniques mentioned above addresses this by providing 32 memories for 32-bit destination addresses, storing routing information with different prefix lengths in different memories, and performing parallel lookups for 32 different routing information. However, providing as many memories as there are prefix lengths that may be used in the routing information and constantly searching for routing information with maximum parallelism increases the circuit size of the router.

[0010] Therefore, in one aspect, an object of the present invention is to improve the performance of packet routing. [Means for solving the problem]

[0011] In one aspect, an information processing device is provided that includes multiple memories, multiple search units, a switch, and a determination unit. The multiple memories store multiple pieces of routing information in a distributed manner, each of which includes a destination address range defined using a prefix length. The multiple search units specify a memory to access from the multiple memories based on correspondence information indicating the correspondence between the multiple prefix lengths and the multiple memories, and search for routing information corresponding to the packet's destination address and the assigned prefix length. The switch connects the multiple memories to the multiple search units, and accesses different memories in parallel based on the access destinations specified by the multiple search units. The determination unit determines the routing information with the longest prefix length from the routing information searched for from the packet using the multiple search units.

[0012] In one embodiment, a packet control method executed by a computer is provided. In another embodiment, a packet control program to be executed by a computer is provided. [Effects of the Invention]

[0013] On the one hand, packet routing performance is improved. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram illustrating an information processing apparatus according to a first embodiment. [Figure 2] FIG. 10 illustrates an information processing system according to a second embodiment. [Figure 3] FIG. 2 is a block diagram illustrating an example of hardware of a server device. [Figure 4] FIG. 2 is a block diagram illustrating an example of a software structure of the server device. [Figure 5] FIG. 1 is a block diagram illustrating an example of the structure and configuration of an FPGA device. [Figure 6] FIG. 10 is a diagram illustrating a first example of searching a routing table. [Figure 7] FIG. 10 is a diagram illustrating a second example of searching the routing table. [Figure 8] FIG. 10 is a block diagram illustrating an example of the structure of a table reference unit in an FPGA. [Figure 9] 10A and 10B are diagrams illustrating examples of a bitmap and a correspondence table. [Figure 10] FIG. 10 is a diagram illustrating an example of selecting a DRAM to which an entry is to be added; [Figure 11] 10 is a flowchart illustrating an example of a procedure for registering an entry in a control unit. [Figure 12] 10 is a flowchart illustrating an example of a procedure for registering an entry in an FPGA. [Figure 13] 10 is a flowchart illustrating an example of a procedure for searching an entry in an FPGA. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present embodiment will be described below with reference to the drawings. [First embodiment] A first embodiment will be described.

[0016] FIG. 1 is a diagram illustrating an information processing apparatus according to a first embodiment. The information processing device 10 of the first embodiment performs packet routing. The information processing device 10 may be called a computer or a router. The information processing device 10 may be a virtual machine or a general-purpose computer that executes application software.

[0017] The information processing device 10 may have a processor such as a central processing unit (CPU), a graphics processing unit (GPU), or a digital signal processor (DSP). The information processing device 10 may also have a hardware accelerator such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The information processing device 10 may also have a memory that stores a program. The program may include instructions to be executed by the processor. The program may also include circuit data for forming a desired logic circuit in the FPGA.

[0018] The information processing device 10 has a plurality of memories such as memories 11a, 11b, and 11c, a plurality of search units such as search units 12a and 12b, a switch 13, and a determination unit 14. The memories 11a, 11b, and 11c correspond to, for example, dynamic random access memories (DRAMs) connected to an FPGA and can be accessed in parallel from the FPGA. The search units 12a and 12b, the switch 13, and the determination unit 14 are, for example, circuit areas formed in the FPGA. The search units 12a and 12b operate based on correspondence information 15. The correspondence information 15 may be stored in a memory. The correspondence information 15 is stored, for example, in a memory included in the FPGA.

[0019] However, the memories 11a, 11b, and 11c may be other types of memories such as SRAM (Static Random Access Memory). The search units 12a and 12b and the determination unit 14 may be processors or processor cores, or may be circuit areas included in an ASIC.

[0020] The memories 11a, 11b, and 11c store a plurality of pieces of routing information in a distributed manner. One piece of routing information is stored in one of the memories. Each memory may store a routing table that stores routing information as entries.

[0021] Each piece of routing information includes a destination address range defined using a prefix length and a packet output destination. The destination address range may be written using CIDR (Classless Inter Domain Routing) notation. The destination address range includes, for example, a prefix corresponding to a network address and a prefix length. In IPv4, the destination address is 32 bits, and the prefix length is any value from 0 to 32. In IPv6, the destination address is 128 bits, and the prefix length is any value from 0 to 128. The packet output destination may include the address of the forwarding destination router and may also include an output port number.

[0022] Multiple routing information may contain routing information with different prefix lengths and inclusive destination address ranges. For example, 192.168.1.0 / 24 includes 192.168.1.128 / 26, 192.168.2.0 / 24 includes 192.168.2.128 / 26, and 192.168.2.128 / 26 includes 192.168.2.160 / 28. Under the longest prefix match rule, if the destination address of a packet belongs to the destination address range of two or more routing information, the packet will be processed based on the routing information with the longest prefix length. 0.0.0.0 / 0 indicates the default route to which all packet destination addresses belong.

[0023] The search units 12a and 12b search in parallel for routing information of different prefix lengths from the destination address of the same packet based on the correspondence information 15. The correspondence information 15 indicates the correspondence between multiple prefix lengths and multiple memories. For example, the correspondence information 15 indicates, for a certain prefix length, the memory that stores the routing information of that prefix length. It is preferable that routing information of the same prefix length be stored in the same memory. One memory may store routing information of two or more prefix lengths. It is preferable that the number of memories is at least one more than the number of search units.

[0024] The search units 12a and 12b are assigned prefix lengths to be handled by them, respectively. Different prefix lengths are dynamically assigned to the search units 12a and 12b, for example, from among prefix lengths in use in the memories 11a, 11b, and 11c. If the number of prefix lengths in use is greater than the number of search units, the search units 12a and 12b may be assigned with a higher priority from the larger prefix lengths. In this case, the search units 12a and 12b may each search for routing information multiple times for the same packet. Searches for unused prefix lengths may be skipped. The prefix lengths in use may be determined based on the correspondence information 15, or may be determined from other information such as a bitmap.

[0025] Search units 12a and 12b identify memories corresponding to the assigned prefix lengths based on correspondence information 15 and specify the memories to be accessed to switch 13. Search units 12a and 12b search in parallel for routing information corresponding to the packet destination address and the assigned prefix length from the memories to be accessed. Search units 12a and 12b output the search results for the routing information to determination unit 14.

[0026] The location in the routing table where routing information is stored may be determined based on the destination address range of the routing information. In this case, the search units 12a and 12b may read out the routing information by specifying an entry address that indicates the location in the routing table. For example, the prefix of the destination address is calculated by masking all bits after the prefix length in the destination address of the packet with 0. The entry address is calculated from the hash value of the calculated prefix.

[0027] The switch 13 connects multiple memories to multiple search units. Each search unit can access any of the memories via the switch 13. The switch 13 accesses different memories in parallel based on the access destinations specified by the search units 12a and 12b. For example, if the search unit 12a specifies the memory 11a and the search unit 12b specifies the memory 11c, the switch 13 enables the search unit 12a to access the memory 11a and the search unit 12b to access the memory 11c in parallel. The switch 13 may be a crossbar switch that dynamically forms an occupied communication path by switching on / off the intersections between the communication lines of the memories 11a, 11b, and 11c and the communication lines of the search units 12a and 12b.

[0028] When the search units 12a and 12b specify an entry address, the switch 13 transmits the entry address and a read signal to the memory to be accessed, receives the routing table entry indicated by the entry address from the memory to be accessed, and transfers the read entry to the search units 12a and 12b.

[0029] The determination unit 14 determines, according to the longest prefix match rule, the routing information with the longest prefix length among the routing information retrieved from the same packet using the search units 12a and 12b. The packet is processed according to the packet output destination indicated by the determined routing information. If no routing information corresponding to the packet's destination address is found and untried prefix lengths remain, the determination unit 14 may cause the search units 12a and 12b to search for routing information with other prefix lengths.

[0030] As described above, the information processing device 10 of the first embodiment stores routing information with different prefix lengths in multiple memories. This reduces the risk of memory access becoming a bottleneck and delaying routing information searches compared to when all routing information is stored in a single memory. Furthermore, multiple search units search for routing information with different prefix lengths in parallel for the same packet. This improves packet routing performance.

[0031] Furthermore, each search unit can access any of the memories via switch 13, and accesses the memory corresponding to the prefix length to be searched based on correspondence information 15. As long as the memory to be accessed is different, memory accesses by multiple search units are parallelized. This speeds up searches for routing information with less memory and fewer search units, and reduces the circuit size, compared to when a fixed number of memories and search units are provided for the number of prefix length candidates, such as 33 for IPv4 and 129 for IPv6.

[0032] The search units may be dynamically assigned different prefix lengths from among prefix lengths in use. This reduces unnecessary searches that search for unused prefix lengths. The number of search units may be less than the number of prefix length candidates. This reduces the circuit size. The search units may search for routing information in descending order of prefix length, and routing information with adjacent prefix lengths in this order may be stored in different memories. This reduces memory access collisions in which different search units access the same memory.

[0033] Furthermore, when the information processing device 10 attempts to add routing information of a new prefix length, it may select a memory that handles the new prefix length based on the correspondence information 15 before the addition. This prevents memory access collisions even after the new routing information is added. Furthermore, the number of memories may be greater than the number of search units. This makes it easier to create the correspondence information 15 so as to prevent memory access collisions.

[0034] [Second embodiment] Next, a second embodiment will be described. FIG. 2 illustrates an information processing system according to the second embodiment.

[0035] The information processing system of the second embodiment uses network function virtualization (NFV) technology to implement various network functions on a general-purpose computer. The information processing system also uses computer virtualization technology to allow multiple virtual network functions (VNFs) to coexist on the same general-purpose computer. The virtual network functions include a virtual load balancer, a virtual firewall, a virtual proxy server, a virtual router, a virtual switch, and the like. This information processing system may be an on-premise system owned by an organization, a system in a data center, or a so-called cloud system.

[0036] The information processing system includes a plurality of server devices such as server devices 31, 32, and 33 connected to a network 30. Each of the server devices 31, 32, and 33 is a server computer on which one or more virtual machines are arranged. The network 30 may include a LAN (Local Area Network) or the Internet. The server device 31 corresponds to the information processing device 10 of the first embodiment.

[0037] FIG. 3 is a block diagram illustrating an example of hardware of the server device. The server device 31 has a CPU 101, a RAM (Random Access Memory) 102, an HDD (Hard Disk Drive) 103, a GPU 104, an input interface 105, a medium reader 106, a communication interface 107, and an FPGA device 108, all of which are connected via a bus. The server devices 32 and 33 may have the same hardware as the server device 31.

[0038] The CPU 101 is a processor that executes program instructions. The CPU 101 loads programs and data stored in the HDD 103 into the RAM 102 and executes the programs. The CPU 101 can also transfer data from the RAM 102 to the FPGA device 108 and transfer data from the FPGA device 108 to the RAM 102. The server device 31 may have multiple processors. A collection of processors may be called a multiprocessor or simply a "processor."

[0039] The RAM 102 is a volatile semiconductor memory that temporarily stores programs executed by the CPU 101 and data used for calculations by the CPU 101. The server device 31 may have a type of memory other than RAM, or may have multiple types of memory.

[0040] The HDD 103 is a non-volatile storage that stores software programs such as an OS (Operating System), middleware, and application software, as well as data. The server device 31 may have other types of storage, such as a flash memory or an SSD (Solid State Drive), or may have multiple types of storage.

[0041] The GPU 104 is a processor that performs image processing in accordance with instructions from the CPU 101 and outputs image data to a display device 111 connected to the server device 31. The display device 111 is, for example, a CRT (Cathode Ray Tube) display, a liquid crystal display, an organic EL (Electro Luminescence) display, or a projector. An output device other than the display device 111, such as a printer, may be connected to the server device 31.

[0042] The input interface 105 receives an input signal from an input device 112 connected to the server device 31. The input device 112 is, for example, a mouse, a touch panel, or a keyboard. A plurality of types of input devices may be connected to the server device 31.

[0043] The medium reader 106 is a reading device that reads programs and data recorded on a recording medium 113. The recording medium 113 is, for example, a magnetic disk, an optical disk, or a semiconductor memory. Magnetic disks include flexible disks (FDs) and HDDs. Optical disks include compact discs (CDs) and digital versatile discs (DVDs).

[0044] The medium reader 106 may copy the programs and data read from the recording medium 113 to the RAM 102 or the HDD 103. The read programs may be executed by the CPU 101. The recording medium 113 may be a portable recording medium and may be used to distribute the programs and data. The recording medium 113 and the HDD 103 may be referred to as "computer-readable recording media."

[0045] The communication interface 107 is connected to the network 30 and communicates with the server devices 32 and 33 via the network 30. The communication interface 107 may be a wired communication interface connected to a wired communication device such as a switch or a router, or may be a wireless communication interface connected to a wireless communication device such as a base station or an access point.

[0046] The FPGA device 108 is a hardware accelerator that includes an FPGA. The FPGA is a programmable device that can reconfigure a logic circuit based on circuit data. The FPGA device 108 may also be called an expansion board. The FPGA device 108 executes some of the processing that can be executed by the CPU 101 on behalf of the CPU 101. The FPGA device 108 may be used to speed up routine and large-volume data processing.

[0047] In the second embodiment, the FPGA device 108 executes at least a part of the packet processing of the virtual router. The FPGA device 108 configures a logic circuit based on circuit data transferred from the RAM 102. The FPGA device 108 processes the packet using the configured logic circuit and outputs the processed packet to the RAM 102.

[0048] FIG. 4 is a block diagram showing an example of the software structure of the server device. The server device 31 has a plurality of virtual machines, such as virtual machines 121, 122, and 123, and a hypervisor 124. The server devices 32 and 33 may have the same software as the server device 31. The virtual machines 121, 122, and 123 may be virtual machines in the narrow sense that run a guest OS, or may be lightweight containers that do not run a guest OS. The CPU 101 executes a program included in the virtual machine image, thereby starting up the virtual machines 121, 122, and 123 on the server device 31.

[0049] The hypervisor 124 is control software that controls the virtual machines 121, 122, and 123. The server device 31 may execute a management OS instead of or together with the hypervisor 124. The hypervisor 124 manages the hardware of the server device 31 and allocates hardware resources to the virtual machines 121, 122, and 123. The hardware resources include the computing power of the CPU 101, the storage area of the RAM 102, the I / O bandwidth of the HDD 103, the communication bandwidth of the communication interface 107, and the like.

[0050] A load balancer 125 is installed in the virtual machine 121. A firewall 126 is installed in the virtual machine 122. A router 127 is installed in the virtual machine 123. The load balancer 125, the firewall 126, and the router 127 are examples of virtual network functions. However, the virtual machines 121, 122, and 123 may also be called virtual network functions.

[0051] The load balancer 125, the firewall 126, and the router 127 transmit packets to each other via the hypervisor 124. The load balancer 125, the firewall 126, and the router 127 also transmit and receive packets to and from the server devices 32 and 33 via the hypervisor 124 and the network 30.

[0052] The hypervisor 124 has a virtual router 128. The virtual router 128 is a software router that implements router functions using software that can be executed on a general-purpose computer. The virtual router 128 forwards packets sent and received by virtual network functions such as the load balancer 125, firewall 126, and router 127 based on header information such as the destination IP address.

[0053] However, if the large number of packets flowing into the virtual router 128 are processed mainly using the CPU 101 and RAM 102, there is a risk of CPU resource shortages. As a result, there is a risk of a decrease in the throughput and response of the packet processing of the virtual router 128. Therefore, the virtual router 128 uses the FPGA device 108 to offload the packet processing load from the CPU 101. The FPGA device 108 may be a general-purpose programmable device that does not have hardware specialized for packet processing.

[0054] The virtual router 128 transmits circuit data defining a logic circuit for packet processing to the FPGA device 108. The circuit data is created in advance by, for example, a user. The virtual router 128 transmits a command to the FPGA device 108 to set a routing table for searching for a packet forwarding destination. The routing information registered in the routing table may be generated autonomously by the virtual router 128 or may be created by the user. In this way, the virtual router 128 delegates packet routing according to the routing table to the FPGA device 108.

[0055] FIG. 5 is a block diagram illustrating an example of the structure and configuration of an FPGA device. The FPGA 108 has an FPGA 130 and a plurality of DRAMs such as DRAMs 137, 138, and 139. The DRAMs 137, 138, and 139 are volatile semiconductor memories connected to the FPGA 130 and accessible in parallel from the FPGA 130. If the number of search units described below is N, the number of DRAMs is N+1 or more.

[0056] By loading the circuit data into the FPGA 130 , a bus controller 131 , a virtual port unit 132 , an FPGA setting unit 133 , a header analysis unit 134 , a table reference unit 135 and a packet switch 136 are formed in the FPGA 130 .

[0057] The bus controller 131 controls communication via a bus between other hardware such as the CPU 101 and the FPGA device 108. The bus controller 131 may include a DMA (Direct Memory Access) controller that communicates directly with the RAM 102.

[0058] The virtual port unit 132 realizes a virtual port by performing packet processing equivalent to that of a communication port of a physical communication interface. For example, the virtual port unit 132 includes, for each virtual port, a receive buffer that temporarily stores packets received by the virtual port and a transmit buffer that temporarily stores packets transmitted from the virtual port. The virtual port unit 132 also reads packets from the receive buffer and passes them to the header analysis unit 134, and transmits the packets in the transmit buffer to an external location outside the FPGA device 108, such as the RAM 102.

[0059] The FPGA setting unit 133 receives a command from outside the FPGA device 108 and sets the FPGA device 108 in accordance with the command. The FPGA setting unit 133 may write routing table entries to the DRAMs 137, 138, and 139 in accordance with the command. The FPGA setting unit 133 may also rewrite control information stored in the table reference unit 135 in accordance with the command.

[0060] The header analysis unit 134 reads the received packet from the virtual port unit 132 and extracts header information from the packet. The header information includes a destination IP address and a tenant ID. The tenant ID is an identifier that identifies a user's virtual network, and is, for example, a VLAN (Virtual LAN) ID or a VXLAN (Virtual Extensible LAN) ID. The header analysis unit 134 outputs the header information to the table reference unit 135.

[0061] The table reference unit 135 searches the routing table stored in the DRAMs 137, 138, and 139 for an entry that matches the header information. The entry associates a range of destination IP addresses with forwarding destination information. The table reference unit 135 holds control information for efficiently searching for entries in the routing table. The control information includes a correspondence table showing the correspondence between prefix lengths used to express a range of destination IP addresses and DRAMs 137, 138, and 139. The control information also includes a bitmap that lists flags indicating prefix lengths currently in use in the routing table. The table reference unit 135 outputs the packet and forwarding destination information to the packet switch 136.

[0062] The packet switch 136 receives the packet and the destination information from the table reference unit 135. The packet switch 136 writes the packet into the receiving buffer of one of the virtual ports included in the virtual port unit 132 in accordance with the destination information.

[0063] The server device 31 has a control unit 140 outside the FPGA device 108. The control unit 140 is implemented using a CPU 101, a RAM 102, and a program. The control unit 140 has a correspondence table storage unit 141 and a routing control unit 142. The correspondence table storage unit 141 is implemented using, for example, a storage area of the RAM 102. The routing control unit 142 is implemented using, for example, the CPU 101 and a program.

[0064] Correspondence table storage unit 141 stores a correspondence table similar to that of table reference unit 135 . The routing control unit 142 accepts new routing information. The new routing information may be input by a user or may be generated autonomously by the virtual router 128. The routing control unit 142 refers to the correspondence table stored in the correspondence table storage unit 141 to determine the DRAM in which to register the new routing information. If the new routing uses an unused prefix length, the routing control unit 142 selects a DRAM to be associated with that prefix length and updates the correspondence table in the correspondence table storage unit 141. The routing control unit 142 notifies the FPGA setting unit 133 of the routing information and the DRAM number, causing the FPGA setting unit 133 to register the routing information in the routing table.

[0065] Here, the longest prefix match rule will be explained. Table reference unit 135 searches the routing table for an entry for the network to which the destination IP address of the packet belongs. However, the routing table may contain multiple entries with prefixes that have different prefix lengths and are in an inclusive relationship. Table reference unit 135 selects the entry with the longest prefix length from among the multiple entries that have the prefix to which the destination IP address of the packet belongs.

[0066] FIG. 6 is a diagram illustrating a first example of a search of the routing table. Routing table 170 is a routing table for IPv4, where the destination IP address is 32 bits. Routing table 170 includes entries 171, 172, and 173. Each entry includes prefix information, a next hop, and an interface. The prefix information is a range of destination IP addresses expressed as a prefix and a prefix length. The next hop is the IP address of the next node to which the packet is forwarded. The interface is the port number of the virtual port that outputs the packet.

[0067] The prefix information for entry 171 is 192.168.1.0 / 24. This prefix information indicates the address range of 192.168.1.0 to 192.168.1.255. The prefix information for entry 172 is 192.168.1.128 / 26. This prefix information indicates the address range of 192.168.1.128 to 192.168.1.191. Therefore, the address range of entry 171 encompasses the address range of entry 172. The prefix information for entry 173 is 0.0.0.0 / 0. Entry 173 is an entry that applies to all packets and indicates a default route. Packets that do not apply to other entries are forwarded according to the forwarding destination information indicated by entry 173.

[0068] An entry address indicating the location where routing information is registered in the routing table 170 is calculated from prefix information. For example, a certain number of lower bits of the hash value of the prefix are used as the entry address.

[0069] Table reference unit 135 reads an entry corresponding to a certain packet using an entry address calculated from the destination IP address of the packet. When searching for an entry with a certain prefix length, table reference unit 135 masks the destination IP address using a mask according to the prefix length and replaces the bits lower than the prefix with 0. This allows the prefix to be calculated assuming a certain prefix length.

[0070] The table reference unit 135 calculates a hash value of the masked destination IP address and extracts a certain number of low-order bits from the hash value to calculate an entry address. For the same packet, the table reference unit 135 calculates different entry addresses corresponding to different prefix lengths and reads multiple entries. Note that each entry may include a tenant ID in addition to prefix information, and the entry address of each entry may be calculated from the hash value of the prefix and tenant ID.

[0071] For simplicity, it is assumed that only three prefix lengths, 0, 24, and 26, are used in routing table 170. Packet 174 contains a destination IP address of 192.168.1.55. Packet 174 does not hit entry 172, but hits entries 171 and 173. Therefore, in accordance with the longest prefix match rule, table reference unit 135 uses the forwarding destination information of entry 171.

[0072] Packet 175 includes a destination IP address of 192.168.1.168. Packet 175 hits entries 171, 172, and 173. Therefore, table reference unit 135 adopts the forwarding destination information of entry 172. Packet 176 includes a destination IP address of 192.168.1.222. Packet 176 does not hit entry 172, but hits entries 171 and 173. Therefore, table reference unit 135 adopts the forwarding destination information of entry 171. Packet 177 includes a destination IP address of 10.25.227.115. Packet 177 does not hit entries 171 or 172, but hits entry 173. Therefore, table reference unit 135 adopts the forwarding destination information of entry 173.

[0073] FIG. 7 is a diagram illustrating a second example of searching the routing table. Routing table 180 is a routing table for IPv6 in which destination IP addresses are 128 bits. Routing table 180 includes entries 181, 182, and 183. The prefix information for entry 181 is 4001:db4::1:0 / 112. This prefix information indicates the address range of 4001:db4::1:0 to 4001:db4::1:ffff.

[0074] The prefix information of entry 182 is 4001:db4::1:c000 / 116. This prefix information indicates the address range of 4001:db4::1:c000 to 4001:db4::1:cfff. Therefore, the address range of entry 181 encompasses the address range of entry 182. The prefix information of entry 183 is :: / 0. Entry 183 is an entry that applies to all packets and indicates a default route.

[0075] For simplicity, it is assumed that only three prefix lengths, 0, 112, and 116, are used in routing table 180. Packet 184 includes a destination IP address of 4001:db4::1:bd0. Packet 184 does not hit entry 182, but hits entries 181 and 183. Therefore, in accordance with the longest prefix match rule, table reference unit 135 uses the forwarding destination information of entry 181.

[0076] Packet 185 includes a destination IP address of 4001:db4::1:c0bd. Packet 185 hits entries 181, 182, and 183. Therefore, table reference unit 135 adopts the forwarding destination information of entry 182. Packet 186 includes a destination IP address of 4001:db4::1:e048. Packet 186 does not hit entry 182, but hits entries 181 and 183. Therefore, table reference unit 135 adopts the forwarding destination information of entry 181. Packet 187 includes a destination IP address of 2004:db8::3864:0:0. Packet 187 does not hit entries 181 or 182, but hits entry 183. Therefore, table reference unit 135 adopts the forwarding destination information of entry 183.

[0077] Next, we will explain the table lookup unit 135 that implements the longest prefix match rule. The table lookup unit 135 searches for entries with different prefix lengths in parallel from the same packet. However, the degree of parallelism in the search is smaller than the number of prefix length candidates available in the routing information. There are 33 prefix length candidates for IPv4 and 129 for IPv6. Furthermore, the table lookup unit 135 selects only prefix lengths that are in use in the routing table as search targets, and skips searches for unused prefix lengths in the routing table.

[0078] FIG. 8 is a block diagram showing an example of the structure of a table reference unit in an FPGA. Table reference unit 135 has a bitmap storage unit 151, a correspondence table storage unit 152, an information input unit 153, a mask generation unit 154, a crossbar switch 155, a priority encoder 156, and a determination unit 157. Table reference unit 135 also has mask registers 161 and 162, mask units 163 and 164, hash units 165 and 166, and search units 167 and 168. Bitmap storage unit 151 and correspondence table storage unit 152 are, for example, registers or SRAMs included in FPGA 130.

[0079] The DRAMs 137, 138, and 139 correspond to the memories 11a, 11b, and 11c in the first embodiment. The search units 167 and 168 correspond to the search units 12a and 12b in the first embodiment. The crossbar switch 155 corresponds to the switch 13 in the first embodiment. The determination unit 157 corresponds to the determination unit 14 in the first embodiment.

[0080] The bitmap storage unit 151 stores a bitmap. A bitmap is a bit string whose length is one more than the number of bits in a destination IP address. The bitmap indicates whether each of multiple prefix lengths is used. If a prefix length is used in at least one entry in the routing table, the bit corresponding to that prefix length is 1. If a prefix length is not used in any entry, the bit corresponding to that prefix length is 0.

[0081] The correspondence table storage unit 152 stores a correspondence table. The correspondence table indicates the correspondence between a plurality of prefix lengths and a plurality of DRAMs. One DRAM corresponds to one prefix length. The correspondence table associates a prefix length with a DRAM number that identifies the DRAM that stores routing information for that prefix length.

[0082] Information input unit 153 receives header information from header analysis unit 134. When information input unit 153 receives new header information, it instructs mask generation unit 154 to generate a mask, and outputs the header information to mask units 163 and 164. Furthermore, in response to a request from determination unit 157, information input unit 153 instructs mask generation unit 154 to generate another mask.

[0083] Mask generation unit 154 generates a mask in response to an instruction from information input unit 153. Mask generation unit 154 references the bitmap stored in bitmap storage unit 151 and selects up to N prefix lengths in use, with the largest being given priority. The prefix lengths in use correspond to the digits of 1 bits included in the bitmap. N is the number of search units. When information input unit 153 instructs mask generation to generate another mask, mask generation unit 154 selects a prefix length in use that is smaller than the prefix length selected previously.

[0084] The mask generation unit 154 generates a mask corresponding to the selected prefix length. The mask is a bit string with the same length as the destination IP address. In the mask, the first bits corresponding to the prefix length are 1, and the bits below are 0. The mask generation unit 154 writes the generated mask to the mask registers 161 and 162.

[0085] The crossbar switch 155 is a switch that connects the search units 167 and 168 with the DRAMs 137, 138, and 139. There are N search units, and N+1 or more DRAMs. The crossbar switch 155 switches ON / OFF the intersections between the communication lines of the search units 167 and 168 and the communication lines of the DRAMs 137, 138, and 139 according to the DRAM numbers specified by the search units 167 and 168.

[0086] This creates an exclusive communication path between one search unit and one DRAM, allowing search units specifying different DRAM numbers to access the desired DRAMs in parallel. If search units 167 and 168 specify the same DRAM number, the crossbar switch 155 processes the access requests sequentially to resolve access conflicts. In this case, one search unit waits for the other search unit to complete its DRAM access.

[0087] Priority encoder 156 receives search results from search units 167 and 168. The search results indicate whether an entry matching the destination IP address is a hit or a miss, and in the case of a hit, the hit entry is included. Priority encoder 156 selects one search result based on the longest prefix match rule and outputs it to determination unit 157. If all search results are misses, priority encoder 156 outputs the search result indicating a miss to determination unit 157. If one or more search results are hits, priority encoder 156 outputs the search result with the longest prefix length among the hit search results to determination unit 157.

[0088] The determination unit 157 determines whether a search result of a hit is obtained for the header information of a certain packet. If a search result of a hit is obtained, the determination unit 157 outputs the transfer destination information included in the search result to the packet switch 136 and instructs the information input unit 153 to input the header information of the next packet. If a search result of a miss is obtained, the determination unit 157 instructs the information input unit 153 to search for an entry with a different prefix length.

[0089] The bitmap stored in bitmap storage unit 151 includes a bit corresponding to prefix length 0, and an entry indicating a default route is registered in the routing table. Therefore, there is at least one entry that corresponds to the header information. However, the bitmap does not have to include a bit corresponding to prefix length 0, and an entry indicating a default route may not be registered in the routing table. In this case, determination unit 157 may detect that there is no entry that corresponds to the header information, and output forwarding destination information indicating the default route to packet switch 136 instead of the forwarding destination information read from the routing table.

[0090] The mask registers 161 and 162 store the masks written from the mask generation unit 154. The mask registers 161 and 162 may further store information on prefix lengths. Mask unit 163 applies the mask stored in mask register 161 to the destination IP address included in the header information received from information input unit 153. The application of the mask is a bit-by-bit logical AND between two bit strings. Mask unit 163 notifies hash unit 165 of the masked destination IP address and prefix length. Similarly, mask unit 164 applies the mask stored in mask register 162 to the destination IP address. Mask unit 164 notifies hash unit 166 of the masked destination IP address and prefix length.

[0091] Hash unit 165 calculates a hash value of the masked destination IP address and notifies search unit 167 of the hash value, prefix, and prefix length. For example, CRC (Cyclic Redundancy Check) 32 is used to calculate the hash value. Similarly, hash unit 166 calculates a hash value of the masked destination IP address and notifies search unit 168 of the hash value, prefix, and prefix length.

[0092] The search unit 167 searches the correspondence table stored in the correspondence table storage unit 152 for a DRAM number corresponding to the prefix length. The search unit 167 also extracts a certain number of lower-order bits from the hash value as an entry address. The search unit 167 specifies the DRAM number and entry address to the crossbar switch 155 and reads one entry from the accessed DRAM. The search unit 167 checks whether the read entry includes the desired prefix and prefix length, and determines whether it is a hit or a miss. The search unit 167 outputs the search result to the priority encoder 156.

[0093] Similarly, the search unit 168 searches the correspondence table stored in the correspondence table storage unit 152 for a DRAM number corresponding to the prefix length. The search unit 168 specifies the DRAM number and the entry address to the crossbar switch 155 and reads one entry. The search unit 168 outputs the search result to the priority encoder 156. Note that the correspondence table may be duplicated in the search units 167 and 168 to resolve conflicts in access to the correspondence table.

[0094] FIG. 9 is a diagram showing an example of a bitmap and a correspondence table. Here, IPv6 packet routing is assumed. Bitmap 158 is stored in bitmap storage unit 151. Bitmap 158 includes 129 bits. The most significant bit corresponds to prefix length 128, and the least significant bit corresponds to prefix length 0. 1 indicates a prefix length in use, and 0 indicates an unused prefix length. Mask generation unit 154 extracts N bits of 1 from the most significant bit to the least significant bit. However, the most significant bit may correspond to prefix length 0, and the least significant bit may correspond to prefix length 128. In that case, mask generation unit 154 extracts N bits of 1 from the least significant bit to the most significant bit.

[0095] The correspondence table 159 is stored in the correspondence table storage unit 152. The correspondence table 159 associates a DRAM number with each of the 129 prefix lengths. DRAM number 1 indicates DRAM 137, DRAM number 2 indicates DRAM 138, and DRAM number 3 indicates DRAM 139. A DRAM number of -1 indicates that there is no corresponding DRAM. The DRAM number corresponding to an unused prefix length is -1.

[0096] Next, the generation of the correspondence table by the control unit 140 will be described. When registering new routing information in the routing table, the control unit 140 extracts the prefix length from the routing information and checks the correspondence table for the DRAM number corresponding to the prefix length. If a DRAM number other than -1 is assigned, the control unit 140 transmits the DRAM number and routing information to the FPGA setting unit 133. The FPGA setting unit 133 calculates an entry address from the routing information and registers the routing information at the location indicated by the DRAM number and entry address.

[0097] If the DRAM number corresponding to a prefix length is −1, a DRAM has not yet been allocated to that prefix length. In this case, the control unit 140 selects a DRAM to allocate to the prefix length and transmits the DRAM number and routing information to the FPGA setting unit 133. The FPGA setting unit 133 calculates an entry address from the routing information and registers the routing information at the location indicated by the DRAM number and entry address. The FPGA setting unit 133 also updates the bitmap 158 and the correspondence table 159.

[0098] FIG. 10 is a diagram showing an example of selecting a DRAM to which an entry is to be added. Here, it is assumed that the number of search units is N=3 and the number of DRAMs is N+1=4. Each time a new prefix length is used, the control unit 140 assigns a DRAM number to that prefix length. For prefix lengths up to the Nth prefix length, the control unit 140 assigns different DRAM numbers. For prefix lengths from the N+1th prefix length onwards, the control unit 140 selects a DRAM number using the following method.

[0099] First, the control unit 140 groups N prefix lengths in use in ascending order based on the correspondence table 159. The prefix lengths in use include the prefix length for which the current DRAM number is selected. The N prefix lengths in the same group are searched in parallel by N search units. The control unit 140 detects an unused DRAM number in the group to which the current prefix length belongs. Since the number of DRAMs is greater than N, two or more DRAM numbers are usually detected.

[0100] 10, the control unit 140 selects the DRAM number of prefix length 114. Prefix lengths 112, 114, and 116 belong to the same group, and DRAM number 4 is assigned to prefix length 112, and DRAM number 1 is assigned to prefix length 116. Therefore, the unused DRAM numbers are 2 and 3.

[0101] Next, the control unit 140 determines the other N groups of prefix lengths that include the current prefix length, taking into consideration the possibility that the group of prefix lengths searched in parallel may shift in the future. The control unit 140 then finally selects an unused DRAM number from the detected DRAM numbers, even within the shifted group. In the example of FIG. 10 , DRAM numbers 3 and 4 are unused in the group of prefix lengths 114, 116, and 119, and DRAM numbers 1 and 3 are unused in the group of prefix lengths 111, 112, and 114. Therefore, the control unit 140 assigns DRAM number 3 to prefix length 114.

[0102] By allocating DRAM for each prefix length using the above method, in principle, the N search units can access different DRAMs in parallel. By increasing the number of DRAMs beyond the number of search units, it becomes easier to allocate DRAM in a way that prevents access conflicts. However, if the number of prefix lengths in use increases, even the above method may not completely resolve access conflicts. In such cases, the following countermeasures can be considered, for example:

[0103] Even if a DRAM number conflicts temporarily within a parallel search group, the control unit 140 may ignore the conflict in the hope of updating the routing table in the future. Because the crossbar switch 155 executes access to the same DRAM in order, the processing of the search units 167 and 168 is executed normally, although there may be some delay. The control unit 140 may also reset the correspondence between prefix lengths and DRAM numbers and reassign DRAM numbers to each prefix length so that access conflicts do not occur. In this case, entries are transferred between the DRAMs 137, 138, and 139 according to the updated correspondence table 159.

[0104] Furthermore, the control unit 140 may intentionally shift the parallel search groups by inserting DRAM number 0, which indicates a dummy DRAM number, into the correspondence table 159. The maximum number of processing times that the search units 167, 168 can perform for the same packet is the number of prefix lengths in use divided by N times. If the number of prefix lengths in use is not a multiple of N, the maximum number of processing times does not increase even if one search unit pauses its entry search once. Therefore, a search unit whose DRAM number corresponding to the assigned prefix length is a dummy pauses its entry search once. The search unit outputs a miss search result without accessing any DRAM.

[0105] Next, the processing procedures of the FPGA 130 and the control unit 140 will be described. FIG. 11 is a flowchart showing an example of a procedure for registering an entry in the control unit. (S10) The routing control unit 142 receives new routing information to be registered and extracts the prefix length from the routing information.

[0106] (S11) The routing control unit 142 refers to the correspondence table and determines whether the prefix length extracted in step S10 is a prefix length that has already appeared in the routing table. If it is a prefix length that has already appeared, the routing control unit 142 identifies the DRAM number that corresponds to the prefix length, and the process proceeds to step S16. If it is not a prefix length that has already appeared, the process proceeds to step S12.

[0107] (S12) The routing control unit 142 groups the prefix lengths used into groups of N prefix lengths in ascending order, and determines which groups of prefix lengths are to be searched in parallel. (S13) The routing control unit 142 refers to the correspondence table and detects an unused DRAM number in the group that includes the current prefix length.

[0108] (S14) The routing control unit 142 selects one DRAM number to be associated with the current prefix length from the DRAM numbers detected in step S13, taking into consideration the DRAM numbers of prefix lengths in use that are close to the current prefix length.

[0109] (S15) The routing control unit 142 records the selected DRAM number in the correspondence table. (S16) The routing control unit 142 transmits the new routing information to be registered and the selected DRAM number to the FPGA setting unit 133.

[0110] FIG. 12 is a flowchart showing an example of a procedure for registering an entry in an FPGA. (S20) The FPGA setting unit 133 receives the routing information and the DRAM number. (S21) The FPGA setting unit 133 extracts a prefix from the routing information, calculates a hash value of the prefix, and determines an entry address based on the hash value.

[0111] (S22) The FPGA setting unit 133 registers the routing information at the position indicated by the entry address in the routing table stored in the DRAM indicated by the DRAM number. (S23) The FPGA setting unit 133 extracts the prefix length of the routing information.

[0112] (S24) FPGA setting unit 133 determines whether the extracted prefix length is a prefix length that has already appeared in the routing table. Whether the prefix length is a prefix length that has already appeared may be determined from the bitmap stored in bitmap storage unit 151, or may be determined from the correspondence table stored in correspondence table storage unit 152. If the prefix length is a prefix length that has already appeared, entry registration is completed. If the prefix length is not a prefix length that has already appeared, processing proceeds to step S25.

[0113] (S25) The FPGA setting unit 133 records the DRAM number in the correspondence table in association with the prefix length extracted in step S23. (S26) The FPGA setting unit 133 rewrites the bit included in the bitmap, which corresponds to the prefix length extracted in step S23, from 0 to 1.

[0114] FIG. 13 is a flowchart showing an example of a procedure for searching for an entry in an FPGA. (S30) The header analysis unit 134 analyzes the packet header and generates header information. (S31) The mask generation unit 154 initializes the repetition number to 0.

[0115] (S32) The mask generation unit 154 selects up to N prefix lengths in use from the bitmap stored in the bitmap storage unit 151 according to the repetition number. (S33) Mask generation unit 154 generates one mask from one selected prefix length, thereby generating up to N masks. Each mask is a bit string in which bits set to 1 continue for the prefix length, and the bits below that are 0. Mask generation unit 154 writes the different masks that have been generated to different mask registers.

[0116] (S34) Mask generation unit 154 adds 1 to the repetition number. The following steps S35 to S38 are executed with a maximum parallelism of N. Here, the processes of mask unit 163, hash unit 165, and search unit 167 will be described as representatives.

[0117] (S35) Mask unit 163 applies the mask stored in mask register 161 to the destination IP address. Specifically, mask unit 163 calculates the logical product of the destination IP address and the mask. Hash unit 165 calculates the hash value of the masked destination IP address.

[0118] (S36) The search unit 167 searches for the DRAM number corresponding to the prefix length. (S37) The search unit 167 determines the entry address from the hash value, specifies the DRAM number and the entry address to the crossbar switch 155, and reads out the entry identified by the DRAM number and the entry address.

[0119] (S38) The search unit 167 checks whether the prefix and prefix length of the read entry are as desired, and determines whether the search is a hit or a miss. (S39) The priority encoder 156 selects one search result from among the search results of the multiple search sections in accordance with the longest prefix match rule.

[0120] (S40) The determination unit 157 determines whether the selected search result indicates a hit. If it is a hit, the process proceeds to step S41, and if it is a miss, the process returns to step S32. (S41) The packet switch 136 transfers the packet of step S30 based on the transfer destination information included in the hit entry.

[0121] As described above, the server device 31 according to the second embodiment offloads the packet routing of the virtual router 128 to the FPGA device 108. This reduces the load on the CPU 101, suppresses performance degradation of other virtual network functions and application software, and improves packet routing performance.

[0122] The FPGA device 108 also stores routing table entries across multiple DRAMs according to prefix length. This reduces the risk of DRAM access becoming a bottleneck and delaying entry searches. Multiple search units also search for entries with different prefix lengths in parallel for the same packet. This improves the performance of entry searches for the longest prefix match rule.

[0123] Furthermore, the search units search for entries by narrowing down the search to prefix lengths present in the routing table. The search units dynamically identify the DRAMs corresponding to the prefix lengths they are responsible for from the correspondence table, and access the DRAMs in parallel via the crossbar switch 155. This allows the FPGA device 108 to implement entry searches with fewer DRAMs and fewer search units, reducing the circuit size, compared to when fixed pairs of search units and DRAMs are prepared for the number of prefix length candidates.

[0124] Furthermore, the control unit 140 dynamically allocates DRAM to a new prefix length each time an entry for that prefix length is registered. At this time, the control unit 140 selects a DRAM to allocate to the new prefix length so that there is no conflict in the DRAM to be accessed among the combinations of prefix lengths searched in parallel. This allows the performance of entry search to be maintained even when the routing table is updated. [Explanation of symbols]

[0125] 10. Information processing equipment 11a, 11b, 11c Memory 12a, 12b Search section 13 Switch 14 Judgment section 15 Compatibility Information

Claims

1. a plurality of memories for storing, in a distributed manner, a plurality of pieces of routing information each including a destination address range defined using a prefix length; a plurality of search units that designate a memory to be accessed from among the plurality of memories based on correspondence information indicating correspondence between a plurality of prefix lengths and the plurality of memories, and search for routing information corresponding to a destination address of a packet and an assigned prefix length; a switch that connects the plurality of memories to the plurality of search units and accesses different memories in parallel based on the access destinations specified by the plurality of search units; a determination unit that determines routing information with the longest prefix length from among the routing information searched for from the packet using the plurality of search units; An information processing device having the above.

2. The plurality of search units are assigned different prefix lengths from among prefix lengths used in the plurality of pieces of routing information.

2. The information processing device according to claim 1.

3. The number of search sections is less than the number of prefix lengths available for routing information.

2. The information processing device according to claim 1.

4. the plurality of search units search for routing information with priority given to a larger prefix length; Among the prefix lengths used in the plurality of pieces of routing information, routing information having prefix lengths adjacent to each other in descending order of prefix length is stored in different memories.

2. The information processing device according to claim 1.

5. The method further includes a control unit that, when adding new routing information having an unused prefix length, selects a memory to be associated with the unused prefix length based on the correspondence between prefix lengths in use and the plurality of memories.

2. The information processing device according to claim 1.

6. The number of memories is greater than the number of search units.

2. The information processing device according to claim 1.

7. Identifying, from among a plurality of memories that store a plurality of pieces of routing information in a distributed manner, a memory to be accessed that corresponds to the prefix length assigned to each of the plurality of search units, based on correspondence information that indicates the correspondence between the plurality of prefix lengths and the plurality of memories; searching in parallel for routing information corresponding to the destination address of the packet and the assigned prefix length using a switch that connects the plurality of search units and the plurality of memories and that accesses different memories in parallel based on the designation of the access destination; determining the routing information with the longest prefix length from among the routing information searched for from the packet using the plurality of search units; A packet control method in which processing is performed by a computer.

8. Identifying, from among a plurality of memories that store a plurality of pieces of routing information in a distributed manner, a memory to be accessed that corresponds to the prefix length assigned to each of the plurality of search units, based on correspondence information that indicates the correspondence between the plurality of prefix lengths and the plurality of memories; searching in parallel for routing information corresponding to the destination address of the packet and the assigned prefix length using a switch that connects the plurality of search units and the plurality of memories and that accesses different memories in parallel based on the designation of the access destination; determining the routing information with the longest prefix length from among the routing information searched for from the packet using the plurality of search units; A packet control program that causes a computer to execute processing.

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