Electro-optical devices and electronic equipment

Abstract

To reduce the resistance of wiring that supplies a power source potential to a light emitting device.SOLUTION: An electro-optical device includes: a light emitting device that emits light according to a current flowing between a pixel electrode and a common electrode; a plurality of pieces of power supply wiring 114 that are provided closer to the pixel electrode and supplied with a power source potential; a plurality of data lines; a data signal output circuit 50 that outputs data signals to the data lines; and conductive wiring 271 that is provided to overlap the data signal output circuit 50 in plan view and supplied with the power supply potential through a plurality of packaging terminals 20a. In plan view, a plurality of pieces of power supply wiring 116 are individually provided between the plurality of data lines and electrically connected with the conductive wiring 271.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] Electro-optical devices using, for example, OLEDs as light-emitting elements driven by current are known. OLED stands for Organic Light Emitting Diode. In these electro-optical devices, pixel circuits including transistors for passing current through the light-emitting elements are provided for each pixel of a displayed image. The transistors supply current to the light-emitting elements according to the brightness level. This causes the light-emitting elements to emit light at a brightness according to the current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-142440 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technique described in Patent Document 1 has a problem in that it is not possible to sufficiently reduce the resistance of the wiring that supplies the power supply potential in the pixel circuit. [Means for solving the problem]

[0005] An electro-optical device according to one aspect of the present disclosure includes a light-emitting element that emits light in response to a current flowing between a pixel electrode and a common electrode, a plurality of power supply wirings including a power supply wiring arranged near the pixel electrode and supplied with a power supply potential, a plurality of data lines arranged along a predetermined direction, a data signal output circuit that outputs a data signal to one of the plurality of data lines, and conductive wiring arranged to overlap the data signal output circuit in a planar view and supplied with the power supply potential via a plurality of mounting terminals, wherein, in a planar view, the plurality of power supply wirings are each arranged between the plurality of data lines and electrically connected to the conductive wiring. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view of an electro-optical device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device. [Figure 3] FIG. 2 is a circuit diagram illustrating a pixel circuit in the electro-optical device. [Figure 4] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 5] FIG. 2 is a plan view showing the arrangement of each element in the electro-optical device. [Figure 6] FIG. 2 is a plan view showing conductive wiring that supplies a high-level potential of a power supply in the electro-optical device. [Figure 7] 1 is a plan view showing conductive wiring and power supply wiring that supply a high-level potential of a power supply in an electro-optical device. [Figure 8] FIG. 2 is a plan view showing a common electrode in the electro-optical device. [Figure 9] FIG. 2 is a diagram showing the arrangement of data signal output circuits in an electro-optical device. [Figure 10] FIG. 2 is a diagram showing the arrangement of pixel circuits in an electro-optical device. [Figure 11] FIG. 2 is a plan view showing a wiring structure in the vicinity of a data signal output circuit. [Figure 12] FIG. 2 is a plan view showing a wiring structure in the vicinity of a data signal output circuit. [Figure 13] FIG. 13 is a partial cross-sectional view taken along line Pp in FIG. [Figure 14] FIG. 10 is a circuit diagram showing a pixel circuit of an electro-optical device according to a modified example. [Figure 15] FIG. 1 is a perspective view showing a head-mounted display using an electro-optical device. [Figure 16] FIG. 2 is a diagram illustrating an optical configuration of a head-mounted display. DETAILED DESCRIPTION OF THE INVENTION

[0007] Electro-optical devices according to embodiments of the present invention will be described below with reference to the drawings. Note that in each drawing, the dimensions and scale of each part are appropriately different from those of the actual parts. Furthermore, the embodiments described below are preferred specific examples, and therefore various technically preferable limitations are applied. However, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.

[0008] FIG. 1 is a perspective view showing the configuration of an electro-optical device according to an embodiment. The electro-optical device 10 is a microdisplay panel that displays images in, for example, a head-mounted display. The electro-optical device 10 includes pixel circuits including light-emitting elements and a drive circuit that drives the pixel circuits. The pixel circuits and the drive circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0009] The electro-optical device 10 is housed in a frame-shaped case 192 that opens to the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194. In the figure, the X direction indicates the direction in which the scanning lines extend in the electro-optical device 10, and the Y direction indicates the direction in which the data lines extend. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and indicates the emission direction of light emitted from the light-emitting element.

[0010] 2 is a block diagram showing the electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 is roughly divided into a power supply circuit 15, a control circuit 30, a data signal output circuit 50, a display area 100, and a scanning line driving circuit 120. In the display area 100, m rows of scanning lines 12 are arranged along the X direction in the figure, and n columns of data lines 14 are arranged along the Y direction so as to be electrically insulated from each other. Note that m and n are integers of 2 or more.

[0011] In the display area 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns. To distinguish the rows in the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from top to bottom in the figure. Similarly, to distinguish the columns in the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from left to right in the figure. Note that an integer i of 1 or more and m or less is used to generalize the scanning lines 12. Similarly, an integer j of 1 or more and n or less is used to generalize the data lines 14.

[0012] The control circuit 30 controls each unit based on video data Vid and a synchronization signal Sync supplied from the host device. The video data Vid specifies the gradation level of pixels in an image to be displayed, for example, by 8 bits for each of the three primary colors. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of video data.

[0013] In this embodiment, the pixels of an image to be displayed and the pixel circuits 110 in the display area 100 correspond one-to-one. The luminance characteristics at the gradation levels indicated by the video data Vid supplied from the host device do not necessarily match the luminance characteristics of the OLED included in the pixel circuit 110. Therefore, in order to cause the OLED to emit light at a luminance corresponding to the gradation levels indicated by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits in this embodiment and outputs the up-converted data as video data Vdata. Therefore, the 10-bit video data Vdata becomes data corresponding to the gradation levels specified by the video data Vid.

[0014] For up-conversion, a look-up table is used that stores in advance the correspondence between the 8 bits of input video data Vid and the 10 bits of output video data Vdata. Also, the control circuit 30 generates various control signals to control each section.

[0015] The scanning line driving circuit 120 is a circuit that outputs various signals to drive the pixel circuits 110 arranged in m rows and n columns, row by row, under control of the control circuit 30. For example, the scanning line driving circuit 120 supplies scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), and / Gwr(m) to the 1st, 2nd, 3rd, ..., (m-1), and mth scanning lines 12 in that order. Generally, the scanning signal supplied to the i-th scanning line 12 is represented as / Gwr(i).

[0016] The data signal output circuit 50 is a circuit that outputs a data signal of a potential corresponding to brightness from a node Out to pixel circuits 110 located in a row selected by the scanning line drive circuit 120. In detail, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 502. The selection circuit group 52 includes selection circuits 520 corresponding to each of the n columns, the first latch circuit group 54 includes first latch circuits L1 corresponding to each of the n columns, and the second latch circuit group 56 includes second latch circuits L2 corresponding to each of the n columns.

[0017] That is, a set of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, and a DA conversion circuit 502 is provided corresponding to each example. The jth column selection circuit 520 instructs the jth column first latch circuit L1 to select the jth column video data from the video data Vdata output from the control circuit 30, and the jth column first latch circuit L1 latches the video data Vdata in accordance with the instruction. The jth column second latch circuit L2 outputs the video data Vdata latched by the jth column first latch circuit L1 to the jth column DA conversion circuit 502 in accordance with control by the control circuit 30. The DA conversion circuit 502 in the jth column converts the 10-bit video data Vdata output from the second latch circuit L2 in the jth column into an analog data signal, and outputs it to the data line 14 in the jth column as a data signal.

[0018] In the figure, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are denoted as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n), respectively. In general, the potential of the data line 14 in the jth column is denoted as Vd(j).

[0019] The power supply circuit 15 generates power supply voltages and potentials for the control circuit 30, the scanning line driving circuit 120, and the data signal output circuit 50. The reference for zero voltage is the ground potential Gnd, but other than that, the terms potential and voltage are not used strictly in this description. In this description, the power supply potential refers to a potential that is approximately constant over time. Further, potentials Vel and Vct, which will be described later, that is, high and low potentials of the power supply in the light emitting elements, which will be described later, are supplied not from the power supply circuit 15 but from the external host device via the FPC board 194 .

[0020] 3 is a circuit diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the ith row and jth column as a representative. As shown in the figure, the pixel circuit 110 includes an OLED 130, p-channel transistors 121 and 122, and a capacitance element 140. The transistors 121 and 122 are, for example, MOS transistors, which are an abbreviation for Metal-Oxide-Semiconductor field-effect transistor.

[0021] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is optically reflective and optically transparent, and is therefore an example of a semi-reflective / semi-transmissive reflective layer. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby emitting white light.

[0022] In the case of a color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light exit side of the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and color filter before being viewed by the observer. Note that the optical resonator is not shown. Furthermore, when the electro-optical device 10 simply displays a monochromatic image with only light and dark, the color filter is omitted.

[0023] In the transistor 121 of the pixel circuit 110 in the i-th row and j-th column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply wiring 114 to which the potential Vel is supplied, and the drain node d is connected to the pixel electrode 131 which is the anode of the OLED 130. The power supply wiring 114 is formed along the X direction in the drawing, and is electrically connected to a power supply wiring 116 formed along the Y direction in the drawing.

[0024] In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, a connection between two or more elements in a semiconductor substrate via different wiring layers and contact holes, even if the connection is not direct.

[0025] A potential Vct is supplied to the common electrode 133, which functions as the cathode of the OLED 130, via the power supply wiring 118. Note that the anode of the OLED 130 is an individual electrode for each pixel circuit 110, whereas the cathode of the OLED 130 is an electrode common to all pixel circuits 110. For this reason, the common electrode 133 can be considered as the power supply wiring 118.

[0026] In the transistor 122 of the pixel circuit 110 in the ith row and jth column, the gate node is connected to the ith row scanning line 12 and the source node is connected to the jth column data line 14. In the capacitance element 140, one end is connected to the gate node g of the transistor 121 and the other end is connected to the power supply wiring 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and the source node s of the transistor 121. Note that the other end of the capacitance element 140 may be connected to another power supply wiring that supplies a potential other than Vel, as long as the potential is kept approximately constant.

[0027] For example, a so-called MOS capacitor formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer and a gate electrode layer of a transistor is used as the capacitive element 140. Note that the parasitic capacitance of the gate node g of the transistor 121 may be used as the capacitive element 140, or a so-called metal capacitor formed by sandwiching an insulating layer between different conductive layers on a semiconductor substrate may be used.

[0028] FIG. 4 is a timing chart for explaining the operation of the electro-optical device 10. As shown in FIG. In the electro-optical device 10, m scanning lines 12 are scanned one by one during a frame (V) period in the order of 1st, 2nd, 3rd, ..., mth rows. In detail, as shown in the figure, the scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) are sequentially and exclusively set to L level by the scanning line driving circuit 120 for each horizontal scanning period (H). In this embodiment, the periods during which adjacent scanning signals / Gwr(1) to / Gwr(m) are at L level are separated in time. Specifically, after scanning signal / Gwr(i-1) changes from L level to H level, the next scanning signal / Gwr(i) goes to L level after a period. This period corresponds to the horizontal blanking interval.

[0029] In this description, the period of one frame (V) refers to the period required to display one frame of the image specified by the video data Vid. If the length of the period of one frame (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Furthermore, the horizontal scanning period (H) is the time interval during which the scanning signals / Gwr(1) to / Gwr(m) sequentially go to the L level, but for convenience in the figure, the start timing of the horizontal scanning period (H) is shown approximately in the center of the horizontal blanking period.

[0030] When one of the scanning signals / Gwr(1) to / Gwr(m), for example the scanning signal / Gwr(i) supplied to the scanning line 12 in the ith row, goes low, the transistor 122 in the pixel circuit 110 in the ith row and jth column, for example, goes on. As a result, the gate node g of the transistor 121 in the pixel circuit 110 is electrically connected to the data line 14 in the jth column.

[0031] In this description, the "on state" of a transistor means that the source node and drain node of the transistor are electrically closed, resulting in a low impedance state, and the "off state" of a transistor means that the source node and drain node are electrically open, resulting in a high impedance state.

[0032] During the horizontal scanning period (H) when the scanning signal / Gwr(i) is at L level, the data signal output circuit 50 converts the grayscale levels of the pixels in the ith row, first column to the ith row, nth column indicated by the video data Vdata into analog potentials Vd(1) to Vd(n) and outputs them as data signals to the first to nth data lines 14. In terms of the jth column, the data signal output circuit 50 converts the grayscale level d(i,j) of the pixel in the ith row, jth column into an analog signal potential Vd(j) and outputs it as a data signal to the jth data line 14. In addition, during the horizontal scanning period (H) when the scanning signal / Gwr(i-1) one row before the scanning signal / Gwr(i) is at L level, the data signal output circuit 50 converts the gradation level d(i-1, j) of the pixel in the (i-1)th row and jth column into an analog signal potential Vd(j) and outputs it as a data signal to the jth data line 14.

[0033] The data signal of the potential Vd(j) is applied to the gate node g of the transistor 121 in the pixel circuit 110 in the ith row and jth column via the jth data line 14, and the potential Vd(j) is held by the capacitance element 140. Therefore, the transistor 121 passes a current to the OLED 130 according to the voltage between the gate node and the source node. Even when the scanning signal Gwr(i) goes to H level and the transistor 122 is turned off, the potential Vd(j) is held by the capacitance element 140, and therefore a current continues to flow through the OLED 130. Therefore, in the pixel circuit 110 at the i-th row and j-th column, the OLED 130 continues to emit light at a brightness corresponding to the voltage held by the capacitance element 140, i.e., the gradation level, until the period of one frame (V) has elapsed and the transistor 122 is turned on again and the voltage of the data signal is applied again.

[0034] Although the pixel circuit 110 in the ith row and jth column has been described here, the OLEDs 130 of the pixel circuits 110 in the ith row and other columns than the jth column also emit light at the luminance indicated by the video data Vdata. Also, the OLEDs 130 of the pixel circuits 110 in rows other than the i-th row emit light at the luminance indicated by the video data Vdata as the scanning signals / Gwr(1) to / Gwr(m) sequentially go to L level. Therefore, in the electro-optical device 10, in a period of one frame (V), the OLEDs 130 in all pixel circuits 110 from row 1, column 1 to row m, column n emit light at the luminance indicated by the video data Vdata, thereby displaying one frame of an image.

[0035] As described above, in the pixel circuit 110, the OLED 130 is provided between the power supply wiring 116 carrying a high power supply potential Vel and the power supply wiring 118 carrying a low power supply potential Vct, and the current flowing through the OLED 130 is controlled by the transistor 121. In this configuration, if the resistance of the wiring supplying the potential Vel is high, the potential Vel, which should be constant, becomes unstable due to a voltage drop, which is one factor that reduces the display quality. In this embodiment, the potential Vel is supplied from the external host device via the mounting terminal 20, as described above. Therefore, a configuration in this embodiment in which the potential Vel is supplied from multiple mounting terminals 20 to the pixel circuit 110 will be described below.

[0036] 5 is a plan view showing the arrangement of each element in the electro-optical device 10. The electro-optical device 10 is rectangular because it is diced from a wafer-shaped semiconductor substrate. Therefore, of the rectangular electro-optical device 10, the symbol for the top side is Ue, the symbol for the bottom side is De, the symbol for the left side is Le, and the symbol for the right side is Re. In the rectangular electro-optical device 10, the top side Ue and bottom side De are aligned along the X direction, which is the extension direction of the scanning lines 12, and the left side Le and right side Re are aligned along the Y direction, which is the extension direction of the data lines 14. In this description, a plan view refers to the electro-optical device 10 viewed from the opposite direction to the Z direction.

[0037] A scanning line driving circuit 120 is provided in the region between the display region 100 and the left side Le, and another scanning line driving circuit 120 is provided in the region between the display region 100 and the right side Re. The two scanning line driving circuits 120 have the same configuration and drive the scanning lines 12, etc. on the left and right sides. In a configuration in which the scanning line driving circuit 120 is provided on only one of the left and right sides, a signal delay occurs on the other side. In contrast, in a configuration in which the scanning line driving circuit 120 is provided on both the left and right sides, signal delay can be prevented. In the electro-optical device 10, a plurality of mounting terminals 20 for connection to one end of the FPC board 194 are provided along the bottom side De. In the area between the display area 100 and the plurality of mounting terminals 20, a data signal output circuit 50 and a control circuit 30 are provided in this order as seen from the display area 100. The length (width) of the display area 100 along the X direction is W1.

[0038] FIG. 6 is a diagram illustrating an outline of conductive wiring connected to the mounting terminals 20 among the components of the electro-optical device 10, which supplies the power supply potentials Vel and Vct to the periphery of the display region 100. In FIG. In this description, the "line" in data line and scanning line refers to a signal supply path. Also, the "wire" in power supply wiring and conductive wiring refers to one element of a signal path formed by patterning a wiring layer on a semiconductor substrate. In other words, the above-mentioned supply path using the "line" is formed by connecting multiple wires via contact holes or the like.

[0039] The conductive wiring 271 is part of a signal path that supplies the power supply potential Vel to the pixel circuit 110, and is T-shaped in plan view. In detail, the conductive wiring 271 includes a base portion 271a connected to a plurality of mounting terminals 20a located near the center among the mounting terminals 20 arranged along the X direction, and an expanded portion 271b that expands from the base portion 271a toward the display region 100. A portion of the conductive wiring 271 overlaps a portion of the data signal output circuit 50 in plan view. The length (width) of the expanded portion 271b of the conductive wiring 271 along the X direction is W2. The width W2 includes the width W1 as shown in the figure and is equal to or greater than the width W1. In addition, the upper side of the expanded portion 271b of the conductive wiring 271, that is, the side facing the display region 100, is denoted as Ade.

[0040] The conductive wiring 273 is part of a signal path that supplies the power supply potential Vct to the pixel circuit 110. The conductive wiring 273 includes a frame portion 273a that surrounds the display region 100 in a planar view, extension portions 273b and 273c, and a connection portion 273d, and is formed in a wiring layer separate from the conductive wiring 271. The extension portion 273b extends from the lower left end of the frame portion 273a along the Y direction, the extension portion 273c extends from the lower right end of the frame portion 273a along the Y direction, and the connection portion 273d connects the extension portions 273b and 273c and is connected to the mounting terminals 20b located to the left of the mounting terminals 20a. A portion of the connection portion 273d passes through a layer below the base portion 271a. Furthermore, a portion of the frame portion 273a of the conductive wiring 273 may overlap with a portion of the scanning line driving circuit 120 in a planar view.

[0041] 7 is a diagram illustrating an outline of power supply wiring 114, 116, and 261, which supply a power supply potential Vel from a conductive wiring 271 to the display area 100, among the components of the electro-optical device 10. In the figure, the power supply wiring 116 and 261 are formed by patterning a wiring layer lower than the uppermost layer among the wiring layers in the semiconductor substrate that constitutes the electro-optical device 10.

[0042] The power supply wiring 261 has a frame shape surrounding the display area 100 in plan view, and a part of the side of the frame along the bottom side De overlaps with the base 271a of the conductive wiring 271 in plan view. The power supply wiring 261 and the conductive wiring 271 are electrically connected by a plurality of contact holes (not shown) provided in this overlapping area.

[0043] In this embodiment, in the display region 100, the pixel circuits 110 are arranged at a pitch Px in the X direction and at a pitch Py in the Y direction. Therefore, the power supply wiring 114 is also arranged at a pitch Py, and the power supply wiring 116 is also arranged at a pitch Px. The power supply wiring 114 and 116 are arranged so as to surround a portion of the pixel circuit 110 in the display region 100 in a plan view. Although details are omitted, the power supply wiring 114 and 116 are electrically connected by contact holes.

[0044] The power supply wiring 116 extends below the display region 100 in the drawing so as to overlap a part of the conductive wiring 271 in a plan view. The power supply wiring 114 extends in the opposite direction to the X direction to a portion of the power supply wiring 261 that is along the left side Le, and also extends in the X direction to a portion of the power supply wiring 261 that is along the right side Re. Therefore, both left and right ends of the power supply wiring 114 overlap with the power supply wiring 261 in a plan view, and the power supply wiring 261 and the power supply wiring 114 are electrically connected to each other at the overlapping portions via contact holes. The power supply wiring 116 is opposite directionThe power supply wiring 116 is extended to a portion of the power supply wiring 261 along the upper side Ue toward the upper side Ue. Therefore, the upper end of the power supply wiring 116 overlaps with the power supply wiring 261 in a plan view, and the power supply wiring 261 and the power supply wiring 116 are electrically connected to each other at this overlapping portion via a contact hole. In addition, in a region where the power supply wiring 116 overlaps a part of the expansion portion 271b of the conductive wiring 271 in a plan view, the power supply wiring 116 and the expansion portion 271b are electrically connected via a contact hole, as will be described later.

[0045] In this manner, in this embodiment, the potential Vel supplied from an external host device via the multiple mounting terminals 20a is supplied to the power supply wiring 261 via the base 271a of the conductive wiring 271, and is supplied to the power supply wiring 116 via the expansion portion 271b. Unlike other wiring, the conductive wiring 271 is wide, and therefore wiring resistance is kept low. The potential Vel is supplied to the power supply wiring 114 along the X direction and the power supply wiring 116 along the Y direction via the conductive wiring 271, and is supplied in a mesh-like manner in plan view by the power supply wirings 114 and 116 in the display region 100. Therefore, according to this embodiment, the wiring resistance in the supply path of the potential Vel from the mounting terminal 20a to the display region 100 is reduced, and degradation of display quality due to voltage drop and voltage non-uniformity can be suppressed.

[0046] FIG. 8 is a plan view showing an outline of the common electrode 133 (power supply wiring 118) that supplies the power supply potential Vct, among the components of the electro-optical device 10. figure In the figure, the common electrode 133 is formed by patterning a transparent conductive layer provided above the wiring layer that forms the conductive wirings 271 and 273, and is provided so as to cover the display area 100 in a planar view. The common electrode 133 may also be a conductive layer that is semi-reflective and semi-transparent. The common electrode 133 is electrically connected to the frame portion 273a of the conductive wiring 273 at a portion that overlaps with the frame portion 273a in a planar view. As a result, a potential Vct is supplied to the common electrode 133 via the multiple mounting terminals 20b and the conductive wirings 273.

[0047] 9 is a plan view showing the arrangement of pixel circuits 110 in the display region 100. As shown in this figure, R pixel circuits 110, B pixel circuits 110, and G pixel circuits 110 are arranged along the X direction, and pixel circuits 110 of the same color are arranged along the Y direction. Therefore, focusing on any one column of data lines 14 corresponds to pixel circuits 110 of the same color. Note that one color is expressed by additive color mixing of RGB pixel circuits 110 adjacent in the X direction. For this reason, strictly speaking, the pixel circuits 110 should be called sub-pixel circuits, but in this embodiment, as described above, it is also possible to display a monochromatic image consisting of only light and dark, so we will not make any distinction and will refer to them as pixel circuits.

[0048] As described above, in the display area 100, the pixel circuits 110 are arranged at intervals of the pitch Px in the X direction, and therefore the data lines 14 are also arranged at intervals of the pitch Px. x That is, pitch P x In other words, the interval is the interval when three data lines 14 required to display one color are taken as one unit. In addition, in the figure, in order to distinguish the data lines 14 by color, the data line corresponding to the R pixel circuit 110 is denoted by the reference symbol 14_1, the data line corresponding to the G pixel circuit 110 is denoted by the reference symbol 14_2, and the data line corresponding to the B pixel circuit 110 is denoted by the reference symbol 14_3. When the colors are not distinguished, the data lines are denoted by the reference symbol 14 as described above.

[0049] FIG. 10 is a diagram showing the arrangement of elements in six adjacent columns of DA conversion circuits 502 in the data signal output circuit 50. As shown in FIG. In the figure, the DA conversion circuit 502 outputs a data signal from the node Out to the R data line 14_1 in order to distinguish between colors in the same way as the data lines 14. of The reference symbol of the DA converter circuit that outputs the signal is 502_1. Similarly, the data signal is output from the node Out to the data line 14_2 of G. ofThe code of the output DA conversion circuit is 502_2, and the data signal is output from the node Out to the data line 14_3 of B. of The code of the output DA conversion circuit is set to 502_3.

[0050] As shown in the figure, DA conversion circuits 502_1, 502_2, and 502_3 are arranged in a line along the Y direction in a range wider than the pitch Px and narrower than the pitch 3·Px. The node Out of the DA conversion circuit 502_1 is connected to the R relay line 14b_1 extending in the Y direction, separately from the R data line 14_1 extending in the opposite direction to the Y direction. Similarly, the node Out of the DA conversion circuit 502_2 is Going in the opposite direction of the Y direction A node Out of the DA conversion circuit 502_3 is connected to a G relay line 14b_2 extending in the Y direction, separately from the G data line 14_2. Going in the opposite direction of the Y direction Separately from the B data line 14_1, it is connected to the B relay line 14b_3 extending in the Y direction.

[0051] When laying out various elements, wiring, etc. on a semiconductor substrate, it is efficient to divide a certain range into blocks and arrange the blocks repeatedly. In addition, it is preferable that the relay lines 14b_1, 14b_2, and 14b_3 be connected to an inspection circuit (not shown) separately provided in the electro-optical device 10 so that defects can be inspected during the manufacturing process. For this reason, the relay lines 14b_1, 14b_2, and 14b_3 are redundant, but are extended in the Y direction as shown by the thick lines in Fig. 10 and connected to an inspection circuit provided, for example, below in the drawing. Note that "redundant" here means that the relay lines 14b_1, 14b_2, and 14b_3 shown by the thick lines are not necessary for transmitting data signals to the display area 100.

[0052] In such a configuration, for example, in the region of the data signal output circuit 50 where the DA conversion circuit 502_1 is provided, relay lines 14b_1 and 14b_2 are provided instead of the R data line 14_1 and the G data line 14_2. In this way, in the region where the data signal output circuit 50 is provided, the data lines 14 or the relay lines 14b are provided along the Y direction, and therefore, in the following, in the region where the data signal output circuit 50 is provided, the data lines 14 and the relay lines 14b will not be particularly distinguished from each other, and will be described as the former data lines 14.

[0053] 11 to 13 are diagrams for explaining specific wiring structures of the conductive wiring 271, the power supply wiring 116, and the data line 14 in a region including the side Ade of the conductive wiring 271. In detail, Fig. 11 and Fig. 12 are plan views showing the configurations of the data lines 14_1, 14_2, and 14_3, the power supply wiring 116, and the conductive wiring 271, and Fig. 13 is a partial cross-sectional view taken along line Pp in Fig. 12.

[0054] As described above, the electro-optical device 10 is formed on a semiconductor substrate, and in the semiconductor substrate, the layers used as conductive layers or wiring layers are, in order from the base material, a semiconductor layer 210, a gate electrode layer 220, a first wiring layer 230, a second wiring layer 240, a third wiring layer 250, a fourth wiring layer 260, and a fifth wiring layer 270, a total of seven layers, as shown in Fig. 13. Therefore, if a plan view of the wiring structure were to be expressed in a single diagram, it would become complicated and difficult to see. Therefore, of the seven wiring layers, Fig. 11 shows only the wiring patterns of the third wiring layer 250 and the fourth wiring layer 260, and Fig. 12 shows only the wiring patterns of the fourth wiring layer 260 and the fifth wiring layer 270.

[0055] 13, the capacitance element constituting the DA conversion circuit 502 is formed by sandwiching a gate insulating layer 280 between an electrode 211 made of a semiconductor layer 210 and an electrode 221 formed by patterning a gate electrode layer 220. The electrode 211 is formed by implanting impurity ions into a p-well region Well, for example. A region St is a trench for separating adjacent element regions.

[0056] The electrode 221 is connected to the wiring 232 through a contact hole Ct2 that opens in the first interlayer insulating layer 281. The first interlayer insulating layer 281 is an insulating layer provided between the gate electrode layer 220 and the first wiring layer 230. 2 is a wiring formed by patterning the first wiring layer 230. Although not specifically shown, the electrode 211 is connected to a wiring formed by patterning the first wiring layer 230, for example, via a contact hole that opens in the gate insulating layer 280 and the first interlayer insulating layer 281.

[0057] The wiring 232 is connected to the wiring 242 via a contact hole Ct4 that opens in the second interlayer insulating layer 282. The second interlayer insulating layer 282 is an insulating layer provided between the first wiring layer 230 and the second wiring layer 240. The wiring 242 is a relay wiring that is formed by patterning the second wiring layer 240. The wiring 242 is connected to the wiring 252 via a contact hole Ct6 that opens in the third interlayer insulating layer 283. The third interlayer insulating layer 283 is an insulating layer provided between the second wiring layer 240 and the third wiring layer 250. The wiring 253 is a relay wiring formed by patterning the third wiring layer 250, and is the power supply wiring 114 that supplies the potential Vel. That is, for convenience of explanation, the wiring 253 and the power supply wiring 114 have been described separately, but they are essentially the same.

[0058] 11 and 13, the wiring 252 is connected to the data line 14_1 through a contact hole Ct8 formed in the fourth interlayer insulating layer 284. The fourth interlayer insulating layer 284 is an insulating layer provided between the third wiring layer 250 and the fourth wiring layer 260. The data line 14_1 is formed by patterning the fourth wiring layer 260. In addition to the data line 14_1, the data lines 14_2 and 14_3 and the power supply wiring 116 are formed by patterning the fourth wiring layer 260. The power supply wiring 116 is provided between the data lines 14_1 and 14_2, between the data lines 14_2 and 14_3, and between the data lines 14_3 and 14_1.

[0059] Of these, the width of the power supply wiring 116 provided between the data lines 14_3 and 14_1, i.e., the width as the length in the X direction, is wider in terms of the circuit configuration than the widths of the other power supply wirings 116. Therefore, in the region where the data signal output circuit 50 is provided in a plan view, the pitch in the X direction at which the data lines 14_1, 14_2, 14_3 and the power supply wiring 116 are provided is unequal, but in the display region 100 at the top in the figure, the pitch (Px) is changed to be equal.

[0060] 12 and 13, the plurality of power supply wirings 116 are connected to the conductive wiring 271 via a plurality of contact holes, for example, contact holes Ct11, Ct12, Ct13, and Ct14, that open in the fifth interlayer insulating layer 285. The fifth interlayer insulating layer 285 is an insulating layer provided between the fourth wiring layer 260 and the fifth wiring layer 270. The conductive wiring 271 is formed by patterning the fifth wiring layer 270 as described above. In addition to the conductive wiring 271, a reflective layer is formed below the pixel electrodes 131 in the display area 100 by patterning the fifth wiring layer 270. Also, in Figure 13, the description of the layers above the conductive wiring 271 is omitted, but in reality, the light-emitting functional layer 132, common electrode 113 (power wiring 118), sealing layer, etc. that constitute the OLED 130 in the display area 100 are provided.

[0061] <Application examples and variations> The above-described embodiment can be modified or applied in various ways as follows.

[0062] In the display region 100, the power supply wirings 114 and 116 that supply the high power supply potential Vel may be multi-layered. For example, in the display region 100, the first wiring layer 230 may be patterned to form power supply wiring along the X direction, the second wiring layer 240 may be patterned to form mesh-like power supply wiring along the X and Y directions, the third wiring layer 250 may be patterned to form power supply wiring along the Y direction, and the fourth wiring layer 260 may be patterned to form mesh-like power supply wiring along the X and Y directions, and these power supply wirings may be electrically connected via contact holes.

[0063] In the electro-optical device 10 according to the embodiment described above, the transistor 121, the OLED 130, and the power supply wiring 118 are arranged in this order with respect to the power supply wiring 116. However, as shown in Fig. 14, the present invention is also applicable to a configuration in which the OLED 130, the transistor 121, and the power supply wiring 118 are arranged in this order. In this configuration, the anode of the OLED 130 serves as a common electrode and is connected to the power supply wiring 116, and the cathode of the OLED 130 serves as a pixel electrode and is connected to the power supply wiring 118 via the transistor 121. Therefore, in the configuration shown in Fig. 14, the wiring resistance of the power supply wiring 118 that supplies the low-level power supply potential Vct to the OLED 130 becomes an issue. In other words, the wiring resistance of the power supply wiring that supplies the power supply potential to the OLED 130 becomes an issue when it is the power supply wiring that supplies the potential closer to the pixel electrode of the OLED 130, i.e., not the common electrode, regardless of whether the power supply potential is high or low.

[0064] Furthermore, in the electro-optical device 10 according to the embodiment, the OLED 130 has been described as an example of a light-emitting element, but other light-emitting elements may be used. For example, an LED may be used as the light-emitting element. In the embodiment, the threshold voltage of the transistor 121 in the pixel circuit 110 is not compensated for, but the threshold voltage may be compensated for. The channel type of the transistors 121 and 122 is not limited to that in the embodiment.

[0065] <Electronic equipment> Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition displays. Therefore, a head-mounted display will be used as an example of the electronic device.

[0066] FIG. 15 is a diagram showing the appearance of a head-mounted display, and FIG. 16 is a diagram showing its optical configuration. First, as shown in Fig. 15, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to ordinary eyeglasses. Furthermore, as shown in Fig. 16, the head mounted display 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320 and behind the lenses 301L and 301R (below in the figure).

[0067] The image display surface of the electro-optical device 10L is disposed on the left side in FIG. 16. As a result, the image displayed by the electro-optical device 10L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed on the right side, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction.

[0068] In this configuration, a person wearing the head-mounted display 300 can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world. Furthermore, in this head-mounted display 300, when the electro-optical device 10L displays the image for the left eye and the electro-optical device 10R displays the image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0069] Electronic devices including the electro-optical device 10 can be applied to not only the head-mounted display 300, but also electronic viewfinders in video cameras and interchangeable lens digital cameras, personal digital assistants, display units of wristwatches, light bulbs of projection projectors, and the like.

[0070] <Additional Notes> From the above description, for example, preferred embodiments of the present disclosure can be understood as follows: Note that, in order to facilitate understanding of each embodiment, reference numerals in the drawings are written in parentheses for convenience, but this is not intended to limit the present invention to the embodiments shown in the drawings.

[0071] <Appendix 1> An electro-optical device (10) according to one aspect (Supplementary Note 1) of the present disclosure includes a light-emitting element (130) that emits light in response to a current flowing between a pixel electrode (131) and a common electrode (133), a plurality of power supply wirings (116) that are arranged near the pixel electrode (131) and supply a power supply potential (Vel), a plurality of data lines (14), a data signal output circuit (50) that outputs a data signal of a potential corresponding to the current to one of the plurality of data lines (14), and a conductive wiring (271) that is arranged to overlap the data signal output circuit (50) in a planar view and that is supplied with the power supply potential (Vel) via a plurality of mounting terminals (20a), and electric The source wiring (116) is provided between the plurality of data lines (14) in a plan view, and is electrically connected to the conductive wiring (271). According to this embodiment, the wiring resistance from the mounting terminal (20a) to the power supply wiring (116), to which the power supply potential (Vel) is supplied, is kept low.

[0072] <Appendix 2> In the specific example (Supplementary Note 2) of Supplementary Note 1, the plurality of data lines (14) and the plurality of power supply wirings (116) are made up of the same wiring layer (260). According to this embodiment, the data lines (14) are shielded by the power supply wirings (116), thereby preventing a decrease in display quality.

[0073] <Appendix 3> In the specific example of Appendix 1 or Appendix 2 (Appendix 3), multiple electric The power supply wiring (116) is electrically connected to the conductive wiring (271) through the contact holes (Ct11 to Ct14). According to this embodiment, the conductive wiring (271) is connected to a plurality of power supply wirings (116).

[0074] <Appendix 4> In a specific example (Supplementary Note 4) of any one of Supplementary Notes 1 to 3, the width (W2) of the conductive wiring (271) in a direction intersecting the extending direction of the plurality of data lines (14) at a portion overlapping with the data signal output circuit (50) in a plan view is equal to or greater than the width (W1) of the display region including the light-emitting elements. According to this embodiment, the wide conductive wiring 271 reduces resistance.

[0075] <Appendix 5> In a specific example (Supplementary Note 5) of any one of Supplementary Notes 1 to 4, the conductive wiring (271) is provided in an upper layer than the plurality of data lines (14). According to this aspect, the data lines (14) are covered and shielded by the conductive wiring (271), thereby suppressing a decrease in display quality. In addition, the conductive wiring (271) being above the data line (14) specifically means that the conductive wiring (271) is formed after the data line 14 is formed, and refers to the positional relationship when the semiconductor substrate material is the lowest layer in a cross-sectional view.

[0076] <Appendix 6> An electronic device according to a specific example (aspect 6) of any one of Supplementary Notes 1 to 5 includes the electro-optical device. [Explanation of symbols]

[0077] 10... electro-optical device, 12... scanning line, 14... data line, 100... display area, 110... pixel circuit, 114, 116... power supply wiring, 121, 122... transistor, 130... OLED (light-emitting element), 131... pixel electrode, 133... common electrode, 271... conductive wiring, Ct11 to Ct14... contact holes.

Claims

1. a light-emitting element that emits light in response to a current flowing between the pixel electrode and the common electrode; a plurality of power supply wirings including a power supply wiring provided near the pixel electrodes and supplied with a power supply potential; a plurality of data lines arranged along a predetermined direction; a data signal output circuit that outputs a data signal to one of the plurality of data lines; a conductive wiring provided so as to overlap the data signal output circuit in a plan view, the conductive wiring being supplied with the power supply potential via a plurality of mounting terminals; Including, In a plan view, the plurality of power supply wirings are respectively provided between the plurality of data lines and electrically connected to the conductive wirings; The plurality of data lines and the plurality of power supply lines are formed in the same wiring layer. Electro-optical device.

2. the plurality of power supply wirings are electrically connected to the conductive wirings via contact holes, respectively; The electro-optical device according to claim 1 .

3. a light-emitting element that emits light in response to a current flowing between the pixel electrode and the common electrode; a plurality of power supply wirings including a power supply wiring provided near the pixel electrodes and supplied with a power supply potential; a plurality of data lines arranged along a predetermined direction; a data signal output circuit that outputs a data signal to one of the plurality of data lines; a conductive wiring provided so as to overlap the data signal output circuit in a plan view, the conductive wiring being supplied with the power supply potential via a plurality of mounting terminals; Including, In a plan view, the plurality of power supply wirings are respectively provided between the plurality of data lines and electrically connected to the conductive wirings; the plurality of power supply wirings are electrically connected to the conductive wirings via contact holes, respectively; Electro-optical device.

4. In a portion of the conductive wiring that overlaps with the data signal output circuit in a plan view, a width in a direction intersecting with an extension direction of the plurality of data lines is equal to or greater than a width of a display area including the light-emitting elements; 4. The electro-optical device according to claim 1.

5. a light-emitting element that emits light in response to a current flowing between the pixel electrode and the common electrode; a plurality of power supply wirings including a power supply wiring provided near the pixel electrodes and supplied with a power supply potential; a plurality of data lines arranged along a predetermined direction; a data signal output circuit that outputs a data signal to one of the plurality of data lines; a conductive wiring provided so as to overlap the data signal output circuit in a plan view, the conductive wiring being supplied with the power supply potential via a plurality of mounting terminals; Including, In a plan view, the plurality of power supply wirings are respectively provided between the plurality of data lines and electrically connected to the conductive wirings; In a portion of the conductive wiring that overlaps with the data signal output circuit in a plan view, a width in a direction intersecting with an extension direction of the plurality of data lines is equal to or greater than a width of a display area including the light-emitting elements; Electro-optical device.

6. the conductive wiring is provided in a layer above the plurality of data lines; 6. The electro-optical device according to claim 1.

7. a light-emitting element that emits light in response to a current flowing between the pixel electrode and the common electrode; a plurality of power supply wirings including a power supply wiring provided near the pixel electrodes and supplied with a power supply potential; a plurality of data lines arranged along a predetermined direction; a data signal output circuit that outputs a data signal to one of the plurality of data lines; a conductive wiring provided so as to overlap the data signal output circuit in a plan view, the conductive wiring being supplied with the power supply potential via a plurality of mounting terminals; Including, In a plan view, the plurality of power supply wirings are respectively provided between the plurality of data lines and electrically connected to the conductive wirings; the conductive wiring is provided in a layer above the plurality of data lines; Electro-optical device.

8. 8. An electronic device comprising the electro-optical device according to claim 1.

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