Display substrate, manufacturing method thereof, and display device

Abstract

To provide a manufacturing method and a display device that enable the frame of a display panel to be made compact.SOLUTION: A display substrate includes a scanning drive circuit, which includes a plurality of shift register units, wherein at least one shift register unit includes a signal output line and an output circuit. The output circuit includes an output transistor and an output reset transistor, and the signal output line includes a first output line part extending along a first direction. The first output line part is coupled to a second electrode of the output transistor through a plurality of first signal via holes provided in an overlap region of signal lines, and the first output line part is coupled to a second electrode of the output reset transistor through a plurality of second signal line via holes provided in the overlap region of the signal lines. The plurality of first signal line via holes are arrayed in order along the first direction, and the plurality of second signal line via holes are arrayed in order along the first direction.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. . [Background technology]

[0002] Active-Matrix Organic Light-Emitting Diode The display panel is a low- It has advantages such as low power consumption, low manufacturing costs, and a wide color gamut, and is widely applicable in various fields. It has been done. The AMOLED display panel has a pixel circuit located in the display area and a scanning circuit located in the peripheral area. a driving circuit, the pixel circuit including a plurality of sub-pixel circuits distributed in an array; The scan driving circuit includes a plurality of shift register units, each of which is , which are used to provide light emitting control signals to the corresponding sub-pixel circuits. are installed in the peripheral area of the AMOLED display panel, so the arrangement method of the scan driving circuit is It determines the width of the frame of the AMOLED display panel. Summary of the Invention [Means for solving the problem]

[0003] In a first aspect, the present disclosure provides an embodiment of a display substrate, the display substrate being attached to a base. a scanning driving circuit and a display area, the scanning driving circuit including a plurality of shift register units; At least one of the plurality of shift register units The unit includes a signal output line and an output circuit, the output circuit including an output transistor and an output a reset transistor; the signal output line includes a first output line portion extending along a first direction; The first output line portion is connected to a plurality of first signal line via holes provided in the overlapping region of the signal lines. the first output line portion is coupled to the second electrode of the output transistor via the The output reset transistor is connected to the second signal line via holes provided in the overlapping region of the lines. the first signal line via holes are connected to the second electrodes of the transistors, and the first signal line via holes are arranged in a first direction. Next, the plurality of second signal line via holes are arranged sequentially along a first direction, The overlapping region of the signal lines includes an overlapping region of a first signal line and an overlapping region of a second signal line. The overlapping area of the first signal line is a projection of the first output line portion at the base and a front projection of the first output line portion. The base of the first source-drain metal pattern includes a second electrode of the output transistor. The overlapping area of the second signal line is an overlapping area of the first output line portion. a second electrode of the output reset transistor; an overlap region with an orthogonal projection at said base of the source-drain metal pattern; In the first direction, any two first signal line via holes arranged sequentially along the first direction a ratio of the maximum distance between the first signal line via holes and the third length is a first predetermined ratio, and a first predetermined distance between the first and second signals; is the length of the overlapping area of the lines in the first direction, In the first direction, any two second signal line via holes arranged sequentially along the first direction the ratio of the maximum distance to the fourth length is a second predetermined ratio, and two adjacent second signal line via holes the minimum distance between the first and second signals in the first direction is a second predetermined distance, and the fourth length is is the length of the overlapping area of the lines in the first direction, the first predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.9, the first predetermined distance is equal to or greater than 1.5 μm and equal to or less than 45 μm, the second predetermined ratio is 0.05 or more and 0.9 or less, The display substrate is provided, wherein the second predetermined distance is 1.5 μm or more and 65 μm or less.

[0004] Optionally, the active layer of the output transistor and the output reset transistor The active layer is arranged along a first direction, and in front of the active layer of the output transistor. The length in the first direction is defined as a first length, and the length of the active layer of the output reset transistor is defined as a The length in the first direction is defined as a second length, and the sum of the first length and the second length is the output actuator. is the tip length, a minimum width of the active layer of the output transistor along the second direction; and the minimum width of the active layer of the transistor along the second direction, the smaller of which is defined as the output active layer. The width of the first direction is set to be a tape width, and the first direction and the second direction intersect with each other.

[0005] Optionally, the ratio of the output active length to the output active width is within a predetermined ratio range. Located within The range of the predetermined ratio is 3 or more and 11 or less.

[0006] Optionally, the output active width is within a predetermined range; The predetermined width ranges from 12 μm to 45 μm.

[0007] Optionally, the active layer of the output transistor and the output reset transistor The active layer is formed by a single continuous first semiconductor layer, and the first semiconductor layer is extending along the direction of the a length of the first semiconductor layer in a first direction is an output active length; The minimum length of the first semiconductor layer in the second direction is the output active length.

[0008] Optionally, the at least one shift register unit further includes a first transistor. Included in The first transistor includes a first active pattern. The wire extends along the second direction, The first transistor is located on a side of the output circuit away from a display area.

[0009] Optionally, the at least one shift register unit includes a second transistor and a second electrode of the second transistor connected to the third transistor; coupled to the second electrode of an orthogonal projection of the gate electrode of the second transistor on the base; and a maximum distance in the second direction between the orthogonal projection of the gate electrode on the base is a third predetermined distance; the law of nature, The second transistor and the third transistor are spaced apart from the display area of the output circuit. It is located on the side.

[0010] Optionally, the third predetermined distance is greater than or equal to 14 μm and less than or equal to 50 μm.

[0011] Optionally, the at least one shift register unit includes a first transistor, a second transistor, further comprising a transistor and a first capacitor; The second electrode of the first transistor and the first electrode of the second transistor are respectively a gate electrode of the first transistor coupled to a second plate of the first capacitor; coupled to the first plate of the capacitor, The first transistor, the first capacitor, and the second transistor are arranged in sequence along a first direction. The first transistor, the first capacitor, and the second transistor are located on a side away from the display region of the output circuit.

[0012] Optionally, the scanning driving circuit further includes a first voltage signal line, and the at least one shift register unit further includes an output reset capacitor. A first electrode plate of the output reset capacitor is coupled to a gate electrode of the output reset transistor, and a second electrode plate of the output reset capacitor is coupled to the first voltage signal line. A maximum width of the second electrode plate of the output reset capacitor in a second direction is a first predetermined width, and a maximum length of the second electrode plate of the output reset capacitor in a first direction is a second predetermined length. The output reset capacitor is located on a side away from the display region of the output circuit, and a front projection of the second electrode plate of the output reset capacitor at a base is within a front projection of the first electrode plate of the output reset capacitor at the base.

[0013] Optionally, the first predetermined width is 3 μm or more and 60 μm or less, and the second predetermined length is 3 μm or more and 20 μm or less.

[0014] Optionally, the first voltage signal line extends along the first direction, and the first voltage signal line is located on a side away from the display region of the output reset capacitor.

[0015] Optionally, the output transistor and the output reset transistor are arranged along the first direction, and the scanning driving circuit further includes a second voltage signal line, and the at least one ​ The shift register unit further includes an output reset capacitor; a second plate of the output reset capacitor coupled to the first voltage signal line; a first electrode of the output transistor coupled to a second voltage signal line; a first electrode of the transistor coupled to a second plate of the output reset capacitor; The output transistor and the output reset transistor are connected to the second voltage signal line. It is located on the far side of the area.

[0016] Optionally, the gate electrode of the output transistor is connected to at least one output gate electrode panel. a first electrode of the output transistor including at least one first electrode pattern; and the second electrode of the output transistor includes at least one second electrode pattern. , The output gate electrode pattern is formed by connecting the first electrode pattern and the second electrode pattern adjacent to each other. It is located between The first electrode pattern, the output gate electrode pattern, and the second electrode pattern are all These also extend along the second direction.

[0017] Optionally, the gate electrode of the output reset transistor is connected to at least one output reset a first electrode of the output reset transistor including at least one gate electrode pattern; and a third electrode pattern, and the second electrode of the output reset transistor is at least Each of the electrodes includes a fourth electrode pattern, The output reset gate electrode pattern is connected to the adjacent third electrode pattern and the fourth electrode pattern. Located between the polar patterns, The third electrode pattern, the output reset gate electrode pattern, and the fourth electrode pattern Each of the electrodes extends along the second direction, The output reset transistor closest to the gate electrode of the output transistor The fourth electrode pattern is also used as the second electrode pattern of the output transistor. .

[0018] Optionally, the active layers of the output transistors are arranged opposite to each other along the first direction. at least two first conductive portions and at least one first channel portion, each of the first channel portions is disposed between two adjacent first conductive portions; The first channel portions correspond one-to-one to the output gate electrode patterns, and each of the first channel portions The orthogonal projections of the channel portions on the base are the same as those of the corresponding output gate electrode patterns. located within an orthogonal projection on the base; The first conductive portion of some of the output transistors is paired with the first electrode pattern. The orthogonal projection of the first electrode pattern on the base and the corresponding first conductive portion and an orthogonal projection of the first electrode pattern at the base of the first electrode pattern. The first via hole is formed in the overlapping region. coupled to the conductive portion; The first conductive portions of the other part of the output transistors are connected to the second electrode pattern. The orthogonal projection of the second electrode pattern on the base and the corresponding first electrode pattern are in one-to-one correspondence. and an orthogonal projection of the electrode portion at the base has a second overlap region, and the second electrode pattern is The corresponding via hole is formed in the second overlapping region. coupled to the first conductive portion.

[0019] Optionally, the active layers of the output reset transistors are opposed along a first direction. at least two second conductive portions and at least one second channel portion each of the second channel portions is provided between two adjacent second conductive portions; And, The second channel portions correspond one-to-one to the output reset gate electrode patterns, The orthogonal projections of the second channel portions on the base are all aligned with the corresponding output reset gates. located within an orthogonal projection of a port electrode pattern on said base; The second conductive portions of some of the output reset transistors are connected to the third electrode pattern. and a one-to-one correspondence is established between the orthogonal projection of the third electrode pattern on the base and the corresponding and an orthogonal projection of the second conductive portion at the base has a third overlap region, and the third electrode pattern is and a corresponding third via hole formed in the third overlapping region. coupled to the second conductive portion, The second conductive portion of the other part of the output reset transistor is connected to the fourth electrode pad. The fourth electrode pattern is orthogonally projected onto the base and the corresponding front electrode pattern is formed in one-to-one correspondence with the turn. and an orthogonal projection of the second conductive portion on the base has a fourth overlapping region, and the fourth electrode pattern The pins are connected to each other through at least one fourth via hole provided in the fourth overlapping region. The second conductive portion is coupled to the corresponding second conductive portion.

[0020] Optionally, the scan driving circuit further includes a second voltage signal line, and the at least one scan the soft resistor unit further includes a fourth transistor; The second voltage signal line is coupled to an electrode conductive connection portion, and the electrode conductive connection portion is arranged along a second direction. The at least one first electrode pattern is arranged sequentially along a first direction. R, The electrode conductive connection portion is connected to a first first electrode pad included in the first electrode of the output transistor. Combined into turns, a first electrode of the fourth transistor is coupled to the electrode conductive connection; the orthogonal projection of the gate electrode of the fourth transistor on the base and the electrode conductive connection The minimum distance in the first direction between the orthogonal projection on the base is a fourth predetermined distance.

[0021] Optionally, the fourth predetermined distance is greater than or equal to 1 μm and less than or equal to 5 μm.

[0022] Optionally, the at least one shift register unit comprises a fourth transistor and 5 transistors, a gate electrode of the fourth transistor is coupled to a gate electrode of the fifth transistor; The gate electrode of the fourth transistor and the gate electrode of the fifth transistor are connected to the first gate electrode. The first gate metal pattern is included in a second gate metal pattern, and the first gate metal pattern extends along the second direction.

[0023] Optionally, the scan driving circuit further includes a first clock signal line, and the fifth transistor a gate electrode of the transistor coupled to the first clock signal line; The first clock signal line extends along a first direction, and the first clock signal line The fifth transistor is located on the side away from the display area.

[0024] Optionally, the at least one shift register unit includes a first transistor, a fourth transistor, a transistor, a fifth transistor, a sixth transistor, and an output capacitor; a first electrode of the fifth transistor is coupled to an input signal terminal; a second electrode coupled to the gate electrode of the sixth transistor; The gate electrode of the sixth transistor is formed by a first gate electrode pattern and a second gate electrode pattern. a second gate electrode pattern; The first gate electrode pattern and the second gate electrode pattern are respectively connected to the output capacitor the first plate of the output capacitor is coupled to the first plate of the output transistor coupled to the gate electrode, a first electrode of the sixth transistor coupled to a gate electrode of the fourth transistor; a second electrode of the sixth transistor is coupled to a second electrode of the fourth transistor, and the output capacitor a second plate of the capacitor coupled to the first electrode of the first transistor; The fourth transistor, the sixth transistor, and the first transistor are connected to the first are arranged sequentially along the direction, The fifth transistor, the sixth transistor, and the first transistor are connected to the first are arranged sequentially along the direction, The output capacitor is located between the sixth transistor and the output circuit.

[0025] Optionally, the at least one shift register unit includes a second transistor, a first a sixth transistor, a seventh transistor, and an eighth transistor. , The active layer of the seventh transistor and the active layer of the eighth transistor are one The second semiconductor layer is formed by a continuous second semiconductor layer extending along a first direction. , The active layer of the seventh transistor is a first transistor arranged sequentially along the first direction. a ninth conductive portion, a ninth channel portion, and a second ninth conductive portion; The second ninth conductive portion is also used as the first tenth conductive portion; The active layer of the eighth transistor is a first transistor that is sequentially disposed along the first direction. a tenth conductive portion, a tenth channel portion, and a second tenth conductive portion; The first ninth conductive portion is used as a second electrode of the seventh transistor, and the second the ninth conductive portion is used as a first electrode of the seventh transistor, and the second 10 conductive portion is used as a first electrode of the eighth transistor, and the seventh transistor the first electrode of the eighth transistor is also used as the second electrode of the eighth transistor, a gate electrode of the seventh transistor coupled to a second plate of the output capacitor; a second electrode of the transistor coupled to the gate electrode of the sixth transistor; a gate electrode of the eighth transistor is coupled to a gate electrode of the first transistor; a first electrode of the eighth transistor coupled to a first voltage signal line; the first voltage signal line extends along a first direction; The sixth transistor, the seventh transistor, the eighth transistor, and the second transistor The transistors are arranged sequentially along a first direction.

[0026] Optionally, the scan driving circuit further includes a second clock signal line, and the second transistor the gate electrode of the seventh transistor is connected to the second clock signal line, Combined, The second clock signal line extends along a first direction, and the second clock signal line is The second transistor is located on the side away from the display area.

[0027] Optionally, the scan driving circuit further includes a second voltage signal line and a signal output line; the signal output line includes a first output line portion and at least one second output line portion; The second voltage signal line and the first output line portion both extend along a first direction, the first output line portion is located between the second voltage signal line and the output circuit; the second output line portion extends along a second direction; The second output line portion is used to provide a light emitting control signal to a pixel circuit in a display area. and The first output line portion and the output circuit are spaced apart from the display area of the second voltage signal line. It is located on the side.

[0028] Optionally, the scan driving circuit includes a first voltage signal line, a second voltage signal line, a first clock signal line, a line and a second clock signal line; The first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line The clock signal lines are all extended in a first direction, an orthogonal projection of the first voltage signal line at the base; and the orthogonal projection of the second clock signal line at the base are both a base of the star unit positioned on a side of the orthogonal projection away from the display area; The orthogonal projection of the second voltage signal line at the base is It is located closer to the display area.

[0029] Optionally, the signal output line further includes at least one second output line portion, Two output line portions are coupled to the first output line portion, and the second output line portion is coupled to the display area. The light emitting element is extended to provide a light emitting control signal to the pixel circuit located in the display area. can be done.

[0030] Optionally, the scan driving circuit includes a first voltage signal line, a second voltage signal line, a first clock signal line, a second clock signal line and a signal output line, The starter unit consists of a first capacitor, an output capacitor, an output reset capacitor, a first transistor transistor, second transistor, third transistor, fourth transistor, fifth transistor a sixth transistor, a seventh transistor and an eighth transistor; the lines of force further include at least one second output line portion; a gate electrode of the output transistor is coupled to a first plate of the output capacitor; A first electrode of the output transistor is coupled to a second voltage signal line, and a second electrode of the output transistor is coupled to a second voltage signal line. an electrode coupled to the signal output line; The gate electrode of the output reset transistor is connected to the first electrode of the output reset capacitor. a first electrode of the output reset transistor coupled to the output reset capacitor a second electrode of the output reset transistor coupled to the signal output line; And, a second plate of the output reset capacitor coupled to the first voltage signal line; a second plate of the capacitor coupled to the gate electrode of the seventh transistor; a first electrode of the first transistor coupled to a second plate of the output capacitor; The second electrode of the first transistor and the first electrode of the second transistor are connected to the first capacitor. a gate electrode of the first transistor coupled to a second plate of the first capacitor; coupled to the first plate of The gate electrode of the second transistor and the gate electrode of the seventh transistor are respectively a second electrode of the second transistor coupled to a second clock signal line; coupled to the second electrode of the a gate electrode of the third transistor coupled to a gate electrode of the output transistor; a first electrode of the third transistor coupled to a first plate of the output reset capacitor; a gate electrode of the fourth transistor is coupled to a gate electrode of the fifth transistor; a first electrode of the fourth transistor coupled to a first electrode of the output transistor; a second electrode of the fourth transistor coupled to a second electrode of the sixth transistor; A gate electrode of the fifth transistor is coupled to the first clock signal line, a first electrode of the fifth transistor is coupled to the input signal terminal, and a second electrode of the sixth transistor is coupled to the input signal terminal; coupled to the gate electrode of the transistor; a first electrode of the sixth transistor coupled to a gate electrode of the fourth transistor; a second electrode of the sixth transistor is coupled to a second electrode of the fourth transistor; a gate electrode of the seventh transistor coupled to a second plate of the output capacitor; The first electrode of the transistor is also used as the second electrode of the eighth transistor, and the seventh transistor a second electrode of the transistor coupled to a gate electrode of the sixth transistor; a gate electrode of the eighth transistor is coupled to a gate electrode of the first transistor; a first electrode of the eighth transistor coupled to a first voltage signal line; The second output line portion is coupled to the first output line portion, and the second output line portion is coupled to the surface and extending to the display area to provide light-emitting control signals to pixel circuits located in the display area. It is used in this regard.

[0031] Optionally, a second voltage signal line is provided on a side of the shift register unit close to the display area. It is The first voltage signal line, the first clock signal line, and the second clock signal line are connected to the It is provided on the side of the soft register unit away from the display area, The first clock signal line, the second clock signal line, and the The first voltage signal line and the second voltage signal line are arranged in sequence or are arranged close to the display area. The second clock signal line, the first clock signal line, and the first voltage The signal lines are arranged in sequence.

[0032] Optionally, the scan driving circuit further includes a first initial signal line and a second initial signal line; The second initial signal line and the first initial signal line are arranged in a direction approaching the display area. The first clock signal line, the second clock signal line, and the first voltage signal line are arranged in sequence. Listed, The first initial signal line and the second initial signal line are arranged in a direction approaching the display area. The first clock signal line, the second clock signal line, and the first voltage signal line are arranged in sequence. Listed, The second initial signal line and the first initial signal line are arranged in a direction approaching the display area. The second clock signal line, the first clock signal line, and the first voltage signal line are arranged in sequence. Listed, The first initial signal line and the second initial signal line are arranged in a direction approaching the display area. The second clock signal line, the first clock signal line, and the first voltage signal line are arranged in sequence. will be listed.

[0033] Optionally, the output transistor and the output reset transistor are located between the output capacitor and the first output line portion, and the output transistor and the output reset transistor are sequentially arranged along the first direction. 、 No. 1 direction to the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the first transistor, the first capacitor, the second transistor, and the output reset transistor are arranged in sequence along the line; the fifth transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are located between the output capacitor and the first voltage signal line; The gate electrode of the fifth transistor and the gate electrode of the fourth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along the second direction.

[0034] Optionally, the display substrate further includes a plurality of rows of pixel circuits disposed on the base; The pixel circuit includes a light emitting control terminal; The shift register unit corresponds to at least one row of the pixel circuits; The signal output lines of the shift register unit are connected to the light emission control lines of the pixel circuits in at least one row. and a light-emitting control signal is provided to the light-emitting control terminal of the pixel circuits of the at least one row. It is used in this regard.

[0035] In a second aspect, an embodiment of the present disclosure provides a method for fabricating a display substrate, the method comprising: The fabrication method includes fabricating a scan drive circuit on a base, the scan drive circuit comprising: a plurality of shift register units, and at least one of the plurality of shift register units Each shift register unit includes an output circuit, and the output circuit includes an output transistor. and an output reset transistor, The method for manufacturing the display substrate includes: A semiconductor layer is fabricated on the base, and a patterning process is performed on the semiconductor layer to form an output transistor. forming an active layer of the output reset transistor and an active layer of the output reset transistor; and, A first gate metal layer is formed on a surface of the semiconductor layer opposite the base; A patterning process is performed on the metal layer to form a gate electrode of the output transistor and a gate electrode of the output reset transistor. forming a gate electrode of the gate transistor; The gate electrode of the output transistor and the gate electrode of the output reset transistor As a mask, a dopant is applied to the portion of the semiconductor layer that is not covered by the gate electrode. The portion of the semiconductor layer that is not covered by the gate electrode is then covered with a conductive film. A portion of the semiconductor layer that is formed as a conductive portion and is covered by the gate electrode as a channel portion; a second gate metal layer is provided on one surface of the first gate metal layer facing the semiconductor layer; A patterning process is performed on the gate metal layer to form a first output line portion extending along a first direction. forming a signal output line including: providing a first insulating layer on one side of the second gate metal layer facing away from the first gate metal layer; , A region where the first insulating layer and the first output line partially overlap is provided with a dielectric film that penetrates the first insulating layer. fabricating a plurality of first signal line via holes and a plurality of second signal line via holes; A source / drain metal layer is formed on the first insulating layer on one side opposite to the second gate metal layer. Then, a patterning process is performed on the source / drain metal layer to form a first source / drain metal layer. forming a pattern and a second source-drain metal pattern; the first source-drain metal pattern includes a second electrode of the output transistor, the second source-drain metal pattern includes a second electrode of the output reset transistor; By doing so, the first output line portion is connected to the output terminal through the plurality of first signal line via holes. a second electrode of the transistor, and the first output line portion is coupled to the second electrode of the plurality of second signal line buses; a second electrode of the output reset transistor via a hole; the signal output line includes a first output line portion extending along a first direction; The plurality of first signal line via holes are sequentially arranged along a first direction, and the plurality of second signal line via holes are The signal line via holes are arranged sequentially along a first direction, In the first direction, any two first signal line via holes arranged sequentially along the first direction a ratio of the maximum distance between the first signal line via holes and the third length is a first predetermined ratio, and a minimum distance in a first direction between the balls is a first predetermined distance; In the first direction, any two second signal line via holes arranged sequentially along the first direction the ratio of the maximum distance to the fourth length is a second predetermined ratio, and two adjacent second signal line via holes a minimum distance in the first direction between the balls is a second predetermined distance; The third length is the length of the overlapping region of the first signal line in the first direction, and the fourth length is the length is the length of the overlapping region of the second signal line in the first direction, the first predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.9, the first predetermined distance is equal to or greater than 1.5 μm and equal to or less than 45 μm; the second predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.9, The second predetermined distance is 1.5 μm or more and 65 μm or less. provide.

[0036] Optionally, the length of the active layer of the output transistor in the first direction is defined as a first length. The length of the active layer of the output reset transistor in the first direction is set to a second length the sum of the first length and the second length is an output active length, a minimum width of the active layer of the output transistor along the second direction; and the minimum width of the active layer of the transistor along the second direction, the smaller of which is defined as the output active layer. The width of the first direction is set to be a tape width, and the first direction and the second direction intersect with each other.

[0037] Optionally, the ratio of the output active length to the output active width is within a predetermined ratio range. Located within The range of the predetermined ratio is 3 or more and 11 or less.

[0038] Optionally, the output active width is within a predetermined range; The predetermined width ranges from 12 μm to 45 μm.

[0039] In a third aspect, the present disclosure further provides a display device including the display substrate described above. do. [Brief explanation of the drawings]

[0040] [Figure 1] 1 is a circuit diagram of at least one embodiment of at least one shift register unit included in a display substrate according to an embodiment of the present disclosure; [Figure 2A] 2 is an operational sequence diagram of at least one embodiment of the shift register unit shown in FIG. 1. [Figure 2B] 1 is a schematic diagram of a display substrate area division in accordance with at least one embodiment of the present disclosure. [Figure 2C] FIG. 2 is a schematic diagram of a connection relationship between a scanning driving circuit and a pixel circuit included in a display substrate according to at least one embodiment of the present disclosure. [Figure 2D] FIG. 1 is a schematic diagram of one layout of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 3A]FIG. 10 is another schematic layout diagram of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 3B] FIG. 10 is yet another schematic layout diagram of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 4] 3A is a schematic diagram showing the maximum distance K1 in the first direction between the first first signal line via hole and the last first signal line via hole arranged sequentially along the first direction, and the maximum distance K2 in the first direction between the first second signal line via hole and the last second signal line via hole arranged sequentially along the first direction. [Figure 5] FIG. 2 is a schematic diagram of an active layer of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 6] FIG. 2 is a schematic diagram of a first gate metal layer of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 7] FIG. 10 is a schematic diagram of a second gate metal layer of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 8] FIG. 1 is a schematic diagram of a via hole used in a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 9] FIG. 2 is a schematic diagram of a source-drain metal layer of a shift register unit in accordance with at least one embodiment of the present disclosure. [Figure 10] Schematic diagram of the source-drain metal layer in Figure 3A. [Figure 11] FIG. 10 is yet another schematic layout diagram of a shift register unit in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0041] Hereinafter, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. As is apparent, the described embodiments are only a part of the present disclosure, and all Based on the embodiments of the present disclosure described, a person skilled in the art would be able to realize the above without any creative effort. Any other conceivable embodiments are within the patentable scope of this disclosure.

[0042] As shown in FIG. 1, at least one embodiment of the present disclosure provides a display substrate, The display substrate includes a scanning driving circuit disposed in a peripheral region thereof, the scanning driving circuit including a first voltage signal signal line VGH, second voltage signal line VGL, first clock signal line CK, second clock signal line CB and a signal output line E0, and the scan driving circuit further includes a plurality of shift register units Included in As shown in FIG. 1, at least one of the plurality of shift register units At least one embodiment of the output resistor unit includes a first capacitor C1, an output capacitor C2, , output reset capacitor C3, output transistor T10, output reset transistor T 9, first transistor T1, second transistor T2, third transistor T3, fourth transistor transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, an eighth transistor T8; The gate electrode G10 of the output transistor T10 is connected to the first pole of the output capacitor C2. The first electrode S10 of the output transistor T10 is coupled to the second voltage signal line C2a. VGL, and the second electrode D10 of the output transistor T10 is coupled to the signal output line E Combined into 0, The gate electrode G9 of the output reset transistor T9 is connected to the output reset capacitor a first electrode S9 of the output reset transistor T9; , coupled to the second plate C3b of the output reset capacitor C3, A second electrode D9 of the transistor T9 is coupled to the signal output line E0, The second plate C3b of the output reset capacitor C3 is coupled to the first voltage signal line VGH. a second electrode C2b of the output capacitor C2 is coupled to a second clock signal line CB; a first electrode S1 of the first transistor T1 is coupled to the second clock signal line CB; The second electrode D1 of the first transistor T1 and the first electrode S2 of the second transistor T2 are respectively coupled to the second plate C1b of the first capacitor C1, and the first transistor a gate electrode G1 of T1 is coupled to a first plate C1a of the first capacitor C1; The gate electrode G2 of the second transistor T2 and the gate electrode G of the seventh transistor T7 7 are respectively coupled to the first clock signal line CB and the first The second electrode D2 is coupled to the second electrode D3 of the third transistor T3. a first electrode S2 of the capacitor T2 is coupled to a second plate C1b of the first capacitor; The gate electrode G3 of the third transistor T3 is connected to the gate of the output transistor T10. The first electrode S3 of the third transistor T3 is coupled to the electrode G10. coupled to line VGH, The gate electrode G4 of the fourth transistor T4 and the gate electrode G5 of the fifth transistor T5 The electrodes G5 are both coupled to the first clock signal line CK, and the third gate of the fourth transistor T4 is connected to the first gate of the fourth transistor T5. The first electrode S4 and the first electrode S10 of the output transistor T10 are both connected to a second voltage signal The second electrode D4 of the fourth transistor T4 is coupled to the line VGL. coupled to the second electrode D6 of the capacitor T6, The gate electrode G5 of the fifth transistor T5 is coupled to the first clock signal line CK. The second electrode D5 of the fifth transistor T5 is connected to the gate electrode G of the sixth transistor T6. 6, and the first electrode S5 of the fifth transistor T5 is coupled to the input signal terminal E1. , The first electrode S1 of the sixth transistor T6 and the gate electrode G4 of the fourth transistor T4 are both coupled to the first clock signal line CK, and the second electrode of the sixth transistor T6 D6 is coupled to the second electrode D4 of the fourth transistor T4, and the sixth transistor T The gate electrode G6 of the sixth transistor is coupled to the second electrode D1 of the fifth transistor, The gate electrode G7 of the seventh transistor T7 and the second electrode C2b of the output capacitor C2 are both coupled to the second clock signal line CB, and the first electrode of the seventh transistor T7 S7 is coupled to the second electrode D8 of the eighth transistor T8, and the seventh transistor T a second electrode D7 of the sixth transistor T7 coupled to a gate electrode G6 of the sixth transistor T6; The gate electrode G8 of the eighth transistor T8 is connected to the gate electrode G1 of the first transistor T1. The first electrode S8 of the eighth transistor T8 is coupled to the first voltage signal line VGH is combined with

[0043] In at least one embodiment of the shift register unit shown in FIG. All of the transistors are p-type transistors, but are not limited to this.

[0044] In at least one embodiment of the present disclosure, at least one of the shift register units shown in FIG. Another embodiment may be, but is not limited to, a light emission control scan drive circuit.

[0045] In at least one embodiment of the present disclosure, the first electrode of the transistor may be a source electrode. Alternatively, the second electrode of the transistor may be a drain electrode. The first electrode may be a drain electrode and the second electrode of the transistor may be a source electrode. Also often.

[0046] In FIG. 1, the symbol N1 is the first node, the symbol N2 is the second node, and the symbol N3 is the is the third node, and symbol N4 is the fourth node.

[0047] In at least one embodiment shown in FIG. 1, the first voltage signal line VGH provides the high voltage Vgh. The second voltage signal line VGL can provide a low voltage Vgl. Not limited to.

[0048] As shown in FIG. 2A, in at least one embodiment of the shift register unit shown in FIG. 1 of the present disclosure, when operating: In the first stage P1, E1 provides a high level, CK provides a low level, CB provides a high level, T5 and T4 are turned on, the potential of N1 is high, T6 is turned off, the potential of N2 is low, so T7, T3 and T10 are turned off, T8 and T1 are turned on, at this time, the potential of N3 is high, CB provides a high level, so T2 is turned off, the voltage across the capacitor does not change suddenly, so the potential of N4 is held at the high level of the previous frame, T9 is turned off, and the potential of the light emission control signal output from E0 is held at the low level of the previous frame; In the second stage P2, E1 and CK all provide a high level, CB provides a low level, T5, T6 and T4 all turn off, the potential of N1 is held at a high level, the potential of N2 is held at a low level, T7, T8 and T1 all turn on, the potential of N3 changes from a high level to a low level, T2 turns on, the potential of N4 is at a low level, T9 turns on, E0 outputs a high level, T3 and T10 all turn off, In the third stage P3, E1 and CB both provide a high level, CK provides a low level, T5 and T4 both turn on, the potential of N1 is a high level, the potential of N2 is a low level, T6 and T7 both turn off, T8 and T1 both turn on, the potential of N3 changes from the low level in the previous stage to a high level, T2 turns off, the potential of N4 is held at a low level, T9 turns on, E0 outputs a high level, T3 and T10 both turn off, In the fourth stage P4, E1 and CB both provide a low level, CK provides a high level, T5 and T4 both turn off, the potential of N1 is a high level, T6 is turned off, the potential of N2 is held at a low level, T7, T8 and T1 all turn on, the voltage of N3 jumps to a low level, T2 is turned on, the potential of N4 is a low level, T9 is turned on, E0 outputs a high level, T3 and T10 all turn off; In the fifth stage P5, E1 and CK all provide a low level, CB provides a high level, T5, T6 and T4 all turn on, the potential of N1 and the potential of N2 are all low level, T7 is turned off, T7 and T1 are both turned on, the voltage of N3 changes to a high level, T2 is turned off, T3 is turned on, the voltage of N4 changes to a high level, T9 is turned off, T10 is turned on, and E0 outputs a low level; In the sixth stage P6, the E1 and CB signals are at a low level, CK is at a high level, T1 and T3 are turned off, the node N1 is held at a low level, T2 is turned on, the voltage at the N2 node is at a high level, T4 and T5 are turned on, T6 is turned off, the N3 node is at a high level, T7 and T8 are turned on, the N4 node is at a high level, T9 is turned off, and T10 is turned on. E0 outputs a low level.

[0049] In the seventh stage P7, E1 and CK both provide low levels, and CB provides high levels. As a result, T5, T6 and T4 are all turned on, and the potential of N1 and the potential of N2 are both At a low level, T7 is turned off, T8 and T1 are both turned on, and the potential of N3 is at a high level, T2 is turned off, T3 is turned on, and the potential of N4 is at a high level. T9 turns off, T10 turns on, E0 outputs a low level,

[0050] In the eighth stage P8, E1 and CB both provide low levels, and CK provides high levels. Then, T5 and T4 are both turned off, the potential of N1 is held at a low level, and T6 The potential of N2 is at a high level, T7 is on, and T8 and T1 are The potential of N3 is at a high level, T2 and T3 are both turned on, and N The voltage at 4 is high level, T9 is off, T10 is on, and E0 is low level. output the rule, After the sixth step, T3 is continuously turned off until E1 receives an input signal in the next frame. T9 is continuously turned off, T5 periodically charges C2, and the potential of N1 drops to low. Therefore, T10 is continuously on and E0 outputs a low level.

[0051] As shown in FIG. 2B, J1 is a display substrate, A0 is a display area, and B Reference numeral B1 denotes the first peripheral region, and reference numeral B2 denotes the second peripheral region.

[0052] A plurality of light-emitting control lines, a plurality of gate lines and a plurality of data lines, and a plurality of gate lines and a plurality of data lines intersecting with each other; The sub-pixels may be provided as follows: A scan driving circuit may be provided in the first peripheral area B1 and / or the second peripheral area B2. The scan driving circuit includes a plurality of shift register units, Among the plurality of shift register units included in the scan drive circuit, The signal output lines of the star unit are respectively connected to A light emission control lines, and the corresponding light emission control lines are The light emitting diodes 102 may be used to provide lighting control signals to the control lines.

[0053] Here, A can be any positive integer. In actual operation, A can be 1, 2, 3, or 4. or other positive integers, the value of A is selected according to the actual situation. That's fine.

[0054] In particular, the light emitting control line is connected to the light emitting control terminal of the pixel circuit of the corresponding row. will be done. Optionally, the display substrate further includes a plurality of rows of pixel circuits disposed on the base; The pixel circuit includes a light emitting control terminal; The shift register unit included in the scan drive circuit Corresponding to the circuit, The signal output lines of the shift register unit are connected to the light emission control lines of the pixel circuits of at least one row. a control terminal for providing a light emitting control signal to the light emitting control terminal of the pixel circuit of the at least one row; It is used to mean:

[0055] In at least one embodiment of the present disclosure, the pixel circuit is provided in an effective display area of a display substrate. The scanning drive circuit may be provided in the peripheral region of the display substrate.

[0056] As shown in FIG. 2C, the symbol Y1 is a scan driving circuit, and the symbol S11 is the scan driving circuit. S1 is the first stage shift register unit included in the scan drive circuit S 1, and the symbol S1N-1 is a second-stage shift register unit included in the scan drive circuit S1N is the N-1th stage shift register unit included in the scan drive circuit the Nth stage shift register unit included in the path S1, where N is an integer greater than 3; In FIG. 2C, R1 denotes the first row pixel circuit, and R2 denotes the second row pixel circuit. , R3 is the third row pixel circuit, R4 is the fourth row pixel circuit, and R2N-3 is the pixel circuit in the (2N-3)th row, symbol R2N-2 is the pixel circuit in the (2N-2)th row, and symbol R 2N-1 is the (2N-1)th row pixel circuit, and symbol R2N is the (2N)th row pixel circuit, S11 provides a lighting control signal to R1 and R2, and S12 provides a lighting control signal to R3 and R4. S1N-1 provides a light emission control signal to R2N-3 and R2N-2, and S1N provides a light emission control signal to R providing a light emission control signal to R2N-1 and R2N; As shown in FIG. 2C, in the peripheral region, the display substrate further includes a gate electrode driving circuit. the gate electrode driving circuit may include a plurality of stages of gate electrode driving units; The gate electrode driving units are one-to-one corresponding to the pixel rows, and the pixels in the corresponding rows are driven by the corresponding gate electrodes. may be used to provide gate electrode drive signals; In FIG. 2C, the symbol Y2 is a gate electrode driving circuit, and the symbol S21 is a gate electrode driving The first row gate electrode driving unit included in the circuit, and symbol S22 is the gate electrode driving circuit The reference symbol S23 denotes a second row gate electrode driving unit included in the gate electrode driving circuit. The reference symbol S24 denotes a third row gate electrode driving unit included in the gate electrode driving circuit. The gate electrode driving circuit includes a fourth row gate electrode driving unit S2N-3. The symbol S2N-2 indicates the gate electrode driving circuit. The 2N-2th row gate electrode driving unit included in the The gate electrode driver unit S2N is the gate electrode driver 2 is a second N-row gate electrode drive unit included in the drive circuit.

[0057] In at least one embodiment shown in FIG. 2D, a first voltage signal line VGH carries a high voltage signal Vgh. a second voltage signal line VGL providing a low voltage signal Vgl; As shown in FIG. 2D, VGL, VGH, CK, and CB are aligned in the direction away from the display area. VGH, VGL, CK, and CB are arranged along the first direction, and VGH, VGL, CK, and CB extend in the first direction, As shown in FIGS. 1 and 2D, at least one embodiment of the shift register unit includes a first Capacitor C1, output capacitor C2, output reset capacitor C3, output transistor T10, output reset transistor T9, first transistor T1, second transistor T2 , the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor a seventh transistor T6, a seventh transistor T7 and an eighth transistor T8; This embodiment of the unit is installed between VGH and VGL, T10 and T9 are arranged along the first direction, C2 is provided on the side of T10 away from VGL, and T5, T6 and T4 are connected to C2 and VGL. It is located between GH and T1 and T3 are provided on the side of T9 away from VGL, and C1 is provided on the side of T3 away from T9. T8 and T2 are provided on the side of C1 away from T8, T5, T7, T8, T2 and C3 are arranged in sequence along the first direction, and T6, C1 and C3 are arranged sequentially along the first direction, and C2, T1, T3 and C3 are arranged sequentially along the first direction. are arranged in sequence, T1 includes a first active pattern, and the first active pattern of T1 is arranged in the vertical direction. It is disadvantageous to be closely aligned between T2 and T3, The width of the second electrode C3b of C3 is long in the horizontal direction, and the width of the second electrode C3b of C3 is long in the second direction of the shift register unit. This is disadvantageous in narrowing the width of the

[0058] In FIG. 2D, E01 denotes the first output line portion of the signal output line, and E021 denotes the second output line portion of the signal output line. The code E022 is the second output line of the signal output line. The force line part, E01 is arranged along the first direction and E021 is arranged along the second direction. E01, E021, and E022 are coupled to each other, and the first direction and the second direction are mutually and E01 is connected to VGL and the output circuit (the output circuit is connected to the output transistor T10 and the output reset transistor T9), and 2 extends to the display area along the second direction to emit light to the pixel circuits located in the display area. It is convenient to provide control signals.

[0059] As shown in FIG. 2D, S7 doubles as D8.

[0060] In FIG. 2D and FIG. 3A, symbol G1 is the gate electrode of T1, symbol S1 is the first gate electrode of T1, and D1 is the second electrode of T1, and G2 is the gate electrode of T2. Symbol S2 is the first electrode of T2, symbol D2 is the second electrode of T2, symbol G3 is the first electrode of T3 The gate electrode of T3 is denoted by symbol S3, and the second electrode of T3 is denoted by symbol D3. , symbol G4 is the gate electrode of T4, symbol S4 is the first electrode of T4, symbol D4 is the G5 is the gate electrode of T5, and S5 is the first electrode of T5. where D5 is the second electrode of T5, G6 is the gate electrode of T6, and S6 is the first electrode of T6, symbol D6 is the second electrode of T6, symbol G7 is the gate voltage of T7. The symbol S7 is the first electrode of T7, the symbol D7 is the second electrode of T7, and the symbol G The symbol S8 is the gate electrode of T8, the symbol S8 is the first electrode of T8, and the symbol G9 is the gate electrode of T9. The symbol S9 is the first electrode of T9, the symbol D9 is the second electrode of T9, and the symbol Symbol G10 is the gate electrode of T10, symbol S10 is the first electrode of T10, symbol D1 0 is the second electrode of T10.

[0061] In at least one embodiment shown in FIG. 2D, the first direction is a vertical direction from top to bottom. The second direction may be a horizontal direction from right to left, but is not limited to this. In operation, the first direction may be a vertical direction from bottom to top, and the second direction may be a vertical direction from bottom to top. The first direction may be horizontal, from left to right, or may be some other direction. The second direction may be another direction.

[0062] In the layout scheme of the gate electrode driving circuit shown in FIG. 2D, the active layer of T9 and the active layer of T9 is formed by one continuous first semiconductor layer, The length of the layer in the first direction is short, so the vertical space of the entire shift register unit is small. Therefore, the width of the shift register unit in the horizontal direction is large, and the shift register unit It is disadvantageous for the elements in the display panel to be closely arranged in the horizontal direction, and the trend toward narrower frames for display substrates is disadvantageous to

[0063] The shift register unit shown in FIG. 2D is an n-th stage shift register included in the scan drive circuit. It may be a unit of saturation, where n is a positive integer.

[0064] Based on the above problems, the inventor of the present disclosure has, through research, By adjusting the layout method of each transistor, the shift register unit By reducing the area occupied by the display, we discovered that we could reduce the width of the display frame. .

[0065] In the layout scheme shown in FIG. 3A, the first voltage signal line VGH supplies the high voltage signal Vgh and the second voltage signal line VGL provides a low voltage signal Vgl, and In the embodiment, the shift register unit is placed between VGH and VGL.

[0066] In FIG. 3A, E01 denotes a first output line portion of the signal output line, and E021 denotes a second output line portion of the signal output line. The code E022 is the second output line of the signal output line. The force line part, E01 is arranged along the first direction and E021 is arranged along the second direction. E01, E021, and E022 are coupled to each other, and the first direction and the second direction are mutually As shown in FIG. 3A, E01 is provided between VGL and the output circuit. E021 and E022 are extended to the display area along the second direction and positioned in the display area. This makes it convenient to provide a light emitting control signal to the pixel circuit.

[0067] For example, in the layout scheme shown in FIG. 3A, the first direction is vertical from top to bottom. The first direction may be a horizontal direction from right to left, but is not limited to this. Not possible.

[0068] The shift register unit shown in FIG. 3A is an n-th stage shift register included in the scan drive circuit. The number of digits may be 1 or 2, and n is a positive integer.

[0069] As shown in FIGS. 1 and 3A, at least one embodiment of the shift register unit includes a first Capacitor C1, output capacitor C2, output reset capacitor C3, output transistor T10, output reset transistor T9, first transistor T1, second transistor T2 , the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor 3A, including a seventh transistor T6, a seventh transistor T7, and an eighth transistor T8. , the output circuit O1 includes the output transistor T10 and the output reset transistor T9 Including, The gate electrode G10 of the output transistor T10 is connected to the first pole of the output capacitor C2. The first electrode S10 of the output transistor T10 is coupled to the second voltage signal line C2a. VGL, and the second electrode D10 of the output transistor T10 is included in the signal output line. a first output line portion E01 connected to the first output line portion E01; The gate electrode G9 of the output reset transistor T9 is connected to the output reset capacitor a first electrode S9 of the output reset transistor T9; , coupled to the second plate C3b of the output reset capacitor C3, The second electrode D9 of the transistor T9 is coupled to the first output line portion E01 included in the signal output line. will be done.

[0070] In the layout scheme of the gate electrode driving circuit shown in FIG. 3A, the active layer of T9 The active layer of T10 may be formed by one continuous first semiconductor layer, The length of the first semiconductor layer in the first direction is increased to form other semiconductor layers included in the shift register unit. By utilizing the extra space in the vertical direction, the width of the shift register unit in the horizontal direction is It is advantageous to narrow the shift register unit so that the elements are closely arranged in the horizontal direction. This is advantageous for the development of narrower picture frames for display substrates.

[0071] As shown in FIG. 3A, the shift register units having the above configuration are arranged in the peripheral area of the display substrate. When the display panel is turned off, the second voltage signal line V GL, the first voltage signal line VGH, the first clock signal line CK, and the second clock signal line CB in this order. Next, the second voltage signal line VGL, the first voltage signal line VGH, the first clock signal line CK, and and the second clock signal line CB extend in the first direction, As shown in Figure 3A, the first capacitor C1, the output capacitor C2, and the output reset capacitor capacitor C3, output transistor T10, output reset transistor T9, first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor transistor T5, sixth transistor T6, seventh transistor T7 and eighth transistor T8 are both placed between VGH and VGL, and the length of the first semiconductor layer pulled up in the first direction is In order to utilize this, move T5, T6, T4, T7 and T8 up, T1 includes a first active pattern, and the first active pattern of T1 is in a second direction. T1 is provided between T8 and C1, and T8, T1 and C1 are provided so as to extend along the direction are arranged sequentially along the first direction, and T1 is placed in the space between T8 and C1. By providing a second transistor, the arrangement between T2 and T3 can be made tighter. The second electrode D2 of the third transistor T2 is coupled to the second electrode D2 of the third transistor T3. For convenience, it is necessary to place T2 and T3 close to each other), and the occupation of the shift register unit The width in the second direction can be further narrowed, Moreover, in the layout scheme shown in FIG. 3A, the shape of C1 and the shapes of T1, T2, and The position where T3 is arranged is further matched, and C1 is formed by utilizing the space between T1, T2 and T3. The electrode plates are provided, In the layout scheme shown in FIG. 3A, the width of the second electrode C3b of C3 in the second direction is The length of the second electrode C3b of C3 in the first direction is set to be small, and the electrode C3 On the premise of securing the area of C3, narrow the width of the C3 plate in the second direction, As shown in FIG. 3A, the orthogonal projection of the second plate C3b of C3 at the base is the first plate C3 is in the orthogonal projection at the base of a.

[0072] Also, as shown in FIG. 3A and FIG. 6 (FIG. 6 is a schematic diagram of the first gate metal layer of FIG. 3A), The gate electrode G6 of T6 is connected to the first gate electrode pattern G61 and the second gate electrode pattern G62. Including the gate electrode pattern G62, T6 is formed as a double gate structure.

[0073] The purpose of the double gate structure design is to design the system included in the scan drive circuit in the second stage P2. When the soft resistor unit outputs the high voltage signal Vgh, T10 should be completely off. When this happens, the high level applied to the gate electrode of T10 is input from the source electrode of T8, Therefore, in the second stage P2, it is necessary to ensure that T8 is turned on, that is, the second node N2 In the second stage P2, the potential of the gate electrode of T6 is set to a high voltage, while in the third stage P3, the potential of the gate electrode of T6 is set to a low voltage. Therefore, the design is such that there is no leakage current across T6, which would cause a rise in the potential of the second node N2. The purpose of this is to set T6 using a double gate design that makes it easier to turn off the T6.

[0074] In at least one embodiment of the present disclosure, the first direction and the second direction are crossed with each other, e.g. For example, the first direction may be perpendicular to the second direction, but is not limited to this.

[0075] Specifically, the included angle between the second direction and the first direction may be adjusted according to actual needs. For example, the second direction is perpendicular to the first direction.

[0076] In at least one embodiment of the present disclosure, the position of the first clock signal line CB and the second clock The positions of the clock signal lines CK may be interchanged, but this is not limitative.

[0077] In the layout scheme shown in FIG. 3A, as shown in FIG. 5 (FIG. 5 is the active The length of the first semiconductor layer 10 in the first direction is the output active length L 1, and the minimum width of the first semiconductor layer 10 in the second direction is the output active width W1. , the output active length L1 is a first predetermined length; The ratio of the output active length L1 to the output active width W1 is within a predetermined ratio range. Located in The output active width W1 is within a predetermined width range, In at least one embodiment of the present disclosure, increasing the output active length L1 In the star unit, elements other than the output circuit have a large L1, so there is space in the vertical direction. Furthermore, the horizontal direction occupied by the shift register unit can be In at least one embodiment of the present disclosure, the output active The width W1 can be reduced, eliminating the horizontal space, and the remaining space can be used for the shift register. The layout can be done by using elements other than the output circuit of the power supply unit. Furthermore, the horizontal space occupied by the shift register unit can be reduced.

[0078] In at least one embodiment of the present disclosure, the range of the predetermined ratio is 3 or more and 11 or less. This may be possible, but is not limited to this.

[0079] In at least one embodiment of the present disclosure, the predetermined width range is greater than or equal to 12 μm and less than or equal to 45 μm. The following may be possible, but is not limited to this.

[0080] In at least one embodiment of the present disclosure, the first predetermined length is greater than or equal to 50 μm and less than or equal to 130 μm. It may be m or less, but is not limited to this.

[0081] As shown in FIGS. 3A and 8, the first output line portion E01 is set in the overlapping region of the signal lines. The second signal line of the output transistor T10 is connected to the first signal line via holes H01. The first output line portion E01 is coupled to the electrode D10, and is provided in the overlapping region of the signal lines. The second signal line via holes H02 are connected to the first terminal of the output reset transistor T9. The first signal line via holes H01 are connected to the second electrode D9, and the first signal line via holes H01 are arranged sequentially along the first direction. the plurality of second signal line via holes H02 are arranged sequentially along the first direction. , 4 and 10 (FIG. 10 is a schematic diagram of the source-drain metal layer of FIG. 3A, and FIG. 10 First source-drain metal pattern Ds1 and second source-drain metal pattern Ds2 ) the overlapping areas of the signal lines are the overlapping areas A01 of the first signal lines and The overlapping area A01 of the first signal line includes an overlapping area A02 of the second signal line. The orthogonal projection of the output line portion E01 at the base and the second electrode D of the output transistor T10 10 includes a first source-drain metal pattern Ds1 and an orthogonal projection of the first source-drain metal pattern Ds1 at the base. The overlapping area A02 of the second signal line is an overlapping area in front of the first output line portion E01. The orthogonal projection on the base and the second electrode D9 of the output reset transistor T9 are included. 2 is the overlap region with the orthogonal projection at the base of the source-drain metal pattern Ds2, As shown in FIGS. 4 and 10, the first signal lines are arranged sequentially along the first direction. the maximum distance K1 in the first direction between the via hole and the last first signal line via hole; The ratio of the length L3 to the length L4 is a third predetermined ratio, and the ratio between two adjacent first signal line via holes is The minimum distance in the first direction is a first predetermined distance, and the third length L3 is the is the length of the overlapping area A01 in the first direction, The first second signal line via hole and the last second signal line via hole are arranged sequentially along the first direction. The ratio of the maximum distance K2 in the first direction to the signal line via hole to the fourth length L4 is a fourth predetermined The minimum distance between two adjacent second signal line via holes in the first direction is The fourth length L4 is a predetermined distance in the first direction of the overlapping area A02 of the second signal line. is the length of

[0082] In at least one embodiment of the present disclosure, the number of the first signal line via holes and the number of the second signal line The number of via holes may be selected according to the actual situation.

[0083] In at least one embodiment of the present disclosure, any two of the electrodes arranged sequentially along the first direction The maximum distance between the first signal line via holes in the first direction is the distance between any two first signal line via holes. is the maximum distance in the first direction between the orthogonal projection of the hole's base and its perimeter, The first signal line via hole and the last first signal line via hole are arranged sequentially along the first direction. The maximum distance K1 in the first direction from the signal line via hole is the distance from the first signal line via hole to the first signal line via hole. the periphery of the orthogonal projection at the base of the via hole and the base of the last first signal line via hole is the maximum distance in the first direction between the orthographic projection perimeter at The minimum distance K01 in the first direction between two adjacent first signal line via holes is is the minimum distance in the first direction around the orthogonal projection of the base of the adjacent first signal line via hole; , The first second signal line via hole and the last second signal line via hole are arranged sequentially along the first direction. The maximum distance K2 in the first direction from the signal line via hole is the distance from the first second signal line via hole to the the periphery of the orthogonal projection at the base of the via hole and the base of the last second signal line via hole is the maximum distance in the first direction between the orthographic projection perimeter at In the first direction, any two second signal line via holes arranged sequentially along the first direction The maximum distance is the periphery of the orthogonal projection of the base of any two second signal line via holes. is the maximum distance in the first direction between The minimum distance K02 in the first direction between two adjacent second signal line via holes is The minimum distance in the first direction between the peripheries of the orthogonal projections at the bases of two adjacent second signal line via holes is.

[0084] In at least one embodiment of the present disclosure, the first predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9. There may be, but is not limited to, The first predetermined distance may be, but is not limited to, 1.5 μm or more and 45 μm or less. figure, The second predetermined ratio may be, but is not limited to, 0.05 or more and 0.9 or less. The second predetermined distance may be, but is not limited to, 1.5 μm or more and 65 μm or less. do not have.

[0085] As shown in FIGS. 3A, 4 and 10, the T10 active layer and the T9 active layer is lengthened in the vertical direction, the third length L3 and the fourth length L4 are also lengthened accordingly. As a result, a plurality of first signal line via holes H01 are uniformly arranged in the overlapping area A01 of the first signal lines. The first signal line via hole from top to bottom and the last first signal line via hole from top to bottom can be arranged in a row. The ratio of the maximum distance K1 in the first direction to the signal line via hole to the third length L3 is a third predetermined The ratio of the first signal line via holes H01 to the first signal line overlapping area A0 1 as tight as possible, so that the second electrode D10 of the output transistor T10 can be more effectively connected to E0 can be combined into 1, As shown in FIGS. 3A, 4 and 10, the T10 active layer and the T9 active layer is lengthened in the vertical direction, the third length L3 and the fourth length L4 are also lengthened accordingly. As a result, a plurality of second signal line via holes H02 are uniformly arranged in the overlapping area A02 of the second signal lines. The first second signal line via hole from top to bottom and the last second signal line via hole from top to bottom can be arranged in a row. The ratio of the maximum distance K2 in the first direction to the signal line via hole to the fourth length L4 is a fourth predetermined ratio. and the plurality of second signal line via holes H02 are located within the overlapping region A02 of the second signal lines. to the second electrode D9 of the output reset transistor T9 as tight as possible, It can be combined with 01.

[0086] In at least one embodiment of the present disclosure, the third predetermined ratio is greater than or equal to 0.05 and less than or equal to 0.9. The fourth predetermined ratio may be 0.05 or more and 0.9 or less, This is not limited to this.

[0087] The display substrate according to at least one embodiment of the present disclosure includes a scanning drive circuit provided on a base. the scanning driving circuit includes a plurality of shift register units; At least one of the plurality of shift register units comprises: The output circuit includes a signal output line and an output circuit, the output circuit including an output transistor and an output reset transistor. Including transistors, the signal output line includes a first output line portion extending along a first direction; The first output line portion is connected to a plurality of first signal line via holes provided in the overlapping region of the signal lines. the first output line portion is coupled to the second electrode of the output transistor via the The output reset transistor is connected to the second signal line via holes provided in the overlapping region of the lines. the first signal line via holes are connected to the second electrodes of the transistors, and the first signal line via holes are arranged in a first direction. Next, the plurality of second signal line via holes are arranged sequentially along a first direction, The overlapping region of the signal lines includes an overlapping region of a first signal line and an overlapping region of a second signal line. The overlapping area of the first signal line is a projection of the first output line portion at the base and a front projection of the first output line portion. The base of the first source-drain metal pattern includes a second electrode of the output transistor. The overlapping area of the second signal line is an overlapping area of the first output line portion. a second electrode of the output reset transistor; an overlap region with an orthogonal projection at said base of the source-drain metal pattern; In the first direction, any two first signal line via holes arranged sequentially along the first direction a ratio of the maximum distance between the first signal line via holes and the third length is a first predetermined ratio, and a first predetermined distance between the first and second signals; is the length of the overlapping area of the lines in the first direction, In the first direction, any two second signal line via holes arranged sequentially along the first direction the ratio of the maximum distance to the fourth length is a second predetermined ratio, and two adjacent second signal line via holes the minimum distance between the first and second signals in the first direction is a second predetermined distance, and the fourth length is is the length of the overlapping area of the lines in the first direction, the first predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.9, the first predetermined distance is equal to or greater than 1.5 μm and equal to or less than 45 μm, the second predetermined ratio is 0.05 or more and 0.9 or less, The second predetermined distance is not less than 1.5 μm and not more than 65 μm.

[0088] Optionally, the active layer of the output transistor and the output reset transistor The active layer is arranged along a first direction, and in front of the active layer of the output transistor. The length in the first direction is defined as a first length, and the length of the active layer of the output reset transistor is defined as a The length in the first direction is defined as a second length, and the sum of the first length and the second length is the output actuator. is the tip length, a minimum width of the active layer of the output transistor along the second direction; and the minimum width of the active layer of the transistor along the second direction, the smaller of which is defined as the output active layer. The width of the first direction is set to be a tape width, and the first direction and the second direction intersect with each other.

[0089] In at least one embodiment of the present disclosure, the output active length and the output active width The ratio is within a predetermined ratio range, and the predetermined ratio range is 3 or more and 11 or less. This is also fine, but it is not limited to this.

[0090] In at least one embodiment of the present disclosure, increasing the output active length Among the output register units, elements other than the output circuit have an increased output active length. The layout can be done by utilizing the extra space in the direction. The horizontal space occupied by the unit can be reduced. In the embodiment, the active layer of the output transistor and the active layer of the output reset transistor As the layer is lengthened in the vertical direction, the third length and the fourth length are lengthened accordingly. Therefore, a plurality of first signal line via holes can be uniformly arranged in the overlapping region of the first signal lines, and the ratio of the maximum distance in the first direction between any two first signal line via holes to the third length is a first predetermined value; The plurality of first signal line via holes are formed in the overlapping region of the first signal lines at a fixed rate. the second electrode of the output transistor to better couple to the first output line portion. can be, As shown in FIGS. 3A, 4 and 10, the active layer of the output transistor and the output reset As the active layer of the gate transistor is lengthened in the vertical direction, the third length and The fourth length is increased, so that the plurality of second signal line via holes are arranged in the overlapping region of the second signal line. and the first direction of any two second signal line via holes from top to bottom. a ratio of the maximum distance to the fourth length is a second predetermined ratio, and the plurality of second signal line via holes The output reset transistor can be tightly packed in the overlapping region of the second signal line. The second electrode can be better coupled to the first output line portion.

[0091] In at least one embodiment of the present disclosure, the output active width is within a predetermined width range. Good too.

[0092] In at least one embodiment of the present disclosure, the output active width can be reduced, and the horizontal The remaining space is allocated to the shift register unit, except for the output circuit. The layout can be performed by using the elements, and the occupancy of the shift register unit can be reduced. It is also possible to reduce the horizontal space required.

[0093] Optionally, as shown in FIGS. 3A and 5, the active layer of the output transistor T10 The active layer of the output reset transistor T9 is a single continuous first semiconductor layer. the first semiconductor layer may be formed by extending along a first direction 10; As shown in FIG. 5, the length of the first semiconductor layer 10 in the first direction is an output active length L 1, The minimum length of the first semiconductor layer 10 in the second direction is the output active length W1. .

[0094] As shown in FIG. 3A, the output transistor T10 and the output reset transistor T11 Although T9 are arranged sequentially along the first direction, this is not limited thereto, and in actual operation, The output reset transistor T9 and the output transistor T10 are arranged sequentially along the first direction. They may be installed in a row.

[0095] In at least one embodiment of the present disclosure, the output reset transistor T9 receives an invalid light emission control signal. The output transistor T10 provides an effective light-emitting control signal. It is used in this regard.

[0096] In at least one embodiment of the present disclosure, the effective light-emitting control signal is a light-emitting control signal of a pixel circuit. It may be a voltage signal that can turn on the control transistor (the light emission control transistor a gate electrode of the transistor is coupled to the light emission control line, and the invalid light emission control signal is It may also be a voltage signal that can turn off the light emission control transistor.

[0097] Specifically, the display area of the display substrate includes a plurality of sub-pixels, At least one of the sub-pixels includes a pixel driving circuit, and the pixel driving circuit includes a transistor. a shift register included in the scan driving circuit, the shift register including a gate line, a light emitting control line, and a data line; The register unit may correspond to at least one light emission control line, and each of the shift registers The signal output line of the star unit is coupled to at least one corresponding light emission control line, The light emitting control signal is provided to the light emitting control line.

[0098] In at least one embodiment of the present disclosure, the active layer of the output transistor and the reset The active layer of the bit transistor may be formed by a single continuous first semiconductor layer. , The active layers of the output transistors are at least two layers that are arranged opposite to each other along a first direction. Each of the first conductive portions may include two first conductive portions and at least one first channel portion, each of the first channel portions is disposed between two adjacent first conductive portions; The active layers of the output reset transistors are arranged opposite to each other along a first direction. and at least one second channel portion. Each of the second channel portions is provided between two adjacent second conductive portions. And, The active layer of the output transistor and the active layer of the output reset transistor The first conductive portion closest to the second conductive portion of the output reset transistor is The output transistor and the output reset transistor may be used as a common component. This allows the layout space of the display to be further reduced, thereby realizing a narrower frame for the display substrate. to be advantageous to both parties.

[0099] As shown in FIG. 5, the active layer of the output transistor T10 and the output reset The active layer of transistor T9 may be formed by a single continuous first semiconductor layer. , The active layers of the output transistors T10 are disposed opposite each other along the first direction. The first conductive portion 111, the second conductive portion 112, the third conductive portion 11 The third and fourth first conductive portions 114, the fifth first conductive portion 115, and the sixth first conductive portion The active layer of the output transistor T10 includes a first channel Part 121, second first channel part 122, third first channel part 123, fourth further comprising a third first channel portion 124 and a fifth first channel portion 125; The first first channel portion 121 is connected to the first first conductive portion 111 and the second first conductive portion 112. the second first conductive portion 112 and the second first channel portion 122 is provided between the second first conductive portion 112 and the third first conductive portion 113. It is The third first channel portion 123 is connected to the third first conductive portion 113 and the second first conductive portion 114. and the fourth conductive portion 114, and the fourth first channel portion 12 4 is provided between the fourth first conductive portion 114 and the fifth first conductive portion 115. The fifth first channel portion 125 is connected to the fifth first conductive portion 115. and the sixth first conductive portion 116, The sixth first conductive portion 116 is the active terminal of the output reset transistor T9. The first conductive portion of the layer is also used as the second conductive portion. The active layers of the output reset transistors T9 are arranged opposite to each other in the first direction. The second conductive portion 132, the third conductive portion 133, and the fourth conductive portion a fifth second conductive portion 134, a fifth second conductive portion 135, and a sixth second conductive portion 136; The active layer of the output reset transistor T9 is the first second channel portion 141 , the second second channel portion 142, the third second channel portion 143, the fourth second channel portion a fifth second channel portion 144 and a fifth second channel portion 145; The first second channel portion 141 includes a first second conductive portion and a second second conductive portion. The second channel portion 142 is provided between the second channel portion 132 and the second channel portion 142. and the third second conductive portion 133. The third second channel portion 143 is connected to the third second conductive portion 133 and the fourth second conductive portion 144. 34, and the fourth second channel portion 144 is provided between the fourth the fifth second conductive portion 134 and the fifth second conductive portion 135; The second channel portion 145 is formed by connecting the fifth second conductive portion 135 and the sixth second conductive portion 136. It is located between 36.

[0100] In the output transistor T10 and the output reset transistor T9, The conductive portions on either side of the channel portion of the transistor correspond to the first conductive portions of the transistor. The first electrode and the second electrode of the transistor may be used as the first electrode and the second electrode of the transistor, respectively. and T10 and T9 may be coupled to the second electrode of the sixth first conductive portion. 116 to allow electrical connection.

[0101] When the first semiconductor layer 10 is fabricated, for example, a first semiconductor material layer is first formed. After that, the gate electrode G10 of the output transistor T10 and the output reset transistor T9 After forming the gate electrode G9, the gate of each transistor is formed in the first semiconductor material layer. The first semiconductor is then coated with a conductive material, and the conductive portion is formed of a portion that is not covered by the conductive electrode. The portion of the semiconductor material layer covered by each transistor is formed as the channel portion. The gate electrode G10 of the output transistor T10 and the output reset transistor T11 are connected to each other. The gate electrode G9 of the transistor T9 is used as a mask to form the first semiconductor material layer. The portion not covered by the gate electrode may be doped.

[0102] The specific configuration of the display substrate described above allows the display substrate described in at least one embodiment of the present disclosure to be In the shift register unit, the output transistor T10 and the output reset The shift register unit may include a plurality of shift transistors T9 arranged along the first direction. The area in the second direction is reduced, so that the display substrate can further meet the development demand for narrower frames. This can be done.

[0103] Specifically, the gate electrode of the output transistor is connected to at least one output gate electrode panel. The first electrode of the output transistor may include at least one first electrode a second electrode of the output transistor including at least one second electrode pattern; Including The output gate electrode pattern is formed by connecting the first electrode pattern and the second electrode pattern adjacent to each other. It is located between The first electrode pattern, the output gate electrode pattern, and the second electrode pattern are all These also extend along the second direction.

[0104] Specifically, the gate electrode of the output reset transistor is connected to at least one output reset transistor. The first electrode of the output reset transistor may include a gate electrode pattern. At least one third electrode pattern, and the second electrode of the output reset transistor , including at least one fourth electrode pattern; The output reset gate electrode pattern is connected to the adjacent third electrode pattern and the fourth electrode pattern. Located between the polar patterns, The third electrode pattern, the output reset gate electrode pattern, and the fourth electrode pattern Each of the electrodes extends along the second direction, The output reset transistor closest to the gate electrode of the output transistor The fourth electrode pattern is also used as the second electrode pattern of the output transistor. .

[0105] In particular, the number of the output reset gate electrode patterns, the number of the first electrode patterns, the number of turns, the number of the second electrode patterns, the number of the output gate electrode patterns, The number of the third electrode patterns and the number of the fourth electrode patterns may be determined according to actual needs. For example, as shown in FIGS. 6 and 9, the number of the output gate electrode patterns may be The number of the output reset gate electrode patterns may be five, and the number of the first electrode patterns may be five. The number of turns may be three, and the number of second electrode patterns may be three. The number of the third electrode patterns may be three, and the number of the fourth electrode patterns may be three. It may be one of the above, but is not limited to this.

[0106] The second electrode of the output transistor and the second electrode of the output reset transistor are Since both are connected to the signal output line, the output transistor and the output reset transistor When performing layout, among the output reset transistors, The fourth electrode pattern closest to the gate electrode is the second electrode pattern of the output transistor. The output transistor and the output reset transistor may be used as a common transistor. This allows the layout space of the monitor to be further reduced, enabling the display board to have a narrower frame. Make it advantageous.

[0107] As shown in FIGS. 3A and 6, in some embodiments, the gate of the output transistor T10 The output electrodes are a first output gate electrode pattern G101 and a second output gate electrode pattern G102. 2. The third output gate electrode pattern G103, the fourth output gate electrode pattern G104, and 5 output gate electrode pattern G105, The gate electrode of the output reset transistor T9 is a first output reset gate electrode pattern. pattern G91, second output reset gate electrode pattern G92, third output reset gate electrode pattern G93, the fourth output reset gate electrode pattern G94 and the fifth output reset gate electrode pattern G95. may include a gate electrode pattern G95, The first output gate electrode pattern G101, the second output gate electrode pattern G102, the third output gate electrode pattern G103, The fourth output gate electrode pattern G103, the fourth output gate electrode pattern G104 and the fifth output gate electrode pattern G105 are The electrode patterns G105 are arranged sequentially along the first direction, First output reset gate electrode pattern G91, second output reset gate electrode pattern G 92, third output reset gate electrode pattern G93, fourth output reset gate electrode pattern The fifth output reset gate electrode pattern G94 and the fifth output reset gate electrode pattern G95 are arranged sequentially along the first direction. And, The first output gate electrode pattern G101, the second output gate electrode pattern G102, the third output gate electrode pattern G103, The fourth output gate electrode pattern G103, the fourth output gate electrode pattern G104 and the fifth output gate electrode pattern G105 are The first and second directions are alternately arranged. Crossed each other, The first output gate electrode pattern G101, the second output gate electrode pattern G102, the third output gate electrode pattern G103, The fourth output gate electrode pattern G103, the fourth output gate electrode pattern G104 and the fifth output gate electrode pattern G105 are The electrode patterns G105 are connected to each other, First output reset gate electrode pattern G91, second output reset gate electrode pattern G 92, third output reset gate electrode pattern G93, fourth output reset gate electrode pattern The fifth output reset gate electrode pattern G94 and the fifth output reset gate electrode pattern G95 are both extended along the second direction. There is, First output reset gate electrode pattern G91, second output reset gate electrode pattern G 92, third output reset gate electrode pattern G93, fourth output reset gate electrode pattern The fifth output reset gate electrode pattern G94 and the fifth output reset gate electrode pattern G95 are coupled to each other, As shown in FIG. 9, the first electrode S10 of the output transistor T10 is connected to the first first electrode S10. the first electrode pattern S101, the second first electrode pattern S102, and the third first electrode pattern S103; Including S103, The second electrode D10 of the output transistor T10 is the first second electrode pattern D101 and a second second electrode pattern D102, The first electrode S9 of the output reset transistor T9 is the first third electrode pattern S9 1, the second third electrode pattern S92 and the third third electrode pattern S93, The second electrode D9 of the output reset transistor T9 is the first fourth electrode pattern D9 The first and second fourth electrode patterns D92 and the third fourth electrode pattern D93 are included, The first fourth electrode pattern D91 is the third fourth electrode pattern included in the output transistor T10. It is used as a two-electrode pattern, As shown in FIGS. 3A to 10, S101 is bound to VGL, and S101 is bound to S102. S103 is coupled to VGL, and S91, S92 and S93 are each a first conductive conductor. the first conductive connection F1 is coupled to the first voltage signal line VGH; As shown in FIGS. 3A to 10, the first output line portion E01 is provided in the overlapping region of the signal lines. The first signal lines are coupled to D101 and D102 through via holes H01. The first output line portion E01 is formed by a plurality of second signal lines provided in an overlapping region of the signal lines. are connected to D91, D92 and D93 through via holes H02, respectively; The plurality of first signal line via holes H01 are sequentially arranged along a first direction, The second signal line via holes H02 are arranged sequentially along the first direction.

[0108] In particular, the active layer of the output transistor is oriented in a first direction. At least two first conductive portions and at least one first channel portion are provided facing each other. and each of the first channel portions may include two adjacent first conductive portions. It is located between The first channel portions correspond one-to-one to the output gate electrode patterns, and each of the first The orthogonal projections of the channel portions on the base are all aligned with the corresponding output gate electrode patterns. is located inside the orthogonal projection at the base of The first conductive portion of some of the output transistors is paired with the first electrode pattern. The orthogonal projection of the first electrode pattern on the base and the corresponding first conductive portion and an orthogonal projection of the first electrode pattern at the base of the first electrode pattern. The first via hole is formed in the overlapping region. coupled to the conductive portion, The first conductive portions of the other part of the output transistors are connected to the second electrode pattern. The orthogonal projection of the second electrode pattern on the base and the corresponding first electrode pattern are in one-to-one correspondence. and an orthogonal projection of the electrode portion at the base has a second overlap region, and the second electrode pattern is The corresponding via hole is formed in the second overlapping region. coupled to the first conductive portion.

[0109] In particular, the active layer of the output reset transistor is At least two second conductive portions and at least one second channel are provided opposite to each other along the each of the second channel portions includes two adjacent second conductive portions; It is set between The second channel portions correspond one-to-one to the output reset gate electrode patterns, The orthogonal projections of the second channel portions on the base are all aligned with the corresponding output reset gates. located within an orthogonal projection of a port electrode pattern on said base; The second conductive portions of some of the output reset transistors are connected to the third electrode pattern. and a one-to-one correspondence is established between the orthogonal projection of the third electrode pattern on the base and the corresponding and an orthogonal projection of the second conductive portion on the base has a third overlap region, and the third electrode pattern is and a corresponding via hole formed in the third overlapping region. coupled to the second conductive portion, The second conductive portion of the other part of the output reset transistor is connected to the fourth electrode pad. The fourth electrode pattern is orthogonally projected onto the base and the corresponding front electrode pattern is formed in one-to-one correspondence with the turn. and an orthogonal projection of the second conductive portion on the base has a fourth overlapping region, and the fourth electrode pattern The pins are connected to each other through at least one fourth via hole provided in the fourth overlapping region. The second conductive portion is coupled to the corresponding second conductive portion.

[0110] As shown in FIGS. 5, 6, 8 and 9, the first first channel portion 121 is The second first channel portion 122 corresponds to the gate electrode pattern G101 and is a second output gate. The third first channel portion 123 corresponds to the third output gate electrode pattern G102. The fourth first channel portion 124 corresponds to the fourth output gate electrode pattern G103. The fifth first channel portion 125 corresponds to the electrode pattern G104, and is a fifth output gate electrode. Compatible with polar pattern G105, The orthogonal projection of the first channel portion 121 at the base of the first output gate electrode pattern Located inside the orthographic projection at the base of G101, The orthogonal projection at the base of the second first channel portion 122 is a second output gate electrode pattern Located inside the orthographic projection at the base of G102, The orthogonal projection at the base of the third first channel portion 123 is a third output gate electrode pattern Located inside the orthographic projection at the base of G103, The orthogonal projection at the base of the fourth first channel portion 124 is a fourth output gate electrode pattern Located inside the orthographic projection at the base of G104, The orthogonal projection at the base of the fifth first channel portion 125 is a fifth output gate electrode pattern Located inside the orthographic projection at the base of the G105, The first conductive portion 111 corresponds to the first electrode pattern S101, and the second conductive portion 111 corresponds to the first electrode pattern S101. The first conductive portion 112 corresponds to the first second electrode pattern D101, and the third first conductive portion The fourth first conductive portion 113 corresponds to the second first electrode pattern S102, and the fourth first conductive portion 114 corresponds to the fourth first electrode pattern S103. 14 corresponds to the second second electrode pattern D102, and the fifth first conductive portion 115 corresponds to the third The sixth first conductive portion 116 corresponds to the first first electrode pattern S103, and the sixth first conductive portion 116 corresponds to the first first electrode pattern S103. Compatible with 4-electrode pattern D91, The sixth first conductive portion 116 is the active terminal of the output reset transistor T9. The first conductive portion of the layer is also used as the second conductive portion. The first second channel portion 141 corresponds to the first output reset gate electrode pattern G91. The second second channel portion 142 is connected to the second output reset gate electrode pattern G92. The third second channel portion 143 corresponds to the third output reset gate electrode pattern G9 3, and the fourth second channel portion 144 corresponds to the fourth output reset gate electrode pattern G94, the fifth second channel portion 145 is a fifth output reset gate electrode pattern. It is compatible with G95, The orthogonal projection at the base of the first second channel portion 141 is the first output reset gate electrode. Located inside the orthographic projection at the base of pattern G91, The orthogonal projection at the base of the second second channel portion 142 is a second output reset gate electrode. Located inside the orthographic projection at the base of pattern G92, The orthogonal projection at the base of the third second channel portion 143 is a third output reset gate electrode. Located inside the orthographic projection at the base of pattern G93, The orthogonal projection at the base of the fourth second channel portion 144 is a fourth output reset gate electrode. Located inside the orthographic projection at the base of pattern G94, The orthogonal projection at the base of the fifth second channel portion 145 is a fifth output reset gate electrode. Located inside the orthographic projection at the base of pattern G95, The second second conductive portion 132 corresponds to the first third electrode pattern S91, and the third The second conductive portion 133 corresponds to the second fourth electrode pattern D92, and the fourth second conductive portion The second conductive portion 134 corresponds to the second third electrode pattern S92, and the fifth second conductive portion 135 corresponds to the The sixth second conductive portion 136 corresponds to the third fourth electrode pattern D93, and the sixth second conductive portion 136 corresponds to the third fourth electrode pattern D94. 3 Electrode pattern S93 is supported. S101 at the base and the orthogonal projection of the first conductive portion 111 at the base. The first overlap region is between the first and second conductive layers. The orthogonal projection at the base of the portion 113 has a second first overlapping area between the first and second overlapping areas. The third first conductive portion 115 is located between the orthogonal projection at the base of the fifth first conductive portion 115 and the orthogonal projection at the base of the fifth first conductive portion 115. The first via hole S101 is provided in the first overlapping region. S102 is coupled to the first conductive portion 111 through the first conductive portion H1, and S103 is coupled to the second conductive portion 112 through the first conductive portion H2. The third first conductive portion 113 is coupled to the third first conductive portion 113 through a first via hole H1 provided in the region. S103 is connected to the third first overlapping region through the first via hole H1. and coupled to the fifth first conductive portion 115, D101 at its base and the orthogonal projection of the second first conductive portion 112 at its base. There is an overlap area between the first and second, and the orthographic projection at the base of D102 and the fourth. The conductive portion 114 has a second overlapping region, and the conductive portion 114 has a second overlapping region. The second conductive portion 112 is coupled to the second conductive portion 112 through a second via hole H2 provided in the region. D102 is connected to the second via hole H2 provided in the second overlapping region. and coupled to the fourth first conductive portion 114, Between the orthogonal projection at the base of D91 and the orthogonal projection at the base of the first second conductive portion 131 The first has a fourth overlapping area, and the third has an orthogonal projection at the base of D92 and a second conductive part. The orthogonal projection at the base of 133 has a second, fourth overlap area with the orthogonal projection at the base of D93. The orthogonal projection has a third fourth overlapping area between the fifth second conductive portion 135, and D91 is connected to the first second via hole H4 provided in the first fourth overlapping region. D92 is coupled to the conductive portion 131, and D93 is coupled to the fourth via provided in the second fourth overlap region. D93 is coupled to the third second conductive portion 133 via hole H4, and D93 is coupled to the third fourth conductive portion 133 via hole H5. The fifth second conductive portion 133 is connected to the fourth via hole H4 provided in the overlapping region. Combined, Between the orthogonal projection at the base of S91 and the orthogonal projection at the base of the second conductive portion 132 The first has a third overlapping area, and the fourth has an orthogonal projection at the base of S92 and a second conductive part. The orthogonal projection at the base of 134 has a second third overlap area with the orthogonal projection at the base of S93. a third overlap between the orthogonal projection and the orthogonal projection at the base of the sixth second conductive portion 136; S91 has a third via hole H3 provided in the first third overlapping region. and S92 is connected to the second second conductive portion 132 via the second third overlap region. and S9 is coupled to the fourth second conductive portion 134 through a third via hole H3 provided therein. 3 is connected to the sixth via hole H3 through the third via hole H3 provided in the third overlapping region. 2 is coupled to conductive portion 136.

[0111] In at least one embodiment of the present disclosure, the number of first via holes, the number of second via holes, the number of third via holes, The number of the three via holes and the number of the fourth via holes may be determined according to actual needs.

[0112] In the layout scheme shown in FIG. 3A, the number of first via holes, the number of second via holes, The number of via holes is three, but in actual operation, The number of holes can be selected according to the actual situation, for example, as shown in FIG. In this layout method, the number of first via holes, the number of second via holes, the number of third via holes, The number of rules may be two. In the layout method shown in FIG. The length of the first semiconductor layer in the first direction is longer (compared to the layout scheme shown in FIG. 3A ). , the width of the first semiconductor layer in the second direction is narrower (compared to the layout scheme shown in FIG. 3A ). This contributes to narrowing the width of the shift register unit in the second direction, realizing a narrow frame. is advantageous.

[0113] In the display substrate according to the above embodiment, the first semiconductor layer 10 is used to form an output reset transistor. The active layer of the output transistor T9 and the active layer of the output transistor T10 are formed. This not only reduces the space taken up by T9 and T10 in the second direction, but also reduces the size of the output reset transistor. The active layer of the output transistor T9 and the active layer of the output transistor T10 are By increasing the size, the width of the T9 channel and the width of the T10 channel are secured, and It ensures the performance of T9 and T10, and also reduces the width of the display board frame. It is possible.

[0114] In at least one embodiment of the present disclosure, FIG. 5 is a schematic diagram of the active layer of FIG. 3A. 6 is a schematic diagram of the first gate metal layer of FIG. 3A, and FIG. 7 is a schematic diagram of the second gate metal layer of FIG. 3A. 8 is a schematic diagram showing the sequential formation of an active layer, a first gate metal layer, and a second gate metal layer. Figure 9 shows a schematic diagram of the via hole fabricated after the source and drain metallization of Figure 3A is installed. FIG. 1 is a schematic diagram of a layer.

[0115] In particular, an active layer, a first gate metal layer, a second gate metal layer, and a second gate metal layer are sequentially formed on the base. A metal layer, a via hole, and a source / drain metal layer are provided to form a display substrate.

[0116] In at least one embodiment of the present disclosure, the at least one shift register unit comprises: In addition to the output transistor and the output reset transistor, it also includes multiple transistors. The conductive portions on both sides of the channel portion of each transistor may be respectively connected to the first The first and second electrodes of the transistor may be the first and second electrodes, respectively. It may be coupled to each of the second electrodes of the transistors.

[0117] As shown in FIGS. 3A to 9, S91, S92, and S93 are the first conductive connection parts F1 , and the first conductive connection F1 is coupled to the first voltage signal line VGH; The orthogonal projection at the base of the first conductive connection F1 and the first reset capacitor C3 a fifth overlapping region between the first conductive connection portion F and the orthogonal projection of the second electrode plate C3b at the base of the first conductive connection portion F; 1 is connected to the output reset terminal through a fifth via hole H5 provided in the fifth overlapping region. It is coupled to the second plate C3b of capacitor C3.

[0118] In particular, the at least one shift register unit comprises: may further comprise a distaster, The first transistor includes a first active pattern. The wire extends along the second direction, The first transistor is located on a side of the output circuit away from a display area. As shown in FIGS. 1 and 3A to 9, the at least one shift register unit may further include a first transistor T1; The first transistor T1 includes a first active pattern A1. The pattern A1 extends along the second direction, The first transistor T1 is located on the side of the output circuit O1 that is farther from the display area. do.

[0119] In at least one embodiment of the present disclosure, the first active pattern A1 in T1 is T2 and T8 are installed closer together to extend along the horizontal direction. It can save space.

[0120] As shown in FIGS. 3A to 9, the first transistor T1 is in the first active pattern A. 1, and the first active patterns A1 include 1-numbered active patterns A1 arranged sequentially along the second direction. The third conductive portion A11, the third channel portion A10 and the second third conductive portion A12 are included. fruit, The first third conductive portion A11 is also used as the first electrode S1 of the first transistor T1, The second third conductive portion A12 is also used as the second electrode D1 of the first transistor T1, The first electrode S1 of the first transistor T1 is connected to the second The second conductive connection F2 is coupled to the orthogonal projection at the base of the second conductive connection F2 and the output connector a sixth overlapping region between the second electrode C2b of the capacitor C2 and the orthogonal projection of the second electrode C2b at the base of the capacitor C2; The second conductive connection portion F2 is connected to the sixth via hole H6 provided in the sixth overlapping region. and coupled to the second plate C2b of the output capacitor C2. The second electrode D1 of T1 is coupled to the third conductive connection F3 through the second connection via hole H21. and an orthogonal projection at the base of the third conductive connection F3 and a projection at the base of the second electrode plate C1b of C1. The seventh overlapping area is between the orthogonal projection of F1 and F2, and F3 is located in the seventh overlapping area. coupled to the second plate C1b of C1 through via hole H7; The gate electrode G1 of T1 is coupled to the first plate C1a of C1, and the gate electrode G1 of T1 is , and is also coupled to the gate electrode G8 of T8.

[0121] As shown in FIG. 3A, the first portion of the plate of the output capacitor C2 between T4 and T10 The width in two directions is narrowed, and the width in the second direction of the part between T7 and T10 of the C2 plate is also narrowed. This saves space in the second direction and allows the remaining area to be used for layout of other elements. Moreover, as shown in FIG. 3A, the length of the electrode plate of C2 in the first direction is also long. This ensures the area of the C2 plate.

[0122] In at least one embodiment of the present disclosure, as shown in FIGS. 1 and 3A to 9, One shift register unit further includes a second transistor T2 and a third transistor T3. It may also include, The orthogonal projection of the gate electrode G2 of the second transistor T2 on the base and the third transistor The maximum distance in the second direction between the orthogonal projection of the gate electrode G3 of the transistor T3 on the base is a third predetermined distance; The second transistor T2 and the third transistor T3 are connected to the display area of the output circuit. It is located on the far side of the The second electrode D2 of the second transistor T2 is connected to the second electrode D of the third transistor T3. Combined into 3.

[0123] In at least one embodiment of the present disclosure, the third predetermined distance is greater than or equal to 14 μm and less than or equal to 50 μm. It may be below, but is not limited to this.

[0124] In particular, the second electrode D2 of the second transistor T2 is connected to the third transistor T3. Since the second electrode D2 of the transistor T3 is connected to the second electrode D2 of the transistor T2, the transistors T2 and T3 are placed close to each other for wiring convenience. It is necessary to place T2 and T3 close to each other, and the shift register unit This can contribute to narrowing the width in the second direction.

[0125] In at least one embodiment of the present disclosure, the gate electrode G2 of the second transistor T2 and the gate electrode G3 of the third transistor T3 is projected orthogonally on the base. The maximum distance between the shadow and the second direction is shorter than the third predetermined distance, which is the base of G2. The maximum distance in the second direction between the orthogonal projection perimeter of and the orthogonal projection perimeter at the base of G3 is It is shorter than a predetermined distance.

[0126] As shown in FIGS. 3A-9, the second transistor T2 includes a second active pattern. , The second active pattern A2 is a first fourth active pattern arranged sequentially along the first direction. a fourth conductive portion A21, a fourth channel portion A20, and a second fourth conductive portion A22; The first fourth conductive portion A21 is also used as the first electrode S2 of the second transistor T2, The second fourth conductive portion A22 is also used as the second electrode D2 of the second transistor T2, The first electrode S2 of the second transistor T2 is connected to the third connection via hole H31. The third conductive connection F3 is coupled to the orthogonal projection at the base of the third conductive connection F3 and the second conductive connection F4 of C1. The seventh overlapping area is between the orthogonal projection at the base of the electrode plate C1b and F3. The second electrode plate C1b of C1 is connected to the seventh via hole H7 provided in the second a first electrode S2 of transistor T2 is coupled to a second plate C1b of transistor T1; The second electrode D2 of the second transistor T2 is connected to the fourth conductive via hole H41 through the fourth connecting via hole H41. coupled to the connection F4, The third transistor T3 includes a third active pattern A3; The third active pattern A3 is a first fifth active pattern arranged sequentially in the second direction. a conductive portion A31, a fifth channel portion A30, and a second fifth conductive portion A32; The first fifth conductive portion A31 is also used as the first electrode S3 of the third transistor T3, The second fifth conductive portion A32 doubles as the second electrode D3 of the third transistor T3; The first electrode S3 of the third transistor T3 is connected to bound to S91, S92 and S93, The second electrode D3 of the third transistor T3 is connected to the fourth conductive via hole H61 through the sixth connecting via hole H61. It is coupled to the connection part F4.

[0127] Optionally, the at least one shift register unit includes a first transistor, a second transistor, a transistor and a first capacitor, wherein: The second electrode of the first transistor and the first electrode of the second transistor are a gate electrode of the first transistor coupled to the second plate of the first capacitor; 1 coupled to the first plate of the capacitor, The first transistor, the first capacitor, and the second transistor are arranged along a first direction. are arranged in order, The first transistor, the first capacitor, and the second transistor form the output circuit. It is located on the side away from the road display area.

[0128] As shown in FIGS. 1 and 3A to 9, the at least one shift register unit The semiconductor device may further include a first transistor T1, a second transistor T2, and a first capacitor C1. Well, here, The second electrode D1 of the first transistor T1 and the first electrode D of the second transistor T2 2 are respectively coupled to the second plate C1b of the first capacitor C1 and the first transistor a gate electrode G1 of the transistor T1 is coupled to a first plate C1a of the first capacitor C1; The first transistor T1, the first capacitor C1, and the second transistor T2 are arranged sequentially along a first direction, The first transistor T1, the first capacitor C1, and the second transistor T2 are It is located on the side away from the display area of the output circuit O1.

[0129] In at least one embodiment of the present disclosure, C1 is located between T1 and T2, and T The arrangement positions of T1, T2 and T3 are matched to the shape of the C1 plate, T3 and C1 are arranged more closely. As shown, the scan driving circuit may further include a first voltage signal line VGH, and the At least one shift register unit further includes an output reset capacitor C3. The first electrode C3a of the output reset capacitor C3 may be connected to the output reset transformer. The second plate C of the output reset capacitor C3 is coupled to the gate electrode G9 of the transistor T9. 3b is coupled to the first voltage signal line VGH; The maximum width of the second plate C3b of the output reset capacitor C3 in the second direction is equal to or less than the first predetermined value. and the maximum length in the first direction of the second plate C3b of the output reset capacitor C3. is a second predetermined length, The output reset capacitor C3 is located on the side of the output circuit O1 that is farther from the display area. And, The orthogonal projection of the second plate C3b of the output reset capacitor C3 on the base is 1. The power reset capacitor C3 has a first plate C3a which is in an orthogonal projection at the base.

[0130] In at least one embodiment of the present disclosure, the first predetermined width is greater than or equal to 3 μm and less than or equal to 60 μm. The second predetermined length may be 3 μm or more and 20 μm or less. , but is not limited to this.

[0131] Optionally, as shown in FIG. 3A, the first voltage signal line VGH extends along a first direction. The first voltage signal line VGH is spaced apart from the display area of the output reset capacitor C3. It is located on the side.

[0132] In at least one embodiment of the present disclosure, the width of the second plate C3b of C3 in the second direction is set to be small. This narrows the width of the shift register unit in the second direction and secures the area of the C3 plate. To achieve this, the length of the second electrode C3b of C3 in the first direction is set to be large.

[0133] As shown in FIGS. 3A to 9, the first plate C3a of C3 is coupled to the gate electrode G9 of T9. , The orthogonal projection of the first electrode plate C3a of C3 at the base and the orthogonal projection of the fourth conductive connection F4 at the base are C3a has an eighth overlapping region between the projection and the eighth overlapping region. C3a is coupled to the fourth conductive connection F4 through a via hole H8. coupled to the second electrode D2 of the transistor T2, S91, S92 and S93 are respectively coupled to the first conductive connection F1, a connection F1 coupled to the first voltage signal line VGH; The orthogonal projection at the base of the first conductive connection F1 and the first reset capacitor C3 a fifth overlapping region between the first conductive connection portion F and the orthogonal projection of the second electrode plate C3b at the base of the first conductive connection portion F; 1 is connected to the output reset terminal through a fifth via hole H5 provided in the fifth overlapping region. The second plate C3b of the capacitor C3 is connected to S91, S92 and S93. are connected to each other.

[0134] In at least one embodiment of the present disclosure, as shown in FIGS. 3A to 9, the output transistor The scanning transistor T10 and the output reset transistor T9 are arranged along a first direction. The driving circuit further includes a second voltage signal line VGL, and the at least one shift register The unit further includes an output reset capacitor C3; The second electrode C3b of the output reset capacitor C3 is connected to the first voltage signal line VGH. Combined, a first electrode S10 of the output transistor T10 is coupled to a second voltage signal line VGL; The first electrode S9 of the output reset transistor T9 is connected to the output reset capacitor C3 coupled to the second electrode C3b of The output transistor T10 and the output reset transistor T9 are connected to the second voltage The signal line VGL is located on the side away from the display area.

[0135] Optionally, the scan driving circuit may further include a second voltage signal line, The other shift register unit may further include a fourth transistor; The second voltage signal line is coupled to an electrode conductive connection, and the electrode conductive connection is The at least one first electrode pattern is arranged sequentially along a first direction. Arranged, The electrode conductive connection portion is a first first electrode included in the first electrode of the output transistor. Combined into a pattern, a first electrode of the fourth transistor is coupled to the electrode conductive connection; the orthogonal projection of the gate electrode of the fourth transistor on the base and the electrode conductive connection The minimum distance in the first direction between the orthogonal projection at the base is a fourth predetermined distance.

[0136] In at least one embodiment of the present disclosure, the base of the gate electrode of the fourth transistor and the orthogonal projection of the electrode conductive connection on the base. The fourth transistor has a gate electrode whose base is orthogonally projected and whose conductive connection The minimum distance in the first direction between the perimeter of the orthogonal projection at the base of the part.

[0137] In at least one embodiment of the present disclosure, the fourth predetermined distance is greater than or equal to 1 μm and less than or equal to 5 μm. This may be the case, but is not limited to this. In at least one embodiment of the present disclosure, the output active length is increased and the fourth transformer the fourth transistor is moved upward, and the gate electrode of the fourth transistor is connected to the electrode conductive connection in the first direction By keeping the distance short, the output active length can be increased to provide more margin in the first direction. The space that is left behind can be used to arrange elements other than the output circuit included in the shift register unit. and further narrowing the width of the shift register unit in the second direction.

[0138] As shown in FIGS. 3A to 9, the scan driving circuit further includes a second voltage signal line VGL. and the at least one shift register unit further includes a fourth transistor T4. It may also include, The second voltage signal line VGL is coupled to the electrode conductive connection F01, F01 extends in the second direction and is connected to the first electrode S10 of the output transistor T10. The first electrode pattern S101, the second electrode pattern S102 and the third electrode pattern S103 are included. The first electrode patterns S103 are sequentially arranged along the first direction, the electrode conductive connection part F01 is coupled to the first electrode pattern S101; The first electrode S4 of the fourth transistor T4 is connected to the first electrode S4 of the fourth transistor T4 through an electrode connection via hole H0. coupled to the polar conductive connection F01, The orthogonal projection of the gate electrode G4 of the fourth transistor T4 on the base and the electrode conductive The minimum distance in the first direction between the orthogonal projection of the connection portion F01 on the base is set to a fourth predetermined distance. Therefore, S101 is moved upward and T4 is also moved upward.

[0139] As shown in FIG. 5, the fourth transistor T4 includes a fourth active pattern A4, The fourth active pattern A4 is a first sixth active pattern arranged sequentially along the first direction. a sixth conductive portion A41, a sixth channel portion A40, and a second sixth conductive portion A42; The first sixth conductive portion A41 is also used as the first electrode S4 of the fourth transistor T4, The second sixth conductive portion A42 also serves as the second electrode D4 of the fourth transistor T4.

[0140] In at least one embodiment of the present disclosure, the at least one shift register unit comprises: may further include a fourth transistor and a fifth transistor; The gate electrode of the fourth transistor is coupled to the gate electrode of the fifth transistor. , The gate electrode of the fourth transistor and the gate electrode of the fifth transistor are connected to the first gate. the first gate metal pattern is included in the second direction, and the first gate metal pattern extends along the second direction. do.

[0141] In particular, the fourth transistor and the fifth transistor are arranged side by side. The fourth transistor may be moved upward and the fifth transistor may also be moved upward. Move towards Optionally, the scan driving circuit may further include a first clock signal line, and the fifth a gate electrode of the transistor is coupled to the first clock signal line; The first clock signal line extends along a first direction, and the first clock signal line The fifth transistor is located on the side away from the display area.

[0142] As shown in FIGS. 1 and 3A to 9, the at least one shift register unit is The scan driving circuit may further include a fourth transistor T4 and a fifth transistor T5. may further include a first clock signal line CK, The gate electrode G4 of the fourth transistor T4 is connected to the gate electrode G5 of the fifth transistor T5. coupled to pole G5, The gate electrode G4 of the fourth transistor T4 and the gate electrode G5 of the fifth transistor T5 The pole G5 is included in the first gate metal pattern 45, and the first gate metal pattern 45 is It extends along two directions, The gate electrode G5 of the fifth transistor T5 is coupled to the first clock signal line CK. R, The first clock signal line CK extends along a first direction, CK is located on the side of the fifth transistor T5 that is farther from the display area.

[0143] As shown in FIGS. 3A to 9, an orthogonal projection at the base of the first gate metal pattern 45 is performed. a ninth overlapping region between the first clock signal line CK and the orthogonal projection of the first clock signal line CK at the base thereof; The first gate metal pattern 45 is connected to the ninth via hole H9 provided in the ninth overlapping region. is coupled to the first clock signal line CK via The first electrode S5 of T5 is coupled to the input signal terminal E1 through a seventh connecting via hole H71. do.

[0144] As shown in FIG. 5, the fifth transistor T5 includes a fifth active pattern A5; The fifth active pattern A5 is the first seventh active pattern arranged sequentially in the first direction. a seventh conductive portion A51, a seventh channel portion A50 and a second seventh conductive portion A52; The first seventh conductive portion A51 is also used as the first electrode S5 of the fifth transistor T5, The second seventh conductive portion A52 also serves as the second electrode D5 of the fifth transistor T5.

[0145] In concrete implementation, as shown in FIG. 1 and FIG. 3A to FIG. 9, The resistor unit includes a first transistor T1, a fourth transistor T4, a fifth transistor T5, and a The inverter may further include a sixth transistor T5, a sixth transistor T6, and an output capacitor C2, The second electrode D5 of the fifth transistor T5 is connected to the gate electrode of the sixth transistor T6. G6, and the first electrode S1 of the fifth transistor T5 is coupled to the input signal terminal E1. R, The gate electrode G6 of the sixth transistor T6 is connected to the first gate electrode pattern. a gate electrode pattern g61 and a second gate electrode pattern g62; The first gate electrode pattern g61 and the second gate electrode pattern g62 are and coupled to the first plate C2a of the output capacitor C2, Plate C2a is coupled to gate electrode S10 of output transistor T10; The first electrode S6 of the sixth transistor T6 is connected to the gate electrode G4 of the fourth transistor T4. and the second electrode D6 of the sixth transistor T6 is coupled to the The second electrode C2b of the output capacitor C2 is coupled to the second electrode D4 of the first transformer. coupled to the first electrode S1 of the transistor T1, The fourth transistor T4, the sixth transistor T6, and the first transistor T1 are sequentially arranged along the first direction, The fifth transistor T5, the sixth transistor T6, and the first transistor T1 are sequentially arranged along the first direction, The output capacitor C2 is located between the sixth transistor T6 and the output circuit O1. It is placed.

[0146] As shown in FIG. 5, the sixth transistor T6 includes a sixth active pattern A6, The sixth active pattern A6 is the first eighth active pattern A1 arranged sequentially in the first direction. Conductive portion A61, first eighth channel portion A601, second eighth conductive portion A62, 2 a third eighth channel portion A602 and a third eighth conductive portion A63; The first eighth conductive portion A61 is also used as the first electrode S6 of the sixth transistor T6, The third eighth conductive portion A63 also serves as the second electrode D6 of the sixth transistor T6.

[0147] As shown in FIGS. 3A to 9, the gate electrode of T6 is included in the second gate metal pattern 60. The second gate metal pattern 60 is U-shaped, and the gate electrodes of T6 are connected to each other. The first gate electrode pattern g61 and the second gate electrode pattern g62 are included. The second gate metal pattern 60 is connected to the fifth conductive connection via an eighth connection via hole H81. coupled to section F5, The second electrode D5 of T5 is connected to the fifth conductive connecting portion F5 through a ninth connecting via hole H91. The second electrode D5 of T5 is connected to the gate electrode of T6. and the first gate electrode pattern g61 and the second gate electrode pattern g62. death, The first electrode S6 of T6 is connected to the sixth conductive connecting portion F6 through the tenth connecting via hole H101. The first gate metal pattern 45 is connected to the first gate electrode 41 through the eleventh connection via hole H111. coupled to the sixth conductive connection F6, The second electrode D6 of T6 is connected to the seventh conductive connecting part F7 through the twelfth connecting via hole H121. The second electrode D4 of T4 is connected to the seventh conductive via hole H131 through the thirteenth connecting via hole H131. and coupled to connection F7 so that the second electrode D6 of T6 is coupled to the second electrode D4 of T4. do.

[0148] In at least one embodiment of the present disclosure, as shown in FIGS. 1 and 3A to 9, One shift register unit includes a second transistor T2, a first transistor T1, a sixth transistor T2, a The circuit may further include a transistor T6, a seventh transistor T7, and an eighth transistor T8. Ugh, here, As shown in FIG. 5, the active layer of the seventh transistor T7 and the active layer of the eighth transistor T8 are The active layer of the transistor T8 may be formed by a single continuous second semiconductor layer 20. The second semiconductor layer 20 extends along a first direction, The active layer of the seventh transistor T7 is formed by the first and second gate electrodes arranged sequentially along the first direction. The ninth conductive portion 211, the ninth channel portion 201, and the second ninth conductive portion 212 are included. fruit, The second ninth conductive portion 212 is also used as the first tenth conductive portion; The active layer of the eighth transistor T8 is formed by the first and second gate electrodes arranged sequentially along the first direction. The tenth conductive portion includes a first tenth conductive portion, a tenth channel portion 202, and a second tenth conductive portion 222. fruit, The first ninth conductive portion 211 is connected to the second electrode D7 of the seventh transistor T7. The second ninth conductive portion 212 is connected to the first electrode S of the seventh transistor T7. 7, and the second tenth conductive portion 222 is used as the eighth transistor T8 The first electrode S7 of the seventh transistor T7 is used as the first electrode S8 of the eighth transistor T8. It is also used as the second electrode D8 of the transistor T8. The gate electrode G7 of the seventh transistor T7 is connected to the second plate C2b of the output capacitor C2. and the second electrode D7 of the seventh transistor T7 is coupled to the coupled to gate electrode G6, The gate electrode G8 of the eighth transistor T8 is connected to the gate electrode G1 of the first transistor T1. The first electrode S8 of the eighth transistor T8 is coupled to the first voltage signal line VGH is combined with the first voltage signal line VGH extends along a first direction; The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and The first and second transistors T1 and T2 are arranged sequentially along a first direction. In at least one embodiment of the present disclosure, as the output active length increases, T5, T4 , T6, T7 and T8 are all moved upward, and the gap in the first direction is used to This narrows the width of the shift register unit in the second direction.

[0149] In addition, the first electrode S7 of the seventh transistor T7 is connected to the second electrode S8 of the eighth transistor T8. D8, that is, in the display substrate according to at least one embodiment of the present disclosure, In the seventh transistor T7 and the eighth transistor T8, the second semiconductor layer 20 The second ninth conductive portion 212 can be directly coupled to the first conductive portion of T7 and T8. Reduce the area occupied in one direction.

[0150] Optionally, as shown in FIGS. 1 and 3A-9, the scan driving circuit may be The line CB may further include a gate electrode G2 of the second transistor T2 and a gate electrode G3 of the seventh transistor T3. The gate electrode G7 of the transistor T7 is coupled to the second clock signal line CB, The second clock signal line CB extends along a first direction, and the second clock signal line C B is located on the side of the second transistor T2 that is farther from the display area.

[0151] As shown in FIGS. 3A to 9, the second electrode D7 of T7 is connected to the fourteenth connection via hole H141. The second electrode D7 of T7 is coupled to the fifth conductive connection F5 via the gate electrode G of T6. Combined into 6, The gate electrode G7 of T7 is coupled to the eighth conductive connection F8 and the ninth conductive connection F9, respectively. And, F8 is coupled to the second clock signal line CB through a fifteenth connecting via hole H151, F9 is coupled to the second conductive connecting portion F2 through the sixteenth connecting via hole H161, and Gate electrode G7 of C7 is coupled to the second plate C2b of C2, The first electrode S8 of T8 is connected to the first voltage signal line V through a seventeenth connecting via hole H171. bound to GH, The gate electrode G8 of T8 is connected to the gate electrode G1 of T1 and the first electrode C1a of C1, respectively. are combined. As shown in FIGS. 3A-9, the gate electrode G2 of T2 is coupled to the tenth conductive connection F10. The tenth conductive connecting portion F10 is connected to the second contact via an eighteenth connecting via hole 181. It is coupled to the lock signal line CB.

[0152] As shown in FIG. 6, the gate electrode G3 of T3 is connected to the output terminal through an eleventh conductive connection F11. The resistor R1 may be coupled to a first plate C2A of capacitor C2.

[0153] As shown in FIG. 9, G8 is connected to the twelfth conductive connecting portion through the twelfth connecting via hole H191. The twelfth conductive connecting portion F12 is connected to the twelfth connecting via hole H121. and coupled to the second electrode D6 of T6. Optionally, the scan driving circuit may further include a second voltage signal line and a signal output line. , the signal output line includes a first output line portion and at least one second output line portion; the second voltage signal line and the first output line portion both extend along a first direction; the first output line portion is located between the second voltage signal line and the output circuit; the second output line portion extends along a second direction; The second output line portion is used to provide a light emitting control signal to a pixel circuit in the display area. and The first output line portion and the output circuit are spaced apart from the display area of the second voltage signal line. It is located on the side.

[0154] In the layout scheme shown in FIG. 3A, the signal output line has two second output line portions. In particular, the number of second output line segments included in the signal output line may vary depending on the actual situation. It may be selected depending on the situation.

[0155] In particular, the scanning driving circuit includes a first voltage signal line, a second voltage signal line, a first may further include a clock signal line and a second clock signal line; The first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line The clock signal lines are all extended in a first direction, an orthogonal projection of the first voltage signal line at the base; and the orthogonal projection of the second clock signal line at the base are both a base of the star unit positioned on a side of the orthogonal projection away from the display area; The orthogonal projection of the second voltage signal line at the base is It is located closer to the display area.

[0156] In at least one embodiment of the present disclosure, the signal output line includes at least one second output line portion. the second output line portion may be coupled to the first output line portion, and the second output line portion may include The line portion is extended to the display area, and light emission control is performed on the pixel circuits located in the display area. It is used to provide a signal.

[0157] Specifically, the first clock signal line, the second clock signal line, and the first voltage signal line The specific location of the first clock may be set according to actual needs. The clock signal line, the second clock signal line and the first voltage signal line are all arranged around the display substrate. The first voltage signal line is located at the base of the first An orthogonal projection of the clock signal line at the base and a orthogonal projection of the second clock signal line at the base The projection is orthogonal projection onto the display substrate surface at the base of the shift register unit. The shift register unit is located on the side away from the display area, thus When the shift register unit is turned off, each transistor of the shift register unit and the first clock excessive overlap between the signal line, the second clock signal line, and the first voltage signal line; By avoiding the occurrence of Contribute further.

[0158] The first clock signal line, the second clock signal line, and the first voltage signal line may be By arranging them so that they all extend along the first direction, the frame of the display substrate can be narrowed. This will further contribute to the realization of

[0159] In at least one embodiment of the present disclosure, the first clock signal output from the first clock signal line The phases of the second clock signal output from the second clock signal line and the second clock signal output from the second clock signal line may be opposite to each other. However, this is not limited to this. In particular, as shown in FIG. 1 and FIG. 3A, the scan driving circuit Signal line VGH, second voltage signal line VGL, first clock signal line CK, second clock signal line C B and a signal output line, and the at least one shift register unit may include a 1 capacitor C1, output capacitor C2, output reset capacitor C3, first transistor transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, Transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8 , may further include an output reset transistor T9 and an output transistor T10; The signal output line includes a first output line portion E01, a first second output line portion E021, and a second a second output line portion E022; The first output line portion E01, the first second output line portion E021, and the second second output line portion E022 E022 are bonded to each other, The first output line portion E01 extends along a first direction, and the first second output line portion The second output line portion E021 and the second output line portion E022 are coupled to each other and extend in a second direction. It is extended along The output transistor T10 and the output reset transistor T9 are arranged along a first direction. are arranged as follows: The gate electrode G10 of the output transistor T10 is connected to the first pole of the output capacitor C2. The first electrode S10 of the output transistor T10 is coupled to the second voltage signal line C2a. VGL, and a second electrode D10 of the output transistor T10 is coupled to the first output line portion Combined with min E01, The gate electrode G9 of the output reset transistor T9 is connected to the output reset capacitor a first electrode S9 of the output reset transistor T9; , coupled to the second plate C3b of the output reset capacitor C3, a second electrode D9 of the transistor T9 is coupled to the first output line portion E01; The second electrode C3b of the output reset capacitor C3 is connected to the first voltage signal line VGH. The second plate C2b of the output capacitor C2 is connected to the gate of the seventh transistor T7. connected to the gate electrode G7, The first electrode S1 of the first transistor T1 is connected to the second electrode C2 of the output capacitor C2. b, and the second electrode D1 of the first transistor T1 and the second electrode D2 of the second transistor T2 The first electrodes D2 are respectively coupled to the second electrodes C1b of the first capacitor C1, The gate electrode G1 of the first transistor T1 is connected to the first electrode C1a of the first capacitor C1. Combined, The gate electrode G2 of the second transistor T2 and the gate electrode G of the seventh transistor T7 7 are respectively coupled to the second clock signal line CB and the first a second electrode D2 coupled to the second electrode D3 of the third transistor T3; The gate electrode G3 of the third transistor T3 is connected to the gate of the output transistor T10. The first electrode S3 of the third transistor T3 is coupled to the output reset coupled to the first plate C3a of capacitor C3; The gate electrode G4 of the fourth transistor T4 is connected to the gate electrode G5 of the fifth transistor T5. The first electrode S4 of the fourth transistor T4 is coupled to the output terminal G5 of the output transistor T1. The second electrode D4 of the fourth transistor T4 is coupled to the first electrode S10 of the fourth transistor T4. coupled to the second electrode D6 of the sixth transistor T6; The gate electrode G5 of the fifth transistor T5 is coupled to the first clock signal line CK. The second electrode D5 of the fifth transistor T5 is connected to the gate electrode G of the sixth transistor T6. 6, and the first electrode S5 of the fifth transistor T5 is coupled to the input signal terminal E1. , The first electrode S6 of the sixth transistor T6 is connected to the gate electrode G4 of the fourth transistor T4. and the second electrode D6 of the sixth transistor T6 is coupled to the coupled to the second electrode D4, The gate electrode G7 of the seventh transistor T7 is connected to the second plate C2b of the output capacitor C2. and the first electrode S7 of the seventh transistor T7 is coupled to the first electrode S8 of the eighth transistor G8. The second electrode D7 of the seventh transistor T7 is also used as the second electrode D8 of the sixth transistor T7. coupled to the gate electrode G6 of the transistor G6, The gate electrode G8 of the eighth transistor T8 is connected to the gate electrode G1 of the first transistor T1. The first electrode S8 of the eighth transistor T8 is coupled to the first voltage signal line VGH is combined with The first second output line portion E021 is coupled to the first output line portion E01, The first second output line portion E021 is extended to the display area and is located in the display area. and providing a light-emitting control signal to the pixel circuit, The second second output line portion E022 is coupled to the first output line portion E01, The second output line portion E022 is extended to the display area and is located in the display area. The pixel circuit is used to provide a light emission control signal to the pixel circuit.

[0160] In particular, the second voltage signal line is connected to the display area of the shift register unit. It may be provided on the near side, The first voltage signal line, the first clock signal line, and the second clock signal line are connected to the It is provided on the side of the soft register unit away from the display area, The first clock signal line, the second clock signal line, and the The first voltage signal line and the second voltage signal line are arranged in sequence or are arranged close to the display area. The second clock signal line, the first clock signal line, and the first voltage The signal lines are arranged in sequence.

[0161] In at least one embodiment of the present disclosure, the scan driving circuit includes a first initial signal line and a second initial signal line. It may further include a signal line, The second initial signal line and the first initial signal line are arranged in a direction approaching the display area. The first clock signal line, the second clock signal line, and the first voltage signal line are arranged in sequence. Listed, The first initial signal line and the second initial signal line are arranged in a direction approaching the display area. The first clock signal line, the second clock signal line, and the first voltage signal line are arranged in sequence. Listed, The second initial signal line and the first initial signal line are arranged in a direction approaching the display area. The second clock signal line, the first clock signal line, and the first voltage signal line are arranged in sequence. Listed, The first initial signal line and the second initial signal line are arranged in a direction approaching the display area. The second clock signal line, the first clock signal line, and the first voltage signal line are arranged in sequence. will be listed.

[0162] As shown in FIG. 3B, at least one embodiment of the shift register unit shown in FIG. 3A Based on this, at least one embodiment of the shift register unit is Further including a first and second initial signal line E12; The first initial signal line E11 and the second initial signal line E12 are both arranged along a first direction. may be extended, As shown in Figure 3B, E12, E11, CB, CK, and VGH approach the display area. The electrodes are arranged in a sequential order along the direction of the arrow. In actual operation, the positions of E11 and E12 may be interchangeable, i.e. E11, E12, CB, CK, and VGH are sequentially aligned along the direction approaching the display area. are arranged.

[0163] Alternatively, as shown in FIG. 3A, the output transistor T10 and the output reset transistor T9 may be located between the output capacitor C2 and the first output line portion E01, and the output transistor T10 and the output reset transistor T9 may be sequentially arranged along the first direction. 、 No. 1 direction to Along the line, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first transistor T1, the first capacitor C1, the second transistor T2, and the output reset transistor T9 are sequentially arranged. the fifth transistor T5, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are located between the output capacitor C2 and the first voltage signal line VGH; The gate electrode G5 of the fifth transistor T5 and the gate electrode G4 of the fourth transistor T4 are included in a first gate metal pattern, and the first gate metal pattern extends along the second direction.

[0164] In at least one embodiment of the present disclosure, the display substrate includes a plurality of rows of The pixel circuit may further include a light emitting control terminal; The shift register unit corresponds to at least one row of the pixel circuits; The signal output lines of the shift register unit are connected to the light emission control lines of the pixel circuits of at least one row. a control terminal for providing a light emitting control signal to the light emitting control terminal of the pixel circuit of the at least one row; It is used to mean:

[0165] In the layout method shown in FIG. 3A, as shown in FIG. 5 (FIG. 5 is the active area of FIG. 3A), The length of the first semiconductor layer 10 in the first direction is the output active length L1. The minimum width of the first semiconductor layer 10 in the second direction is the output active width W1, the output active length L1 is a first predetermined length; The ratio of the output active length L1 to the output active width W1 is within a predetermined ratio range. Located within The output active width W1 is within a predetermined width range, In the layout scheme shown in FIG. 3A of the present disclosure, the output active length L1 is By increasing the L1 of the elements other than the output circuit of the shift register unit, The layout can be done by utilizing the extra vertical space, and the shift register The horizontal space occupied by the unit can be reduced, and in at least one embodiment of the present disclosure, This reduces the output active width W1, saving space in the horizontal direction. However, in the shift register unit, elements other than the output circuit are used to change the layout. This also reduces the horizontal space occupied by the shift register unit. can be done.

[0166] In the layout scheme shown in FIG. 3A of the present disclosure, T5, T4, T6, T7 and T8 Move the shift register up and use the extra vertical space to create a layout. The horizontal space occupied by the star unit can be reduced, In the layout scheme shown in FIG. 3A of the present disclosure, the active pattern of T1 is arranged horizontally. By changing the installation direction, it is possible to make the distance between T2 and T3 closer and also to change the installation direction of T1, T2 , the arrangement position of T3 further matches the shape of the C1 plate, In the layout scheme shown in FIG. 3A of the present disclosure, the shape of the first electrode plate of C3 and the By changing the shape of the second plate, the width of the C3 plate in the second direction is narrowed, and the shift register unit This contributes to the tight horizontal alignment of the lattices.

[0167] In the layout scheme shown in FIG. 3A of the present disclosure, as shown in FIGS. The first output line portion E01 is formed by a plurality of first signal line via holes provided in an overlapping region of the signal lines. the first output terminal H01 is coupled to the second electrode D10 of the output transistor T10; The force line portion E01 is connected to a plurality of second signal line via holes H provided in the overlapping region of the signal lines. 02 is coupled to the second electrode D9 of the output reset transistor T9, The first signal line via holes H01 are arranged sequentially along a first direction, and the plurality of second signal lines The via holes H02 are arranged sequentially along the first direction, 4 and 10 (FIG. 10 is a schematic diagram of the source-drain metal layer of FIG. 3A, and FIG. 10 First source-drain metal pattern Ds1 and second source-drain metal pattern Ds2 ) the overlapping areas of the signal lines are the overlapping areas A01 of the first signal lines and The overlapping area A01 of the first signal line includes an overlapping area A02 of the second signal line. The orthogonal projection of the output line portion E01 at the base and the second electrode D of the output transistor T10 10 includes a first source-drain metal pattern Ds1 and an orthogonal projection of the first source-drain metal pattern Ds1 at the base. The overlapping area A02 of the second signal line is an overlapping area in front of the first output line portion E01. The orthogonal projection on the base and the second electrode D9 of the output reset transistor T9 are included. 2 is the overlap region with the orthogonal projection at the base of the source-drain metal pattern Ds2, As shown in FIG. 4, the first signal line via holes are arranged sequentially along the first direction. and the last first signal line via hole in the first direction, a maximum distance K1; a third length L3; is a third predetermined ratio, and the ratio in the first direction between two adjacent first signal line via holes is The minimum distance is a first predetermined distance, and the third length L3 is the overlapping area of the first signal line. is the length of A01 in the first direction, The first second signal line via hole and the last second signal line via hole are arranged sequentially along the first direction. The ratio of the maximum distance K2 of the signal line via hole in the first direction to the fourth length L4 is a fourth predetermined ratio. In this case, the minimum distance in the first direction between two adjacent second signal line via holes is The fourth length L4 is a constant distance in the first direction of the overlapping area A02 of the second signal line. It's the length.

[0168] In at least one embodiment of the present disclosure, the number of the first signal line via holes and the number of the second signal line The number of via holes may be selected according to the actual situation.

[0169] As shown in FIGS. 3A, 4 and 10, the T10 active layer and the T9 active layer is lengthened in the vertical direction, the third length L3 and the fourth length L4 are accordingly lengthened. As a result, a plurality of first signal line via holes H01 are uniformly arranged in the overlapping area A01 of the first signal lines. The first signal line via hole from top to bottom and the last first signal line via hole from top to bottom can be arranged in a row. The ratio of the maximum distance K1 in the first direction to the signal line via hole to the third length L3 is a third predetermined The ratio of the first signal line via holes H01 to the first signal line overlapping area A0 1 as tight as possible, so that the second electrode D10 of the output transistor T10 can be more effectively connected to E0 Bind to 1, As shown in FIGS. 3A, 4 and 10, the T10 active layer and the T9 active layer is lengthened in the vertical direction, the third length L3 and the fourth length L4 are accordingly lengthened. As a result, a plurality of second signal line via holes H02 are uniformly arranged in the overlapping area A02 of the second signal lines. The first second signal line via hole from top to bottom and the last second signal line via hole from top to bottom can be arranged in a row. The ratio of the maximum distance K2 in the first direction to the signal line via hole to the fourth length L4 is a fourth predetermined The ratio of the second signal line via holes H02 to the second signal line overlap area A0 2 as tight as possible, so that the second electrode D9 of the output reset transistor T9 can be It can be bound to E01.

[0170] In at least one embodiment of the present disclosure, the semiconductor layer shown in FIG. 5 and the first gate electrode shown in FIG. A first gate insulating layer may be further provided between the gate metal layer and the first gate insulating layer. A second gate insulating layer is further provided between the first gate metal layer and the second gate metal layer shown in FIG. 7 and the source metal layer shown in FIG. 9. An insulating layer may be further provided between the drain metal layer and the drain electrode.

[0171] In addition, when manufacturing the display substrate according to at least one embodiment of the present disclosure, first, providing a semiconductor material layer and performing a patterning process on the semiconductor material layer; An active layer is formed, and as shown in FIG. 5, a first semiconductor layer 10, a second semiconductor layer 20, a first Active pattern A1, second active pattern A2, third active pattern A3, Fourth active pattern A4, fifth active pattern A5 and sixth active pattern Form A6, forming a first gate insulating layer on a surface of the active layer opposite the base; forming a first gate metal layer on the first gate insulating layer facing away from the active layer; The first gate metal layer is patterned to form a shift register unit, as shown in FIG. the gate electrodes of the transistors included in the a, the first electrode plate C1a of the first capacitor C1 and the first electrode plate C2A of the output capacitor C2 Accomplished, The gate electrode of each transistor is used as a mask, and the gate electrode of the active layer is The portion of the active layer that is not covered with the dopant is doped. A portion of the active layer that is not covered by the gate electrode is formed as a conductive portion. The portion of the gate electrode that is covered with the gate electrode is formed as a channel portion, and the conductive The conductive portion is used as the first electrode or the second electrode, or the conductive portion is used as the first electrode or the second electrode. is coupled to the second electrode, a second gate metal layer is provided on one surface of the second gate insulating layer facing away from the first gate metal layer; The second gate metal layer is patterned to form signal output lines, input lines, and The input signal terminal E1, the second plate C3b of the output reset capacitor C3, the first plate C3b of the first capacitor C1 forming the second plate C1b and the first plate C2b of the output capacitor C2; an insulating layer is provided on one surface of the second gate metal layer facing away from the second gate insulating layer; As shown in FIG. 8, the active layer, the first gate insulating layer, the first gate metal layer, the second gate a plurality of via holes are provided in a base provided with an insulating layer, a second gate metal layer, and an insulating layer; a source / drain metal layer is provided on one side of the insulating layer facing the second gate metal layer; The source-drain metal layer is patterned, and the first voltage signal is applied to the source-drain metal layer as shown in FIG. line VGH, second voltage signal line VGL, first clock signal line CK, second clock signal line CB, the second electrode of the output reset transistor T9, the first electrode of the output transistor T10, the second electrode of the output transistor T10, the first electrode of the output transistor T10 Forms poles.

[0172] At least one embodiment of the present disclosure provides a method for manufacturing a display substrate, which includes: the scan driving circuit includes a plurality of shift register units; At least one of the plurality of shift register units is an output an output circuit including an output transistor and an output reset transistor; , A semiconductor layer is fabricated on the base, and a patterning process is performed on the semiconductor layer to form an output transistor. forming an active layer of the output reset transistor and an active layer of the output reset transistor; and, A first gate metal layer is formed on a surface of the semiconductor layer opposite the base; A patterning process is performed on the metal layer to form a gate electrode of the output transistor and a gate electrode of the output reset transistor. forming a gate electrode of the gate transistor; The gate electrode of the output transistor and the gate electrode of the output reset transistor As a mask, a dopant is applied to the portion of the semiconductor layer that is not covered by the gate electrode. The portion of the semiconductor layer that is not covered by the gate electrode is then covered with a conductive film. The conductive layer is formed as a conductive portion, and the portion of the conductive layer that is covered by the gate electrode is forming the channel portion; a second gate metal layer is provided on one surface of the first gate metal layer facing the semiconductor layer; A patterning process is performed on the base metal layer to form a first output line portion extending along a first direction. forming a signal output line including: providing a first insulating layer on one side of the second gate metal layer facing away from the first gate metal layer; , A region where the first insulating layer and the first output line partially overlap is provided with a dielectric film that penetrates the first insulating layer. fabricating a plurality of first signal line via holes and a plurality of second signal line via holes; A source / drain metal layer is formed on the first insulating layer on one side opposite to the second gate metal layer. Then, a patterning process is performed on the source / drain metal layer to form a first source / drain metal layer. forming a pattern and a second source-drain metal pattern; the first source-drain metal pattern includes a second electrode of the output transistor, the second source-drain metal pattern includes a second electrode of the output reset transistor; By doing so, the first output line portion is connected to the output terminal through the plurality of first signal line via holes. a second electrode of the transistor, and the first output line portion is coupled to the second electrode of the plurality of second signal line buses; a second electrode of the output reset transistor via a hole; the signal output line includes a first output line portion extending along a first direction; The plurality of first signal line via holes are sequentially arranged along a first direction, and the plurality of second signal line via holes are The signal line via holes are arranged sequentially along a first direction, In the first direction, any two first signal line via holes arranged sequentially along the first direction a ratio of the maximum distance between the first signal line via holes and the third length is a first predetermined ratio, and a minimum distance in a first direction between the balls is a first predetermined distance; In the first direction, any two second signal line via holes arranged sequentially along the first direction the ratio of the maximum distance to the fourth length is a second predetermined ratio, and two adjacent second signal line via holes a minimum distance in the first direction between the balls is a second predetermined distance; The third length is the length of the overlapping region of the first signal line in the first direction, and the fourth length is the length is the length of the overlapping region of the second signal line in the first direction, the first predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.9, the first predetermined distance is equal to or greater than 1.5 μm and equal to or less than 45 μm; the second predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.9, The second predetermined distance is equal to or greater than 1.5 μm and equal to or less than 65 μm.

[0173] In at least one embodiment of the present disclosure, increasing the output active length Among the output register units, elements other than the output circuit have an increased output active length. The layout can be done by utilizing the extra space in the direction, and the shift register unit can be used. The lateral space occupied by the knit can be reduced, and in at least one embodiment of the present disclosure, , the output active width can be reduced, saving space in the horizontal direction and The elements of the shift register unit other than the output circuit are used to perform layout. This allows the shift register unit to occupy less horizontal space. Cut. Optionally, the length of the active layer of the output transistor in the first direction is defined as a first length. The length of the active layer of the output reset transistor in the first direction is set to a second length the sum of the first length and the second length is an output active length, a minimum width of the active layer of the output transistor along the second direction; and the minimum width of the active layer of the transistor along the second direction, the smaller of which is defined as the output active layer. The width of the first direction is set to be a tape width, and the first direction and the second direction intersect with each other.

[0174] Optionally, the first predetermined length is greater than or equal to 50 μm and less than or equal to 130 μm; Optionally, the ratio of the output active length to the output active width is within a predetermined ratio range. The predetermined ratio may be within a range of 3 or more and 11 or less.

[0175] In at least one embodiment of the present disclosure, the output active width is within a predetermined width range. Good too.

[0176] Optionally, the predetermined width range is greater than or equal to 12 μm and less than or equal to 45 μm. The first output line portion is connected to a plurality of first signal line via holes provided in the overlapping region of the signal lines. the first output line portion is coupled to the second electrode of the output transistor via the The output reset transistor is connected to the second signal line via holes provided in the overlapping region of the lines. the first signal line via holes are connected to the second electrodes of the transistors, and the first signal line via holes are arranged in a first direction. Next, the plurality of second signal line via holes are arranged sequentially along a first direction, The overlapping region of the signal lines includes an overlapping region of a first signal line and an overlapping region of a second signal line. The overlapping area of the first signal line is a projection of the first output line portion at the base and a front projection of the first output line portion. The base of the first source-drain metal pattern includes a second electrode of the output transistor. The overlapping area of the second signal line is an overlapping area of the first output line portion. a second electrode of the output reset transistor; an overlap region with an orthogonal projection at said base of the source-drain metal pattern; In the first direction, any two first signal line via holes arranged sequentially along the first direction a ratio of the maximum distance between the first signal line via holes and the third length is a first predetermined ratio, and a first predetermined distance between the first and second signals; is the length of the overlapping area of the lines in the first direction, In the first direction, any two second signal line via holes arranged sequentially along the first direction the ratio of the maximum distance to the fourth length is a second predetermined ratio, and two adjacent second signal line via holes the minimum distance between the first and second signals in the first direction is a second predetermined distance, and the fourth length is The length of the line overlap area in the first direction.

[0177] Active pattern of output transistor and active pattern of output reset transistor As the turn is lengthened in the vertical direction, the third and fourth lengths are also lengthened accordingly. By this, a plurality of first signal line via holes can be uniformly arranged in the overlapping region of the first signal lines, and The ratio of the maximum distance in the first direction between any two first signal line via holes to the third length is a predetermined ratio, and the plurality of first signal line via holes can be formed in an overlapping region of the first signal lines. 1. The second electrode of the output transistor can be tightened as much as possible to better couple the second electrode of the output transistor to the first output line portion. , The active layer of the output transistor and the active layer of the output reset transistor are arranged vertically. As a result, the third and fourth lengths are lengthened, and thus multiple The second signal line via holes may be uniformly arranged in the overlapping region of the second signal lines, and any two a ratio of the maximum distance of the second signal line via hole in the first direction to the fourth length is a second predetermined ratio; The plurality of second signal line via holes are arranged as closely as possible to the overlapping region of the second signal lines. Therefore, the second electrode of the output reset transistor can be better coupled to the first output line portion. This can be done.

[0178] Optionally, the manufacturing method of the display substrate according to at least one embodiment of the present disclosure further comprises: The method may further include disposing the first transistor on a side of the first transistor away from the display area. The step of fabricating the first transistor further comprises: Forming the active layer of the output transistor and the active layer of the output reset transistor and a first active pattern of the first transistor extending along the second direction. This includes forming a ring.

[0179] In at least one embodiment of the present disclosure, the first active pattern is formed to extend along the second direction. The first transistor is placed between the eighth transistor and the first capacitor. The eighth transistor, the first transistor, and the first capacitor are arranged in sequence along the first direction. By arranging them, the first transistor is disposed in the space between the eighth transistor and the first capacitor. By placing the second transistor and the third transistor closer together (see above), The second electrode of the second transistor is coupled to the second electrode of the third transistor, so that the wiring For convenience, it is also necessary to provide the second and third transistors nearby. The width of the soft register unit in the second direction can be further reduced.

[0180] Optionally, the manufacturing method of the display substrate according to at least one embodiment of the present disclosure further comprises: The second and third transistors are disposed on the side of the first transistor away from the display area. may further include fabricating The step of fabricating the second transistor and the third transistor includes: The gate electrode of the output transistor and the gate electrode of the output reset transistor and forming a gate electrode of the second transistor and a gate electrode of the third transistor. forming a contact electrode; an orthogonal projection of the gate electrode of the second transistor on the base; and a maximum distance in the second direction between the orthogonal projection of the gate electrode on the base is a third predetermined distance; do.

[0181] Optionally, the third predetermined distance is greater than or equal to 14 μm and is 50 μm.

[0182] In particular, the second electrode of the second transistor is connected to the third transistor. Since the second transistor is coupled to the second electrode, the second transistor and the third transistor are arranged close to each other for convenience of wiring. It is necessary to provide the second and third transistors close to each other. This can contribute to narrowing the width of the shift register unit in the second direction. Cut.

[0183] In particular, the method for manufacturing a display substrate according to at least one embodiment of the present disclosure includes: An output reset capacitor is fabricated on the side of the output transistor away from the display area. and the step of fabricating the output reset capacitor further comprises: Form the gate electrode of the output transistor and the gate electrode of the output reset transistor, and form the first electrode plate of the output reset capacitor coupled to the gate electrode of the output reset transistor, and form the signal output line and form the second electrode plate of the output reset transistor, including: The maximum width in the second direction of the second electrode plate of the output reset capacitor is a first predetermined width, and the maximum length in the first direction of the second electrode plate of the output reset capacitor is a second predetermined length, wherein the orthographic projection of the second electrode plate of the output reset capacitor on the base is within the orthographic projection of the first electrode plate of the output reset capacitor on the base.

[0184] Optionally, the first predetermined width is 3 μm or more and 60 μm or less, and the second predetermined length is 3 μm or more and 20 μm or less. In at least one embodiment of the present disclosure, the width in the second direction of the first electrode plate of the output reset capacitor and the width in the second direction of the second electrode plate of the output reset capacitor are set to be small, and the length in the first direction of the first electrode plate of the output reset capacitor and the length in the first direction of the second electrode plate of the output reset capacitor are set to be large. On the premise of ensuring the area of the electrode plate of the output reset capacitor, the width in the second direction occupied by the electrode plate of the output reset capacitor is narrowed.

[0185] In at least one embodiment of the present disclosure, the signal output line may include at least one second output line portion, the second output line portion is coupled to the first output line portion, and the second output line portion extends to the display area and emits light to the pixel circuit located in the display area to control It is used to provide a control signal.

[0186] A display device according to at least one embodiment of the present disclosure includes the display substrate described above.

[0187] The display substrate according to the above embodiment can realize a narrow frame, so the embodiment of the present disclosure When the display device according to the present invention includes the display substrate described above, the beneficial effect of a narrow frame can be similarly achieved. , and will not be repeated here.

[0188] The display device provided in at least one embodiment of the present disclosure may be used in a mobile phone, a tablet, a television, Display panel, notebook PC, digital photo frame, navigator, etc. The component may be any product or part that:

[0189] Unless otherwise defined, technical or scientific terms used in this disclosure are those to which this disclosure pertains. As used in this disclosure, " The use of "first," "second," and similar words does not denote any order, quantity, or importance. It is used only to distinguish between different components, without regard to the Any similar word means that the element or item that appears before the word is the same as the element or item that appears after the word. "Connection" means to cover elements or items that are connected to the The words "coupled" or "connected" and similar words mean a direct connection, not just a physical or mechanical connection. "Top", "bottom", "left", "right", etc. , are merely used to indicate relative positional relationships, and if the absolute position of the object being described changes, the relative position The placement relationship may also change accordingly.

[0190] It should be noted that an element such as a layer, film, region, or substrate may be positioned "above" or "below" another element. When an element is said to be positioned, it means that the element is "directly" located "above" or "below" another element. Alternatively, an intermediate element may be interposed between these elements. In the above, the specific features, structures, materials or characteristics may be used in any one or more of the examples or examples. can be combined in any suitable manner.

[0191] The above description is a preferred embodiment of the present disclosure, and it is understood by those skilled in the art that Various changes and modifications may be made without departing from the spirit of the present disclosure. Modifications are intended to be within the scope of this disclosure.

Claims

1. A display substrate, comprising: a scan driving circuit and a display area provided on a base; the scan driving circuit comprising a plurality of shift register units; at least one of the plurality of shift register units comprising a signal output line and an output circuit; the output circuit comprising an output transistor and an output reset transistor; the signal output line includes a first output line portion extending along a first direction; the active layer of the output transistor and the active layer of the output reset transistor are arranged along a first direction, the length of the active layer of the output transistor in the first direction is defined as a first length, the length of the active layer of the output reset transistor in the first direction is defined as a second length, and the sum of the first length and the second length is defined as an output active length; a minimum width of the active layer of the output transistor along the second direction and a minimum width of the active layer of the output reset transistor along the second direction, the smaller of which is an output active width, and the first direction and the second direction intersect with each other; a ratio of the output active length to the output active width within a predetermined ratio range, the predetermined ratio range being equal to or greater than 3 and equal to or less than 11; or the output active width is within a predetermined range; The predetermined width range is 12 μm or more and 45 μm or less, The scan driving circuit further includes a first clock signal line and a second clock signal line.

2. the first output line portion is coupled to a second electrode of the output transistor through a plurality of first signal line via holes provided in an overlapping region of the signal line, the first output line portion is coupled to a second electrode of the output reset transistor through a plurality of second signal line via holes provided in the overlapping region of the signal line, the plurality of first signal line via holes are arranged sequentially along a first direction, and the plurality of second signal line via holes are arranged sequentially along the first direction; the overlapping region of the signal lines includes an overlapping region of a first signal line and an overlapping region of a second signal line, the overlapping region of the first signal line being an overlapping region of an orthogonal projection of the first output line portion at the base and an orthogonal projection of a first source-drain metal pattern including a second electrode of the output transistor at the base, and the overlapping region of the second signal line being an overlapping region of an orthogonal projection of the first output line portion at the base and an orthogonal projection of a second source-drain metal pattern including a second electrode of the output reset transistor at the base, a ratio of a distance in the first direction between a first first signal line via hole and a last first signal line via hole among a plurality of first signal line via holes sequentially arranged along the first direction to a third length is a first predetermined ratio, and the third length is a length in the first direction of an overlapping region of the first signal lines; a ratio of a distance in the first direction between a first second signal line via hole and a last second signal line via hole among a plurality of second signal line via holes sequentially arranged along the first direction to a fourth length is a second predetermined ratio, and the fourth length is a length in the first direction of an overlapping region of the second signal lines; The first predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.9, or The display substrate of claim 1 , wherein the second predetermined ratio is equal to or greater than 0.05 and equal to or less than 0.

9.

3. an active layer of the output transistor and an active layer of the output reset transistor are formed by a single continuous first semiconductor layer, and the first semiconductor layer extends along a first direction; a length of the first semiconductor layer in a first direction is an output active length; The display substrate of claim 1 , wherein the minimum width of the first semiconductor layer in the second direction is the output active width.

4. The at least one shift register unit further includes a first transistor, the first transistor includes a first active pattern, and the first active pattern extends along a second direction; the first transistor is located on a side of the output circuit away from a display area, or the at least one shift register unit further includes a second transistor and a third transistor, a second electrode of the second transistor being coupled to a second electrode of the third transistor; a maximum distance in a second direction between an orthogonal projection of the gate electrode of the second transistor on the base and an orthogonal projection of the gate electrode of the third transistor on the base is a third predetermined distance; the second transistor and the third transistor are located on a side of the output circuit away from a display area, the third predetermined distance is equal to or greater than 14 μm and equal to or less than 50 μm, or the at least one shift register unit further includes a first transistor, a second transistor, and a first capacitor; a second electrode of the first transistor and a first electrode of the second transistor are respectively coupled to a second plate of the first capacitor, and a gate electrode of the first transistor is coupled to a first plate of the first capacitor; the first transistor, the first capacitor, and the second transistor are sequentially arranged along a first direction; the first transistor, the first capacitor, and the second transistor are located on a side of the output circuit away from a display area, or the scan driving circuit further includes a first voltage signal line, and the at least one shift register unit further includes an output reset capacitor, a first electrode of the output reset capacitor being coupled to a gate electrode of the output reset transistor, and a second electrode of the output reset capacitor being coupled to the first voltage signal line; a maximum width of the second plate of the output reset capacitor in the second direction is a first predetermined width; the maximum length of the second plate of the output reset capacitor in the first direction is a second predetermined length; the output reset capacitor is located on a side of the output circuit away from a display area, and an orthogonal projection of a second plate of the output reset capacitor on the base is within an orthogonal projection of a first plate of the output reset capacitor on the base; the first predetermined width is 3 μm or more and 60 μm or less, and the second predetermined length is 3 μm or more and 20 μm or less; or 2. The display substrate of claim 1, wherein the first voltage signal line extends along a first direction, and the first voltage signal line is located on a side of the output reset capacitor that is farther from a display area.

5. the output transistor and the output reset transistor are arranged along a first direction, the scan driving circuit further includes a second voltage signal line, and the at least one shift register unit further includes an output reset capacitor; a second plate of the output reset capacitor coupled to the first voltage signal line; a first electrode of the output transistor coupled to a second voltage signal line, and a first electrode of the output reset transistor coupled to a second plate of the output reset capacitor; The display substrate according to claim 4 , wherein the output transistor and the output reset transistor are located on a side of the second voltage signal line away from a display area.

6. a gate electrode of the output transistor includes at least one output gate electrode pattern, a first electrode of the output transistor includes at least one first electrode pattern, and a second electrode of the output transistor includes at least one second electrode pattern; the output gate electrode pattern is located between the first electrode pattern and the second electrode pattern, which are adjacent to each other; the first electrode pattern, the output gate electrode pattern, and the second electrode pattern all extend along a second direction; or a gate electrode of the output reset transistor includes at least one output reset gate electrode pattern, a first electrode of the output reset transistor includes at least one third electrode pattern, and a second electrode of the output reset transistor includes at least one fourth electrode pattern; the output reset gate electrode pattern is located between the third electrode pattern and the fourth electrode pattern, which are adjacent to each other; the third electrode pattern, the output reset gate electrode pattern, and the fourth electrode pattern all extend along a second direction; The display substrate according to claim 5 , wherein the fourth electrode pattern of the output reset transistor that is closest to the gate electrode of the output transistor also serves as the second electrode pattern of the output transistor.

7. an active layer of the output transistor includes at least two first conductive portions and at least one first channel portion that are provided opposite to each other along a first direction, and each of the first channel portions is provided between two adjacent first conductive portions; the first channel portions correspond one-to-one to the output gate electrode patterns, and orthogonal projections of the first channel portions on the base are all located within orthogonal projections of the corresponding output gate electrode patterns on the base; the first conductive portions of some of the output transistors correspond one-to-one to the first electrode patterns, an orthogonal projection of the first electrode pattern on the base and an orthogonal projection of the corresponding first conductive portion on the base have a first overlapping region, and the first electrode pattern is coupled to the corresponding first conductive portion through at least one first via hole provided in the first overlapping region; 7. The display substrate of claim 6, wherein the first conductive portions of other parts of the output transistors correspond one-to-one to the second electrode patterns, a second overlapping region is formed between the orthogonal projection of the second electrode pattern on the base and the orthogonal projection of the corresponding first conductive portion on the base, and the second electrode pattern is coupled to the corresponding first conductive portion through at least one second via hole provided in the second overlapping region.

8. an active layer of the output reset transistor includes at least two second conductive portions and at least one second channel portion provided opposite to each other along a first direction, each second channel portion being provided between two adjacent second conductive portions, the second channel portions being in one-to-one correspondence with the output reset gate electrode patterns, and orthogonal projections of the second channel portions at the base are all located within orthogonal projections of the corresponding output reset gate electrode patterns at the base; the second conductive portions of some of the output reset transistors correspond one-to-one to the third electrode patterns, an orthogonal projection of the third electrode pattern on the base and an orthogonal projection of the corresponding second conductive portion on the base have a third overlapping region, and the third electrode pattern is coupled to the corresponding second conductive portion through at least one third via hole provided in the third overlapping region; 7. The display substrate of claim 6, wherein the second conductive portions of another part of the output reset transistors correspond one-to-one to the fourth electrode patterns, a fourth overlapping region is formed between a normal projection of the fourth electrode pattern on the base and a normal projection of the corresponding second conductive portion on the base, and the fourth electrode pattern is coupled to the corresponding second conductive portion through at least one fourth via hole provided in the fourth overlapping region.

9. the scan driving circuit further includes a second voltage signal line, and the at least one shift register unit further includes a fourth transistor; the second voltage signal line is coupled to an electrode conductive connection portion, the electrode conductive connection portion extends along a second direction, and the at least one first electrode pattern is sequentially arranged along a first direction; the electrode conductive connection is coupled to a first first electrode pattern included in the first electrode of the output transistor; a first electrode of the fourth transistor coupled to the electrode conductive connection; a minimum distance in a first direction between an orthogonal projection of the gate electrode of the fourth transistor on the base and an orthogonal projection of the electrode conductive connection on the base is a fourth predetermined distance; 7. The display substrate of claim 6, wherein the fourth predetermined distance is equal to or greater than 1 [mu]m and equal to or less than 5 [mu]m.

10. the at least one shift register unit further includes a fourth transistor and a fifth transistor; a gate electrode of the fourth transistor is coupled to a gate electrode of the fifth transistor; the gate electrode of the fourth transistor and the gate electrode of the fifth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along a second direction; and the gate electrode of the fifth transistor is coupled to the first clock signal line; The display substrate of claim 1 , wherein the first clock signal line extends along a first direction, and the first clock signal line is located on a side of the fifth transistor that is farther from a display area.

11. the at least one shift register unit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, and an output capacitor; a first electrode of the fifth transistor coupled to an input signal terminal, a second electrode of the fifth transistor coupled to a gate electrode of the sixth transistor; a gate electrode of the sixth transistor including a first gate electrode pattern and a second gate electrode pattern coupled to each other; the first gate electrode pattern and the second gate electrode pattern are respectively coupled to a first plate of the output capacitor, the first plate of the output capacitor being coupled to a gate electrode of the output transistor; a first electrode of the sixth transistor coupled to a gate electrode of a fourth transistor, a second electrode of the sixth transistor coupled to a second electrode of the fourth transistor, and a second plate of the output capacitor coupled to a first electrode of the first transistor; the fourth transistor, the sixth transistor, and the first transistor are sequentially arranged along the first direction, the fifth transistor, the sixth transistor, and the first transistor are sequentially arranged along the first direction, The display substrate according to claim 1 , wherein the output capacitor is located between the sixth transistor and the output circuit.

12. the at least one shift register unit further includes a second transistor, a first transistor, a sixth transistor, a seventh transistor, and an eighth transistor; an active layer of the seventh transistor and an active layer of the eighth transistor are formed by a single continuous second semiconductor layer, and the second semiconductor layer extends along a first direction; an active layer of the seventh transistor including a first ninth conductive portion, a ninth channel portion, and a second ninth conductive portion sequentially disposed along a first direction; The second ninth conductive portion is also used as the first tenth conductive portion, an active layer of the eighth transistor including a first tenth conductive portion, a tenth channel portion, and a second tenth conductive portion sequentially disposed along a first direction; the first ninth conductive portion is used as a second electrode of the seventh transistor, the second ninth conductive portion is used as a first electrode of the seventh transistor, the second tenth conductive portion is used as a first electrode of the eighth transistor, and the first electrode of the seventh transistor is also used as a second electrode of the eighth transistor; a gate electrode of the seventh transistor coupled to a second plate of an output capacitor, a second electrode of the seventh transistor coupled to a gate electrode of the sixth transistor; a gate electrode of the eighth transistor coupled to a gate electrode of the first transistor; a first electrode of the eighth transistor coupled to a first voltage signal line; the first voltage signal line extends along a first direction; the sixth transistor, the seventh transistor, the eighth transistor, and the second transistor are sequentially arranged along a first direction, a gate electrode of the second transistor and a gate electrode of the seventh transistor are respectively coupled to the second clock signal line; The display substrate according to claim 1 , wherein the second clock signal line extends along a first direction and is located on a side of the second transistor that is farther from a display area.

13. the scanning driving circuit further includes a second voltage signal line and a signal output line; the signal output line includes a first output line portion and at least one second output line portion; the second voltage signal line and the first output line portion both extend along a first direction, and the first output line portion is located between the second voltage signal line and the output circuit; the second output line portion extends along a second direction; the second output line portion is used to provide a light emitting control signal to a pixel circuit in a display area; the first output line portion and the output circuit are located on a side of the second voltage signal line that is farther from the display area, or the scanning driving circuit further includes a first voltage signal line and a second voltage signal line; the first voltage signal line, the second voltage signal line, the first clock signal line, and the second clock signal line all extend along a first direction; an orthogonal projection of the first voltage signal line on the base, an orthogonal projection of the first clock signal line on the base, and an orthogonal projection of the second clock signal line on the base are all located on a side of the orthogonal projection of the shift register unit on the base away from the display area; an orthogonal projection of the second voltage signal line at the base is located on a side of the shift register unit closer to the display area; or 2. The display substrate of claim 1, wherein the signal output line further includes at least one second output line portion coupled to the first output line portion, the second output line portion extending to the display area, and used to provide a light-emitting control signal to a pixel circuit located in the display area.

14. the scan driving circuit further includes a first voltage signal line, a second voltage signal line, and a signal output line; the at least one shift register unit further includes a first capacitor, an output capacitor, an output reset capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and the signal output line further includes at least one second output line portion; a gate electrode of the output transistor coupled to a first plate of the output capacitor, a first electrode of the output transistor coupled to a second voltage signal line, and a second electrode of the output transistor coupled to the signal output line; a gate electrode of the output reset transistor is coupled to a first plate of the output reset capacitor, a first electrode of the output reset transistor is coupled to a second plate of the output reset capacitor, and a second electrode of the output reset transistor is coupled to the signal output line; a second plate of the output reset capacitor coupled to the first voltage signal line, and a second plate of the output capacitor coupled to the gate electrode of the seventh transistor; a first electrode of the first transistor is coupled to a second plate of the output capacitor, a second electrode of the first transistor and a first electrode of the second transistor are each coupled to a second plate of the first capacitor, and a gate electrode of the first transistor is coupled to the first plate of the first capacitor; a gate electrode of the second transistor is coupled to the second clock signal line, and a second electrode of the second transistor is coupled to a second electrode of the third transistor; a gate electrode of the third transistor coupled to a gate electrode of the output transistor; a first electrode of the third transistor coupled to a first plate of the output reset capacitor; a gate electrode of the fourth transistor is coupled to a gate electrode of the fifth transistor; a first electrode of the fourth transistor is coupled to a first electrode of the output transistor; and a second electrode of the fourth transistor is coupled to a second electrode of the sixth transistor. a gate electrode of the fifth transistor is coupled to the first clock signal line, a first electrode of the fifth transistor is coupled to an input signal terminal, and a second electrode of the fifth transistor is coupled to a gate electrode of the sixth transistor; a first electrode of the sixth transistor coupled to a gate electrode of a fourth transistor, and a second electrode of the sixth transistor coupled to a second electrode of the fourth transistor; a gate electrode of the eighth transistor is coupled to a gate electrode of the first transistor, and a first electrode of the eighth transistor is coupled to a first voltage signal line; the second output line portion is coupled to the first output line portion, and the second output line portion is extended to the display area and used to provide a light emission control signal to a pixel circuit located in the display area; a second voltage signal line is provided on a side of the shift register unit close to a display area, and the first voltage signal line, the first clock signal line, and the second clock signal line are provided on a side of the shift register unit farther from the display area, the first clock signal line, the second clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area, or the second clock signal line, the first clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area, the scan driving circuit further includes a first initial signal line and a second initial signal line; When the first clock signal line, the second clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area, the second initial signal line, the first initial signal line, the first clock signal line, the second clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area; or the first initial signal line, the second initial signal line, the first clock signal line, the second clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area; When the second clock signal line, the first clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area, the second initial signal line, the first initial signal line, the second clock signal line, the first clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area; or the first initial signal line, the second initial signal line, the second clock signal line, the first clock signal line, and the first voltage signal line are sequentially arranged along a direction approaching the display area; the output transistor and the output reset transistor are located between the output capacitor and the first output line portion, and the output transistor and the output reset transistor are sequentially arranged along the first direction; the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the first transistor, the first capacitor, the second transistor, and the output reset transistor are sequentially arranged along a first direction; the fifth transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are located between the output capacitor and the first voltage signal line; 2. The display substrate of claim 1, wherein the gate electrode of the fifth transistor and the gate electrode of the fourth transistor are included in a first gate metal pattern, and the first gate metal pattern extends along the second direction.

15. The display substrate further includes a plurality of rows of pixel circuits disposed on the base, the pixel circuits including a light-emitting control terminal; The shift register unit corresponds to at least one row of the pixel circuits; 2. The display substrate according to claim 1, wherein the signal output lines of the shift register units are coupled to the light-emitting control terminals of the pixel circuits of the at least one row, and are used to provide light-emitting control signals to the light-emitting control terminals of the pixel circuits of the at least one row.

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