Display substrate, display device

Abstract

The present disclosure provides a display substrate and a display device, the display substrate including a base and a plurality of sub-pixels arrayed on the base, the sub-pixels including a data line pattern extending in a first direction, a power signal line pattern including a portion extending in the first direction, and a sub-pixel driving circuit, the sub-pixel driving circuit including two switch transistors, a driving transistor, and a storage capacitor, a first electrode plate of the storage capacitor is coupled to a gate of the driving transistor, a second electrode plate of the storage capacitor is coupled to a gate of the driving transistor, second electrodes of the two switch transistors are both coupled to a first electrode of the driving transistor, and an orthogonal projection of the second electrode of at least one of the two switch transistors on the base at least partially overlaps with an orthogonal projection of the power signal line pattern on the base and at least partially overlaps with an orthogonal projection of the second electrode plate of the storage capacitor on the base.

Description

[Technical Field]

[0001] This application claims priority to application number PCT / CN2019 / 121948, filed November 29, 2019, the entire contents of which are incorporated herein by reference. The present disclosure relates to the technical field of displays, and in particular to display substrates and display devices. [Background technology]

[0002] Organic Light-Emitting Diode (OLED) display products are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high definition, excellent flexibility, and high luminous efficiency.

[0003] Meanwhile, as the range of use of OLED display products expands, the demand for display quality of OLED display products is increasing. Among the various factors that affect the display quality of display products, crosstalk caused by the pixel circuit structure included in display products is a major factor that has attracted widespread attention. Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] A first aspect of the present disclosure provides a display substrate including a base and a plurality of sub-pixels arranged in an array on the base, the sub-pixels comprising: a data line pattern extending in a first direction; a first shield member at least a portion of which extends in the first direction; a drive transistor; a first transistor coupled to the gate of the drive transistor; a second shield member coupled to the first shield member; Including, the first transistor has a double-gate structure, and the first transistor includes a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, respectively; and a second electrode of the driving transistor is coupled to the fourth semiconductor pattern or the fifth semiconductor pattern; an orthogonal projection of the second shielding member on the base at least partially overlaps with an orthogonal projection of the sixth conductor pattern on the base; At least a portion of the first shielding member is positioned between the second pole of the driving transistor and a data line pattern in an adjacent sub-pixel, providing a display substrate.

[0006] Optionally, the second shield member is closer to the base than the first shield member.

[0007] Optionally, an overlap area between an orthogonal projection of the first shield member on the base and an orthogonal projection of the second pole of the drive transistor on the base is defined as E1, an area of a portion of the orthogonal projection of the second pole of the drive transistor on the base that does not overlap with the orthogonal projection of the first shield member on the base is defined as E2, and E1 <E2である。

[0008] Optionally, in a second direction, the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the first shield member on the base is L1, and the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the data line pattern in the adjacent subpixel on the base is L2, where L1≦L2.

[0009] Optionally, the channel length of the driving transistor is L3, where L1≦L2≦L3.

[0010] Optionally, the minimum linear distance between the second pole of the driving transistor and the data line pattern in the adjacent sub-pixel is L4, and the minimum linear distance between the second pole of the driving transistor and the first shielding member is L5, and L5 <L4である。

[0011] Optionally, the sub-pixel further includes a connecting line, and the gate of the driving transistor is coupled to the second electrode of the first transistor through the connecting line; The orthogonal projection of the second shielding member on the base is located between the orthogonal projection of the end of the connecting line coupled to the second pole of the first transistor on the base and the orthogonal projection of the data line pattern in the adjacent subpixel on the base.

[0012] Optionally, the length of the first shielding member in the first direction is greater than the length of the connecting wire.

[0013] Optionally, a portion of the second pole of the driving transistor that does not overlap with the first shielding member has a length extending in the first direction defined as L6, and a portion of the first shielding member has a length extending in the first direction defined as L7, where L6≦L7.

[0014] Optionally, there is a gap between the orthogonal projection of the first shield member on the base and the orthogonal projection of the second pole of the drive transistor on the base.

[0015] Optionally, the sub-pixel further includes a fourth transistor, a first pole of the fourth transistor is coupled to the data line pattern, and a second pole of the fourth transistor is coupled to the first pole of the driving transistor; The orthogonal projection of the second shield member onto the base does not overlap with the orthogonal projection of the fourth transistor in an adjacent subpixel onto the base.

[0016] Optionally, the first shield member and the second shield member are for receiving a first fixed potential signal.

[0017] Optionally, the subpixel further includes a storage capacitor, the storage capacitor including a first plate coupled to the gate of the drive transistor and a second plate for receiving a second fixed potential signal; a gap is provided between an orthogonal projection of the second electrode plate on the base and an orthogonal projection of the first shield member on the base; The orthogonal projection of the second pole of the drive transistor onto the base includes a portion located within the gap.

[0018] Optionally, the first fixed potential signal is the same as the second fixed potential signal.

[0019] Optionally, the second pole of the drive transistor is closer to the base than the first shield member and the second shield member.

[0020] Optionally, the active layer of the first transistor and the active layer of the drive transistor are provided in the same layer and are of a monolithic structure.

[0021] Optionally, the minimum linear distance from the first shield member to the second pole of the driving transistor is greater than the minimum linear distance from the second shield member to the sixth conductor pattern.

[0022] Optionally, the sub-pixel comprises: a reset signal line pattern and an initialization signal line pattern each extending in a second direction intersecting the first direction; a second transistor having a gate coupled to the reset signal line pattern, a first pole coupled to the initialization signal line pattern, and a second pole coupled to the gate of the driving transistor; Further includes:

[0023] Optionally, an orthogonal projection of a contact portion of the second shield member that contacts the first shield member on the base does not overlap with an orthogonal projection of an active layer of the second transistor on the base; a distance from the contact portion to the sixth conductor pattern is smaller than a distance from the contact portion to a second electrode of the driving transistor; The distance from the orthogonal projection of the contact portion on the base to the orthogonal projection of the sixth conductor pattern on the base is smaller than the distance between the orthogonal projection of the contact portion on the base and the orthogonal projection of the data line pattern on the base.

[0024] Optionally, the sub-pixel comprises: a light-emitting control signal line pattern extending in the second direction; a power supply signal line pattern including a portion extending in the first direction; a fifth transistor having a gate coupled to the light-emitting control signal line pattern, a first electrode coupled to the power supply signal line pattern, and a second electrode coupled to the first electrode of the driving transistor; Further includes:

[0025] Optionally, the sub-pixel further includes a light-emitting element and a sixth transistor having a gate coupled to the light-emitting control signal line pattern, a first pole coupled to the second pole of the driving transistor, and a second pole coupled to the light-emitting element.

[0026] A second aspect of the present disclosure is a display substrate including a base and a plurality of sub-pixels arranged in an array on the base, the sub-pixels comprising: a data line pattern extending in a first direction; a first shield member at least a portion of which extends in the first direction; a drive transistor; a first transistor coupled to the gate of the drive transistor; a second shield member coupled to the first shield member; Including, the first transistor has a double-gate structure, and the first transistor includes a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, respectively; and a second electrode of the driving transistor is coupled to the fourth semiconductor pattern or the fifth semiconductor pattern; a linear distance from a portion of the second shielding member that contacts the first shielding member to the sixth conductor pattern is smaller than a linear distance from the portion to a second pole of the drive transistor; A display substrate is provided in which the distance from the orthogonal projection on the base of the contact portion of the second shielding member that contacts the first shielding member to the orthogonal projection of the sixth conductor pattern on the base is smaller than the distance between the orthogonal projection on the base of the contact portion and the orthogonal projection on the base of the data line pattern.

[0027] Optionally, the second shield member is closer to the base than the first shield member.

[0028] Optionally, an overlap area between an orthogonal projection of the first shield member on the base and an orthogonal projection of the second pole of the drive transistor on the base is defined as E1, an area of a portion of the orthogonal projection of the second pole of the drive transistor on the base that does not overlap with the orthogonal projection of the first shield member on the base is defined as E2, and E1 <E2である。

[0029] Optionally, in a second direction, the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the first shield member on the base is L1, and the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the data line pattern in the adjacent subpixel on the base is L2, where L1≦L2.

[0030] Optionally, the length of the channel of the driving transistor in the second direction is L3, where L1≦L2≦L3.

[0031] Optionally, the minimum linear distance between the second pole of the driving transistor and the data line pattern in the adjacent sub-pixel is L4, and the minimum linear distance between the second pole of the driving transistor and the first shielding member is L5, and L5 <L4である。

[0032] Optionally, the sub-pixel further includes a connecting line, and the gate of the driving transistor is coupled to the second electrode of the first transistor through the connecting line; The orthogonal projection of the second shielding member on the base is located between the orthogonal projection of the end of the connecting line coupled to the second pole of the first transistor on the base and the orthogonal projection of the data line pattern in the adjacent subpixel on the base.

[0033] Optionally, the length of the first shielding member in the first direction is greater than the length of the connecting wire.

[0034] Optionally, a portion of the second pole of the driving transistor that does not overlap with the first shielding member has a length extending in the first direction defined as L6, and a portion of the first shielding member has a length extending in the first direction defined as L7, where L6≦L7.

[0035] Optionally, there is a gap between the orthogonal projection of the first shield member on the base and the orthogonal projection of the second pole of the drive transistor on the base.

[0036] Optionally, the sub-pixel further includes a fourth transistor, a first pole of the fourth transistor is coupled to the data line pattern, and a second pole of the fourth transistor is coupled to the first pole of the driving transistor; The orthogonal projection of the second shield member onto the base does not overlap with the orthogonal projection of the fourth transistor in an adjacent subpixel onto the base.

[0037] Optionally, the first shield member and the second shield member are for receiving a first fixed potential signal.

[0038] Optionally, the subpixel further includes a storage capacitor, the storage capacitor including a first plate coupled to the gate of the drive transistor and a second plate for receiving a second fixed potential signal; a gap is provided between an orthogonal projection of the second electrode plate on the base and an orthogonal projection of the first shield member on the base; The orthogonal projection of the second pole of the drive transistor onto the base includes a portion located within the gap.

[0039] Optionally, the first fixed potential signal is the same as the second fixed potential signal.

[0040] Optionally, the second pole of the drive transistor is closer to the base than the first shield member and the second shield member.

[0041] Optionally, the active layer of the first transistor and the active layer of the drive transistor are provided in the same layer and are of a monolithic structure.

[0042] Optionally, the minimum linear distance from the first shield member to the second pole of the driving transistor is greater than the minimum linear distance from the second shield member to the sixth conductor pattern.

[0043] Optionally, the sub-pixel comprises: a reset signal line pattern and an initialization signal line pattern each extending in a second direction intersecting the first direction; a second transistor having a gate coupled to the reset signal line pattern, a first pole coupled to the initialization signal line pattern, and a second pole coupled to the gate of the driving transistor; Further includes:

[0044] Optionally, an orthogonal projection of a portion of the second shield member that contacts the first shield member onto the base does not overlap with an orthogonal projection of an active layer of the second transistor onto the base; The minimum linear distance between the portion of the first shielding member extending in the first direction and the second shielding member is smaller than the minimum linear distance between the data line pattern in an adjacent subpixel and the second shielding member.

[0045] Optionally, the sub-pixel comprises: a light-emitting control signal line pattern extending in the second direction; a power supply signal line pattern including a portion extending in the first direction; a fifth transistor having a gate coupled to the light-emitting control signal line pattern, a first electrode coupled to the power supply signal line pattern, and a second electrode coupled to the first electrode of the driving transistor; Further includes:

[0046] Optionally, the sub-pixel further includes a light-emitting element and a sixth transistor having a gate coupled to the light-emitting control signal line pattern, a first pole coupled to the second pole of the driving transistor, and a second pole coupled to the light-emitting element.

[0047] A third aspect of the present disclosure provides a display device including the above-mentioned display substrate.

[0048] The drawings described herein are intended to provide a further understanding of the present disclosure and constitute a part of the present disclosure, and the illustrative embodiments of the present disclosure and the description thereof are intended to interpret the present disclosure and do not constitute undue limitations on the present disclosure. [Brief explanation of the drawings]

[0049] [Figure 1] FIG. 2 is a structural schematic diagram of a sub-pixel driving circuit according to an embodiment of the present disclosure. [Figure 2] FIG. 10 is an operation sequence diagram corresponding to a sub-pixel driving circuit according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a first layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a first layout schematic diagram of an active film layer according to an embodiment of the present disclosure. [Figure 5] FIG. 2 is a first schematic layout diagram of a first gate metal layer according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a first schematic layout diagram of a second gate metal layer according to an embodiment of the present disclosure. [Figure 7]1 is a first schematic layout diagram of a source-drain metal layer according to an embodiment of the present disclosure. FIG. [Figure 8] FIG. 4 is a cross-sectional view taken along the A1A2 direction in FIG. [Figure 9] FIG. 10 is a second layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a third layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 11] FIG. 10 is a fourth layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 12] FIG. 10 is a fifth layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 13] 12 is a cross-sectional view taken along the B1B2 direction in FIG. 11. FIG. [Figure 14] FIG. 10 is a sixth layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 15] FIG. 2 is a first layout schematic diagram of a plurality of sub-pixels on a display substrate according to an embodiment of the present disclosure. [Figure 16] FIG. 7 is a seventh layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a cross-sectional view taken along the C1C2 direction in FIG. [Figure 18] FIG. 2 is a second layout schematic diagram of an active film layer according to an embodiment of the present disclosure. [Figure 19] FIG. 10 is an eighth layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 20] FIG. 9 is a ninth layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 21] FIG. 10 is a schematic diagram of a tenth layout of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 22] 22 is a cross-sectional view taken along the D1D2 direction in FIG. 21. FIG. [Figure 23]FIG. 10 is a schematic layout diagram of a third metal layer. [Figure 24] FIG. 10 is a second layout schematic diagram of a plurality of sub-pixels on a display substrate according to an embodiment of the present disclosure. [Figure 25] 10A and 10B are schematic diagrams illustrating a crosstalk phenomenon occurring at the gate of a driving transistor in the related art. [Figure 26] FIG. 11 is an eleventh layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 27] FIG. 12 is a twelfth layout schematic diagram of a sub-pixel driving circuit on a display substrate according to an embodiment of the present disclosure. [Figure 28] FIG. 10 is a cross-sectional view schematically illustrating two adjacent subpixel driving circuits taken along the D1D2 direction. DETAILED DESCRIPTION OF THE INVENTION

[0050] In order to further describe the display substrate and the display device according to the embodiments of the present disclosure, a detailed description will be given below with reference to the accompanying drawings.

[0051] In the related art, there are various causes of crosstalk in OLED display products. Among them, the main crosstalk is crosstalk generated in the drive transistor due to the data line pattern located around the drive transistor in the subpixel driving circuit. More specifically, when the subpixel driving circuit is laid out, various types of transistors with different functions are included around the drive transistor in the subpixel driving circuit, and these transistors are all configured with multi-layer conductive patterns. Moreover, various types of signal line patterns for transmitting different signals are also provided around the drive transistor. When the subpixel driving circuit is operating, the conductive patterns included in the various types of transistors and signal changes on the various types of signal line patterns are all likely to cause crosstalk in the drive transistor, which will ultimately affect the operating performance of the drive transistor.

[0052] In view of the existence of the above problems, the inventors of the present disclosure have conducted research and found that the crosstalk that affects the operating performance of the driving transistor mainly includes crosstalk problems caused by coupling between the data line pattern and the gate of the driving transistor, and crosstalk problems caused by coupling between the data line pattern and the first pole of the driving transistor.

[0053] After further research, the inventors of the present disclosure found that by forming a pattern with a fixed potential on the first pole of the driving transistor and using this pattern with a fixed potential to shield the first pole of the driving transistor, thereby reducing the coupling effect between the data line pattern located near the first pole of the driving transistor and the first pole of the driving transistor, the crosstalk problem caused by the data line pattern in the driving transistor can be alleviated, and a better display effect can be achieved in display products.

[0054] It should be noted that one or more embodiments described herein correspond to a display substrate having a 7T1C (i.e., seven thin film transistors and one capacitor) subpixel driving circuit. In another embodiment, the display substrate may include a different subpixel driving circuit, for example, a number other than seven thin film transistors and one or more capacitors.

[0055] As shown in FIG. 1, the display substrate according to the present disclosure includes a plurality of sub-pixels, and each sub-pixel may include a gate line pattern GATE, a first reset signal line pattern RST1, a first initialization signal line pattern VINT1, a data line pattern DATA, a light-emitting control signal line pattern EM, a power supply signal line pattern VDD, a second reset signal line pattern RST2, and a second initialization signal line pattern VINT2.

[0056] Each subpixel driving circuit in each subpixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. Also, in FIG. 1, a first capacitor C1 is included, and the first capacitor C1 is a parasitic capacitor.

[0057] Taking one subpixel driving circuit as an example, all of the transistors included in the subpixel driving circuit are P-type transistors, of which the first transistor T1 has a double-gate structure, with the gate 201g of the first transistor T1 coupled to the gate line pattern GATE, the source S1 of the first transistor T1 coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 coupled to the gate 203g of the third transistor T3.

[0058] The second transistor T2 has a double-gate structure, in which a gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1, a source S2 of the second transistor T2 is coupled to the first initialization signal line pattern VINT1, and a drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0059] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the source S4 of the fourth transistor T4 is coupled to the data line pattern DATA, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0060] The gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power supply signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0061] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element OLED.

[0062] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light-emitting element OLED, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line pattern VINT2.

[0063] A first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3, and a second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0064] As shown in FIG. 2, when the subpixel driving circuit having the above structure is in operation, each operation period includes a first reset period P1, a write compensation period P2, a second reset period P3 and a light emitting period P4.

[0065] During the first reset period P1, the first reset signal input by the first reset signal line pattern RST1 is at an active level, the second transistor T2 is turned on, and the initialization signal transmitted by the first initialization signal line pattern VINT1 is input to the gate 203g of the third transistor T3, thereby clearing the gate-source voltage Vgs held in the third transistor T3 in the previous frame and resetting the gate 203g of the third transistor T3.

[0066] During the write compensation period P2, the first reset signal is at an inactive level, the second transistor T2 is turned off, and the gate scanning signal input by the gate line pattern GATE is at an active level, controlling the first transistor T1 and the fourth transistor T4 to be turned on. The data signal is written into the data line pattern DATA and transmitted to the source S3 of the third transistor T3 via the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, causing the third transistor T3 to form a diode structure. The first transistor T1, the third transistor T3, and the fourth transistor T4 work together to compensate the threshold voltage of the third transistor T3. If the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to eventually reach Vdata+Vth, where Vdata is the data signal voltage value and Vth is the threshold voltage of the third transistor T3.

[0067] In the second reset period P3, the gate scanning signal is at an inactive level, the first transistor T1 and the fourth transistor T4 are both turned off, the second reset signal input through the second reset signal line RST2 is at an active level, and controls the seventh transistor T7 to be turned on, and the initialization signal transmitted through the second initialization signal line pattern VINT2 is input to the anode of the light emitting element OLED, preventing the light emitting element OLED from emitting light.

[0068] During the light-emitting period P4, the light-emitting control signal written by the light-emitting control signal line pattern EM is at an active level, controlling the fifth transistor T5 and the sixth transistor T6 to be turned on, so that the power signal transmitted by the power signal line pattern VDD is input to the source S3 of the third transistor T3. At the same time, the gate 203g of the third transistor T3 is maintained at Vdata+Vth, so that the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power signal. A drain current generated based on this gate-source voltage flows to the anode of the corresponding light-emitting element OLED, thereby driving the corresponding light-emitting element OLED to emit light.

[0069] As shown in FIG. 3 , when fabricating the subpixel driving circuit, the layout of the film layers corresponding to the subpixel driving circuit is an active film layer, a gate insulating layer, a first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer, a first source-drain metal layer, and a third interlayer insulating layer, which are stacked in order in a direction away from the base.

[0070] 4, the active film layers are used to form the channel regions (e.g., 101pg-107pg), source forming regions (e.g., 101ps-107ps), and drain forming regions (e.g., 101pd-107pd) of each transistor in the subpixel driving circuit. The active film layers corresponding to the source forming regions and the drain forming regions have doping effects, and therefore their conductive properties are superior to those of the active film layer corresponding to the channel region. The active film layers can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the source regions and the drain regions can be regions doped with n-type impurities or p-type impurities.

[0071] It should also be noted that the active film layer corresponding to the source formation region and the drain formation region may be directly used as the corresponding source or drain, or a metal material may be used to fabricate the source in contact with the source formation region, and a metal material may be used to fabricate the drain in contact with the drain formation region.

[0072] As shown in FIG. 5, the first gate metal layer is used to form the gates (e.g., 201g to 207g) of each transistor in the subpixel driving circuit, as well as structures such as the gate line pattern GATE, the light emission control signal line pattern EM, the first reset signal line pattern RST1, and the second reset signal line pattern RST2 included in the display substrate, and the gate 203g of the third transistor T3 in each subpixel driving circuit also serves as the first electrode Cst1 of the storage capacitor Cst in the corresponding subpixel driving circuit.

[0073] As shown in FIG. 6, the second gate metal layer is used to form a second electrode Cst2 of the storage capacitor Cst, and a first initialization signal line pattern VINT1 and a second initialization signal line pattern VINT2 included in the display substrate.

[0074] As shown in FIGS. 1, 3 and 7, the first source-drain metal layer is used to form the sources (e.g., S1 to S7) and drains (e.g., D1 to D7) of each transistor in the subpixel driving circuit, as well as the data line patterns (e.g., DATA1 and DATA2) and power signal line patterns VDD included in the display substrate.

[0075] More specifically, continuing with Figure 3, Figure 4, 7 to 10, the gate 201g of the first transistor T1 covers the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.

[0076] The gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source forming region 102ps, and the drain D2 of the second transistor T2 is located in the second drain forming region 102pd.

[0077] The gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source forming region 103ps, and the drain D3 of the third transistor T3 is located in the third drain forming region 103pd.

[0078] The gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source forming region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain forming region 104pd.

[0079] The gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source forming region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain forming region 105pd.

[0080] The gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source forming region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain forming region 106pd.

[0081] The gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source forming region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain forming region 107pd.

[0082] The gate 203g of the third transistor T3 doubles as a first plate Cst1 of the storage capacitor Cst, and a second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0083] It should be noted that the connecting lines 401, 402, and 403 in Fig. 1 are all formed from the first source-drain metal layer, and their specific layouts are as shown in Fig. 3 and Fig. 7. The first capacitor C1 in Fig. 1 is a parasitic capacitor, and as shown in Fig. 3, there is an overlapping region between the orthogonal projection on the base of the second plate Cst2 of the storage capacitor Cst and the orthogonal projection on the base of the downward extension portion of the fourth drain forming region 104pd corresponding to the fourth transistor T4, and this overlapping region is formed as the illustrated first capacitor C1.

[0084] Furthermore, in a display substrate according to the present disclosure, a plurality of sub-pixels included therein may be arranged to form an array, the plurality of sub-pixels being divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels, each of the sub-pixels in each row including a plurality of sub-pixels aligned in a second direction, each of the sub-pixels in each column including a plurality of sub-pixels aligned in a first direction, the first direction and the second direction intersect, and the gate line pattern GATE, first reset signal line pattern RST1, first initialization signal line pattern VINT1, light emission control signal line pattern EM, second reset signal line pattern RST2, and second initialization signal line pattern VINT2 included in the sub-pixels may all extend in the second direction, and the data line pattern DATA and power supply signal line pattern VDD included in the sub-pixels all extend in the first direction.

[0085] The gate line patterns GATE located in the same row may be formed as a single gate line with an integrated structure, the first reset signal line patterns RST1 located in the same row may be formed as a single first reset signal line with an integrated structure, the first initialization signal line pattern VINT1 located in the same row may be formed as a single first initialization signal line with an integrated structure, the light emission control signal line patterns EM located in the same row may be formed as a single light emission control signal line with an integrated structure, the second reset signal line pattern RST2 located in the same row may be formed as a single second reset signal line with an integrated structure, and the second initialization signal line pattern VINT2 located in the same row may be formed as a single second initialization signal line with an integrated structure. The data line patterns DATA located in the same column may be formed as a single data line with an integrated structure, and the power supply signal line patterns VDD located in the same column may be formed as a single power supply signal line with an integrated structure.

[0086] In order to simplify the layout space of the subpixels, the second reset signal line corresponding to the subpixels in a certain row may also be used as the first reset signal line corresponding to the subpixels in the next adjacent row, and similarly, the second initialization signal line corresponding to the subpixels in a certain row may also be used as the first initialization signal line corresponding to the subpixels in the next adjacent row.

[0087] 3 , in some embodiments, taking the subpixel driving circuit included in one subpixel as an example, in a first direction (e.g., Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on a first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gates of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located on a second side of the gate of the driving transistor. Exemplarily, the first and second sides of the gate of the driving transistor are opposite sides of the gate of the driving transistor in the first direction. Furthermore, the first side of the gate of the driving transistor may be an upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor may be a lower side of the gate of the driving transistor T1. The bottom side of the display substrate is the side where the IC is bonded, and the bottom side of the gate of the driving transistor is the side closer to the IC of the gate of the driving transistor. The top side is the opposite side of the bottom side, and is the side farther from the IC of the gate of the driving transistor.

[0088] 3 , in the second direction (e.g., the X direction), the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor T1, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor T1. Exemplarily, the third and fourth sides of the gate of the driving transistor are opposite sides of the gate of the driving transistor T1 in the second direction X. Furthermore, the third side of the gate of the driving transistor may be on the left side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor may be on the right side of the gate of the driving transistor. Regarding the left and right sides, for example, in the same subpixel, the first data line pattern DATA1 is on the left side of the power supply signal line pattern VDD, and the power supply signal line pattern VDD is on the right side of the first data line pattern DATA1.

[0089] 3 and 8, an embodiment of the present disclosure is a display substrate including a base 50 and a plurality of sub-pixels arranged in an array on the base 50, wherein the sub-pixels include: a data line pattern (e.g., DATA1 in FIG. 3) extending in a first direction; an initialization signal line pattern (e.g., VINT1 in FIG. 3) including a portion extending in a second direction intersecting the first direction and for transmitting an initialization signal having a fixed potential; a subpixel driving circuit including a driving transistor (e.g., T3 in FIG. 3), a first transistor T1 coupled to a gate of the driving transistor, and a first shielding member 404 coupled to the initialization signal line pattern, wherein an orthogonal projection of the first shielding member 404 on the base 50 is located between an orthogonal projection of the first transistor T1 on the base 50 and an orthogonal projection of a target data line pattern (e.g., DATA2 in FIG. 3) on the base 50, and a next subpixel adjacent to the subpixel in the second direction includes the target data line pattern; The present invention provides a display substrate including:

[0090] Specifically, the display substrate generally includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes a data line pattern (e.g., DATA1 in FIG. 3) extending in a first direction and an initialization signal line pattern (e.g., VINT1 in FIG. 3) at least a portion of which extends in a second direction, the data line pattern for transmitting a data signal, and the initialization signal line pattern for transmitting an initialization signal having a fixed potential, and for example, the first direction includes the Y direction, and the second direction includes the X direction.

[0091] The target data line pattern is a data line pattern included in the next sub-pixel adjacent to the current sub-pixel in the second direction.

[0092] Each subpixel further includes a subpixel drive circuit and a light-emitting element corresponding to the subpixel drive circuit in a one-to-one relationship. The light-emitting element includes an anode, an organic light-emitting material layer, and a cathode, which are stacked together. The anode is coupled to the corresponding subpixel drive circuit, and the light-emitting element emits light when driven by a drive signal supplied by the subpixel drive circuit.

[0093] 1, 3 and 4, taking the case where the subpixel driving circuit includes the above-mentioned 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) is coupled to the drain D1 of the first transistor T1, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1 via a connecting line 401. In the X direction, the minimum distance between the orthogonal projection of the first channel region 101pg of the first transistor T1 on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in FIG. 3 ) on the base 50 is smaller than the minimum distance between the orthogonal projection of the third channel region 103pg of the third transistor T3 on the base 50 and the orthogonal projection of the target data line pattern on the base 50. Please note that the minimum distance between the orthogonal projection of the channel region (e.g., the first channel region 101pg and the third channel region 103pg) on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) on the base 50 means the minimum distance between the boundary of the channel region closest to the target data line pattern in the orthogonal projection on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) on the base 50.

[0094] In the subpixel driving circuit having the above structure, any change in the data signal transmitted by the target data line pattern will affect the performance of the first transistor T1, which will further affect the operating performance of the third transistor T3 because the first transistor T1 is coupled to the third transistor T3 via the connecting line 401.

[0095] In contrast, the embodiment of the present disclosure provides a first shielding member 404 coupled to the initialization signal line pattern (e.g., VINT1 in FIG. 3 ) in the subpixel driving circuit, and the first shielding member 404 has the same fixed potential as the initialization signal. The orthogonal projection of the first shielding member 404 on the base 50 is positioned between the orthogonal projection of the first transistor T1 on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in FIG. 3 ) on the base 50. This reduces the impact of changes in the signal transmitted through the target data line pattern on the performance of the first transistor T1, and further reduces the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, thereby alleviating the problem of vertical crosstalk, so that the display substrate can achieve a better display effect when used for display.

[0096] Furthermore, by coupling the first shielding member 404 with the initialization signal line pattern as described above, not only is the first shielding member 404 provided with a fixed potential, but the voltage of the initialization signal line pattern is also strengthened, which makes the voltage of the initialization signal transmitted by the initialization signal line pattern more stable, thereby further contributing to the operating performance of the subpixel driving circuit.

[0097] It should be noted that in addition to coupling the first shielding member 404 to the initialization signal line pattern, the first shielding member 404 may also be coupled to a power supply signal line pattern VDD included in the sub-pixel, so that the first shielding member 404 has the same fixed potential as the power supply signal transmitted by the power supply signal line pattern VDD.

[0098] As shown in FIG. 27, the minimum straight-line distance between the orthogonal projection of the second pole of the driving transistor (i.e., the drain D3 of the third transistor T3) on the base and the orthogonal projection of the first shield member 404 on the base is defined as L1, and the minimum straight-line distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the data line pattern DATA2 in the adjacent subpixel on the base is defined as L2.

[0099] The length of the channel of the driving transistor (ie, the third channel region 103pg) in the second direction is defined as L3, where L1≦L2≦L3.

[0100] As shown in FIG. 28, the minimum linear distance between the second pole of the driving transistor and the data line pattern (e.g., DATA2) in the adjacent subpixel is L4, the minimum linear distance between the second pole of the driving transistor and the first shielding member is L5, and L5 <L4である。

[0101] As shown in FIG. 27, the length of the portion of the second pole of the driving transistor that does not overlap with the first shielding member 404 extending in the first direction is L6, and the length of the first shielding member 404 extending in the first direction is L7, where L6≦L7.

[0102] As shown in FIG. 27, the active layer of the first transistor T1 and the active layer of the driving transistor (i.e., the third transistor T3) are provided in the same layer, have an integral structure, and can be formed by the same pattern formation process.

[0103] The second pole of the driving transistor T1 and the sixth conductor pattern are provided on the same layer and have an integral structure. The second shielding member 301 is located between the active layer of the first transistor T1 and the first shielding member 404, so that the minimum linear distance from the first shielding member 404 to the second pole of the driving transistor T1 is greater than the minimum linear distance from the second shielding member 301 to the sixth conductor pattern.

[0104] The first shield member 404 and the data line pattern (e.g., DATA2) in the adjacent subpixel are provided in the same layer and can be formed using the same patterning process. The minimum linear distance between the portion of the first shield member 404 extending in the first direction and the second shield member 301 is smaller than the minimum linear distance between the data line pattern in the adjacent subpixel and the second shield member 301.

[0105] Although the above-described method of coupling the first shielding member 404 and the power signal line pattern VDD can ensure that the first shielding member 404 has a fixed potential, the parasitic capacitance generated by the power signal line pattern VDD increases, which increases the RC load of the power signal line pattern VDD and is unfavorable for reducing vertical crosstalk.

[0106] As shown in FIG. 3, in some embodiments, the gate 201g of the first transistor T1 and the gate line pattern GATE are an integral structure, and the gate 201g of the first transistor T1 is a part of the integral structure that can form an overlap region with an active film layer in a direction perpendicular to the base.

[0107] As shown in FIG. 3, in some embodiments, the plurality of sub-pixels include a plurality of rows of sub-pixels, each row of sub-pixels including a plurality of the sub-pixels arranged in the second direction, the initialization signal line patterns located in the sub-pixels of the same row are sequentially combined to form an initialization signal line corresponding to the row of sub-pixels, and the first shielding member 404 extends in the first direction and is combined with at least one of the initialization signal lines.

[0108] Specifically, the plurality of sub-pixels are divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels aligned in a second direction, and each column of sub-pixels includes a plurality of sub-pixels aligned in a first direction, and the first direction and the second direction may intersect, and the initialization signal line patterns located in the sub-pixels of the same row are sequentially coupled to form one initialization signal line corresponding to the sub-pixels of the row.

[0109] As described above, by arranging the first shielding member 404 to extend in the first direction and be coupled to at least one of the initialization signal lines, the first shielding member 404 can reduce the impact of changes in the signal transmitted through the target data line pattern on the performance of the first transistor T1, and further reduce the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, thereby mitigating the problem of vertical crosstalk. Therefore, when the display substrate is used for display, not only can a better display effect be achieved, but the voltage of the initialization signal line can also be strengthened, making the voltage of the initialization signal transmitted through the initialization signal line more stable, which is more beneficial to the operating performance of the sub-pixel driving circuit.

[0110] As shown in FIG. 9, in some embodiments, the first shield member 404 is coupled to two of the initialization signal lines adjacent to it.

[0111] Specifically, when the first shielding member 404 and the initialization signal line are coupled together, the coupling manner between the first shielding member 404 and the initialization signal line, and the specific structure and installation method of the first shielding member 404 can all be various. For example, as shown in FIG. 3, the first shielding member 404 may be coupled to each of the two initialization signal lines adjacent to it. With this installation method, the orthogonal projection of the first shielding member 404 on the base 50 can be located not only between the orthogonal projection of the first transistor T1 on the base 50 and the orthogonal projection of the target data line pattern on the base 50, but also between the orthogonal projection of the connecting line 401 on the base 50 and the orthogonal projection of the target data line pattern on the base 50. In addition, the orthogonal projection of the first shielding member 404 on the base 50 can be located between the orthogonal projection of the driving transistor (i.e., the third transistor T3) on the base 50 and the orthogonal projection of the target data line pattern on the base 50.

[0112] The above-mentioned arrangement effectively reduces the first crosstalk occurring between the target signal line pattern and the first transistor T1 and the second crosstalk occurring between the target signal line pattern and the connecting line 401, thereby reducing indirect crosstalk to the driving transistor due to the first crosstalk and the second crosstalk. In addition, the above-mentioned arrangement effectively reduces the direct crosstalk occurring between the target signal line pattern and the driving transistor, thereby better ensuring the operating performance of the display substrate.

[0113] Continuing to refer to FIG. 3, in some embodiments, the first shield member 404 and the initialization signal line pattern (e.g., VINT1 in FIG. 3) are provided on different layers, there is a first overlap region between the orthogonal projection of the first shield member 404 on the base 50 and the orthogonal projection of the initialization signal line pattern on the base, and the first shield member 404 is coupled to the initialization signal line pattern via a first throw hole provided in the first overlap region.

[0114] Specifically, the first shielding member 404 may be provided on the same layer as the initialization signal line pattern, or on a different layer. If the first shielding member 404 and the initialization signal line pattern are provided on different layers, the first shielding member 404 may be provided so that there is a first overlapping region in both the orthogonal projection of the first shielding member 404 on the base 50 and the orthogonal projection of the initialization signal line pattern on the base 50. In this case, by providing a first throw-hole in the first overlapping region, coupling between the first shielding member 404 and the initialization signal line can be achieved.

[0115] It should be noted that the above statement "the first shielding member 404 may be provided in the same layer as the initialization signal line pattern" includes at least one of various cases, such as a case where the first shielding member 404 and the initialization signal line pattern are located on the same horizontal plane, a case where the first shielding member 404 and the initialization signal line pattern are located in the same film layer, a case where the first shielding member 404 and the initialization signal line pattern are both provided on the surface of the same insulating layer opposite to the base, and a case where the first shielding member 404 and the initialization signal line pattern are formed in a single pattern configuration process.

[0116] The above phrase "the first shielding member 404 may be provided in a layer different from the initialization signal line pattern" includes at least one of various cases, such as a case where the first shielding member 404 and the initialization signal line pattern are not located in the same film layer, and a case where the first shielding member 404 and the initialization signal line pattern cannot be formed in a single pattern configuration process.

[0117] In some embodiments, the first shielding member 404 and the data line pattern (eg, DATA1 in FIG. 3) may be made of the same material.

[0118] In some embodiments, the display substrate includes a first interlayer insulating layer, and the first shielding member 404 and the data line pattern (e.g., DATA1 in FIG. 3) may both be located on the surface of the interlayer insulating layer opposite the base.

[0119] Specifically, by providing the first shielding member 404 according to the above-described method, the first shielding member 404 and the data line pattern can be simultaneously formed on the surface of the inter-layer insulating layer opposite the base in a single patterning process, and the need for an additional patterning process to fabricate the first shielding member 404 can be avoided, thereby favorably simplifying the manufacturing flow of the display substrate and saving manufacturing costs.

[0120] As shown in FIG. 3, in some embodiments, the subpixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, wherein the second transistor T2 is: a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, the third conductor pattern having a conductive performance superior to that of the first semiconductor pattern and that of the second semiconductor pattern; a first gate pattern and a second gate pattern coupled to each other, wherein an orthogonal projection of the first gate pattern on the base 50 partially overlaps an orthogonal projection of the first semiconductor pattern on the base 50, and an orthogonal projection of the second gate pattern on the base 50 partially overlaps an orthogonal projection of the second semiconductor pattern on the base 50; an orthogonal projection of the third conductor pattern on the base 50, an orthogonal projection of the first gate pattern on the base 50, and an orthogonal projection of the second gate pattern on the base 50 do not overlap each other; The orthogonal projection of the third conductor pattern on the base 50 at least partially overlaps with the orthogonal projection of the initialization signal line pattern (for example, VINT1 in FIG. 3) on the base 50.

[0121] Specifically, as shown in FIG. 7, the second transistor T2 has a double-gate structure, and the first and second semiconductor patterns included therein are connected to the channel region (FIG. 4 102pg in the figure), while the third conductor pattern 102px included therein is doped and therefore has better conductive properties than the first semiconductor pattern and the second semiconductor pattern, and the first gate pattern and the second gate pattern included in the second transistor T2 cover the first semiconductor pattern and the second semiconductor pattern in a one-to-one correspondence and can jointly serve as the gate 202g of the second transistor T2.

[0122] In the second transistor T2 having the above structure, the third conductor pattern 102px has good conductivity and is not covered by a gate pattern, so that it is prone to coupling with other nearby conductive patterns, resulting in crosstalk. In the technical solution according to the above embodiment, the orthogonal projection of the third conductor pattern on the base 50 and the orthogonal projection of the initialization signal line pattern (e.g., VINT1 in FIG. 3 ) on the base 50 are at least partially overlapped, so that the initialization signal line pattern can shield the third conductor pattern 102px. Furthermore, because the initialization signal line pattern transmits an initialization signal having a fixed potential, the coupling between the third conductor pattern 102px and other nearby conductive patterns is more effectively reduced, thereby stabilizing the operating performance of the display substrate.

[0123] As shown in FIG. 4 , in some embodiments, the subpixel driving circuit further includes a first extending portion extending from the first semiconductor pattern, where the first extending portion has better conductive properties than the first semiconductor pattern, and the first extending portion includes a first portion 61, a second portion 62, and a third portion 63, where the first portion 61 and the third portion 63 all extend in the first direction, the second portion 62 extends in the second direction, one end of the second portion 62 is coupled to the first portion 61, the other end of the second portion 62 is coupled to the third portion 63, and the end of the third portion 63 farther from the second portion 62 is coupled to the first transistor T1.

[0124] Specifically, the first extension portion may be fabricated together with the first semiconductor pattern in a single pattern formation process, and after the first semiconductor pattern is formed, the first extension portion may be doped so that the conductive performance of the first extension portion is superior to that of the first semiconductor pattern.

[0125] After adding the first shielding member 404, the first extension portion is configured as described above, so that the second transistor T2 is coupled to the gate of the first transistor T1 and the gate of the driving transistor through the first extension portion, which contributes to reducing the impact on the performance of the first transistor T1 and the performance of the second transistor T2 caused by changes in the signal transmitted through the target data line pattern. Furthermore, the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern is reduced, and the problem of vertical crosstalk is alleviated, so that the display substrate can achieve a better display effect when used for display.

[0126] As shown in FIGS. 3 and 4, in some embodiments, the first transistor T1 is a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, respectively, the sixth conductor pattern having a conductive property superior to that of the fourth semiconductor pattern and that of the fifth semiconductor pattern; a third gate pattern and a fourth gate pattern coupled to each other, wherein an orthogonal projection of the third gate pattern on the base 50 partially overlaps an orthogonal projection of the fourth semiconductor pattern on the base 50, and an orthogonal projection of the fourth gate pattern on the base 50 partially overlaps an orthogonal projection of the fifth semiconductor pattern on the base 50; The orthogonal projection of the sixth conductor pattern on the base 50, the orthogonal projection of the third gate pattern on the base 50, and the orthogonal projection of the fourth gate pattern on the base 50 do not overlap with each other.

[0127] Specifically, as shown in FIG. 4, the first transistor has a double-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included therein are formed as the channel region of the first transistor (corresponding to symbol 101pg in FIG. 4), while the sixth conductor pattern 101px included therein is doped and therefore has better conductive performance than the fourth semiconductor pattern and the fifth semiconductor pattern, and the third gate pattern and the fourth gate pattern included in the first transistor cover the fourth semiconductor pattern and the fifth semiconductor pattern in a one-to-one correspondence, and can jointly serve as the gate 201g of the first transistor T1.

[0128] As shown in FIG. 10, in some embodiments, the orthogonal projection of the first shield member 404 on the base 50 at least partially overlaps with the orthogonal projection of the sixth conductor pattern 101px on the base 50.

[0129] Specifically, in the first transistor T1 having the above structure, the sixth conductor pattern 101px has good conductivity and is not covered by a gate pattern, so that it is prone to coupling with other nearby conductive patterns, resulting in crosstalk. In the technical solution according to the above embodiment, the orthogonal projection of the first shielding member 404 on the base 50 and the orthogonal projection of the sixth conductor pattern 101px on the base 50 are at least partially overlapped, so that the first shielding member 404 can shield the sixth conductor pattern 101px. Furthermore, because the first shielding member 404 has a fixed potential, the coupling between the sixth conductor pattern 101px and other nearby conductive patterns is more effectively reduced, thereby stabilizing the operating performance of the display substrate.

[0130] 11, 12 and 13, in some embodiments, the subpixel driving circuit further includes a second shielding member 301 coupled to the first shielding member 404, and the orthogonal projection of the second shielding member 301 on the base 50 at least partially overlaps with the orthogonal projection of the sixth conductor pattern 101px on the base 50.

[0131] Specifically, as described above, by arranging the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the sixth conductor pattern 101px on the base 50 so that they at least partially overlap, the second shielding member 301 can shield the sixth conductor pattern 101px. Furthermore, since the second shielding member 301 and the first shielding member 404 are coupled together, the second shielding member 301 has a fixed potential, which more effectively reduces the coupling effect between the sixth conductor pattern 101px and other conductive patterns in its vicinity, thereby making the operating performance of the display substrate more stable.

[0132] Therefore, in the display substrate according to the above embodiment, since the first shielding member 404 and the second shielding member 301 both have a fixed potential, the formation of a parasitic capacitor between the first transistor T1 and the target data line pattern (e.g., DATA2) can be more effectively prevented or reduced, and vertical crosstalk defects can be effectively prevented or reduced.

[0133] Furthermore, the second shield member 301 may be provided so that the orthogonal projection on the base 50 covers the entire orthogonal projection on the base 50 of the sixth conductor pattern.

[0134] Specifically, by arranging the second shielding member 301 so that the orthogonal projection of the sixth conductor pattern 101px on the base 50 covers the entire orthogonal projection of the sixth conductor pattern 101px on the base 50, the second shielding member 301 can completely block the sixth conductor pattern 101px, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other conductive patterns in its vicinity, and more preferably improving the operational stability of the display substrate.

[0135] In some embodiments, the second shielding member 301 is provided on a different layer from the first shielding member 404, and there is a second overlapping region between the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the first shielding member 404 on the base 50, and the second shielding member 301 and the first shielding member 404 are connected via a second throw hole provided in the overlapping region.

[0136] Specifically, the second shielding member 301 may be provided in the same layer as the first shielding member 404, or in a different layer. If the second shielding member 301 and the first shielding member 404 are provided in different layers, they may be provided so that there is a second overlapping region between the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the first shielding member 404 on the base 50. In this case, by providing a second throw hole in the overlapping region, coupling between the second shielding member 301 and the first shielding member 404 via the second throw hole can be achieved.

[0137] In some embodiments, the second shielding member 301 and the initialization signal line pattern may be made of the same material.

[0138] In some embodiments, the display substrate further includes a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern (e.g., VINT1 in FIG. 3) may both be located on the surface of the second interlayer insulating layer opposite the base.

[0139] Specifically, as described above, the second shielding member 301 and the initialization signal line pattern are made of the same material, and the second shielding member 301 and the initialization signal line pattern (e.g., VINT1 in Figure 3) are both positioned on the surface of the second interlayer insulating layer opposite the base. This allows the second shielding member 301 and the initialization signal line pattern to be formed simultaneously using the same pattern formation process, thereby avoiding the need to add a separate manufacturing process dedicated to manufacturing the second shielding member 301, thereby favorably simplifying the manufacturing flow of the display substrate and saving production costs.

[0140] As shown in FIG. 3 , in some embodiments, the subpixel further includes a power signal line pattern VDD, which includes a portion extending in the first direction. The subpixel driving circuit further includes a storage capacitor Cst, a first electrode Cst1 of the storage capacitor Cst doubles as the gate of the driving transistor, and a second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, and the second electrode Cst2 of the storage capacitor Cst is located on a surface of the second interlayer insulating layer opposite to the base.

[0141] Specifically, the storage capacitor Cst included in the subpixel driving circuit has a first electrode Cst1 and a second electrode Cst2, the first electrode Cst1 and the second electrode Cst2 are arranged opposite to each other, the first electrode Cst1 is coupled to the gate of the driving transistor, and the second electrode Cst2 is coupled to the power signal line pattern VDD. When the storage capacitor Cst is laid out, the first electrode Cst1 can also be used as the gate of the driving transistor, which ensures the coupling between the storage capacitor Cst and the gate of the driving transistor and reduces the space occupied by the subpixel driving circuit, thereby contributing to improving the resolution of the display substrate. Furthermore, by arranging the second electrode Cst2 of the storage capacitor Cst to be located on the surface of the second interlayer insulating layer opposite to the base, the second electrode Cst2 of the storage capacitor Cst, the second shielding member 301, and the initialization signal line pattern can be simultaneously formed using the same pattern formation process, which advantageously simplifies the manufacturing process of the display substrate and reduces production costs.

[0142] As shown in FIG. 14 , in some embodiments, the sub-pixel further includes a reset signal line pattern (e.g., RST1 in FIG. 3 ) extending in a second direction intersecting the first direction, and the sub-pixel driving circuit includes: a first conductive connection portion 405, the orthogonal projection of which on the base 50 covers at least a part of the orthogonal projection of the sixth conductor pattern 101px on the base 50; a second transistor T2, the first pole (e.g., source S2) of which is coupled to the initialization signal line pattern (e.g., VINT1) via the first conductive connection 405, the second pole (e.g., drain D2) of which is coupled to the gate of the driving transistor, and the gate 202g of which is coupled to the reset signal line pattern (e.g., RST1); Further includes:

[0143] Specifically, the first conductive connection part 405 can be made of a metal material and can be formed in the same pattern forming process as the data line pattern.

[0144] As described above, by arranging the first conductive connection portion 405 so that the orthogonal projection on the base 50 of the sixth conductor pattern 101px is covered at least a portion of the orthogonal projection on the base 50, the first conductive connection portion 405 can shield the sixth conductor pattern 101px. Furthermore, since the first conductive connection portion 405 and the initialization signal line pattern are coupled to each other, the first conductive connection portion 405 has a fixed potential, which more effectively reduces the coupling effect between the sixth conductor pattern 101px and other conductive patterns in its vicinity, thereby making the operating performance of the display substrate more stable.

[0145] As shown in FIG. 3 , in some embodiments, the sub-pixel further includes a gate line pattern GATE, an emission control signal line pattern EM, a reset signal line pattern (e.g., RST1 in FIG. 3 ), and a power supply signal line pattern VDD, wherein the gate line pattern GATE, the emission control signal line pattern EM, and the reset signal line pattern all extend in the second direction, and the power supply signal line pattern VDD includes a portion extending in the first direction; the sub-pixel driving circuit further includes a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7; a gate of the driving transistor (e.g., the gate 203g of the third transistor T3) is coupled to the second pole of the first transistor T1, a first pole of the driving transistor is coupled to the second pole of the fifth transistor T5, and a second pole of the driving transistor is coupled to the first pole of the first transistor T1; The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE; a gate 202g of the second transistor T2 is coupled to the reset signal line pattern, a first pole of the second transistor T2 is coupled to the initialization signal line pattern, and a second pole of the second transistor T2 is coupled to the gate of the driving transistor; a gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, a first pole of the fourth transistor T4 is coupled to the data line pattern (e.g., DATA1 in FIG. 3), and a second pole of the fourth transistor T4 is coupled to the first pole of the driving transistor; a gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and a first electrode of the fifth transistor T5 is coupled to the power supply signal line pattern VDD; a gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, a first pole of the sixth transistor T6 is coupled to a second pole of the driving transistor T1, and a second pole of the sixth transistor T6 is coupled to a light emitting element in the sub-pixel; The gate 207g of the seventh transistor T7 is coupled to a reset signal line pattern (e.g., RST2) included in the next adjacent subpixel in the first direction, a first pole of the seventh transistor T7 is coupled to an initialization signal line pattern (e.g., VINT2) included in the next subpixel, and a second pole of the seventh transistor T7 is coupled to a light-emitting element in the subpixel.

[0146] Specifically, the display substrate may include a plurality of sub-pixels arranged in an array, the sub-pixels being divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels, each row of sub-pixels including a plurality of sub-pixels aligned in a second direction, each column of sub-pixels including a plurality of sub-pixels aligned in a first direction, and the first direction intersects with the second direction.

[0147] It should be noted that the next adjacent sub-pixel in the first direction refers to the next adjacent sub-pixel located in the same column as the seventh transistor T7.

[0148] By arranging the subpixels and the subpixel driving circuits included therein in the above-described structure, it is possible to effectively reduce the layout space occupied by the subpixel driving circuits, on the premise that the operational performance of the subpixel driving circuits is guaranteed, thereby contributing to improving the resolution of the display substrate.

[0149] It should be noted that the gate of each transistor included in the sub-pixel driving circuit and the functional pattern associated therewith may be formed as an integral structure. For example, the gate of the first transistor and the gate of the fourth transistor are both integral with the correspondingly associated gate line pattern, the gate of the fifth transistor and the gate of the sixth transistor are both integral with the correspondingly associated light-emitting control signal line pattern, and the gate of the second transistor and the gate of the seventh transistor are both integral with the correspondingly associated reset signal line pattern.

[0150] In addition, the first transistor T1 is for performing threshold compensation for the driving transistor (e.g., the third transistor T3), the second transistor T2 is for resetting the gate of the driving transistor, the fourth transistor T4 is for writing the data signal transmitted by the data line pattern, the fifth transistor T5 is for writing the power signal transmitted by the power signal line pattern to the first electrode of the driving transistor, the sixth transistor T6 is for controlling whether the corresponding light-emitting element emits light, and the seventh transistor T7 is for resetting the anode of the light-emitting element.

[0151] In some embodiments, the sub-pixel further includes a gate line pattern GATE, an emission control signal line pattern EM, a reset signal line pattern RST, and a power supply signal line pattern VDD, wherein the gate line pattern GATE, the emission control signal line pattern EM, and the reset signal line pattern RST all extend in the second direction, the power supply signal line pattern VDD includes a portion extending in the first direction, and the orthogonal projection of the first shielding member 404 on the base 50 partially overlaps with the orthogonal projection of the gate line pattern GATE on the base 50 and the orthogonal projection of the emission control signal line pattern EM on the base 50, respectively.

[0152] Specifically, by laying out the first shielding member 404 according to the above manner, the first shielding member 404 can isolate both the first transistor T1 and the driving transistor from the target data line pattern (e.g., DATA2), thereby contributing to reducing crosstalk to the first transistor T1 and the driving transistor due to changes in the data signal in the target data line pattern.

[0153] In some embodiments, the coupling manner between the second pole of the seventh transistor T7 and the light-emitting element in the sub-pixel may be various. For example, the orthogonal projection of the anode of the light-emitting element on the base and the orthogonal projection of the second pole of the seventh transistor T7 on the base overlap, and the anode of the light-emitting element can be coupled to the second pole of the seventh transistor T7 through a throw-hole provided at the overlapping location; or the orthogonal projection of the anode of the light-emitting element on the base and the orthogonal projection of the second pole of the seventh transistor T7 on the base do not overlap, and the sub-pixel driving circuit further includes a second conductive connector 406 and a third conductive connector 407, and the orthogonal projection of the anode of the light-emitting element on the base and the orthogonal projection of a first end of the third conductive connector 407 on the base overlap, and the light-emitting element the anode of the light-emitting element is coupled to the first end of the third conductive connection 407 through a throw-hole at the overlapping location, the second end of the third conductive connection 407 and the first end of the second conductive connection 406 overlap, and the second end of the third conductive connection 407 and the first end of the second conductive connection 406 are coupled through a throw-hole at the overlapping location, the orthogonal projection of the second pole of the seventh transistor T7 on the base and the orthogonal projection of the second end of the second conductive connection 406 on the base overlap, and the second pole of the seventh transistor T7 is coupled to the second end of the second conductive connection 406 through a throw-hole at the overlapping location, and thus it is realized that the anode of the light-emitting element can be coupled to the second pole of the seventh transistor T7 through the second conductive connection 406 and the third conductive connection 407.

[0154] When the anode of the light-emitting element is coupled to the second pole of the seventh transistor T7 via the second conductive connection 406 and the third conductive connection 407, the second conductive connection 406 may include a portion extending in the first direction, the anode of the light-emitting element may be located above the light-emitting control signal line pattern in the corresponding sub-pixel, and the second pole of the seventh transistor T7 may be located below the light-emitting control signal line pattern in the corresponding sub-pixel.

[0155] As shown in FIGS. 15 and 24, the structure of the three color sub-pixels will be described by taking the illustrated three color sub-pixels as an example.

[0156] The light-emitting element in the first-color sub-pixel includes a first anode 601, a first organic light-emitting material layer, and a first cathode, which are sequentially stacked along a direction away from the base, and the orthogonal projection of the first anode 601 on the base and the orthogonal projection of the second pole of the corresponding seventh transistor T7 on the base partially overlap, and the first anode 601 is coupled to the second pole of the corresponding seventh transistor T7 through a throw-off hole at the overlapping portion.

[0157] The light-emitting element in the second-color subpixel includes a second anode 602, a second organic light-emitting material layer, and a second cathode, which are sequentially stacked along a direction away from the base, and the orthogonal projection of the second anode 602 on the base does not overlap with the orthogonal projection of the second pole of the corresponding seventh transistor T7 on the base. The subpixel driving circuit in the second-color subpixel further includes a second conductive connection 406 and a third conductive connection 407, and the second anode 602 is coupled to the second pole of the corresponding seventh transistor T7 via the second conductive connection 406 and the third conductive connection 407.

[0158] The light-emitting element in the third-color sub-pixel includes a third anode 603, a third organic light-emitting material layer, and a third cathode, which are sequentially stacked along a direction away from the base, and the orthogonal projection of the third anode 603 on the base and the orthogonal projection of the second pole of the corresponding seventh transistor T7 on the base partially overlap, and the third anode 603 is coupled to the second pole of the corresponding seventh transistor T7 through a throw-off hole at the overlapping portion.

[0159] For example, as shown in FIG. 15, the anodes of the organic light-emitting elements of the sub-pixels of each color all include a main electrode and a connection electrode, and the main electrodes are all hexagonal in shape.

[0160] 15 , the first anode 601 of the first color subpixel includes a first body electrode 6011 and a first connecting electrode 6012, the first body electrode 6011 and the first connecting electrode 6012 may be integral with each other, and the first connecting electrode 6012 may be connected to the second pole of the seventh transistor T7 of the first color subpixel through a connecting hole. The second anode 602 of the second color subpixel includes a second body electrode 6021 and a second connecting electrode 6022, the second body electrode 6021 and the second connecting electrode 6022 may be integral with each other, and the second connecting electrode 6022 may be connected to the second pole of the seventh transistor T7 of the second color subpixel through a second conductive connector 406 and a third conductive connector 407. The third anode 603 of the third color subpixel includes a third body electrode 6031 and a third connecting electrode 6032, the third body electrode 6031 and the third connecting electrode 6032 are integral with each other, and the third connecting electrode 6032 may be connected to the second electrode of the seventh transistor T7 of the third color subpixel through a connecting hole.

[0161] For example, the first connection electrode 6012 of a first-color subpixel is located farther from the data line pattern of the pixel circuit of the subpixel with respect to the center of the first body electrode 6011 in the X direction, and farther from the light-emitting control signal line of the pixel circuit of the subpixel with respect to the center of the first body electrode 6011 in the Y direction. For example, the first connection electrode 6012 and the first body electrode 6011 of the first-color subpixel are arranged in the Y direction, and the first connection electrode 6012 is located in the lower right corner of the first body electrode 6011. For example, the second connection electrode 6022 of a second-color subpixel is located farther from the data line of the pixel circuit of the subpixel with respect to the center of the second body electrode 6021 in the X direction, and nearer to the light-emitting control signal line of the pixel circuit of the subpixel with respect to the center of the second body electrode 6021 in the Y direction. For example, the second connection electrode 6022 and the second body electrode 6021 of a subpixel of a second color are aligned in the Y direction, and the second connection electrode 6022 is located at the bottom right corner of the first body electrode 1231. For example, the third connection electrode 6032 and the third body electrode 6031 of a subpixel of a third color are aligned in the X direction, and the third connection electrode 6032 is located closer to the right side of the third body electrode 6031, i.e., the side of the pixel circuit of the subpixel that is closer to the shielding line.

[0162] As shown in FIG. 15 , the first body electrode 6011 of the first anode 601 of the first color subpixel covers the driving transistor of the first color subpixel, the second body electrode 6021 of the second anode 602 of the second color subpixel has almost no overlap or partial overlap with the driving transistor of the second color subpixel, and the third body electrode 6031 of the third anode 603 of the third color subpixel has no overlap with the driving transistor of the third color subpixel.

[0163] 15 , the first body electrode 6011 of a first-color subpixel 601 (e.g., a blue subpixel) overlaps with the gate line pattern and the light-emission control signal line pattern, the second body electrode 6021 of a second-color subpixel (e.g., a red subpixel) overlaps with the gate line pattern and the reset signal line pattern, and the third body electrode 6031 of a third-color subpixel (e.g., a green subpixel) overlaps with the light-emission control signal line pattern, the reset signal line pattern of the subpixel drive circuit of the next row, and the initialization signal line pattern of the subpixel drive circuit of the next row. For example, the third body electrode 6031 of a third-color subpixel (e.g., a green subpixel) overlaps with the pixel drive circuit region of the first-color subpixel (e.g., a blue subpixel) adjacent to it in the next row.

[0164] For example, the first body electrode 6011 of the first-color subpixel 601 overlaps with the driving transistor of the adjacent third-color subpixel, and the first body electrode 6011 of the first-color subpixel 601 overlaps with the data line pattern in its subpixel driving circuit, the first shield member 404, and the data line pattern in the subpixel driving circuit of the adjacent second-color subpixel. The second body electrode 6021 of the second-color subpixel does not overlap with the data line pattern in its subpixel driving circuit, but overlaps with the power signal line pattern in its subpixel driving circuit and both the power signal line pattern and the data line pattern in the subpixel driving circuit of the adjacent third-color subpixel. The third body electrode 6031 of the third-color subpixel overlaps with both the data line pattern and the power signal line pattern in its subpixel driving circuit and also overlaps with the power signal line pattern in the subpixel driving circuit of the adjacent second-color subpixel.

[0165] For example, as shown in FIG. 15, the first body electrode 6011 of the first color subpixel 601 is provided with a first connection electrode 6012 connected to it on the side closer to the reset signal line pattern of the next row, the second body electrode 6021 of the second color subpixel is provided with a second connection electrode 6022 connected to it on the side closer to the reset signal line pattern of the next row, and the third body electrode 6031 of the third color subpixel is provided with a third connection electrode 6032 connected to it on the side closer to the seventh transistor T7.

[0166] 15 , the first connecting electrode 6012 of a first-color subpixel 601 overlaps with the second pole of the seventh transistor T7 in its subpixel driving circuit. The second connecting electrode 6022 of a second-color subpixel does not overlap with the second pole of the seventh transistor T7 in its subpixel driving circuit, while the second pole of the seventh transistor T7 of the second-color subpixel overlaps with the third body electrode 6031 of a third-color subpixel. The third connecting electrode 6032 of the third-color subpixel overlaps with the second pole of the seventh transistor T7 in its subpixel driving circuit.

[0167] As shown in FIG. 26, an embodiment of the present disclosure is a display substrate including a base 50 and a plurality of sub-pixels arrayed on the base 50, wherein the sub-pixels include: a data line pattern (e.g., DATA1) extending in a first direction; an initialization signal line pattern (e.g., VINT1) including a portion extending in a second direction intersecting the first direction and for transmitting an initialization signal having a fixed potential; The display substrate further includes a subpixel driving circuit including a driving transistor (e.g., a third transistor T3), a first transistor T1 coupled to the gate of the driving transistor, and a first shielding member 404 coupled to the initialization signal line pattern, wherein the first shielding member 404 is for forming a coupling capacitor with a first pole (i.e., source S1) of the first transistor T1, and the orthogonal projection of the first shielding member 404 on the base 50 and the orthogonal projection of a target data line pattern (e.g., DATA2) on the base 50 do not overlap, and the target data line pattern is included in a next subpixel adjacent to the subpixel in the second direction.

[0168] Specifically, the display substrate generally includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes a data line pattern (e.g., DATA1 in FIG. 3) extending in a first direction and an initialization signal line pattern (e.g., VINT1 in FIG. 3) at least a portion of which extends in a second direction, the data line pattern for transmitting a data signal, and the initialization signal line pattern for transmitting an initialization signal having a fixed potential, and for example, the first direction includes the Y direction, and the second direction includes the X direction.

[0169] The target data line pattern is a data line pattern included in the next sub-pixel adjacent to the current sub-pixel in the second direction.

[0170] Each subpixel further includes a subpixel drive circuit and a light-emitting element corresponding to the subpixel drive circuit in a one-to-one relationship. The light-emitting element includes an anode, an organic light-emitting material layer, and a cathode, which are stacked together. The anode is coupled to the corresponding subpixel drive circuit, and the light-emitting element emits light when driven by a drive signal supplied by the subpixel drive circuit.

[0171] 1, 3 and 4, taking the case where the subpixel driving circuit includes the above-mentioned 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) is coupled to the drain D1 of the first transistor T1, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1 via a connecting line 401. In the X direction, the minimum distance between the orthogonal projection of the first channel region 101pg of the first transistor T1 on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in FIG. 3 ) on the base 50 is smaller than the minimum distance between the orthogonal projection of the third channel region 103pg of the third transistor T3 on the base 50 and the orthogonal projection of the target data line pattern on the base 50. Please note that the minimum distance between the orthogonal projection of the channel region (e.g., the first channel region 101pg and the third channel region 103pg) on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) on the base 50 means the minimum distance between the boundary of the channel region closest to the target data line pattern in the orthogonal projection on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) on the base 50.

[0172] In the subpixel driving circuit having the above structure, any change in the data signal transmitted by the target data line pattern will affect the performance of the first transistor T1, which will further affect the operating performance of the third transistor T3 because the first transistor T1 is coupled to the third transistor T3 via the connecting line 401.

[0173] In contrast, the embodiment of the present disclosure provides a first shielding member 404 coupled to the initialization signal line pattern (e.g., VINT1 in FIG. 3 ) in the subpixel driving circuit. The first shielding member 404 has the same fixed potential as the initialization signal. The first shielding member 404 is configured to form a coupling capacitor with the first pole (i.e., source S1) of the first transistor T1. This reduces the impact of changes in the signal transmitted through the target data line pattern on the performance of the first transistor T1, and further reduces the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, thereby alleviating the problem of vertical crosstalk. Therefore, the display substrate can achieve a better display effect when used for display.

[0174] Furthermore, by coupling the first shielding member 404 with the initialization signal line pattern as described above, not only is the first shielding member 404 provided with a fixed potential, but the voltage of the initialization signal line pattern is also strengthened, which makes the voltage of the initialization signal transmitted by the initialization signal line pattern more stable, thereby further contributing to the operating performance of the subpixel driving circuit.

[0175] It should be noted that in addition to coupling the first shielding member 404 to the initialization signal line pattern, the first shielding member 404 may also be coupled to a power supply signal line pattern VDD included in the sub-pixel, so that the first shielding member 404 has the same fixed potential as the power supply signal transmitted by the power supply signal line pattern VDD.

[0176] Although the above-described method of coupling the first shielding member 404 and the power signal line pattern VDD can ensure that the first shielding member 404 has a fixed potential, the parasitic capacitance generated by the power signal line pattern VDD increases, which increases the RC load of the power signal line pattern VDD and is unfavorable for reducing vertical crosstalk.

[0177] As shown in FIG. 3, in some embodiments, the gate 201g of the first transistor T1 and the gate line pattern GATE are an integral structure, and the gate 201g of the first transistor T1 is a part of the integral structure that can form an overlap region with an active film layer in a direction perpendicular to the base.

[0178] As shown in FIG. 3, in some embodiments, the plurality of sub-pixels include a plurality of rows of sub-pixels, each row of sub-pixels including a plurality of the sub-pixels arranged in the second direction, the initialization signal line patterns located in the sub-pixels of the same row are sequentially combined to form an initialization signal line corresponding to the row of sub-pixels, and the first shielding member 404 extends in the first direction and is combined with at least one of the initialization signal lines.

[0179] Specifically, the plurality of sub-pixels are divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels aligned in a second direction, and each column of sub-pixels includes a plurality of sub-pixels aligned in a first direction, and the first direction and the second direction may intersect, and the initialization signal line patterns located in the sub-pixels of the same row are sequentially coupled to form one initialization signal line corresponding to the sub-pixels of the row.

[0180] As described above, by arranging the first shielding member 404 to extend in the first direction and be coupled to at least one of the initialization signal lines, the first shielding member 404 can reduce the impact of changes in the signal transmitted through the target data line pattern on the performance of the first transistor T1, and further reduce the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, thereby mitigating the problem of vertical crosstalk. Therefore, when the display substrate is used for display, not only can a better display effect be achieved, but the voltage of the initialization signal line can also be strengthened, making the voltage of the initialization signal transmitted through the initialization signal line more stable, which is more beneficial to the operating performance of the sub-pixel driving circuit.

[0181] As shown in FIG. 9, in some embodiments, the first shield member 404 is coupled to two of the initialization signal lines adjacent to it.

[0182] Specifically, when the first shielding member 404 and the initialization signal line are coupled together, the coupling manner between the first shielding member 404 and the initialization signal line, and the specific structure and installation method of the first shielding member 404 can all be various. For example, as shown in FIG. 3, the first shielding member 404 may be coupled to each of the two initialization signal lines adjacent to it. With this installation method, the orthogonal projection of the first shielding member 404 on the base 50 can be located not only between the orthogonal projection of the first transistor T1 on the base 50 and the orthogonal projection of the target data line pattern on the base 50, but also between the orthogonal projection of the connecting line 401 on the base 50 and the orthogonal projection of the target data line pattern on the base 50. In addition, the orthogonal projection of the first shielding member 404 on the base 50 can be located between the orthogonal projection of the driving transistor (i.e., the third transistor T3) on the base 50 and the orthogonal projection of the target data line pattern on the base 50.

[0183] The above-mentioned arrangement effectively reduces the first crosstalk occurring between the target signal line pattern and the first transistor T1 and the second crosstalk occurring between the target signal line pattern and the connecting line 401, thereby reducing indirect crosstalk to the driving transistor due to the first crosstalk and the second crosstalk. In addition, the above-mentioned arrangement effectively reduces the direct crosstalk occurring between the target signal line pattern and the driving transistor, thereby better ensuring the operating performance of the display substrate.

[0184] Continuing to refer to FIG. 3, in some embodiments, the first shield member 404 and the initialization signal line pattern (e.g., VINT1 in FIG. 3) are provided on different layers, there is a first overlap region between the orthogonal projection of the first shield member 404 on the base 50 and the orthogonal projection of the initialization signal line pattern on the base, and the first shield member 404 is coupled to the initialization signal line pattern via a first throw hole provided in the first overlap region.

[0185] Specifically, the first shielding member 404 may be provided on the same layer as the initialization signal line pattern, or on a different layer. If the first shielding member 404 and the initialization signal line pattern are provided on different layers, the first shielding member 404 may be provided so that there is a first overlapping region in both the orthogonal projection of the first shielding member 404 on the base 50 and the orthogonal projection of the initialization signal line pattern on the base 50. In this case, by providing a first throw-hole in the first overlapping region, coupling between the first shielding member 404 and the initialization signal line can be achieved.

[0186] It should be noted that the above statement "the first shielding member 404 may be provided in the same layer as the initialization signal line pattern" includes at least one of various cases, such as a case where the first shielding member 404 and the initialization signal line pattern are located on the same horizontal plane, a case where the first shielding member 404 and the initialization signal line pattern are located in the same film layer, a case where the first shielding member 404 and the initialization signal line pattern are both provided on the surface opposite the base of the same insulating layer, and a case where the first shielding member 404 and the initialization signal line pattern are formed in a single pattern construction process.

[0187] The above phrase "the first shielding member 404 may be provided in a layer different from the initialization signal line pattern" includes at least one of various cases, such as a case where the first shielding member 404 and the initialization signal line pattern are not located in the same film layer, and a case where the first shielding member 404 and the initialization signal line pattern cannot be formed in a single pattern configuration process.

[0188] In some embodiments, the first shielding member 404 and the data line pattern (eg, DATA1 in FIG. 3) may be made of the same material.

[0189] In some embodiments, the display substrate may include a first interlayer insulating layer, and the first shielding member 404 and the data line pattern (e.g., DATA1 in FIG. 3) may both be located on the surface of the interlayer insulating layer opposite the base.

[0190] Specifically, by providing the first shielding member 404 according to the above-described method, the first shielding member 404 and the data line pattern can be simultaneously formed on the surface of the interlayer insulating layer opposite the base in a single patterning process, and the need to add a separate patterning process for manufacturing the first shielding member 404 can be avoided, thereby favorably simplifying the manufacturing flow of the display substrate and saving manufacturing costs.

[0191] As shown in FIG. 3, in some embodiments, the subpixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, wherein the second transistor T2 is: a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, the third conductor pattern having a conductive performance superior to that of the first semiconductor pattern and that of the second semiconductor pattern; a first gate pattern and a second gate pattern coupled to each other, wherein an orthogonal projection of the first gate pattern on the base 50 partially overlaps an orthogonal projection of the first semiconductor pattern on the base 50, and an orthogonal projection of the second gate pattern on the base 50 partially overlaps an orthogonal projection of the second semiconductor pattern on the base 50; an orthogonal projection of the third conductor pattern on the base 50, an orthogonal projection of the first gate pattern on the base 50, and an orthogonal projection of the second gate pattern on the base 50 do not overlap each other; The orthogonal projection of the third conductor pattern on the base 50 at least partially overlaps with the orthogonal projection of the initialization signal line pattern (for example, VINT1 in FIG. 3) on the base 50.

[0192] Specifically, as shown in FIG. 7, the second transistor T2 has a double-gate structure, and the first and second semiconductor patterns included therein are connected to the channel region (FIG. 4 102pg in the figure), while the third conductor pattern 102px included therein is doped and therefore has better conductive properties than the first semiconductor pattern and the second semiconductor pattern, and the first gate pattern and the second gate pattern included in the second transistor T2 cover the first semiconductor pattern and the second semiconductor pattern in a one-to-one correspondence and can jointly serve as the gate 202g of the second transistor T2.

[0193] In the second transistor T2 having the above structure, the third conductor pattern 102px has good conductivity and is not covered by a gate pattern, so that it is prone to coupling with other nearby conductive patterns, resulting in crosstalk. In the technical solution according to the above embodiment, the orthogonal projection of the third conductor pattern on the base 50 and the orthogonal projection of the initialization signal line pattern (e.g., VINT1 in FIG. 3 ) on the base 50 are at least partially overlapped, so that the initialization signal line pattern can shield the third conductor pattern 102px. Furthermore, because the initialization signal line pattern transmits an initialization signal having a fixed potential, the coupling between the third conductor pattern 102px and other nearby conductive patterns is more effectively reduced, thereby stabilizing the operating performance of the display substrate.

[0194] As shown in FIG. 4 , in some embodiments, the subpixel driving circuit further includes a first extending portion extending from the first semiconductor pattern, where the first extending portion has better conductive properties than the first semiconductor pattern, and the first extending portion includes a first portion 61, a second portion 62, and a third portion 63, where the first portion 61 and the third portion 63 all extend in the first direction, the second portion 62 extends in the second direction, one end of the second portion 62 is coupled to the first portion 61, the other end of the second portion 62 is coupled to the third portion 63, and the end of the third portion 63 farther from the second portion 62 is coupled to the first transistor T1.

[0195] Specifically, the first extension portion may be fabricated together with the first semiconductor pattern in a single pattern formation process, and after the first semiconductor pattern is formed, the first extension portion may be doped so that the conductive performance of the first extension portion is superior to that of the first semiconductor pattern.

[0196] After adding the first shielding member 404, the first extension portion is configured as described above, so that the second transistor T2 is coupled to the gate of the first transistor T1 and the gate of the driving transistor through the first extension portion, which contributes to reducing the impact on the performance of the first transistor T1 and the performance of the second transistor T2 caused by changes in the signal transmitted through the target data line pattern. Furthermore, the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern is reduced, and the problem of vertical crosstalk is alleviated, so that the display substrate can achieve a better display effect when used for display.

[0197] As shown in FIGS. 3 and 4, in some embodiments, the first transistor T1 is a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, respectively, the sixth conductor pattern having a conductive property superior to that of the fourth semiconductor pattern and that of the fifth semiconductor pattern; a third gate pattern and a fourth gate pattern coupled to each other, wherein an orthogonal projection of the third gate pattern on the base 50 partially overlaps an orthogonal projection of the fourth semiconductor pattern on the base 50, and an orthogonal projection of the fourth gate pattern on the base 50 partially overlaps an orthogonal projection of the fifth semiconductor pattern on the base 50; The orthogonal projection of the sixth conductor pattern on the base 50, the orthogonal projection of the third gate pattern on the base 50, and the orthogonal projection of the fourth gate pattern on the base 50 do not overlap with each other.

[0198] Specifically, as shown in FIG. 4, the first transistor has a double-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included therein are formed as the channel region of the first transistor (corresponding to symbol 101pg in FIG. 4), while the sixth conductor pattern 101px included therein is doped and therefore has better conductive performance than the fourth semiconductor pattern and the fifth semiconductor pattern, and the third gate pattern and the fourth gate pattern included in the first transistor cover the fourth semiconductor pattern and the fifth semiconductor pattern in a one-to-one correspondence, and can jointly serve as the gate 201g of the first transistor T1.

[0199] As shown in FIG. 10, in some embodiments, the orthogonal projection of the first shield member 404 on the base 50 at least partially overlaps with the orthogonal projection of the sixth conductor pattern 101px on the base 50.

[0200] Specifically, in the first transistor T1 having the above structure, the sixth conductor pattern 101px has good conductivity and is not covered by a gate pattern, so that it is prone to coupling with other nearby conductive patterns, resulting in crosstalk. In the technical solution according to the above embodiment, the orthogonal projection of the first shielding member 404 on the base 50 and the orthogonal projection of the sixth conductor pattern 101px on the base 50 are at least partially overlapped, so that the first shielding member 404 can shield the sixth conductor pattern 101px. Furthermore, because the first shielding member 404 has a fixed potential, the coupling between the sixth conductor pattern 101px and other nearby conductive patterns is more effectively reduced, thereby stabilizing the operating performance of the display substrate.

[0201] 11, 12 and 13, in some embodiments, the subpixel driving circuit further includes a second shielding member 301 coupled to the first shielding member 404, and the orthogonal projection of the second shielding member 301 on the base 50 at least partially overlaps with the orthogonal projection of the sixth conductor pattern 101px on the base 50.

[0202] Specifically, as described above, by arranging the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the sixth conductor pattern 101px on the base 50 so that they at least partially overlap, the second shielding member 301 can shield the sixth conductor pattern 101px. Furthermore, since the second shielding member 301 and the first shielding member 404 are coupled together, the second shielding member 301 has a fixed potential, which more effectively reduces the coupling effect between the sixth conductor pattern 101px and other conductive patterns in its vicinity, thereby making the operating performance of the display substrate more stable.

[0203] Therefore, in the display substrate according to the above embodiment, since the first shielding member 404 and the second shielding member 301 both have a fixed potential, the formation of a parasitic capacitor between the first transistor T1 and the target data line pattern (e.g., DATA2) can be more effectively prevented or reduced, and vertical crosstalk defects can be effectively prevented or reduced.

[0204] Furthermore, the second shield member 301 may be provided so that the orthogonal projection on the base 50 covers the entire orthogonal projection on the base 50 of the sixth conductor pattern.

[0205] Specifically, by arranging the second shielding member 301 so that the orthogonal projection of the sixth conductor pattern 101px on the base 50 covers the entire orthogonal projection of the sixth conductor pattern 101px on the base 50, the second shielding member 301 can completely shield the sixth conductor pattern 101px, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other conductive patterns in its vicinity, and more preferably improving the operational stability of the display substrate.

[0206] In some embodiments, the second shielding member 301 is provided on a different layer from the first shielding member 404, and there is a second overlapping region between the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the first shielding member 404 on the base 50, and the second shielding member 301 and the first shielding member 404 are connected via a second throw hole provided in the overlapping region.

[0207] Specifically, the second shielding member 301 may be provided in the same layer as the first shielding member 404, or in a different layer. If the second shielding member 301 and the first shielding member 404 are provided in different layers, they may be provided so that there is a second overlapping region between the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the first shielding member 404 on the base 50. In this case, by providing a second throw hole in the overlapping region, coupling between the second shielding member 301 and the first shielding member 404 via the second throw hole can be achieved.

[0208] In some embodiments, the second shielding member 301 and the initialization signal line pattern may be made of the same material.

[0209] In some embodiments, the display substrate further includes a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern (e.g., VINT1 in FIG. 3) may both be located on the surface of the second interlayer insulating layer opposite the base.

[0210] Specifically, as described above, the second shielding member 301 and the initialization signal line pattern are made of the same material, and the second shielding member 301 and the initialization signal line pattern (e.g., VINT1 in Figure 3) are both positioned on the surface of the second interlayer insulating layer opposite the base. This allows the second shielding member 301 and the initialization signal line pattern to be formed simultaneously using the same pattern formation process, thereby avoiding the need to add a separate manufacturing process dedicated to manufacturing the second shielding member 301, thereby favorably simplifying the manufacturing flow of the display substrate and saving production costs.

[0211] As shown in FIG. 3 , in some embodiments, the subpixel further includes a power signal line pattern VDD, which includes a portion extending in the first direction. The subpixel driving circuit further includes a storage capacitor Cst, a first electrode Cst1 of which doubles as the gate of the driving transistor, and a second electrode Cst2 of which is coupled to the power signal line pattern VDD, and the second electrode Cst2 of the storage capacitor Cst is located on a surface of the second interlayer insulating layer opposite to the base.

[0212] Specifically, the storage capacitor Cst included in the subpixel driving circuit has a first electrode Cst1 and a second electrode Cst2, the first electrode Cst1 and the second electrode Cst2 are arranged opposite to each other, the first electrode Cst1 is coupled to the gate of the driving transistor, and the second electrode Cst2 is coupled to the power signal line pattern VDD. When the storage capacitor Cst is laid out, the first electrode Cst1 can also be used as the gate of the driving transistor, which ensures the coupling between the storage capacitor Cst and the gate of the driving transistor and reduces the space occupied by the subpixel driving circuit, thereby contributing to improving the resolution of the display substrate. Furthermore, by arranging the second electrode Cst2 of the storage capacitor Cst to be located on the surface of the second interlayer insulating layer opposite to the base, the second electrode Cst2 of the storage capacitor Cst, the second shielding member 301, and the initialization signal line pattern can be formed simultaneously using the same pattern formation process, which advantageously simplifies the manufacturing flow of the display substrate and reduces production costs.

[0213] As shown in FIG. 14 , in some embodiments, the sub-pixel further includes a reset signal line pattern (e.g., RST1 in FIG. 3 ) extending in a second direction intersecting the first direction, and the sub-pixel driving circuit includes: a first conductive connection portion 405, the orthogonal projection of which on the base 50 covers at least a part of the orthogonal projection of the sixth conductor pattern 101px on the base 50; a second transistor T2, the first pole (e.g., source S2) of which is coupled to the initialization signal line pattern (e.g., VINT1) via the first conductive connection 405, the second pole (e.g., drain D2) of which is coupled to the gate of the driving transistor, and the gate 202g of which is coupled to the reset signal line pattern (e.g., RST1); Further includes:

[0214] Specifically, the first conductive connection part 405 can be made of a metal material and can be formed in the same pattern forming process as the data line pattern.

[0215] As described above, by arranging the first conductive connection portion 405 so that the orthogonal projection of the sixth conductor pattern 101px on the base 50 covers at least a portion of the orthogonal projection of the sixth conductor pattern 101px on the base 50, the first conductive connection portion 405 can shield the sixth conductor pattern 101px. Furthermore, since the first conductive connection portion 405 and the initialization signal line pattern are coupled to each other, the first conductive connection portion 405 has a fixed potential, which more effectively reduces the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, thereby making the operating performance of the display substrate more stable.

[0216] As shown in FIG. 3 , in some embodiments, the sub-pixel further includes a gate line pattern GATE, an emission control signal line pattern EM, a reset signal line pattern (e.g., RST1 in FIG. 3 ), and a power supply signal line pattern VDD, wherein the gate line pattern GATE, the emission control signal line pattern EM, and the reset signal line pattern all extend in the second direction, and the power supply signal line pattern VDD includes a portion extending in the first direction; the sub-pixel driving circuit further includes a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7; a gate of the driving transistor (e.g., the gate 203g of the third transistor T3) is coupled to the second pole of the first transistor T1, a first pole of the driving transistor is coupled to the second pole of the fifth transistor T5, and a second pole of the driving transistor is coupled to the first pole of the first transistor T1; The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE; a gate 202g of the second transistor T2 is coupled to the reset signal line pattern, a first pole of the second transistor T2 is coupled to the initialization signal line pattern, and a second pole of the second transistor T2 is coupled to the gate of the driving transistor; a gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, a first pole of the fourth transistor T4 is coupled to the data line pattern (e.g., DATA1 in FIG. 3), and a second pole of the fourth transistor T4 is coupled to the first pole of the driving transistor; a gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and a first electrode of the fifth transistor T5 is coupled to the power supply signal line pattern VDD; a gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, a first pole of the sixth transistor T6 is coupled to a second pole of the driving transistor T1, and a second pole of the sixth transistor T6 is coupled to a light emitting element in the sub-pixel; The gate 207g of the seventh transistor T7 is coupled to a reset signal line pattern (e.g., RST2) included in the next adjacent subpixel in the first direction, a first pole of the seventh transistor T7 is coupled to an initialization signal line pattern (e.g., VINT2) included in the next subpixel, and a second pole of the seventh transistor T7 is coupled to a light-emitting element in the subpixel.

[0217] Specifically, the display substrate may include a plurality of sub-pixels arranged in an array, the sub-pixels being divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels, each row of the sub-pixels including a plurality of sub-pixels aligned in a second direction, and each column of the sub-pixels including a plurality of sub-pixels aligned in a first direction, such that the first direction and the second direction intersect.

[0218] It should be noted that the next adjacent sub-pixel in the first direction refers to the next adjacent sub-pixel located in the same column as the seventh transistor T7.

[0219] By arranging the subpixels and the subpixel driving circuits included therein in the above-described structure, it is possible to effectively reduce the layout space occupied by the subpixel driving circuits, on the premise that the operational performance of the subpixel driving circuits is guaranteed, thereby contributing to improving the resolution of the display substrate.

[0220] It should be noted that the gate of each transistor included in the sub-pixel driving circuit and the functional pattern associated therewith may be formed as an integral structure. For example, the gate of the first transistor and the gate of the fourth transistor are both integral with the correspondingly associated gate line pattern, the gate of the fifth transistor and the gate of the sixth transistor are both integral with the correspondingly associated light-emitting control signal line pattern, and the gate of the second transistor and the gate of the seventh transistor are both integral with the correspondingly associated reset signal line pattern.

[0221] In addition, the first transistor T1 is for performing threshold compensation for the driving transistor (e.g., the third transistor T3), the second transistor T2 is for resetting the gate of the driving transistor, the fourth transistor T4 is for writing the data signal transmitted by the data line pattern, the fifth transistor T5 is for writing the power signal transmitted by the power signal line pattern to the first electrode of the driving transistor, the sixth transistor T6 is for controlling whether the corresponding light-emitting element emits light, and the seventh transistor T7 is for resetting the anode of the light-emitting element.

[0222] In some embodiments, the sub-pixel further includes a gate line pattern GATE, an emission control signal line pattern EM, a reset signal line pattern RST, and a power supply signal line pattern VDD, wherein the gate line pattern GATE, the emission control signal line pattern EM, and the reset signal line pattern RST all extend in the second direction, the power supply signal line pattern VDD includes a portion extending in the first direction, and the orthogonal projection of the first shielding member 404 on the base 50 partially overlaps with the orthogonal projection of the gate line pattern GATE on the base 50 and the orthogonal projection of the emission control signal line pattern EM on the base 50, respectively.

[0223] Specifically, by laying out the first shielding member 404 according to the above manner, the first shielding member 404 can isolate both the first transistor T1 and the driving transistor from the target data line pattern (e.g., DATA2), thereby contributing to reducing crosstalk to the first transistor T1 and the driving transistor due to changes in the data signal in the target data line pattern.

[0224] In some embodiments, the coupling manner between the second pole of the seventh transistor T7 and the light-emitting element in the sub-pixel may be various. For example, the orthogonal projection of the anode of the light-emitting element on the base and the orthogonal projection of the second pole of the seventh transistor T7 on the base overlap, and the anode of the light-emitting element can be coupled to the second pole of the seventh transistor T7 through a throw-hole provided at the overlapping location; or the orthogonal projection of the anode of the light-emitting element on the base and the orthogonal projection of the second pole of the seventh transistor T7 on the base do not overlap, and the sub-pixel driving circuit further includes a second conductive connector 406 and a third conductive connector 407, and the orthogonal projection of the anode of the light-emitting element on the base and the orthogonal projection of a first end of the third conductive connector 407 on the base overlap, and the light-emitting element the anode of the light-emitting element is coupled to the first end of the third conductive connection 407 through a throw-hole at the overlapping location, the second end of the third conductive connection 407 and the first end of the second conductive connection 406 overlap, and the second end of the third conductive connection 407 and the first end of the second conductive connection 406 are coupled through a throw-hole at the overlapping location, the orthogonal projection of the second pole of the seventh transistor T7 on the base and the orthogonal projection of the second end of the second conductive connection 406 on the base overlap, and the second pole of the seventh transistor T7 is coupled to the second end of the second conductive connection 406 through a throw-hole at the overlapping location, and thus it is realized that the anode of the light-emitting element can be coupled to the second pole of the seventh transistor T7 through the second conductive connection 406 and the third conductive connection 407.

[0225] When the anode of the light-emitting element is coupled to the second pole of the seventh transistor T7 via the second conductive connection 406 and the third conductive connection 407, the second conductive connection 406 may include a portion extending in the first direction, the anode of the light-emitting element may be located above the light-emitting control signal line pattern in the corresponding sub-pixel, and the second pole of the seventh transistor T7 may be located below the light-emitting control signal line pattern in the corresponding sub-pixel.

[0226] As shown in FIG. 15, the structure of the three color sub-pixels will be described by taking the illustrated three color sub-pixels as an example.

[0227] The light-emitting element in the first-color sub-pixel includes a first anode 601, a first organic light-emitting material layer, and a first cathode, which are sequentially stacked along a direction away from the base, and the orthogonal projection of the first anode 601 on the base and the orthogonal projection of the second pole of the corresponding seventh transistor T7 on the base partially overlap, and the first anode 601 is coupled to the second pole of the corresponding seventh transistor T7 through a throw-off hole at the overlapping portion.

[0228] The light-emitting element in the second-color subpixel includes a second anode 602, a second organic light-emitting material layer, and a second cathode, which are sequentially stacked along a direction away from the base, and the orthogonal projection of the second anode 602 on the base does not overlap with the orthogonal projection of the second pole of the corresponding seventh transistor T7 on the base. The subpixel driving circuit in the second-color subpixel further includes a second conductive connection 406 and a third conductive connection 407, and the second anode 602 is coupled to the second pole of the corresponding seventh transistor T7 via the second conductive connection 406 and the third conductive connection 407.

[0229] The light-emitting element in the third-color sub-pixel includes a third anode 603, a third organic light-emitting material layer, and a third cathode, which are sequentially stacked along a direction away from the base, and the orthogonal projection of the third anode 603 on the base and the orthogonal projection of the second pole of the corresponding seventh transistor T7 on the base partially overlap, and the third anode 603 is coupled to the second pole of the corresponding seventh transistor T7 through a throw-off hole at the overlapping portion.

[0230] For example, as shown in FIG. 15, the anodes of the organic light-emitting elements of the sub-pixels of each color all include a main electrode and a connection electrode, and the main electrodes are all hexagonal in shape.

[0231] 15 , the first anode 601 of the first color subpixel includes a first body electrode 6011 and a first connecting electrode 6012, the first body electrode 6011 and the first connecting electrode 6012 may be integral with each other, and the first connecting electrode 6012 may be connected to the second pole of the seventh transistor T7 of the first color subpixel through a connecting hole. The second anode 602 of the second color subpixel includes a second body electrode 6021 and a second connecting electrode 6022, the second body electrode 6021 and the second connecting electrode 6022 may be integral with each other, and the second connecting electrode 6022 may be connected to the second pole of the seventh transistor T7 of the second color subpixel through a second conductive connector 406 and a third conductive connector 407. The third anode 603 of the third color subpixel includes a third body electrode 6031 and a third connecting electrode 6032, the third body electrode 6031 and the third connecting electrode 6032 are integral with each other, and the third connecting electrode 6032 may be connected to the second electrode of the seventh transistor T7 of the third color subpixel through a connecting hole.

[0232] For example, the first connection electrode 6012 of a first-color subpixel is located farther from the data line pattern of the pixel circuit of the subpixel with respect to the center of the first body electrode 6011 in the X direction, and farther from the light-emitting control signal line of the pixel circuit of the subpixel with respect to the center of the first body electrode 6011 in the Y direction. For example, the first connection electrode 6012 and the first body electrode 6011 of the first-color subpixel are arranged in the Y direction, and the first connection electrode 6012 is located in the lower right corner of the first body electrode 6011. For example, the second connection electrode 6022 of a second-color subpixel is located farther from the data line of the pixel circuit of the subpixel with respect to the center of the second body electrode 6021 in the X direction, and nearer to the light-emitting control signal line of the pixel circuit of the subpixel with respect to the center of the second body electrode 6021 in the Y direction. For example, the second connection electrode 6022 and the second body electrode 6021 of a subpixel of a second color are aligned in the Y direction, and the second connection electrode 6022 is located at the bottom right corner of the first body electrode 1231. For example, the third connection electrode 6032 and the third body electrode 6031 of a subpixel of a third color are aligned in the X direction, and the third connection electrode 6032 is located closer to the right side of the third body electrode 6031, i.e., the side of the pixel circuit of the subpixel that is closer to the shielding line.

[0233] As shown in FIG. 15 , the first body electrode 6011 of the first anode 601 of the first color subpixel covers the driving transistor of the first color subpixel, the second body electrode 6021 of the second anode 602 of the second color subpixel has almost no overlap or partial overlap with the driving transistor of the second color subpixel, and the third body electrode 6031 of the third anode 603 of the third color subpixel has no overlap with the driving transistor of the third color subpixel.

[0234] 15 , the first body electrode 6011 of a first-color subpixel 601 (e.g., a blue subpixel) overlaps with the gate line pattern and the light-emission control signal line pattern, the second body electrode 6021 of a second-color subpixel (e.g., a red subpixel) overlaps with the gate line pattern and the reset signal line pattern, and the third body electrode 6031 of a third-color subpixel (e.g., a green subpixel) overlaps with the light-emission control signal line pattern, the reset signal line pattern of the subpixel drive circuit of the next row, and the initialization signal line pattern of the subpixel drive circuit of the next row. For example, the third body electrode 6031 of a third-color subpixel (e.g., a green subpixel) overlaps with the pixel drive circuit region of the first-color subpixel (e.g., a blue subpixel) adjacent to it in the next row.

[0235] For example, the first body electrode 6011 of the first-color subpixel 601 overlaps with the driving transistor of the adjacent third-color subpixel, and the first body electrode 6011 of the first-color subpixel 601 overlaps with the data line pattern in its subpixel driving circuit, the first shield member 404, and the data line pattern in the subpixel driving circuit of the adjacent second-color subpixel. The second body electrode 6021 of the second-color subpixel does not overlap with the data line pattern in its subpixel driving circuit, but overlaps with the power signal line pattern in its subpixel driving circuit and both the power signal line pattern and the data line pattern in the subpixel driving circuit of the adjacent third-color subpixel. The third body electrode 6031 of the third-color subpixel overlaps with both the data line pattern and the power signal line pattern in its subpixel driving circuit and also overlaps with the power signal line pattern in the subpixel driving circuit of the adjacent second-color subpixel.

[0236] For example, as shown in FIG. 15, the first body electrode 6011 of the first color subpixel 601 is provided with a first connection electrode 6012 connected to it on the side closer to the reset signal line pattern of the next row, the second body electrode 6021 of the second color subpixel is provided with a second connection electrode 6022 connected to it on the side closer to the reset signal line pattern of the next row, and the third body electrode 6031 of the third color subpixel is provided with a third connection electrode 6032 connected to it on the side closer to the seventh transistor T7.

[0237] 15 , the first connecting electrode 6012 of a first-color subpixel 601 overlaps with the second pole of the seventh transistor T7 in its subpixel driving circuit. The second connecting electrode 6022 of a second-color subpixel does not overlap with the second pole of the seventh transistor T7 in its subpixel driving circuit, while the second pole of the seventh transistor T7 of the second-color subpixel overlaps with the third body electrode 6031 of a third-color subpixel. The third connecting electrode 6032 of the third-color subpixel overlaps with the second pole of the seventh transistor T7 in its subpixel driving circuit.

[0238] An embodiment of the present disclosure further provides a display device including a display substrate according to the above embodiment.

[0239] In the display substrate according to the above embodiment, the first shielding member 404 is provided to reduce the impact of changes in the signal transmitted through the target data line pattern on the performance of the first transistor T1, and further reduce the coupling effect between the gate of the driving transistor (i.e., 203g) and the target data line pattern, thereby alleviating the problem of vertical crosstalk, so that the display substrate can achieve a better display effect when used for display. In addition, in the display substrate according to the above embodiment, the coupling of the first shielding member 404 with the initialization signal line pattern not only allows the first shielding member 404 to have a fixed potential, but also strengthens the voltage of the initialization signal line pattern, making the voltage of the initialization signal transmitted through the initialization signal line pattern more stable, which further contributes to the operating performance of the subpixel driving circuit.

[0240] Therefore, when a display device according to an embodiment of the present disclosure includes the above display substrate, it also has the above beneficial effects, which will not be repeated here.

[0241] It should be noted that the display device can be any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet PC, etc.

[0242] An embodiment of the present disclosure is a manufacturing method for manufacturing a display substrate according to the above embodiment, the manufacturing method comprising: The method includes fabricating a plurality of sub-pixels arranged in an array on a base 50, the sub-pixels comprising: a data line pattern (e.g., DATA1 in FIG. 3) extending in a first direction; an initialization signal line pattern (e.g., VINT1 in FIG. 3) including a portion extending in a second direction intersecting the first direction and for transmitting an initialization signal having a fixed potential; The present invention further provides a method for manufacturing a display substrate, the method including a subpixel driving circuit including a driving transistor (e.g., T3 in FIG. 3), a first transistor T1 coupled to a gate of the driving transistor, and a first shielding member 404 coupled to the initialization signal line pattern, wherein an orthogonal projection of the first shielding member 404 on the base 50 is located between an orthogonal projection of the first transistor T1 on the base 50 and an orthogonal projection of a target data line pattern (e.g., DATA2 in FIG. 3) on the base 50, and a next subpixel adjacent to the subpixel in the second direction includes the target data line pattern.

[0243] When the display substrate is fabricated using the fabrication method according to the embodiment of the present disclosure, a first shielding member 404 coupled to the initialization signal line pattern (e.g., VINT1 in FIG. 3 ) is provided in the subpixel driving circuit, and the first shielding member 404 has the same fixed potential as the initialization signal. The orthogonal projection of the first shielding member 404 on the base 50 is positioned between the orthogonal projection of the first transistor T1 on the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in FIG. 3 ) on the base 50. This first shielding member 404 reduces the impact of changes in the signal transmitted through the target data line pattern on the performance of the first transistor T1, and further reduces the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, thereby alleviating the problem of vertical crosstalk. Therefore, the display substrate can achieve a better display effect when used for display.

[0244] Furthermore, when the display substrate is manufactured using the manufacturing method according to the embodiment of the present disclosure, the first shielding member 404 is coupled to the initialization signal line pattern, which not only provides a fixed potential to the first shielding member 404 but also strengthens the voltage of the initialization signal line pattern, thereby making the voltage of the initialization signal transmitted by the initialization signal line pattern more stable, thereby further contributing to the operating performance of the subpixel driving circuit.

[0245] As shown in FIG. 16, an embodiment of the present disclosure is a display substrate including a base 50 and a plurality of sub-pixels arrayed on the base 50, wherein the sub-pixels include: a data line pattern (e.g., DATA1) extending in a first direction; a power supply signal line pattern VDD including a portion extending in the first direction; A sub-pixel driving circuit includes two switch transistors (e.g., a fourth transistor T4 and a fifth transistor T5), a driving transistor (e.g., a third transistor T3), and a storage capacitor Cst, wherein a first electrode Cst1 of the storage capacitor Cst is coupled to a gate of the driving transistor (e.g., a gate 203g of the third transistor T3), a second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, and a second electrode Cst3 of the two switch transistors (e.g., a drain D of the fourth transistor T4) is coupled to the power signal line pattern VDD. the drain D5 of the fourth and fifth transistors T4 and T5) are both coupled to the first electrode of the driving transistor (e.g., the source S3 of the third transistor T3), and the orthogonal projection of the second electrode of at least one of the two switch transistors on the base 50 at least partially overlaps with the orthogonal projection of the power supply signal line pattern VDD on the base 50 and at least partially overlaps with the orthogonal projection of the second electrode Cst2 of the storage capacitor Cst on the base 50.

[0246] Specifically, the display substrate generally includes a plurality of sub-pixels arranged in an array, and each sub-pixel includes a data line pattern (e.g., DATA1) extending in a first direction and a power signal line pattern VDD, at least a portion of which extends in the first direction. For example, the first direction includes the Y direction, and the second direction includes the X direction.

[0247] It should be noted that the specific structure of the power supply signal line pattern VDD may vary. For example, the power supply signal line pattern VDD has a mesh structure, and the mesh-structured power supply signal line pattern VDD includes a portion extending in the first direction.

[0248] Each subpixel further includes a subpixel drive circuit and a light-emitting element corresponding to the subpixel drive circuit in a one-to-one relationship. The light-emitting element includes an anode, an organic light-emitting material layer, and a cathode, which are stacked together. The anode is coupled to the corresponding subpixel drive circuit, and the light-emitting element emits light when driven by a drive signal supplied by the subpixel drive circuit.

[0249] More specifically, as shown in FIG. 16 , taking the case where the subpixel driving circuit includes the above-mentioned 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) also serves as the first plate Cst1 of the storage capacitor Cst, the second plate Cst2 of the storage capacitor Cst is located on the opposite side of the base of the first plate Cst1, the orthogonal projection of the first plate Cst1 on the base at least partially overlaps with the orthogonal projection of the second plate Cst2 on the base, and the orthogonal projection of the second plate Cst2 on the base at least partially overlaps with both the orthogonal projection of the second pole of at least one switch transistor among the fourth transistor T4 and the fifth transistor T5 on the base 50 and the orthogonal projection of the power supply signal line pattern VDD on the base 50.

[0250] As can be seen from the specific structure of the display substrate described above, in the display substrate according to the embodiment of the present disclosure, the second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second electrode Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted by the power signal line pattern VDD. Meanwhile, the second electrodes of the two switch transistors are both coupled to the first electrode of the drive transistor, and the orthogonal projection of the second electrode of at least one of the two switch transistors on the base 50 at least partially overlaps with the orthogonal projection of the power signal line pattern VDD on the base 50. By arranging the second plate Cst2 of the storage capacitor Cst so as to at least partially overlap with the orthogonal projection of the bipolar plate Cst2 on the base 50, both the second plate Cst2 of the storage capacitor Cst and the power supply signal line pattern VDD can shield the second pole of at least one of the two switch transistors, thereby reducing the crosstalk phenomenon that occurs in the second pole of at least one of the two switch transistors due to signals in other conductive patterns (e.g., signal line patterns) around at least one of the two switch transistors, and further reducing the crosstalk phenomenon that occurs in the first pole of the drive transistor due to the same signals.

[0251] As shown in FIG. 16 , in some embodiments, the second poles of the two switch transistors (e.g., the fourth transistor T4 and the fifth transistor T5) and the first pole of the drive transistor (e.g., the third transistor T3) are an integral structure, and the integral structure includes a first conductive portion 108 extending in the first direction, and there is a first overlap region between the orthogonal projection of the first conductive portion 108 on the base, the orthogonal projection of the power supply signal line pattern VDD on the base, and the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst on the base 50, and the first overlap region does not overlap with the orthogonal projection of the data line pattern (e.g., DATA1) on the base 50.

[0252] Specifically, by forming the second poles of the two switch transistors and the first pole of the drive transistor as an integral structure, the second poles of the two switch transistors and the first pole of the drive transistor can be formed in a single patterning process.

[0253] In the display substrate according to the above embodiment, the integrated structure includes a first conductive part 108 extending in the first direction, the orthogonal projection of the data line pattern on the base is located on a side of the orthogonal projection of the first conductive part 108 on the base that is farther from the orthogonal projection of the driving transistor on the base, and there is a first overlap region between the orthogonal projection of the first conductive part 108 on the base, the orthogonal projection of the power supply signal line pattern VDD on the base, and the orthogonal projection of the second electrode Cst2 of the storage capacitor Cst on the base 50. This allows both the second electrode Cst2 of the storage capacitor Cst and the power supply signal line pattern VDD to shield the first conductive part 108, thereby reducing crosstalk occurring in the first conductive part 108 due to signals transmitted on the data line pattern, and further reducing crosstalk occurring in the first electrode of the driving transistor due to the same signals.

[0254] As shown in FIG. 16, in some embodiments, the orthogonal projection of the first pole of the drive transistor onto the base 50 may be arranged to be located within the orthogonal projection of the second plate Cst2 of the storage capacitor Cst onto the base.

[0255] According to the above-mentioned arrangement, the second electrode Cst2 of the storage capacitor Cst can completely cover the first electrode of the driving transistor, thereby more effectively reducing the crosstalk phenomenon occurring at the first electrode of the driving transistor due to the signal transmitted through the data line pattern.

[0256] As shown in FIGS. 16 and 17 , in some embodiments, the sub-pixel further includes a gate line pattern GATE and a light-emitting control signal line pattern EM extending in a second direction intersecting the first direction, respectively; the subpixel driving circuit further includes a first transistor T1 and a sixth transistor T6, and the two switch transistors include a fourth transistor T4 and a fifth transistor T5; a gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, a first electrode of the fourth transistor T4 is coupled to the data line pattern (e.g., DATA1), a second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, a gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, and a first electrode of the fifth transistor T5 is coupled to the power supply signal line pattern VDD; a gate 201g of the first transistor T1 is coupled to the gate line pattern GATE, a second pole of the first transistor T1 is coupled to the gate of the driving transistor; the first pole of the first transistor T1, the first pole of the sixth transistor T6, and the second pole of the driving transistor are formed as an integral structure, and the integral structure includes a second conductive part 109 extending in the first direction; a gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, and a second pole of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel; The orthogonal projection of the channel region of the driving transistor (e.g., 103pg in FIG. 18 ) on the base is located between the orthogonal projection of the first conductive portion 108 on the base 50 and the orthogonal projection of the second conductive portion 109 on the base 50, and in the second direction, the minimum distance between the orthogonal projection of the channel region of the driving transistor on the base and the orthogonal projection of the first conductive portion 108 on the base is smaller than the minimum distance between the orthogonal projection of the channel region on the base 50 and the orthogonal projection of the second conductive portion 109 on the base.

[0257] Specifically, the display substrate may include a plurality of subpixels arranged in an array, the subpixels being divided into a plurality of rows and a plurality of columns, each row including a plurality of subpixels aligned in a second direction, each column including a plurality of subpixels aligned in a first direction, the first direction intersecting the second direction, and each column including a plurality of subpixels aligned in a first direction. The subpixel driving circuits included in the subpixels in each column are located between the data line pattern included in the subpixels in that column and the data line pattern included in the subpixels in the next column adjacent to the subpixels in that column.

[0258] It should be explained that the minimum distance between the orthogonal projection of the channel region of the driving transistor on the base and the orthogonal projection of the first conductive portion 108 on the base in the second direction means the distance between the boundary of the channel region of the driving transistor on the base that is closest to the orthogonal projection of the first conductive portion 108 on the base in the second direction, and the orthogonal projection of the first conductive portion 108 on the base; and the minimum distance between the orthogonal projection of the channel region of the driving transistor on the base 50 and the orthogonal projection of the second conductive portion 109 on the base in the second direction means the distance between the boundary of the channel region of the driving transistor on the base that is closest to the orthogonal projection of the second conductive portion 109 on the base in the second direction.

[0259] More specifically, each subpixel driving circuit included in a subpixel is located between two adjacent data line patterns (e.g., DATA1 and DATA2), and the data transmitted by the two data line patterns changes. Therefore, when the data changes, crosstalk to the gate of the driving transistor in the subpixel driving circuit is likely to occur, as shown in FIG. 25, and further affect the operational stability of the driving transistor.

[0260] In the technical solution according to the above embodiment, the fourth transistor T4, the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all disposed in the peripheral region of the driving transistor, and one of the two data line patterns (for example, DATA1) is disposed on the fourth transistor T4 and the fifth transistor T5 at a side farther from the driving transistor, and the other of the two data line patterns (for example, DATA2) is disposed on the first transistor T1 and the sixth transistor T6 at a side farther from the driving transistor, and the orthogonal projection of the channel region (for example, 103pg in FIG. 18) of the driving transistor on the base is By arranging the DATA2 so that the orthogonal projection of the channel region of the driving transistor on the base 50 is located between the orthogonal projection of the first conductive portion 108 on the base 50 and the orthogonal projection of the second conductive portion 109 on the base 50, and the minimum distance between the orthogonal projection of the channel region of the driving transistor on the base and the orthogonal projection of the first conductive portion 108 on the base is smaller than the minimum distance between the orthogonal projection of the channel region on the base and the orthogonal projection of the second conductive portion 109 on the base, the distance between the channel region of the driving transistor and DATA2 is maximized under the premise that an appropriate distance from DATA1 is guaranteed for the channel region of the driving transistor, thereby more effectively reducing crosstalk caused by DATA2 to the driving transistor.

[0261] Moreover, since the portion of the channel region of the driving transistor close to DATA1 can be covered by the power signal line pattern VDD, crosstalk from DATA1 to the channel region of the driving transistor can be effectively reduced. As a result, in the technical solution according to the above embodiment, even if the distance between the channel region of the driving transistor and DATA is short, the impact of crosstalk is small.

[0262] Furthermore, since the second electrode Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted through the power signal line pattern VDD, and there is a first overlap region among the orthogonal projection of the first conductive portion 108 on the base, the orthogonal projection of the power signal line pattern VDD on the base, and the orthogonal projection of the second electrode Cst2 of the storage capacitor Cst on the base 50, both the second electrode Cst2 of the storage capacitor Cst and the power signal line pattern VDD can shield the first conductive portion 108, thereby reducing crosstalk occurring in the first conductive portion 108 due to the signal transmitted through DATA1, and further reducing crosstalk occurring in the first electrode and channel region of the drive transistor due to the same signal.

[0263] As shown in FIG. 16 , in some embodiments, the sub-pixel further includes a gate line pattern GATE and a light-emitting control signal line pattern EM extending in a second direction intersecting the first direction; the subpixel driving circuit further includes a first transistor T1 and a sixth transistor T6, and the two switch transistors include a fourth transistor T4 and a fifth transistor T5; a gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, a first electrode of the fourth transistor T4 is coupled to the data line pattern (e.g., DATA1), a second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, a gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, and a first electrode of the fifth transistor T5 is coupled to the power supply signal line pattern VDD; a gate 201g of the first transistor T1 is coupled to the gate line pattern GATE, a second pole of the first transistor T1 is coupled to the gate of the driving transistor; the first pole of the first transistor T1, the first pole of the sixth transistor T6, and the second pole of the driving transistor are formed as an integral structure, and the integral structure includes a second conductive part 109 extending in the first direction; a gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, and a second pole of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel; The orthogonal projection of the channel region of the driving transistor (e.g., 103pg in FIG. 18 ) on the base is located between the orthogonal projection of the first conductive portion 108 on the base and the orthogonal projection of the second conductive portion 109 on the base, and both the first pole and the second pole of the driving transistor include a first portion extending in the second direction, and the length of the first portion of the first pole extending in the second direction is different from the length of the first portion of the second pole extending in the second direction.

[0264] Specifically, as described above, the first pole and the second pole of the driving transistor both include a first portion extending in the second direction, and the length of the first portion of the first pole extending in the second direction is different from the length of the first portion of the second pole extending in the second direction, specifically including the following two cases:

[0265] In the first case, the length H1 of the first portion of the first pole extending in the second direction is made shorter than the length H2 of the first portion of the second pole extending in the second direction, so that the channel region of the driving transistor (e.g., 103pg in Figure 18) is close to the data line pattern (e.g., DATA1) included in the subpixel in which it is located and far from the data line pattern (e.g., DATA2) included in the next subpixel adjacent to the subpixel in which it is located in the second direction.As for the channel region of the driving transistor, the distance between the channel region of the driving transistor and DATA2 is maximized, provided that an appropriate distance from DATA1 is guaranteed, so that crosstalk caused by DATA2 to the driving transistor can be more effectively reduced. On the other hand, since both the second electrode Cst2 of the storage capacitor Cst and the power signal line pattern VDD can shield the first conductive part 108, crosstalk occurring in the first conductive part 108 due to the signal transmitted through DATA1 is reduced, and further, crosstalk occurring in the first electrode and channel region of the driving transistor due to the same signal is reduced.

[0266] In the second case, the length of the first portion of the first pole extending in the second direction is made longer than the length of the first portion of the second pole extending in the second direction, so that the channel region of the driving transistor (e.g., 103pg in Figure 18) is far from the data line pattern (e.g., DATA1) included in the subpixel in which it is located and is close to the data line pattern (e.g., DATA2) included in the next subpixel adjacent to the subpixel in which it is located in the second direction.As for the channel region of the driving transistor, under the premise that an appropriate distance from DATA2 is guaranteed, the distance between the channel region of the driving transistor and DATA1 is maximized, so that the crosstalk caused by DATA1 to the driving transistor is more effectively reduced. Furthermore, if the display substrate includes a first shielding member that can completely isolate DATA2 from the second conductive part 109, the crosstalk that occurs in the second conductive part 109 due to the signal transmitted on DATA2 can be reduced, and the crosstalk phenomenon that occurs in the second pole and channel region of the driving transistor due to the same signal can be further reduced.

[0267] As shown in FIG. 16 , in some embodiments, the sub-pixel further includes an initialization signal line pattern (e.g., VINT1) including a portion extending in a second direction intersecting the first direction and for transmitting an initialization signal having a fixed potential; The subpixel drive circuit further includes a second transistor T2 coupled to the gate of the drive transistor, the second transistor T2 a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, the third conductor pattern having a conductive performance superior to that of the first semiconductor pattern and that of the second semiconductor pattern; a first gate pattern and a second gate pattern coupled to each other, wherein an orthogonal projection of the first gate pattern on the base at least partially overlaps with an orthogonal projection of the first semiconductor pattern on the base, and an orthogonal projection of the second gate pattern on the base at least partially overlaps with an orthogonal projection of the second semiconductor pattern on the base; an orthogonal projection of the third conductor pattern on the base does not overlap with either an orthogonal projection of the first gate pattern on the base or an orthogonal projection of the second gate pattern on the base; The orthogonal projection of the third conductor pattern on the base at least partially overlaps with the orthogonal projection of the initialization signal line pattern on the base.

[0268] Specifically, as shown in FIG. 16 , the second transistor T2 has a double-gate structure, and the first semiconductor pattern and the second semiconductor pattern included therein are formed as the channel region of the second transistor T2 (corresponding to the position of symbol 102pg in FIG. 18 ). The third conductor pattern 102px included therein is doped, and therefore its conductive performance is superior to that of the first semiconductor pattern and the second semiconductor pattern. The first gate pattern and the second gate pattern included in the second transistor T2 cover the first semiconductor pattern and the second semiconductor pattern in a one-to-one correspondence, and can jointly serve as the gate 202g of the second transistor T2.

[0269] In the second transistor T2 having the above structure, the third conductor pattern 102px has good conductivity and is not covered by a gate pattern, so that it is prone to coupling with other nearby conductive patterns, resulting in crosstalk. In the technical solution according to the above embodiment, the orthogonal projection of the third conductor pattern on the base 50 is at least partially overlapped with the orthogonal projection of the initialization signal line pattern on the base 50, so that the initialization signal line pattern can shield the third conductor pattern 102px. Furthermore, because the initialization signal line pattern transmits an initialization signal having a fixed potential, the coupling between the third conductor pattern 102px and other nearby conductive patterns is better reduced, thereby making the operating performance of the display substrate more stable.

[0270] 16 and 18 , in some embodiments, the subpixel driving circuit further includes a first extending portion extending from the first semiconductor pattern, where the first extending portion has better conductive properties than the first semiconductor pattern, and the first extending portion includes a first portion 61, a second portion 62, and a third portion 63, where the first portion 61 and the third portion 63 all extend in the first direction, the second portion 62 extends in the second direction, one end of the second portion 62 is coupled to the first portion 61, the other end of the second portion 62 is coupled to the third portion 63, and the end of the third portion 63 farther from the second portion 62 is coupled to the first transistor T1.

[0271] Specifically, the first extension portion may be fabricated together with the first semiconductor pattern in a single pattern formation process, and after the first semiconductor pattern is formed, the first extension portion may be doped so that the conductive performance of the first extension portion is superior to that of the first semiconductor pattern.

[0272] After adding the first shielding member 404, the first extension portion is configured as described above, so that the second transistor T2 is coupled to the gate of the first transistor T1 and the gate of the driving transistor through the first extension portion, which contributes to reducing the impact on the performance of the first transistor T1 and the performance of the second transistor T2 caused by changes in the signal transmitted through the target data line pattern. Furthermore, the impact of coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern is reduced, and the problem of vertical crosstalk is alleviated, so that the display substrate can achieve a better display effect when used for display.

[0273] In some embodiments, the first transistor comprises: a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, respectively, the sixth conductor pattern having a conductive property superior to that of the fourth semiconductor pattern and that of the fifth semiconductor pattern; a third gate pattern and a fourth gate pattern coupled to each other, wherein an orthogonal projection of the third gate pattern on the base partially overlaps an orthogonal projection of the fourth semiconductor pattern on the base, and an orthogonal projection of the fourth gate pattern on the base partially overlaps an orthogonal projection of the fifth semiconductor pattern on the base; The orthogonal projection of the sixth conductor pattern onto the base does not overlap with either the orthogonal projection of the third gate pattern onto the base or the orthogonal projection of the fourth gate pattern onto the base.

[0274] Specifically, as shown in FIG. 16 , the first transistor has a double-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern included therein are formed as the channel region of the first transistor (corresponding to symbol 101pg in FIG. 18 ), and the sixth conductor pattern 101px included therein is doped and therefore has superior conductive performance to the fourth semiconductor pattern and the fifth semiconductor pattern, and the third gate pattern and the fourth gate pattern included in the first transistor cover the fourth semiconductor pattern and the fifth semiconductor pattern in a one-to-one correspondence, and can collectively serve as the gate 201g of the first transistor T1.

[0275] As shown in FIG. 19 , in some embodiments, the sub-pixel further includes an initialization signal line pattern (e.g., VINT1) including a portion extending in a second direction intersecting the first direction and for transmitting an initialization signal having a fixed potential; The subpixel driving circuit further includes a first shielding member 404 coupled to the initialization signal line pattern, and the orthogonal projection of the first shielding member 404 on the base 50 at least partially overlaps with the orthogonal projection of the sixth conductor pattern 101px on the base 50.

[0276] In the technical solution according to the above embodiment, the orthogonal projection of the first shielding member 404 on the base 50 and the orthogonal projection of the sixth conductor pattern 101px on the base 50 are arranged to at least partially overlap, so that the first shielding member 404 can shield the sixth conductor pattern 101px. Furthermore, since the first shielding member 404 has a fixed potential, the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby is more effectively reduced, making the operating performance of the display substrate more stable.

[0277] As shown in FIG. 20 , in some embodiments, the sub-pixel further includes an initialization signal line pattern (e.g., VINT1) including a portion extending in a second direction intersecting the first direction and for transmitting an initialization signal having a fixed potential; The subpixel driving circuit further includes a first shielding member 404 coupled to the initialization signal line pattern and a second shielding member 301 coupled to the first shielding member 404, and an orthogonal projection of the second shielding member 301 on the base at least partially overlaps with an orthogonal projection of the sixth conductor pattern on the base.

[0278] Specifically, as described above, by arranging the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the sixth conductor pattern 101px on the base 50 so that they at least partially overlap, the second shielding member 301 can shield the sixth conductor pattern 101px. Furthermore, since the second shielding member 301 and the first shielding member 404 are coupled together, the second shielding member 301 has a fixed potential, which more effectively reduces the coupling effect between the sixth conductor pattern 101px and other conductive patterns in its vicinity, thereby making the operating performance of the display substrate more stable.

[0279] Therefore, in the display substrate according to the above embodiment, since the first shielding member 404 and the second shielding member 301 both have a fixed potential, the formation of a parasitic capacitor between the first transistor T1 and the target data line pattern (e.g., DATA2) can be more effectively prevented or reduced, and vertical crosstalk defects can be effectively prevented or reduced.

[0280] As shown in Figures 21 and 22, in some embodiments, the plurality of sub-pixels include a plurality of rows of sub-pixels, each row of sub-pixels including a plurality of the sub-pixels aligned in the second direction, the initialization signal line patterns located in the sub-pixels of the same row are sequentially combined to form an initialization signal line corresponding to the row of sub-pixels, and the first shielding member 404 extends in the first direction and is combined with the two initialization signal lines adjacent to it.

[0281] In some embodiments, the shape of the power supply signal line pattern can be laid out according to actual needs. For example, in the second direction, the width of the power supply signal line pattern near the channel region of the driving transistor can be made smaller than the width of the power supply signal line pattern far from the channel region of the driving transistor, thereby reducing the influence of the power supply signal line pattern on the gate of the driving transistor near the channel region of the driving transistor.

[0282] In some embodiments, as shown in Figure 23, a compensation pattern 408 may be provided within the display substrate, and the compensation pattern 408 may be connected in parallel with the power signal line pattern to improve the transmission performance of the power signal line pattern. It should be noted that the compensation pattern 408 may be provided in the same layer and made of the same material as the third conductive connection, so that the compensation pattern 408 and the third conductive connection may be formed using the same pattern forming process.

[0283] In some embodiments, in one sub-pixel, the orthogonal projection of the power supply signal line pattern VDD on the base completely covers the orthogonal projection of the first conductive portion 108 on the base.

[0284] In some embodiments, in one subpixel, the orthogonal projection of the power supply signal line pattern VDD on the base covers the orthogonal projections of the first semiconductor pattern, the second semiconductor pattern, and the third conductor pattern of the second transistor T2 on the base, and also covers at least a portion of the orthogonal projection of the first pole of the second transistor T2 on the base and at least a portion of the orthogonal projection of the second pole of the second transistor T2 on the base.

[0285] In some embodiments, the first shielding member 404 is an extension structure extending from the initialization signal line pattern.

[0286] Specifically, by configuring the first shielding member 404 to have an extension structure extending from the initialization signal line pattern, the first shielding member 404 and the initialization signal line pattern can be formed using the same pattern configuration process, which more effectively simplifies the manufacturing process flow of the display substrate.

[0287] As shown in FIG. 20 , in some embodiments, the first shield member 404 is provided in a layer different from the initialization signal line pattern, a first overlapping region exists between the orthogonal projection of the first shield member 404 on the base 50 and the orthogonal projection of the initialization signal line pattern on the base 50, and the first shield member is coupled to the initialization signal line pattern via a first throw-hole provided in the first overlapping region. The second shielding member 301 is provided on a different layer from the first shielding member 404, and there is a second overlapping region between the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the first shielding member 404 on the base 50, and the second shielding member 301 and the first shielding member 404 are connected via a second throw hole provided in the overlapping region.

[0288] Specifically, the first shielding member 404 may be provided on the same layer as the initialization signal line pattern, or on a different layer. If the first shielding member 404 and the initialization signal line pattern are provided on different layers, the first shielding member 404 may be provided so that there is a first overlapping region in both the orthogonal projection of the first shielding member 404 on the base 50 and the orthogonal projection of the initialization signal line pattern on the base 50. In this case, by providing a first throw-hole in the first overlapping region, coupling between the first shielding member 404 and the initialization signal line can be achieved. Similarly, the second shielding member 301 may be provided in the same layer as the first shielding member 404, or in a different layer. If the second shielding member 301 and the first shielding member 404 are provided in different layers, they may be provided so that there is a second double region between the orthogonal projection of the second shielding member 301 on the base 50 and the orthogonal projection of the first shielding member 404 on the base 50. In this case, by providing a second throw hole in the double region, coupling between the second shielding member 301 and the first shielding member 404 via the second throw hole can be achieved.

[0289] In some embodiments, the first shielding member 404 and the data line pattern are made of the same material.

[0290] In some embodiments, the display substrate includes a first interlayer insulating layer, and the first shielding member 404 and the data line pattern are both located on the surface of the interlayer insulating layer opposite the base.

[0291] Specifically, by providing the first shielding member 404 according to the above-described method, the first shielding member 404 and the data line pattern can be simultaneously formed on the surface of the interlayer insulating layer opposite the base in a single patterning process, and the need to add a separate patterning process for manufacturing the first shielding member 404 can be avoided, thereby favorably simplifying the manufacturing flow of the display substrate and saving manufacturing costs.

[0292] In some embodiments, the second shield member 301 and the initialization signal line pattern are made of the same material.

[0293] In some embodiments, the display substrate further includes a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern are both located on the surface of the second interlayer insulating layer opposite the base.

[0294] Specifically, as described above, the second shielding member 301 and the initialization signal line pattern are made of the same material, and the second shielding member 301 and the initialization signal line pattern (e.g., VINT1 in Figure 3) are both positioned on the surface of the second interlayer insulating layer opposite the base. This allows the second shielding member 301 and the initialization signal line pattern to be formed simultaneously using the same pattern formation process, thereby avoiding the need to add a separate manufacturing process dedicated to manufacturing the second shielding member 301, thereby favorably simplifying the manufacturing flow of the display substrate and saving production costs.

[0295] In some embodiments, the first electrode Cst1 of the storage capacitor Cst doubles as the gate of the driving transistor, the second electrode Cst2 of the storage capacitor Cst and the second shield member 301 are made of the same material, and the second electrode Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer opposite the base 50.

[0296] Specifically, the storage capacitor Cst included in the subpixel driving circuit has a first electrode Cst1 and a second electrode Cst2, the first electrode Cst1 and the second electrode Cst2 are arranged opposite to each other, the first electrode Cst1 is coupled to the gate of the driving transistor, and the second electrode Cst2 is coupled to the power signal line pattern VDD. When the storage capacitor Cst is laid out, the first electrode Cst1 can also be used as the gate of the driving transistor, which ensures the coupling between the storage capacitor Cst and the gate of the driving transistor and reduces the space occupied by the subpixel driving circuit, thereby contributing to improving the resolution of the display substrate. Furthermore, by arranging the second electrode Cst2 of the storage capacitor Cst to be located on the surface of the second interlayer insulating layer opposite to the base, the second electrode Cst2 of the storage capacitor Cst, the second shielding member 301, and the initialization signal line pattern can be formed simultaneously using the same pattern formation process, which advantageously simplifies the manufacturing flow of the display substrate and reduces production costs.

[0297] In some embodiments, the sub-pixel further includes a reset signal line pattern (e.g., RST1) extending in a second direction intersecting the first direction, and the sub-pixel driving circuit includes: a first conductive connection portion 405, the orthogonal projection of which on the base 50 covers at least a part of the orthogonal projection of the sixth conductor pattern 101px on the base 50; a second transistor T2, the first pole (e.g., source S2) of which is coupled to the initialization signal line pattern (e.g., VINT1) via the first conductive connection 405, the second pole (e.g., drain D2) of which is coupled to the gate of the driving transistor, and the gate 202g of which is coupled to the reset signal line pattern (e.g., RST1); Further includes:

[0298] Specifically, the first conductive connection part 405 can be made of a metal material and can be formed in the same pattern forming process as the data line pattern.

[0299] As described above, by arranging the first conductive connection portion 405 so that the orthogonal projection of the sixth conductor pattern 101px on the base 50 covers at least a portion of the orthogonal projection of the sixth conductor pattern 101px on the base 50, the first conductive connection portion 405 can shield the sixth conductor pattern 101px. Furthermore, since the first conductive connection portion 405 and the initialization signal line pattern are coupled to each other, the first conductive connection portion 405 has a fixed potential, which more effectively reduces the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, thereby making the operating performance of the display substrate more stable.

[0300] As shown in FIG. 16 , in some embodiments, the sub-pixel further includes a gate line pattern GATE, a light-emitting control signal line pattern EM, a reset signal line pattern (e.g., RST1), and an initialization signal line pattern (e.g., VINT1), and the gate line pattern GATE, the light-emitting control signal line pattern EM, the reset signal line pattern, and the initialization signal line pattern all extend in a second direction intersecting the first direction; The two switch transistors include a fourth transistor T4 and a fifth transistor T5; the sub-pixel driving circuit further includes a first transistor T1, a second transistor T2, a sixth transistor T6 and a seventh transistor T7; a gate of the driving transistor (e.g., the gate 203g of the third transistor T3) is coupled to the second pole of the first transistor T1, a first pole of the driving transistor is coupled to the second pole of the fifth transistor T5, and a second pole of the driving transistor is coupled to the first pole of the first transistor T1; The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE; a gate 202g of the second transistor T2 is coupled to the reset signal line pattern, a first pole of the second transistor T2 is coupled to the initialization signal line pattern, and a second pole of the second transistor T2 is coupled to the gate of the driving transistor; The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, and the first electrode of the fourth transistor T4 is coupled to the data line pattern (e.g., 16 DATA1) in the signal line DATA1, and coupled to the second pole of the fourth transistor T4 and the first pole of the driving transistor T5; a gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, and a first electrode of the fifth transistor T5 is coupled to the power supply signal line pattern VDD; a gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, a first pole of the sixth transistor T6 is coupled to a second pole of the driving transistor T1, and a second pole of the sixth transistor T6 is coupled to a light emitting element in the sub-pixel; The gate 207g of the seventh transistor T7 is coupled to a reset signal line pattern (e.g., RST2) included in the next adjacent subpixel in the first direction, a first pole of the seventh transistor T7 is coupled to an initialization signal line pattern (e.g., VINT2) included in the next subpixel, and a second pole of the seventh transistor T7 is coupled to a light-emitting element in the subpixel.

[0301] Specifically, the display substrate may include a plurality of sub-pixels arranged in an array, the sub-pixels being divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels, each row of the sub-pixels including a plurality of sub-pixels aligned in a second direction, and each column of the sub-pixels including a plurality of sub-pixels aligned in a first direction, such that the first direction and the second direction intersect.

[0302] It should be noted that the next adjacent sub-pixel in the first direction refers to the next adjacent sub-pixel located in the same column as the seventh transistor T7.

[0303] By arranging the subpixels and the subpixel driving circuits included therein in the above-described structure, it is possible to effectively reduce the layout space occupied by the subpixel driving circuits, on the premise that the operational performance of the subpixel driving circuits is guaranteed, thereby contributing to improving the resolution of the display substrate.

[0304] An embodiment of the present disclosure further provides a display device including a display substrate according to the above embodiment.

[0305] In the display substrate according to the above embodiment, the second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second electrode Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted by the power signal line pattern VDD. Meanwhile, the second electrodes of the two switch transistors are both coupled to the first electrode of the drive transistor, and the orthogonal projection of the second electrode of at least one of the two switch transistors on the base 50 at least partially overlaps with the orthogonal projection of the power signal line pattern VDD on the base 50. By arranging the second electrode Cst2 of the storage capacitor Cst and the power supply signal line pattern VDD so as to at least partially overlap with the orthogonal projection on the substrate 50, both the second electrode Cst2 of the storage capacitor Cst and the power supply signal line pattern VDD can shield the second electrode of at least one of the two switch transistors, thereby reducing the crosstalk phenomenon that occurs at the second electrode of at least one of the two switch transistors due to signals in other conductive patterns (e.g., signal line patterns) around at least one of the two switch transistors, and further reducing the crosstalk phenomenon that occurs at the first electrode of the drive transistor due to the same signals.

[0306] Therefore, when a display device according to an embodiment of the present disclosure includes the above display substrate, it also has the above beneficial effects, which will not be repeated here.

[0307] An embodiment of the present disclosure is a method for fabricating a display substrate, the method including fabricating a plurality of sub-pixels arranged in an array on a base, the sub-pixels including: a data line pattern extending in a first direction; a power signal line pattern including a portion extending in the first direction; and a sub-pixel driving circuit including two switch transistors, a driving transistor, and a storage capacitor, a first plate of the storage capacitor being coupled to a gate of the driving transistor; a second plate of the storage capacitor being coupled to the power signal line pattern; second poles of the two switch transistors being both coupled to a first pole of the driving transistor; and an orthogonal projection of the second pole of at least one of the two switch transistors on the base at least partially overlapping with an orthogonal projection of the power signal line pattern on the base and at least partially overlapping with an orthogonal projection of the second plate of the storage capacitor on the base.

[0308] In the display substrate manufactured using the manufacturing method according to the embodiment of the present disclosure, the second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second electrode Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted through the power signal line pattern VDD, while the second electrodes of the two switch transistors are both coupled to the first electrode of the drive transistor, and the orthogonal projection of the second electrode of at least one of the two switch transistors on the base 50 at least partially overlaps with the orthogonal projection of the power signal line pattern VDD on the base 50, and the second electrode Cst2 of the storage capacitor Cst By arranging the second plate Cst2 of the storage capacitor Cst so as to at least partially overlap with the orthogonal projection of the second plate Cst2 of the storage capacitor Cst on the base 50, both the second plate Cst2 of the storage capacitor Cst and the power supply signal line pattern VDD can shield the second pole of at least one of the two switch transistors, thereby reducing the crosstalk phenomenon that occurs at the second pole of at least one of the two switch transistors due to signals in other conductive patterns (e.g., signal line patterns) around at least one of the two switch transistors, and further reducing the crosstalk phenomenon that occurs at the first pole of the drive transistor due to the same signals.

[0309] It should be noted that the embodiments in this specification are all described in a progressive manner, and the same or similar parts of each embodiment may be cross-referenced, and the description of each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, and therefore, the description is relatively brief, and relevant parts may be referred to in the description of the product embodiments.

[0310] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings that are understandable to those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or priority, but are intended to distinguish different components from one another. Terms with similar meanings, such as "comprise" or "include," mean that the preceding element or component covers the elements or objects listed thereafter or their equivalents, and do not exclude other elements or objects. Terms with similar meanings, such as "connect" or "connected," may mean not only physical or mechanical connection, but also electrical connection, direct or indirect connection. Terms such as "upper," "lower," "left," and "right" only indicate relative positions, and if the absolute position of the described object is changed, the relative positions will also change appropriately.

[0311] As will be understood, when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" on or "under" the other element, or may be located via an intermediate element.

[0312] In the above description of the embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

[0313] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto. Anyone skilled in the art can easily think of modifications and substitutions within the technical scope disclosed in the present disclosure, and all of them should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be subject to the scope of protection of the claims.

Claims

1. A display substrate including a base and a plurality of sub-pixels arranged in an array on the base, the sub-pixels comprising: a data line pattern extending in a first direction; a first shield member at least a portion of which extends in the first direction; a drive transistor; a first transistor electrically connected to the gate of the drive transistor; a second shielding member electrically connected to the first shielding member; Including, the first transistor has a double-gate structure, the first transistor includes a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern electrically connected to the fourth semiconductor pattern and the fifth semiconductor pattern, respectively; a second pole of the driving transistor is electrically connected to the fourth semiconductor pattern or the fifth semiconductor pattern; an orthogonal projection of the second shielding member on the base at least partially overlaps with an orthogonal projection of the sixth conductor pattern on the base; At least a portion of the first shielding member is located between the second pole of the driving transistor and a data line pattern in an adjacent sub-pixel; The display substrate, wherein the first shielding member and the second shielding member both have a fixed potential.

2. The display substrate according to claim 1 , wherein the second shielding member is closer to the base than the first shielding member.

3. 2. The display substrate of claim 1, wherein in the second direction, L1 is the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the first shielding member on the base, and L2 is the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the data line pattern in the adjacent subpixel on the base, and L1≦L2.

4. 4. The display substrate according to claim 3, wherein the channel length of the driving transistor is L3, and L1≦L2≦L3.

5. 2. The display substrate of claim 1, wherein a minimum linear distance between the second pole of the driving transistor and the data line pattern in the adjacent subpixel is L4, a minimum linear distance between the second pole of the driving transistor and the first shielding member is L5, and L5<L4.

6. the sub-pixel further includes a connecting line, and a gate of the driving transistor is electrically connected to a second electrode of the first transistor through the connecting line; 2. The display substrate of claim 1, wherein a positive projection of the second shielding member on the base is located between a positive projection of an end of the connecting line electrically connected to the second electrode of the first transistor on the base and a positive projection of a data line pattern in an adjacent subpixel on the base.

7. The display substrate according to claim 6 , wherein a length of the first shielding member in the first direction is greater than a length of the connecting line.

8. 2. The display substrate of claim 1, wherein a length L6 of a portion of the second electrode of the driving transistor that does not overlap with the first shielding member in the first direction, a length L7 of the first shielding member in the first direction, and L6≦L7.

9. The display substrate of claim 1 , wherein there is a gap between the orthogonal projection of the first shielding member on the base and the orthogonal projection of the second pole of the driving transistor on the base.

10. The sub-pixel further includes a fourth transistor, a first pole of the fourth transistor electrically connected to the data line pattern, and a second pole of the fourth transistor electrically connected to the first pole of the driving transistor; The display substrate of claim 1 , wherein an orthogonal projection of the second shield member onto the base does not overlap an orthogonal projection of the fourth transistor in the adjacent subpixel onto the base.

11. The display substrate according to claim 1 , wherein the first shielding member and the second shielding member are for receiving a first fixed potential signal.

12. the subpixel further includes a storage capacitor, the storage capacitor including a first plate electrically connected to the gate of the drive transistor and a second plate for receiving a second fixed potential signal; a gap is provided between an orthogonal projection of the second electrode plate on the base and an orthogonal projection of the first shield member on the base; The display substrate of claim 11 , wherein the orthogonal projection of the second pole of the driving transistor onto the base includes a portion located within the gap.

13. The display substrate of claim 12 , wherein the first fixed potential signal is the same as the second fixed potential signal.

14. The display substrate according to claim 2 , wherein the second pole of the driving transistor is closer to the base than the first shielding member and the second shielding member.

15. The display substrate according to claim 1 , wherein the active layer of the first transistor and the active layer of the driving transistor are disposed in the same layer and have an integral structure.

16. The display substrate according to claim 1 , wherein a minimum linear distance from the first shielding member to the second pole of the driving transistor is greater than a minimum linear distance from the second shielding member to the sixth conductor pattern.

17. The sub-pixels are a reset signal line pattern and an initialization signal line pattern each extending in a second direction intersecting the first direction; a second transistor having a gate electrically connected to the reset signal line pattern, a first electrode electrically connected to the initialization signal line pattern, and a second electrode electrically connected to the gate of the driving transistor; The display substrate of claim 1 further comprising:

18. an orthogonal projection of a contact portion of the second shield member that contacts the first shield member on the base does not overlap with an orthogonal projection of an active layer of the second transistor on the base; a distance from an orthogonal projection of the contact portion on the base to an orthogonal projection of the sixth conductor pattern on the base is smaller than a distance from an orthogonal projection of the contact portion on the base to an orthogonal projection of the second electrode of the drive transistor on the base; 18. The display substrate of claim 17, wherein a distance from an orthogonal projection of the contact portion on the base to an orthogonal projection of the sixth conductor pattern on the base is smaller than a distance between an orthogonal projection of the contact portion on the base and an orthogonal projection of the data line pattern on the base.

19. The sub-pixels are a light-emitting control signal line pattern extending in the second direction; a power supply signal line pattern including a portion extending in the first direction; a fifth transistor having a gate electrically connected to the light-emitting control signal line pattern, a first electrode electrically connected to the power supply signal line pattern, and a second electrode electrically connected to the first electrode of the driving transistor; The display substrate of claim 17 further comprising:

20. 20. The display substrate of claim 19, wherein the sub-pixel further comprises a light-emitting element; and a sixth transistor, the sixth transistor having a gate electrically connected to the light-emitting control signal line pattern, a first electrode electrically connected to the second electrode of the driving transistor, and a second electrode electrically connected to the light-emitting element.

21. A display substrate including a base and a plurality of sub-pixels arranged in an array on the base, the sub-pixels comprising: a data line pattern extending in a first direction; a first shield member at least a portion of which extends in the first direction; a drive transistor; a first transistor electrically connected to the gate of the drive transistor; a second shielding member electrically connected to the first shielding member; Including, the first transistor has a double gate structure, the first transistor includes a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern electrically connected to the fourth semiconductor pattern and the fifth semiconductor pattern, respectively, a second pole of the driving transistor is electrically connected to the fourth semiconductor pattern or the fifth semiconductor pattern, and a linear distance from a portion of the second shielding member that contacts the first shielding member to the sixth conductor pattern is shorter than a linear distance from the portion to the second pole of the driving transistor; a distance from an orthogonal projection on the base of a contact portion of the second shielding member that contacts the first shielding member to an orthogonal projection of the sixth conductor pattern on the base is smaller than a distance between an orthogonal projection of the contact portion on the base and an orthogonal projection of the data line pattern on the base; The display substrate, wherein the first shielding member and the second shielding member both have a fixed potential.

22. The display substrate of claim 21 , wherein the second shielding member is closer to the base than the first shielding member.

23. 22. The display substrate of claim 21, wherein in the second direction, L1 is the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of the first shielding member on the base, and L2 is the minimum linear distance between the orthogonal projection of the second pole of the driving transistor on the base and the orthogonal projection of a data line pattern in an adjacent subpixel on the base, and L1≦L2.

24. 24. The display substrate of claim 23, wherein the length of the channel of the driving transistor in the second direction is L3, where L1≦L2≦L3.

25. 22. The display substrate of claim 21, wherein a minimum linear distance between the second pole of the driving transistor and the data line pattern in an adjacent subpixel is L4, a minimum linear distance between the second pole of the driving transistor and the first shielding member is L5, and L5<L4.

26. the sub-pixel further includes a connecting line, and a gate of the driving transistor is electrically connected to a second electrode of the first transistor through the connecting line; 22. The display substrate of claim 21, wherein a positive projection of the second shielding member on the base is located between a positive projection of an end of the connecting line electrically connected to the second electrode of the first transistor on the base and a positive projection of a data line pattern in an adjacent subpixel on the base.

27. The display substrate of claim 26 , wherein a length of the first shielding member in the first direction is greater than a length of the connecting line.

28. 22. The display substrate of claim 21, wherein a length L6 of a portion of the second electrode of the driving transistor that does not overlap with the first shielding member in the first direction, a length L7 of the first shielding member in the first direction, and L6≦L7.

29. 22. The display substrate of claim 21, wherein there is a gap between the orthogonal projection of the first shielding member on the base and the orthogonal projection of the second pole of the driving transistor on the base.

30. The sub-pixel further includes a fourth transistor, a first pole of the fourth transistor electrically connected to the data line pattern, and a second pole of the fourth transistor electrically connected to the first pole of the driving transistor; 22. The display substrate of claim 21, wherein an orthogonal projection of the second shield member onto the base does not overlap an orthogonal projection of a fourth transistor in an adjacent subpixel onto the base.

31. The display substrate of claim 21 , wherein the first shielding member and the second shielding member are for receiving a first fixed potential signal.

32. the subpixel further includes a storage capacitor, the storage capacitor including a first plate electrically connected to the gate of the drive transistor and a second plate for receiving a second fixed potential signal; a gap is provided between an orthogonal projection of the second electrode plate on the base and an orthogonal projection of the first shield member on the base; 32. The display substrate of claim 31, wherein the orthogonal projection of the second pole of the drive transistor onto the base includes a portion that is located within the gap.

33. 33. The display substrate of claim 32, wherein the first fixed potential signal is the same as the second fixed potential signal.

34. The display substrate of claim 22 , wherein the second pole of the driving transistor is closer to the base than the first shielding member and the second shielding member.

35. 22. The display substrate according to claim 21, wherein the active layer of the first transistor and the active layer of the driving transistor are provided in the same layer and are an integral structure.

36. The display substrate of claim 21 , wherein a minimum linear distance from the first shielding member to the second pole of the driving transistor is greater than a minimum linear distance from the second shielding member to the sixth conductor pattern.

37. The sub-pixels are a reset signal line pattern and an initialization signal line pattern each extending in a second direction intersecting the first direction; a second transistor having a gate electrically connected to the reset signal line pattern, a first electrode electrically connected to the initialization signal line pattern, and a second electrode electrically connected to the gate of the driving transistor; 22. The display substrate of claim 21 further comprising:

38. an orthogonal projection of a portion of the second shield member that contacts the first shield member onto the base does not overlap with an orthogonal projection of an active layer of the second transistor onto the base; 38. The display substrate of claim 37, wherein a minimum linear distance between the portion of the first shielding member extending in the first direction and the second shielding member is smaller than a minimum linear distance between a data line pattern in an adjacent subpixel and the second shielding member.

39. The sub-pixels are a light-emitting control signal line pattern extending in the second direction; a power supply signal line pattern including a portion extending in the first direction; a fifth transistor having a gate electrically connected to the light-emitting control signal line pattern, a first electrode electrically connected to the power supply signal line pattern, and a second electrode electrically connected to the first electrode of the driving transistor; 38. The display substrate of claim 37 further comprising:

40. 40. The display substrate of claim 39, wherein the sub-pixel further comprises a light-emitting element; and a sixth transistor having a gate electrically connected to the light-emitting control signal line pattern, a first electrode electrically connected to the second electrode of the driving transistor, and a second electrode electrically connected to the light-emitting element.

41. A display device comprising the display substrate according to any one of claims 1 to 40.

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