Shift register circuit, GOA circuit, display device, and driving method thereof

Abstract

A shift register circuit, an array substrate row driving circuit, and a display device are provided. The shift register circuit includes a shift register unit 10. The shift register unit 10 includes a pull-up node (PU), a pull-down node (PD), and a touch potential control circuit 11. The touch potential control circuit 11 is connected to a touch potential control terminal (EN), an output terminal (OUT_N), the pull-up node (PU), the pull-down node (PD), and a low-level output terminal of the shift register unit 10, respectively. The touch potential control circuit 11 controls the output terminal (OUT_N), the pull-up node (PU), and the pull-down node (PD) of the shift register unit 10 to be connected to the low-level output terminal under the control of the touch potential control terminal (EN) during a touch phase.

Description

[Technical Field]

[0001] Cross-reference to related applications This application claims priority from Chinese Patent Application No. 201720080616.3, filed in China on January 22, 2017, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to the field of display driving technology, and in particular to a shift register circuit, a GOA circuit, a display device, and a driving method thereof. [Background technology]

[0003] LCD screens used in mobile phones and panel computers integrate touch functionality, becoming a popular design method for small and medium-sized panels. The gate driver circuits for small and medium-sized LCD screens usually adopt the Gate On Array (GOA) method, which means that the gate driver circuits are fabricated on the array substrate. However, if the GOA circuit outputs gate drive signals during the touch phase, it will seriously interfere with the realization of the touch function, reducing touch sensitivity and causing the touch function to be disabled. Summary of the Invention [Means for solving the problem]

[0004] The present disclosure mainly aims to provide a shift register circuit, a GOA circuit, and a display device that solves the problem that, in the related art, a method of forcibly pulling down a signal at a gate signal output terminal during a touch stage is commonly used, but at this time, the GOA circuit is still in an operating state, and the overall power consumption of the GOA circuit and the display panel increases.

[0005] To achieve the above object, an embodiment of the present disclosure provides a shift register circuit including a shift register unit, wherein an output end of the shift register unit is connected to a gate driving signal line, and the shift register unit includes a pull-up node, a pull-down node, a pull-up node control circuit, a pull-down node control circuit, and an output circuit, wherein the pull-up node control circuit is connected to the pull-up node, the pull-down node control circuit is connected to the pull-up node and the pull-down node, respectively, and the output circuit is connected to the pull-up node, the pull-down node, and an output end of the shift register unit, respectively, and the shift register circuit further includes a touch potential control circuit connected to a touch potential control end, an output end of the shift register unit, the pull-up node, the pull-down node, and a low-level output end, respectively, and configured to control the pull-up node and the pull-down node to be both connected to the low-level output end under control of the touch potential control end during a touch phase.

[0006] In practice, the touch potential control circuit further controls the output terminal of the shift register unit to be connected to the low-level output terminal under the control of the touch potential control terminal during the touch stage.

[0007] When implemented, the touch potential control circuit includes: a first touch potential control transistor, the first electrode of which is connected to the touch potential control terminal, the second electrode of which is connected to the low-level output terminal, and the third electrode of which is connected to the output terminal of the shift register unit; a second touch potential control transistor arranged so that a first pole is connected to the touch potential control terminal, a second pole is connected to the low level output terminal, and a third pole is connected to the pull-up node; a third touch potential control transistor arranged so that a first pole is connected to the touch potential control terminal, a second pole is connected to the pull-down node, and a third pole is connected to the low-level output terminal; Equipped with.

[0008] In implementation, the first touch potential control transistor, the second touch potential control transistor, and the third touch potential control transistor are all n-type transistors, and the touch potential control terminal outputs a high level in the touch stage and a low level in the display stage.

[0009] In implementation, the first touch potential control transistor, the second touch potential control transistor, and the third touch potential control transistor are all p-type transistors, and the touch potential control terminal outputs a low level in the touch stage and a high level in the display stage.

[0010] In implementation, the pull-up node control circuit comprises a first pull-up node control sub-circuit and a second pull-up node control sub-circuit, wherein the first pull-up node control sub-circuit is respectively connected to a first scan control end, a second scan control end, a first scan level end, a second scan level end and the pull-up node, and the second pull-up node control sub-circuit is respectively connected to the pull-up node, the pull-down node and the low level output end.

[0011] In implementation, the output circuit is further connected to the first clock signal output terminal and the low level output terminal, respectively. The pull-down node control circuit includes a first pull-down node control sub-circuit and a second pull-down node control sub-circuit. The first pull-down node control sub-circuit is connected to the first scan level terminal, the second scan level terminal, the second clock signal output terminal, the third clock signal output terminal, the high level output terminal, the pull-down node, and the pull-down control node, respectively. The second pull-down node control sub-circuit is connected to the pull-up node, the pull-down node, and the low level output terminal, respectively.

[0012] In implementation, the output circuit controls the output terminal of the shift register unit to be connected to the first clock signal output terminal when the potential of the pull-up node is high, and to be connected to the low-level output terminal when the potential of the pull-down node is high. The second pull-down node control sub-circuit controls the pull-down node to be connected to the low-level output terminal when the potential of the pull-up node is high. The second pull-up node control sub-circuit controls the pull-up node to be connected to the low-level output terminal when the potential of the pull-down node is high.

[0013] When implemented, the first pull-down node control sub-circuit comprises: a first pull-down node control transistor, the first pole of which is connected to the first scan level end, the second pole of which is connected to the second clock signal output end, and the second pole of which is connected to the pull-down control node; a second pull-down node control transistor, the first pole of which is connected to the second scan level end, the second pole of which is connected to the pull-down control node, and the third pole of which is connected to the third clock signal output end; and a third pull-down node control transistor, the first pole of which is connected to the pull-down control node, the second pole of which is connected to the high level output end, and the third pole of which is connected to the pull-down node.

[0014] In implementation, the second pull-down node control sub-circuit includes a fourth pull-down node control transistor and a pull-down node control capacitor, the fourth pull-down node control transistor having a first pole connected to the pull-up node, a second pole connected to the pull-down node, and a third pole connected to the low-level output terminal, and the pull-down node control capacitor having a first terminal connected to the low-level output terminal and a second terminal connected to the pull-down node.

[0015] When implemented, the output circuit includes: a first pull-up transistor arranged to have a first pole connected to the high-level output terminal and a second pole connected to the pull-up node; a second pull-up transistor arranged to have a first pole connected to a third pole of the first pull-up transistor, a second pole connected to the output terminal of the shift register unit, and a third pole connected to the first clock signal output terminal; and a pull-down transistor arranged to have a first pole connected to the pull-down node, a second pole connected to the low-level output terminal, and a third pole connected to the output terminal of the shift register unit.

[0016] When implemented, when scanning in the forward direction, the first scan control terminal is an input terminal, the second scan control terminal is a reset terminal, the first scan level terminal is a high-level output terminal, and the second scan level terminal is a low-level output terminal. When scanning in the reverse direction, the first scan control terminal is a reset terminal, the second scan level terminal is an input terminal, the first scan level terminal is a low-level output terminal, and the second scan level terminal is a high-level output terminal. The first pull-up node control subcircuit controls the potential of the pull-up node to a high level under the control of the input terminal in the input stage, and to a low level under the control of the reset terminal in the reset stage.

[0017] When implemented, the first pull-up node control subcircuit comprises: a first scan transistor arranged to have a first pole connected to the first scan control terminal, a second pole connected to the first scan level terminal, and a third pole connected to the pull-up node; and a second scan transistor arranged to have a first pole connected to the second scan control terminal, a second pole connected to the pull-up node, and a third pole connected to the second scan level terminal.

[0018] In implementation, the second pull-up node control sub-circuit comprises a pull-up node control transistor, a first pole of which is connected to the pull-down node, a second pole of which is connected to the low-level output terminal, and a third pole of which is connected to the pull-up node.

[0019] In practice, the shift register circuit further includes a charge / discharge circuit, which is connected to the pull-up node and the output terminal of the shift register unit, respectively.

[0020] In implementation, the charging / discharging circuit includes a storage capacitor, a first end of which is connected to the pull-up node and a second end of which is connected to the output end of the shift register unit.

[0021] The present disclosure further provides a GOA circuit comprising a plurality of cascaded shift register circuits as described above.

[0022] The present disclosure further provides a display device including the gate drive circuit.

[0023] The present disclosure further provides a method for driving a display device, wherein in a touch step, the touch potential control circuit controls the touch potential control terminal so that both the pull-up node and the pull-down node are connected to the low-level output terminal.

[0024] In practice, in the touch step, the touch potential control circuit, under the control of the touch potential control terminal, further controls the output terminal of the shift register unit to be connected to the low-level output terminal. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a diagram illustrating the configuration of a shift register unit according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a configuration diagram of a shift register unit according to another embodiment of the present disclosure. [Figure 3] FIG. 3 is a configuration diagram of a shift register unit according to still another embodiment of the present disclosure. [Figure 4] FIG. 4 is a circuit diagram of a specific embodiment of a shift register unit according to the present disclosure. [Figure 5] FIG. 5 is a working sequence diagram of a specific embodiment of the shift register unit shown in FIG. 4 of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] The technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Of course, the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments that can be obtained without requiring creative work by those skilled in the art are all within the scope of protection of the present disclosure.

[0027] The transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, the gate is referred to as the first pole. To distinguish between the two poles other than the gate of the transistor, the other two poles are referred to as the second pole and the third pole, respectively. In actual operation, the second pole may be the drain and the third pole may be the source, or the second pole may be the source and the third pole may be the drain.

[0028] 1, a shift register circuit according to an embodiment of the present disclosure includes a shift register unit 10. The output terminal OUT_N of the shift register unit 10 is connected to a gate driving signal line. The shift register unit includes a pull-up node PU, a pull-down node PD, a charge / discharge circuit, a pull-up node control circuit, a pull-down node control circuit, and an output circuit. The pull-up node control circuit is connected to the pull-up node PU, the pull-down node control circuit is connected to the pull-up node PU and the pull-down node PD, respectively, the charge / discharge circuit is connected to the pull-up node PU and the output terminal OUT_N of the shift register unit, respectively, and the output circuit is connected to the pull-up node PU, the pull-down node PD, and the output terminal OUT_N of the shift register unit, respectively.

[0029] The shift register circuit further includes a touch potential control circuit 11. The touch potential control circuit 11 is connected to a touch potential control terminal EN, the output terminal OUT_N of the shift register unit 10, the pull-up node PU, the pull-down node PD, and a low-level output terminal that outputs a low level VGL. During a touch stage, under control of the touch potential control terminal EN, the touch potential control circuit 11 controls the output terminal OUT_N of the shift register unit 10, the pull-up node PU, and the pull-down node PD to be connected to the low-level output terminal that outputs the low level VGL.

[0030] The shift register unit according to the disclosed embodiment employs a touch potential control circuit 11 to pull down the gate driving signal output from the output terminal OUT_N of the shift register unit 10, the potential of the pull-up node PU, and the potential of the pull-down node PD to a low level during the touch stage, thereby preventing the GOA circuit from outputting the gate driving signal and preventing the shift register unit from entering an operating state, thereby reducing the overall power consumption of the GOA circuit and the display panel and improving the touch accuracy.

[0031] In order to improve the accuracy of touch, the gate driving signal needs to be kept at a low level during the touch phase, i.e., the shift register circuit is in a locked state during the touch phase, i.e., the pull-up node potential and the pull-down node potential are in a pull-down state, which reduces the overall power consumption of the gate driving circuit (which includes a multi-stage shift register circuit) and the display panel.

[0032] As shown in FIG. 2, the shift register unit 10 includes a pull-up node PU, a pull-down node PD, a charge / discharge circuit 21, a pull-up node control circuit 22, a pull-down node control circuit 23, and an output circuit 24.

[0033] The pull-up node control circuit 22 is connected to the pull-up node PU.

[0034] The pull-down node control circuit 23 is connected to the pull-up node PU and the pull-down node PD.

[0035] The charge / discharge circuit 21 is connected to the pull-up node PU and the output terminal OUT_N of the shift register unit.

[0036] The output circuit 24 is connected to the pull-up node PU, the pull-down node PD, and the output terminal OUT_N of the shift register unit.

[0037] Specifically, the touch potential control circuit can include a first touch potential control transistor, a second touch potential control transistor, and a third touch potential control transistor.

[0038] Here, the first electrode of the first touch potential control transistor is connected to the touch potential control terminal, the second electrode is connected to the low level output terminal, and the third electrode is connected to the output terminal of the shift register unit.

[0039] A first electrode of a second touch potential control transistor is connected to the touch potential control terminal, a second electrode is connected to the low level output terminal, and a third electrode is connected to the pull-up node.

[0040] A third touch potential control transistor has a first electrode connected to the touch potential control terminal, a second electrode connected to the pull-down node, and a third electrode connected to the low-level output terminal.

[0041] In a specific implementation, the first touch potential control transistor, the second touch potential control transistor and the third touch potential control transistor are all n-type transistors, and the touch potential control terminal outputs a high level in the touch stage and a low level in the display stage; alternatively, the first touch potential control transistor, the second touch potential control transistor and the third touch potential control transistor are all p-type transistors, and the touch potential control terminal outputs a low level in the touch stage and a high level in the display stage.

[0042] In actual operation, the first pole may be the gate, the second pole may be the source, and the third pole may be the drain, or the first pole may be the gate, the second pole may be the drain, and the third pole may be the source.

[0043] As shown in FIG. 3, in the shift register unit according to the disclosed embodiment, the touch potential control circuit may include a first touch potential control transistor MTC1, a second touch potential control transistor MTC2 and a third touch potential control transistor MTC3.

[0044] Here, the gate of the first touch potential control transistor MTC1 is connected to the touch potential control terminal EN, the source is connected to the low level output terminal that outputs the low level VGL, and the drain is connected to the output terminal OUT_N of the shift register unit 10.

[0045] The second touch potential control transistor MTC2 has a gate connected to the touch potential control terminal EN, a source connected to the low level output terminal that outputs the low level VGL, and a drain connected to the pull-up node PU.

[0046] The third touch potential control transistor MTC3 has a gate connected to the touch potential control terminal EN, a source connected to the pull-down node PD, and a drain connected to the low level output terminal that outputs the low level VGL.

[0047] During actual operation, in the touch stage, EN outputs a high level, so that MTC1, MTC2 and MTC3 are all turned on, and OUT_N, PU and PD are all at a low level VGL.

[0048] Specifically, the output circuit is further connected to the pull-up node, the pull-down node, the first clock signal output terminal, the low-level output terminal and the output terminal of the shift register unit, respectively.

[0049] A first end of the charging / discharging circuit is connected to the pull-up node, and a second end of the charging / discharging circuit is connected to the output end of the shift register unit.

[0050] The pull-up node control circuit comprises a first pull-up node control sub-circuit and a second pull-up node control sub-circuit, and the pull-down node control circuit comprises a first pull-down node control sub-circuit and a second pull-down node control sub-circuit.

[0051] The first pull-up node control sub-circuit is connected to a first scan control end, a second scan control end, a first scan level end, a second scan level end and the pull-up node, respectively.

[0052] The second pull-up node control subcircuit is connected to the pull-up node, the pull-down node, and the low-level output, respectively.

[0053] a first pull-down node control subcircuit connected to the first scan level end, the second scan level end, the second clock signal output end, the third clock signal output end, the high level output end outputting a high level, the pull-down node, and the pull-down control node, for controlling the pull-down control node to be connected to the second clock signal output end under the control of the first scan level end when scanning in the forward direction, and for controlling the pull-down node to be connected to the high level output end when the second clock signal output end outputs a high level; and for controlling the pull-down control node to be connected to the third clock signal output end under the control of the second scan level end when scanning in the reverse direction, and for controlling the pull-down node to be connected to the high level output end when the third clock signal output end outputs a high level;

[0054] The second pull-down node control subcircuit is connected to the pull-up node, the pull-down node, and the low-level output, respectively.

[0055] Specifically, the first pull-down node control subcircuit comprises: a first pull-down node control transistor, the first pole of which is connected to the first scan level terminal, the second pole of which is connected to the second clock signal output terminal, and the third pole of which is connected to the pull-down control node; a second pull-down node control transistor, the first pole of which is connected to the second scan level terminal, the second pole of which is connected to the pull-down control node, and the third pole of which is connected to the third clock signal output terminal; a third pull-down node control transistor arranged to have a first pole connected to the pull-down control node, a second pole connected to the high-level output terminal, and a third pole connected to the pull-down node; It can be equipped with:

[0056] In concrete implementation, when scanning in the forward direction, the first scanning control end is the input end, the second scanning control end is the reset end, the first scanning level end is the high level output end, and the second scanning level end is the low level output end; when scanning in the reverse direction, the first scanning control end is the reset end, the second scanning level end is the input end, the first scanning level end is the low level output end, and the second scanning level end is the high level output end.

[0057] The first pull-up node control subcircuit controls the potential of the pull-up node to a high level under the control of an input terminal in an input phase, and to a low level under the control of a reset terminal in a reset phase.

[0058] Specifically, the first pull-up node control sub-circuit comprises: a first scan transistor, the first pole of which is connected to the first scan control terminal, the second pole of which is connected to the first scan level terminal, and the third pole of which is connected to the pull-up node; a second scan transistor, the first pole of which is connected to the second scan control terminal, the second pole of which is connected to the pull-up node, and the third pole of which is connected to the second scan level terminal; It can be equipped with:

[0059] Specifically, the output circuit controls the output terminal of the shift register unit to be connected to the first clock signal output terminal when the potential of the pull-up node is at a high level, and controls the output terminal of the shift register unit to be connected to the low-level output terminal when the potential of the pull-down node is at a high level.

[0060] The second pull-down node control subcircuit controls the pull-down node to be connected to the low-level output terminal when the potential of the pull-up node is at a high level.

[0061] The second pull-up node control subcircuit controls the pull-up node to be connected to the low-level output terminal when the potential of the pull-down node is at a high level.

[0062] Specifically, the output circuit comprises: a first pull-up transistor arranged such that a first pole is connected to the high-level output terminal and a second pole is connected to the pull-up node; a second pull-up transistor, the first pole of which is connected to the third pole of the first pull-up transistor, the second pole of which is connected to the output terminal of the shift register unit, and the third pole of which is connected to the first clock signal output terminal; a pull-down transistor having a first pole connected to the pull-down node, a second pole connected to the low-level output terminal, and a third pole connected to the output terminal of the shift register unit; It can be equipped with:

[0063] The second pull-down node control circuit includes: a fourth pull-down node control transistor arranged such that a first pole is connected to the pull-up node, a second pole is connected to the pull-down node, and a third pole is connected to the low-level output; a pull-down node control capacitor having a first end connected to the low-level output end and a second end connected to the pull-down node; It can be equipped with:

[0064] The second pull-up node control subcircuit may include a pull-up node control transistor arranged with a first pole connected to the pull-down node, a second pole connected to the low-level output, and a third pole connected to the pull-up node.

[0065] The charging / discharging circuit may include a storage capacitor having a first end connected to the pull-up node and a second end connected to the output end of the shift register unit.

[0066] The shift register circuit according to the present disclosure will be described below by way of a specific embodiment.

[0067] As shown in FIGS. 2 and 4, a specific embodiment of the shift register circuit according to the present disclosure includes a shift register unit 10 and a touch potential control circuit 11.

[0068] Here, the touch potential control circuit 11 includes a first touch potential control transistor MTC1, a second touch potential control transistor MTC2, and a third touch potential control transistor MTC3.

[0069] The first touch potential control transistor MTC1 has a gate connected to the touch potential control terminal EN, a source connected to the low level output terminal outputting the low level VGL, and a drain connected to the output terminal OUT_N of the shift register unit.

[0070] The second touch potential control transistor MTC2 has a gate connected to the touch potential control terminal EN, a source connected to the low level output terminal that outputs the low level VGL, and a drain connected to the pull-up node PU.

[0071] The third touch potential control transistor MTC3 has a gate connected to the touch potential control terminal EN, a source connected to the pull-down node PD, and a drain connected to the low level output terminal that outputs the low level VGL.

[0072] 2 and 4, the shift register unit 10 includes a pull-up node PU, a pull-down node PD, a charge / discharge circuit 21, a pull-up node control circuit 22, a pull-down node control circuit 23, and an output circuit 24. Here, the pull-up node control circuit 22 includes a first pull-up node control subcircuit 221 and a second pull-up node control subcircuit 223. The pull-down node control circuit 23 includes a first pull-down node control subcircuit 231 and a second pull-down node control subcircuit 233.

[0073] As shown in FIG. 4, the first pulldown node control subcircuit 231 includes a first pulldown node control transistor MDC1, a second pulldown node control transistor MDC2, and a third pulldown node control transistor MDC3.

[0074] The first pull-down node control transistor MDC1 has a gate connected to the first scan level terminal CN, a source connected to the second clock signal output terminal CK2, and a drain connected to the pull-down control node PDCN.

[0075] The gate of the second pull-down node control transistor MDC2 is connected to the second scan level terminal CNB, the source is connected to the pull-down control node PDCN, and the drain is connected to the third clock signal output terminal CK3.

[0076] The third pull-down node control transistor MDC3 has a gate connected to the pull-down control node PDCN, a source connected to a high-level output terminal that outputs a high level VGH, and a drain connected to the pull-down node PD.

[0077] The first pullup node control subcircuit 221 comprises a first scan transistor MS1 and a second scan transistor MS2.

[0078] The first scan transistor MS1 has a gate connected to the input terminal OUT_N-1, a source connected to the first scan level terminal CN, and a drain connected to the pull-up node PU.

[0079] The second scan transistor MS2 has a gate connected to the reset terminal OUT_N+1, a source connected to the pull-up node PU, and a drain connected to the second scan level terminal CNB.

[0080] The output circuit 24 includes a first pull-up transistor MU1, a second pull-up transistor MU2, and a pull-down transistor MD.

[0081] The gate of the first pull-up transistor MU1 is connected to a high-level output terminal that outputs a high level VGH, and the source is connected to the pull-up node PU.

[0082] The second pull-up transistor MU2 has a gate connected to the drain of the first pull-up transistor MU1, a source connected to the output terminal OUT_N of the shift register unit, and a drain connected to the first clock signal output terminal CK1.

[0083] The pull-down transistor MD has a gate connected to the pull-down node PD, a source connected to a low level output terminal outputting a low level VGL, and a drain connected to the output terminal OUT_N of the shift register unit.

[0084] The second pull-down node control subcircuit 233 includes a fourth pull-down node control transistor MDC4 and a pull-down node control capacitor Cdc, whose gate is connected to the pull-up node PU, whose source is connected to the pull-down node PD, and whose drain is connected to a low-level output terminal for outputting a low-level voltage VGL.

[0085] A first end of the pull-down node control capacitor Cdc is connected to a low-level output terminal that outputs a low level VGL, and a second end of the pull-down node Cdc is connected to the pull-down node PD.

[0086] The second pull-up node control subcircuit 223 includes a pull-up node control transistor MUC, whose gate is connected to the pull-down node PD, whose source is connected to a low-level output terminal that outputs a low level VGL, and whose drain is connected to the pull-up node PU.

[0087] The charging / discharging circuit 21 includes a storage capacitor Cs, a first end of which is connected to the pull-up node PU, and a second end of which is connected to the output terminal OUT_N of the shift register unit.

[0088] In the specific embodiment of the shift register circuit shown in FIG. 4 of the present disclosure, CN outputs a high level and CNB outputs a low level.

[0089] 5 is a sequence diagram of the operation of the specific embodiment of the shift register circuit shown in FIG. 4 of the present disclosure. As shown in FIG. 5, in the first stage T1, i.e., the input stage, OUT_N-1 outputs a high level, MS1 is turned on, the potential of PU rises, MD4 is turned on, the potential of PD is pulled down, and Cs is charged.

[0090] In the second stage T2, i.e., the output stage, MS1 is turned off, and due to the bootstrap effect of Cs, the potential of PU continues to rise, MU2 is turned on, OUT_N outputs a high level, and the potential of PD is still in the pull-down state.

[0091] In the third stage T3, i.e., the reset stage, MS2 turns on, the potential of PU is pulled down, and CK2 outputs a high level, so the potential of PDCN becomes high, MDC3 turns on, the potential of PD is pulled up, MDC4 and MD are both turned on, and the potential of PU and the gate drive signal output by OUT_N are pulled down, charging Cdc.

[0092] In the fourth stage T4, i.e., the touch stage, EN outputs a high level, MTC1, MTC2 and MTC3 are all turned on, and the gate driving signal output from OUT_N, the potential of PU and the potential of PD are all pulled down, which not only increases the touch sensitivity but also reduces the power consumption of the display panel.

[0093] The GOA circuit according to the disclosed embodiment comprises a plurality of cascaded shift register circuits as described above.

[0094] A display device according to an embodiment of the present disclosure includes the gate drive circuit.

[0095] The above are optional implementation modes of the present disclosure, and those skilled in the art can make some improvements and modifications without departing from the above principles of the present disclosure, and these improvements and modifications should be considered within the protection scope of the present disclosure.

Claims

1. a shift register circuit including a shift register unit, an output terminal of the shift register unit being connected to a gate driving signal line, the shift register unit including a pull-up node control circuit, a pull-up node whose potential is controlled by the pull-up node control circuit, a pull-down node control circuit, a pull-down node whose potential is controlled by the pull-down node control circuit, and an output circuit, the pull-up node control circuit being connected to the pull-up node, the pull-down node control circuit being connected to the pull-up node and the pull-down node, respectively, and the output circuit being connected to the pull-up node, the pull-down node, and the output terminal of the shift register unit, respectively; The shift register circuit comprises: a touch potential control circuit connected to a touch potential control terminal, an output terminal of the shift register unit, the pull-up node, the pull-down node, and a low level output terminal, respectively, and controlling the pull-up node and the pull-down node to be both connected to the low level output terminal and both set to a low level under the control of the touch potential control terminal during a touch step; a charging / discharging circuit connected to the pull-up node and the output terminal of the shift register unit, the charging / discharging circuit includes a storage capacitor, a first end of the storage capacitor is connected to the pull-up node, and a second end of the storage capacitor is connected to the output end of the shift register unit; The touch potential control circuit further controls, during the touch stage, the output terminal of the shift register unit to be connected to the low level output terminal under the control of the touch potential control terminal, so as to be at a low level; Shift register circuit.

2. The touch potential control circuit includes: a first touch potential control transistor, the first electrode of which is connected to the touch potential control terminal, the second electrode of which is connected to the low-level output terminal, and the third electrode of which is connected to the output terminal of the shift register unit; a second touch potential control transistor arranged so that a first pole is connected to the touch potential control terminal, a second pole is connected to the low level output terminal, and a third pole is connected to the pull-up node; a third touch potential control transistor arranged so that a first pole is connected to the touch potential control terminal, a second pole is connected to the pull-down node, and a third pole is connected to the low-level output terminal; 2. The shift register circuit of claim 1, comprising:

3. The first touch potential control transistor, the second touch potential control transistor, and the third touch potential control transistor are all n-type transistors, and the touch potential control terminal outputs a high level in the touch stage and a low level in the display stage.

3. The shift register circuit of claim 2.

4. The first touch potential control transistor, the second touch potential control transistor, and the third touch potential control transistor are all p-type transistors, and the touch potential control terminal outputs a low level in the touch stage and a high level in the display stage.

3. The shift register circuit of claim 2.

5. the pullup node control circuit comprises a first pullup node control subcircuit and a second pullup node control subcircuit; the first pull-up node control subcircuit is connected to a first scan control end, a second scan control end, a first scan level end, a second scan level end and the pull-up node, respectively; The second pull-up node control subcircuit is connected to the pull-up node, the pull-down node, and the low-level output terminal, respectively.

5. The shift register circuit according to claim 1.

6. the output circuit is further connected to the first clock signal output terminal and the low level output terminal, respectively; the pull-down node control circuit comprises a first pull-down node control sub-circuit and a second pull-down node control sub-circuit; the first pull-down node control subcircuit is respectively connected to the first scan level end, the second scan level end, the second clock signal output end, the third clock signal output end, a high level output end, the pull-down node and a pull-down control node; The second pull-down node control subcircuit is connected to the pull-up node, the pull-down node, and the low-level output terminal, respectively.

6. The shift register circuit according to claim 5.

7. the output circuit controls the output terminal of the shift register unit to be connected to the first clock signal output terminal when the potential of the pull-up node is at a high level, and the output terminal of the shift register unit to be connected to the low-level output terminal when the potential of the pull-down node is at a high level; the second pull-down node control subcircuit controls the pull-down node to be connected to the low-level output terminal when the potential of the pull-up node is at a high level; The second pull-up node control subcircuit controls the pull-up node to be connected to the low-level output terminal when the potential of the pull-down node is at a high level.

7. The shift register circuit of claim 6.

8. the first pull-down node control subcircuit comprising: a first pull-down node control transistor, the first pole of which is connected to the first scan level end, the second pole of which is connected to the second clock signal output end, and the third pole of which is connected to the pull-down control node; a second pull-down node control transistor, the first pole of which is connected to the second scan level end, the second pole of which is connected to the pull-down control node, and the third pole of which is connected to the third clock signal output end; a third pull-down node control transistor arranged to have a first pole connected to the pull-down control node, a second pole connected to the high-level output terminal, and a third pole connected to the pull-down node; 7. The shift register circuit of claim 6, comprising:

9. the second pulldown node control subcircuit comprising a fourth pulldown node control transistor and a pulldown node control capacitor; a first pole of the fourth pull-down node control transistor is connected to the pull-up node, a second pole is connected to the pull-down node, and a third pole is connected to the low-level output terminal; The pull-down node control capacitor has a first end connected to the low-level output end and a second end connected to the pull-down node.

9. The shift register circuit of claim 8.

10. The output circuit a first pull-up transistor arranged such that a first pole is connected to the high-level output terminal and a second pole is connected to the pull-up node; a second pull-up transistor having a first pole connected to the third pole of the first pull-up transistor, a second pole connected to the output terminal of the shift register unit, and a third pole connected to the first clock signal output terminal; a pull-down transistor having a first pole connected to the pull-down node, a second pole connected to the low-level output terminal, and a third pole connected to the output terminal of the shift register unit; 7. The shift register circuit of claim 6, comprising:

11. When scanning in a forward direction, the first scanning control end becomes an input end, the second scanning control end becomes a reset end, the first scanning level end becomes a high level output end, and the second scanning level end becomes a low level output end; when scanning in a reverse direction, the first scanning control end becomes a reset end, the second scanning level end becomes an input end, the first scanning level end becomes a low level output end, and the second scanning level end becomes a high level output end; The first pull-up node control subcircuit controls the potential of the pull-up node to a high level under the control of an input terminal during an input phase, and controls the potential of the pull-up node to a low level under the control of a reset terminal during a reset phase.

6. The shift register circuit according to claim 5.

12. the first pull-up node control subcircuit comprising: a first scanning transistor, the first pole of which is connected to the first scanning control end, the second pole of which is connected to the first scanning level end, and the third pole of which is connected to the pull-up node; a second scanning transistor arranged such that a first pole is connected to the second scanning control terminal, a second pole is connected to the pull-up node, and a third pole is connected to the second scanning level terminal; 12. The shift register circuit of claim 11, comprising:

13. the second pullup node control subcircuit comprising a pullup node control transistor; The pull-up node control transistor has a first electrode connected to the pull-down node, a second electrode connected to the low-level output terminal, and a third electrode connected to the pull-up node.

6. The shift register circuit according to claim 5.

14. A GOA circuit comprising a plurality of cascaded shift register circuits according to any one of claims 1 to 13.

15. A display device comprising the GOA circuit according to claim 14.

16. 16. A method for driving a display device according to claim 15, In the touch step, the touch potential control circuit controls the pull-up node and the pull-down node to be both connected to the low-level output terminal under the control of the touch potential control terminal. A driving method including:

17. In the touch step, the touch potential control circuit further controls the output terminal of the shift register unit to be connected to the low level output terminal under the control of the touch potential control terminal. The driving method according to claim 16.

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