Camera device with verification support function, verification support device, and verification support method for camera device

Abstract

It enables observation of each observation item corresponding to the input / output signals to the camera device, the control signals from the control PC, and the internal signals of the camera device on a time axis with nanosecond accuracy. [Solution] In a camera device in which multiple controlled units that operate in response to multiple commands are controlled, log data on the control of each controlled unit, which is an integrated log data of a timestamp with nanosecond accuracy and data for checking control items, is stored in a log storage circuit arranged corresponding to each controlled unit.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to a camera device having a verification support function, a verification support device, and a verification support method for a camera device. [Background technology]

[0002] For example, video systems have been introduced to automate factories, etc. The video systems monitor the inside of the factory by placing camera devices at multiple locations within the factory.

[0003] At this point, it is possible that a malfunction or error may occur in the video system. In such cases, to determine the root cause, verification of each camera device itself is required.

[0004] Conventionally, it is common to use measuring instruments such as oscilloscopes and logic analyzers to verify the operation of camera devices themselves. By probing the signals to be observed, it is possible to observe parallel input / output signals and internal signals. However, there are limitations to the signals that can be observed.

[0005] For video systems, a system control unit (usually a PC (personal computer), hereafter referred to as the control PC) that controls the video system externally is connected to the camera device. In order to perform detailed verification, it is necessary to have the control PC control the camera device and observe whether the camera device is responding correctly to this control (the so-called control status). However, because the control PC uses a serial interface, it is difficult to observe the overall control status using measuring equipment such as the oscilloscope and logic analyzer mentioned above.

[0006] To solve this problem, a known technique is to observe the serial interface using a measuring device such as a bus analyzer. However, this method only verifies the information output to the serial interface, which means that it is not possible to directly observe the input / output signals or internal signals of the camera device mentioned above.

[0007] Depending on the content of the verification, there may be cases where it is desired to simultaneously perform both the input / output signals and internal signals of the camera device (observation of the first measurement method) and the control status by the control PC (observation of the second measurement method). For example, when exposure start control, which starts exposure for the camera device, is initiated inside the camera device, and exposure time change control, which changes the exposure time, is performed from an external control device, there may be cases where it is desired to observe these two types of control on the same time axis. In such cases, it is necessary to perform observations using both the first and second measurement methods. In other words, The first measurement method is to use measuring equipment such as the oscilloscope and logic analyzer to verify the internal operation of the camera device. The second measurement method is to observe the serial interface using a measuring device similar to a bus analyzer.

[0008] However, the method using the two different types of measuring instruments described above has the drawback that it is not possible to simultaneously observe multiple control situations for the camera device on the same time axis.

[0009] Furthermore, if the first and second measurement methods are adopted, they require the use of measuring equipment separate from the camera device, making it difficult to integrate them into the factory where the camera device is actually in operation.

[0010] To solve this problem, a known technique involves creating a verification log using software control in the central processing unit (CPU) built into the control PC or camera device. This has the advantage that the camera's verification function is configured using software in the CPU, eliminating the need for dedicated measurement equipment and eliminating connection issues with the measurement equipment. However, the timing accuracy depends on the performance of the control PC or camera's built-in CPU, resulting in a lower accuracy than dedicated measurement equipment (measured in milliseconds). [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-023644 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-211606 [Patent Document 3] Japanese Patent Application Publication No. 10-93754 Summary of the Invention [Problem to be solved by the invention]

[0012] As described above, conventional video systems have a problem in that it is difficult to accurately observe on the same time axis the timing of changes in the operating state of each part of the camera device relative to the timing of input of various control signals to the camera device. In addition, in situations where it is difficult to connect measuring equipment, one technique is to create logs using software that controls a control PC or camera device, but this involves creating logs in milliseconds, which reduces temporal accuracy.

[0013] Therefore, in order to solve the above problems, the present invention aims to provide a camera device, a verification support device, and a verification support method for a camera device that has a verification support function that makes it possible to observe each observation item corresponding to each of the control signals from the control PC and the internal signals of the camera device on the same time axis, and further makes it possible to store each single log data that integrates each observation item with a timestamp common to each observation item in an independent hardware storage circuit. [Means for solving the problem]

[0014] According to one embodiment, a packet transmitting / receiving circuit for receiving serial data from a computer; a camera control circuit that receives control data from the packet transmission / reception circuit; an image sensor control circuit that is controlled by the camera control circuit and controls an image sensor; a timestamp control circuit that outputs a timestamp; a first log storage circuit, a second log storage circuit, and a third log storage circuit configured as hardware for storing log data that integrates the timestamp and control item check data for each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit when a command instructing the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit to operate is given; an arbitration circuit that, when selecting each log data from the first log storage circuit, the second log storage circuit, and the third log storage circuit as a write target to a memory, sequentially selects the log data as a write target in order from the oldest timestamp value; a write control circuit that sequentially writes each of the selected log data into the memory; A camera device having a verification support function is provided. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a camera device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of the log memory 101 in FIG. [Figure 3]FIG. 3 is a timing chart showing an example of the operation of the main parts of the camera device according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, an embodiment will be described with reference to the drawings. Fig. 1 shows the overall configuration when one embodiment is applied to a camera device 1. The camera device of this embodiment uses an interface capable of high-speed communication, such as USB 3.0, Ethernet, Camera Link, or CoaXPress.

[0017] A control PC 3 is connected to the camera device 1 via a serial interface 2. During normal operation, the control PC 3 stores imaging conditions (commands) such as exposure time and white balance in packets and transmits them to the camera device 1 via the serial interface 2.

[0018] The camera device 1 receives packets sent from the control PC 3 using the packet transmission / reception circuit 107, extracts commands, and transmits them to the camera control circuit 108. The camera control circuit 108 controls the image sensor control circuit 109 according to the content of the commands, and the image sensor control circuit 109 controls the image sensor 110. For example, the image sensor control circuit 109 controls the exposure time of the image sensor 110, reads video data captured by the image sensor 110, and converts the video data into a predetermined format. The converted video data is sent to the packet transmission / reception circuit 107 by the camera control circuit 108. The video data is organized into packets by the packet transmission / reception circuit 107 and transmitted to the control PC 3 via the serial interface 2. The camera control circuit 108 may also send video data to an external input / output control circuit 111.

[0019] The external input / output control circuit 111 can receive camera control signals from outside the camera device 1, and inputs the camera control signals to the camera control circuit 108. The camera control signals are transmitted via a parallel interface.

[0020] The external input / output control circuit 111 is often used by on-site users in a factory, whereas the control PC 3 is installed primarily by the manufacturer that delivered the video system or the manager of the factory where the camera device is used, and is used to perform pre-set system control.

[0021] Next, a system for acquiring log data on the operation and control status of the camera device 1 will be described.

[0022] First, 101 denotes a log memory, 102 denotes a log data transmission / reception circuit, and 103 to 106 denote log storage circuits. The log memory 101 can store log data held in the log storage circuits 103, 104, 105, and 106. In response to control from the packet transmission / reception circuit 107, the log data transmission / reception circuit 102 can read out the log data stored in the log memory 101 and input it to the packet transmission / reception circuit 107. The above log processing block is configured by hardware, and may be constructed on a dedicated board, for example.

[0023] The log storage circuit 103 stores data that is a pair of part or all of the received command and the timestamp from the timestamp control circuit 112 at the time of reception.

[0024] In this specification, data sent from the control PC 3 is called a "command," and a response to this is called an "acknowledgement." In contrast, internal control using control data generated within the camera device (e.g., generated by the camera control unit 108) is called "control." Based on this premise, the following control item check data is defined. That is, "control item check data" may be data in which part or all of a command is paired with a timestamp, and is hereinafter referred to as "single log data." Here, the "control item check data" may be the camera control content, the control location, or a code that combines these. Furthermore, the "control item check data" may be a code of identification data (for example, an address, name, or operation name) assigned to a function (which may be called a controlled unit) within the camera device that is to be controlled by the command. Furthermore, to control each function of the camera, an address is assigned to each camera function (controlled unit), and a so-called memory-mapped I / O method may be incorporated into the "control item check data" and used. Essentially, the data should be such that it is possible to confirm what control was performed on which part of the camera device. The same can be said for the log data described below.

[0025] The single log data is written from the log storage circuits 103, 104, 105, and 106 to the log memory 101 (details of the log memory 101 are shown in FIG. 2).

[0026] Furthermore, the camera control circuit 108 interprets the command received from the packet transmission / reception circuit 107, returns an acknowledgement, and controls (changes, switching, adjustments, etc.) the operating state of the camera device 1. For example, if the control content of the received command relates to the operating state of the image sensor 110, it transmits the control data to the image sensor control circuit 109. The control data in this case includes shutter timing (exposure time) setting, readout control, and readout area selection / switching.

[0027] This system allows the image sensor 110 to set the frame angle of view and switch the readout area, and also allows the frame frequency of the readout video data to be set to a high frequency.

[0028] In the above operation, the log storage circuit 105 stores, as single log data, the change in the operating state of the camera control circuit 108 and the timestamp of the timestamp control circuit 112. Thereafter, this single log data is written to the log memory 101.

[0029] The basic clock for the operation of the camera control circuit 108 is synchronized with the basic clock from the timestamp control circuit 112. The timestamp control circuit 112 is also connected to the timestamp control circuits or camera control circuits of other camera devices (not shown) and maintains a synchronous relationship.

[0030] The log storage circuit 105 may also store the internal temperature, power supply voltage, and power saving state of the camera device as log data in the control item check data, which are known by the camera control circuit 108. These conditions can be displayed on the display unit of the control PC 3.

[0031] The image sensor control circuit 109 controls the image sensor 110 based on the above-mentioned control contents (exposure time setting, selection and switching of readout areas, etc.) given by the camera control circuit .

[0032] At this time, the log storage circuit 106 stores single log data that is a pair of control item check data (part or all of the control or identification data, etc.) when various controls based on the specific control content are executed on the image sensor 110 and a timestamp at the time of reception from the timestamp control circuit 112. This single log data is then written to the log memory 101.

[0033] The video data acquired by the image sensor 110 reaches the packet transmission / reception circuit 107 via the image sensor control circuit 109 and the camera control circuit 108. Even when the video data acquired by the image sensor 110 reaches the packet transmission / reception circuit 107 via the image sensor control circuit 109 and the camera control circuit 108, the control item check data and each timestamp are stored in the corresponding log storage circuits 106, 105, and 103 in each circuit.

[0034] The video data is constructed into packets by the packet transmission / reception circuit 107 and transmitted from the serial interface 2 to the control PC 3 .

[0035] At this time, the log storage circuit 103 stores the control item check data, which indicates that the video data has been transmitted, and the time stamp as single log data. This single log data is then written to the log memory 101.

[0036] The log storage circuit 103 also receives information such as the occurrence of an error on the communication path and the recovery processing status from the status of the packet transmission / reception circuit 107, and stores these observation items as log data together with a timestamp as single log data. This single log data is then written to the log memory 101.

[0037] The camera device 1 also has an external input / output control circuit 111. This external input / output control circuit 111 has a function of accepting control input from the outside. For example, when the external input / output control circuit 111 accepts control to start imaging from the outside, it notifies the camera control circuit 108 of this control. Furthermore, for example, if the camera device 1 is set to output an imaging timing pulse, the imaging timing pulse generated by the camera control circuit 108 can be output via the external input / output control circuit 111.

[0038] When the external input / output control circuit 111 receives the above-mentioned external control, the log storage circuit 104 stores the control item check data and the time stamp at that time. At this time, the control item check data naturally includes identification data that indicates that the external input / output control circuit 111 has received the control.

[0039] The external input / output is connected to devices other than the control PC 3, such as a photoelectric sensor. These devices and the control PC 3 are not synchronized, and the commands input to the packet transmission / reception circuit 107 and the controls input to the external input / output circuit 111 are asynchronous. In such cases, it can be difficult to identify the input order of the commands and controls and the order in which they are propagated to the camera control circuit 108. However, in this embodiment, this identification becomes possible with high accuracy of nanoseconds, as will be described later with reference to FIG. 3.

[0040] As described above, the log storage circuits 103, 104, 105, and 106 can store status information within the camera device with nanosecond precision, which is finer than millisecond precision on the time axis, based on the timestamp provided by the timestamp control circuit 112. This is because the log storage circuits 103, 104, 105, and 106 are configured as hardware, with one-to-one correspondence to the packet transmission / reception circuit 107, external input / output control circuit 111, camera control circuit 108, and image sensor circuit 109. With this configuration, there is no influence of software processing steps based on the CPU processing speed.

[0041] The contents of the single log data stored in the log storage circuits 103, 104, 105, and 106 can be roughly summarized as follows: Log storage circuit 103: Command, acknowledge, error occurrence on communication line, Log storage circuit 104: Changes in the state of external inputs and outputs Log storage circuit 105: Changes in the camera's internal state, temperature changes, power supply voltage changes, power saving state, Log storage circuit 106: Image sensor operating state.

[0042] Next, a command packet transmitted and received in the serial interface 2 will be described. The command packet output by the camera control PC 3 during PC control includes data indicating the access mode (read / write), address (e.g., memory-mapped I / O address), and write data (for write access). However, this is not limited to the above method, and any means for identifying each part of the camera device, such as a circuit name or function name, may be used as control item check data. In the case of memory-mapped I / O addresses, when the same address is controlled consecutively, a count value is incremented by one to the same address each time control is performed. The added value of the memory-mapped I / O address is reset, for example, after all log data has been read from the log memory 101.

[0043] Furthermore, the acknowledge packet sent from the camera device 1 to the camera control PC 3 may include a control status (normal completion / error, etc.) and read data (at the time of read access) in the control item check data.

[0044] As described above, the overall log data, which is a collection of the individual log data stored in the log memory 101, can be read out by the control PC 3 at any time. When a readout request for the overall log data is received from the control PC 3, the log data transmission / reception circuit 102 transmits the overall log data stored in the log memory 101 to the packet transmission / reception circuit 107. The packet transmission / reception circuit 107 generates the overall log data in packet form and transmits it to the control PC 3 via the serial interface 2. This operation enables the control PC 3 to read out the overall log data stored in the log memory 101 via the serial interface 2 at any time.

[0045] The log memory 101 is not limited to a FIFO (First-In First-Out) or ring buffer implementation. It is also possible to use it as an image memory or other memory for other purposes, rather than as an independent memory. In addition to the memory function, the log memory 101 also has the functions (or controlled units) of arbitrating the writing of the log storage circuits 103, 104, 105, and 106, and suspending and resuming the storage operation.

[0046] FIG. 2 shows an example in which the log memory 101 is configured as a randomly accessible memory.

[0047] Reference numeral 1011 denotes a read control circuit, 1012 denotes a memory, 1013 denotes a write control circuit, and 1014 denotes a write arbitration circuit.

[0048] Of the single log data transmitted from the log storage circuits 103, 104, 105, and 106, the write arbitration circuit 1014 selects the single log data to be written in order, starting with the oldest timestamp value. At this time, the other single log data that is not selected as the write target is temporarily stored in the log storage circuits 103, 104, 105, and 106 and will not be lost. The single log data selected as the write target is transmitted to the write control circuit 1013. The write control circuit 1013 writes the single log data so that it is added to the end of the entire log data.

[0049] When a request to transmit the entire log data is received from the log data transmission / reception circuit 102, the read control circuit 1011 reads the entire log data from the memory 1012 and transmits it to the log data transmission / reception circuit 102. At this time, the read control circuit 1011 controls the transmission of timestamp values ​​in chronological order, starting from the oldest, while referencing the write address pointer of the write control circuit 1013 as necessary.

[0050] The write control circuit 1013 also controls the transition between enabled and disabled states of the write operation of the entire log data. The write control circuit 1013 receives commands from the control PC 3 and can control state transitions such as pausing the saving of the entire log data, accepting control to resume, and automatically pausing the saving in response to preset trigger conditions. Commands related to the above transitions are given directly to the log memory 101 from the packet transmission / reception circuit 107.

[0051] The overall log data stored in the log memory 101 can include not only the above-mentioned commands, controls, changes in the internal state of the camera due to controls, the operating state of the image sensor, and changes in the state of external input and output, but also changes in the surrounding conditions of the camera, such as the occurrence of errors on the communication line and the recovery processing state, temperature, power supply voltage, and power saving state.

[0052] As described above, according to this embodiment, information required for verification, such as commands from the control PC, the operating state of the image sensor control, and changes in the state of GPIO (General-purpose input / output), is stored in the log memory along with highly accurate timestamps that share a common time axis, which has the advantage that verification can be performed by referencing various types of data on the same time axis.

[0053] Furthermore, log acquisition is performed using the camera's timestamp as the time base. This does not depend on a control PC, so it has the advantage of being able to obtain nanosecond or finer time base accuracy (higher accuracy than the clock frequency of the camera control circuit being used) even when not using a measurement device.

[0054] FIG. 3 is an explanatory diagram showing an example of a log data acquisition sequence in time series when log data is acquired in the camera device according to this embodiment.

[0055] This is a timing chart showing when events that require saving as logs occur in the packet transmission / reception circuit 107, the external input / output control circuit 111, the camera control circuit 108, and the image sensor control circuit 109, and the write control circuit 1013 (shown in FIG. 2) writes these events to the memory 1012 (shown in FIG. 2). The log saving circuits 103 to 106 are omitted for simplification.

[0056] When the packet transmission / reception circuit 107 receives the command X1 transmitted from the control PC 3, the log storage circuit 103 transmits the command together with the timestamp T1 of the timestamp control circuit 112 to the log memory 101.

[0057] Since there is no other writing in progress, the write control circuit 1013 (FIG. 2) in the log memory 101 immediately writes the received timestamp T1 and command W1 to the memory 1012 (T1, W1).

[0058] Next, when the camera control circuit 108 changes the operating state of the camera device 1 to X2 based on the previous command X1, the log storage circuit 105 transmits the operating state change to the log memory 101 together with the timestamp T2 of the timestamp control circuit 112. At this time, the write control circuit 1013 (shown in FIG. 2) in the log memory 101 is writing a command, so after the write operation W1 of this command is completed, it writes the timestamp T2 and the operating state change W2.

[0059] In the above case, the write control circuit 1013 puts the writing of the operating state change W2 into a standby state, but since the log storage circuit 105 holds the value of the timestamp T2 at the time when the operating state change X2 occurred, the value of the timestamp T2 will not be shifted due to a delay in writing.

[0060] Next, an example in which an external input / output change X3 in the external input / output control circuit 111 and an image sensor control X4 in the image sensor control circuit 109 occur almost simultaneously will be described.

[0061] When an external input / output change X3 occurs in the external input / output control circuit 111, the log storage circuit 104 transmits the external input / output change X3 to the log memory 101 together with a timestamp T3 from the timestamp control circuit 112. At almost the same time as this transmission but later, if the image sensor control circuit 109 performs image sensor control X4 based on a change X2 in the operating state of the camera control circuit 108, the log storage circuit 106 transmits the image sensor control X4 to the log memory 101 together with the timestamp T4 from the timestamp control circuit 112.

[0062] At this time, the write control circuit 1013 is writing the operation state change W2, so the external input / output change W3 and image sensor control W4 are waiting to be written. After writing the operation state change W2 is completed, the write control circuit 1013 starts writing the timestamp T3 and external input / output change W3, and then the timestamp T4 and image sensor control W4 in the order of arrival of the write operations.

[0063] Furthermore, when the packet transmission / reception circuit 107 transmits an acknowledgement X5 in response to the command while writing the external input / output change W3, the log storage circuit 103 transmits the acknowledgement together with the timestamp T5 of the timestamp control circuit 112 to the log memory 101. At this time, because the write of the image sensor control W4 is first put into a standby state, the write control circuit 1013 writes the timestamp T5 and the acknowledgement W5 after writing the image sensor control W4. As described above, in this system, single log data to be stored next in the memory 101 may occur when the write process of the single log data to be stored first in the memory 101 has not yet been completed. In such a case, the order in which the multiple single log data to be stored occurs can be managed using the timestamps of a high-speed clock by multiple log storage circuits configured in hardware.

[0064] When all write standby states are released, the write control circuit 1013 returns to its operation of immediately writing after a write request arrives. When the packet transmission / reception circuit 107 transmits the video data information X6, the log storage circuit 103 transmits the video data information together with the timestamp T6 of the timestamp control circuit 112 to the log memory 101. Since there are no writes in the standby state, the write control circuit 1013 immediately starts writing the timestamp T6 and the video data information W6.

[0065] As described above, in this embodiment, even if the timing at which a command is given and the period of operation in response to it do not match (i.e., even if the interval is a very short interval of nanoseconds), the timing at which the command is given is managed in chronological order using a timestamp.

[0066] This allows for accurate management of the control timing of the camera device and the operating status corresponding to that control. The control PC 3 also includes a means for receiving log data from the memory 101 that stores the log data and displaying, for example, an identification mark for each log data in chronological order of the timestamp. The identification mark for the log data may be identification data identifying the control item check data, or a predetermined sequence of colors or patterns set in the controlled unit. Furthermore, since the control item check data can be identified even when it has passed through the external input / output control circuit 111, external access status can also be easily analyzed. While one log storage circuit 105 is provided corresponding to the camera control circuit 108 in the figure, multiple log storage circuits may be provided in parallel.

[0067] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims. Furthermore, the scope of the present invention also includes cases in which each component of the claims is expressed separately, as a combination of multiple components, or as a combination of these components. Furthermore, multiple embodiments may be combined, and examples composed of such combinations are also within the scope of the invention.

[0068] The present invention is also applicable when the claims are expressed as control logic, as a program including instructions for causing a computer to execute the program, or as a computer-readable recording medium containing the instructions. The names and terms used are not intended to be limiting, and other expressions that have substantially the same content and intent are also included in the present invention. [Explanation of symbols]

[0069] 1···Camera device, 2···Serial interface, 3···Control PC, 101···Log memory, 102···Log data transmission / reception circuit, 103, 104, 105, 106···Log storage circuit, 107, 212···Packet transmission / reception circuit, 108···Camera control circuit, 109···Image sensor control circuit, 110···Image sensor, 111···External input / output control circuit, 1011···Read control circuit, ···Memory, 1013···Write control circuit, 1014···Write arbitration circuit

Claims

1. a packet transmission / reception circuit for receiving serial data from a computer; a camera control circuit that receives control data from the packet transmission / reception circuit; an image sensor control circuit that is controlled by the camera control circuit and controls an image sensor; a timestamp control circuit that outputs a timestamp; a first log storage circuit, a second log storage circuit, and a third log storage circuit configured as hardware for storing log data that integrates the timestamp and control item check data for each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit when a command instructing the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit to operate is given; an arbitration circuit that, when selecting each log data from the first log storage circuit, the second log storage circuit, and the third log storage circuit as a write target to a memory, sequentially selects the log data as a write target in order from the oldest timestamp value; a write control circuit that sequentially writes each of the selected log data into the memory; A camera device having a verification support function.

2. 2. A camera device with a verification support function as described in claim 1, further comprising a fourth log storage circuit, wherein log data including control item check data and a timestamp is input to the fourth log storage circuit from an external input / output control circuit that receives control different from the interface of the serial data received by the packet transmission / reception circuit.

3. 2. The camera device according to claim 1, wherein a log data transmission / reception circuit for transmitting the log data to an external device is connected to the memory.

4. A verification support device to which the camera device according to claim 1 is connected, The computer includes a means for receiving the log data from a memory that stores the log data and displaying the log data in chronological order of the timestamps.

5. A verification support method for a camera device using a camera control circuit that receives control data from a packet transmission / reception circuit that receives serial data from a computer, an image sensor control circuit that is controlled by the camera control circuit and controls an image sensor, and a timestamp control circuit that outputs a timestamp, comprising: When a command instructing an operation of each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit is given to each of the first log storage circuit, the second log storage circuit, and the third log storage circuit configured as hardware, the first log storage circuit, the second log storage circuit, and the third log storage circuit store log data that integrates the timestamp and control item check data for each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit, when selecting each piece of log data from the first log storage circuit, the second log storage circuit, and the third log storage circuit as a write target to a memory, selecting the pieces of log data as a write target in order from the oldest timestamp value; sequentially writing each of the selected log data into the memory; A method for supporting verification of a camera device.

6. 6. The method for supporting verification of a camera device according to claim 5, further comprising transmitting the log data stored in the memory to an external device.

Images