Constant gain and self-calibration techniques for RF amplifiers.

Abstract

To provide a calibration method and a radio frequency integrated circuit for an RF amplifier requiring high precision RF amplifier gain.SOLUTION: The present invention provides a method for maintaining constant amplifier gain over process variations, temperature changes, and supply voltage changes through automatic adjustment of an amplifier bias current. In the method, by a bias generator including a first transistor (M1) and a second transistor (M2) formed by duplicating the same M1 on the basis of a size ratio K, a bias current or a bias voltage is generated, this bias generator is calibrated using a calibration circuit and N transistors in an RFIC, and the bias generator is used to maintain a constant Gm bias on the RFIC.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Application No. 62 / 802,344, filed February 7, 2019, entitled "RF Amplifier Gain Stabilization and Self-Calibration Techniques," the subject matter of which is incorporated herein by reference.

[0002] The disclosed embodiments relate generally to wireless network communications, and more particularly to a radio frequency (RF) amplifier with high precision amplifier gain in a phased array antenna. [Background technology]

[0003] In antenna theory, a phased antenna array typically refers to an array of antennas that generate beams of radio waves, which can be electrically steered to point the beams in different directions without moving the antenna. Beamforming is a technique that can steer an array of antennas to transmit radio signals in a specific direction. The phase and amplitude of each signal are added constructively and destructively to concentrate energy into a narrow beam or lobe. A sidelobe is an antenna's far-field radiation pattern that is not the main lobe. In the case of multiple array antennas operating in a high-density area, each array antenna has its own unique beam aimed at a specific user (direction). Radiation from the antenna sidelobe of one antenna causes interference to signals received by users from adjacent antennas. In the case of a multiple-beam array antenna, each antenna beam is oriented in a specific direction. Radiation from the antenna sidelobe of one antenna beam causes interference to signals received by users from adjacent antenna beams.

[0004] A typical phased-array antenna configuration uses multiple radio frequency integrated circuits (RFICs), such as beamforming RFICs. Each signal path of an antenna element includes a variable gain amplifier and a phase shifter. The signal from each antenna element is amplified and phase-shifted by different amounts (amplitude and phase tapering) to control antenna sidelobes. For example, Chebyshev or Taylor tapering is typically used to attenuate antenna sidelobes. Therefore, calibration of amplifier gain in the RFIC (providing consistent gain) is important to achieve precise amplitude tapering. To achieve low sidelobes, the typical required accuracy for amplitude tapering is 0.375 dB or less, and 6 or 7 bits of accuracy are required for the phase shifters. Note that in dynamic phase shifter designs (such as quadrature modulators), phase accuracy is achieved by high-precision amplitude gain control in the in-phase and quadrature amplifiers.

[0005] Due to the increasing bandwidth shortage experienced by mobile carriers, unused millimeter-wave (mmWave) frequency bands around 24 GHz and 300 GHz are being explored for next-generation 5G wideband cellular communications networks. To support directional communications using narrow beams in mmWave networks, 5G base stations typically support multiple beams using phased array antennas. The sidelobes of one beam interfere with the main beam of another. To achieve the signal-to-interference ratio requirements for high-order modulation signals such as 256QAM, which allow full bandwidth use in each of the multiple beams, it is desirable to control the peak sidelobe level to below -40 dB to -45 dB. Without amplitude and phase tapering (uniform illumination), the peak antenna sidelobe is limited to below -13 dB from the main lobe.

[0006] RF amplifiers within RFICs are subject to 1) PVT variations (wafer process, power supply voltage, and temperature variations) (which can result in several dB of variation if not compensated for), and 2) random variations due to transistor or passive element size variations (this requirement is usually met by limiting the transistors, capacitors, and resistors used inside the RFIC to a minimum size). To meet high-precision requirements for amplitude tapering across the antenna array (such as 0.375 dB), it is necessary to calibrate the RFIC and amplifiers across the antenna array. To reduce manufacturing complexity and post-manufacturing antenna calibration costs, it is desirable for the RFIC to be self-calibrating by design for various manufacturing processes, be able to track the full range of different temperatures, or be calibrated during the manufacturing process by automatic test equipment. Summary of the Invention [Problem to be solved by the invention]

[0007] There is a need for a calibration method for RF amplifiers that requires high accuracy of RF amplifier gain. [Means for solving the problem]

[0008] Radio frequency (RF) amplifier designs, including RFICs implemented in CMOS, CaAs, SiGe, or other silicon processes, are subject to gain variations due to wafer process variations, temperature changes, and power supply voltage changes, as well as random variations. We propose four methods to achieve constant amplifier gain through either on-chip wafer calibration or self-calibration. The proposed methods maintain constant amplifier gain over process, temperature, and power supply voltage variations through automatic adjustment of the amplifier bias current. With proposed method 1, a constant transconductance Gm with improved gain accuracy is maintained through wafer calibration. With proposed method 2, a constant transconductance Gm is maintained through time-domain averaging across different transistors. With proposed method 3, a constant Gm*R or RF gain is maintained by taking into account the impedance of the RF amplifier's matching network. With proposed method 4, transistors are first calibrated (selected) using method 1 to reduce tolerances, and then method 3 is applied.

[0009] Other embodiments and advantages are described in the detailed description below. This summary is not intended to define the invention. The invention is defined by the claims. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a simplified block diagram of multiple phased array antennas using bias generators according to one embodiment. [Figure 2] FIG. 2 is a simplified circuit diagram of a bias generator that supports a constant gm bias used in a radio frequency amplifier in an RFIC. [Figure 3] FIG. 3 illustrates a first method for using a calibration circuit to provide a precise transistor size ratio to a bias generator. [Figure 4] FIG. 4 shows the improvement of the first method for the maximum error due to the calibration error of the transistor size. [Figure 5]FIG. 5 is a flow diagram of a first method for maintaining a constant transconductance (Gm) bias in a radio frequency integrated circuit (RFIC) according to an embodiment. [Figure 6] FIG. 6 illustrates a second method that uses time domain averaging during operation to provide a constant Gm for the bias generator. [Figure 7] FIG. 7 shows an improvement of the constant Gm bias generator by reducing the Gm interpolation error due to the nonlinearity of the IV characteristic curve. [Figure 8] FIG. 8 is a flow diagram of a second method for maintaining a constant transconductance (Gm) bias in a radio frequency integrated circuit (RFIC) according to one embodiment. [Figure 9] FIG. 9 illustrates a third method for providing a constant Gm*Requivalent or constant gain to an RF amplifier according to one embodiment. [Figure 10] FIG. 10 is a simplified circuit diagram of a bias generator that supports constant gm*R or constant gain according to the third method. DETAILED DESCRIPTION OF THE INVENTION

[0011] Reference will now be made in detail to several embodiments of the invention, examples of which are illustrated in the accompanying drawings.

[0012] 1 is a simplified block diagram of multiple phased array antennas using bias generators according to one embodiment. A beamforming cellular mobile communication network 100 includes a base station BS 101 and multiple user terminals, such as UEs 102 and 103. The cellular mobile communication network uses directional communication with narrow beams and may support multi-gigabit data rates. One example of such a cellular network is a millimeter wave (mmWave) network that utilizes the mmWave frequency band. In such mmWave networks, directional communication is achieved by beamforming, where a phased antenna array having multiple antenna elements applies multiple sets of beamforming weights (phase shift values) to form multiple beam patterns. This is required to overcome high path loss in mmWave networks and provide mobility support for UEs 102 and 103.

[0013] In the example of FIG. 1, BS 101 includes multiple phased array antennas 110 connected to a combiner / distributor network 120. In multiple array antennas operating in a high-density area, each array antenna has its own unique beam pointed toward a particular UE (direction). Radiation from the antenna sidelobes of one antenna causes interference to signals received by the UE from adjacent antennas. In the case of a multiple beam array antenna, each antenna beam is pointed toward a particular UE at a given time. Radiation from the antenna sidelobes of one antenna beam causes interference to signals received by the UE from adjacent antenna beams pointed toward a different UE.

[0014] A typical phased array antenna configuration uses multiple radio frequency integrated circuits (RFICs), such as beamforming RFICs. Each signal path of an antenna element contains a variable gain amplifier and a phase shifter. The signal from each antenna element is amplified and phase shifted by different amounts (amplitude and phase tapering) to control antenna sidelobes. For example, Chebyshev or Taylor tapering is typically used to attenuate antenna sidelobes. Therefore, calibration of the amplifier gain in the RFIC (providing consistent gain) is important to achieve precise amplitude tapering. To achieve low sidelobes, the typical required accuracy for amplitude tapering is 0.375 dB or less, and 6 or 7 bits of accuracy are required for the phase shifter.

[0015] RF amplifiers within RFICs are subject to 1) PVT variations (wafer process, power supply voltage, and temperature variations) (which can result in several dB of variation if not compensated for), and 2) random variations due to transistor or passive element size variations (this requirement is usually met by limiting the transistors, capacitors, and resistors used inside the RFIC to a minimum size). To meet high-precision requirements for amplitude tapering across the antenna array (such as 0.375 dB), it is necessary to calibrate the RFIC and amplifiers across the antenna array. To reduce manufacturing complexity and post-manufacturing antenna calibration costs, it is desirable for the RFIC to be self-calibrating by design for various manufacturing processes, be able to track the full range of different temperatures, or be calibrated during the manufacturing process by automatic test equipment.

[0016] According to one embodiment, a self-calibrating constant transconductance (Gm) bias generator is used to maintain the transconductance gain of RF amplifiers across all RFICs in the phased array antenna. In the example of FIG. 1, multiple sets of constant Gm bias generators 1, 2, 3, etc. are used to provide bias currents to the RFICs in the phased array antenna 110. Constant Gm bias circuits are widely used in many RF amplifier applications, including instrumentation amplifiers, power detector power amplifiers, and power amplifier signal backoff controls. The constant Gm is converted to a fixed current by using a voltage provided by a bandgap reference. If the Gm and reference voltage are PVT-independent, the fixed current generated using these parameters is also PVT-independent and can be used as the primary bias current for large RFICs. Note that the transistor size of the bias generator needs to replicate the transistor size used in the RF amplifier to maintain good tracking of Gm. As a result, multiple sets of constant Gm bias generators with various transistor sizes are needed for RF amplifiers with different transistor sizes across all RFICs in the phased array antenna 110.

[0017] For each constant Gm bias generator, a high-precision and temperature-stable off-chip external resistor is used as a reference, and a transistor size ratio K is used to obtain a high-precision Gm. Note that the size ratio K is critical to obtain an accurate value of Gm. In the first method, multiple transistors are included in the RFIC, (K+1) transistors with close Gm matching are selected, and one of the (K+1) transistors is selected to provide the best matching ratio K. In the second method, a high-precision clock is used to select one of the (K+1) transistors by round-robin, and an averaging circuit is used to average the current or voltage bias over (K+1) cycles. In the third method, a more accurate Gm*R is obtained by taking into account the impedance of the matching network. equivalent or provide a constant gain for the RF amplifier.

[0018] 2 is a simplified circuit diagram of a bias generator 201 that supports a constant Gm bias used for an RF amplifier in an RFIC. The bias generator 201 includes a pair of transistors M1 and M2, with the gates of M1 and M2 coupled to each other via an external resistor R EXT Transistor M1 has a size of W / L, and transistor M2 has a size of K*(W / L). m The bias is R EXT and transistor size ratio Only by K, i.e., g m =2 / R EXT *(1-1 / √K), where R EXT is a precision resistor with zero temperature coefficient. Therefore, Gm and the reference voltage are independent of PVT, and therefore the fixed current generated using these parameters is also independent of PVT, and can be used as the main bias current for large RFICs. In Figure 2, Iref1 and Iref2 are different bias current mirrors used for different RF amplifiers.

[0019] Note that the size ratio K between transistors M1 and M2 is critical to obtain an accurate value of Gm. Furthermore, transistor M1 must replicate the transistor used in the RF amplifier to maintain good tracking of Gm. Thus, using the same transistor type and size is important. As a result, transistor M2 is formed by replicating K identical transistors M1 with the same size (W / L). Furthermore, the current density of the transistor must be the same as that of the RF amplifier. Therefore, while increasing the transistor size can improve the accuracy of the size ratio K, having large-sized M1 and M2 transistors is undesirable for achieving low power consumption and a small RFIC.

[0020] Based on the above considerations, we propose four different methods to achieve a constant Gm bias generator with self-calibration to maintain the transconductance gain of RF amplifiers across all RFICs in a phased array antenna. In the first method (210), multiple transistors are included in the RFIC to optimize the best match. ratio A second method (220) uses a precision clock to select one of the (K+1) transistors in a round-robin fashion, and an averaging circuit to average the current or voltage bias over the (K+1) cycles. A third method (230) takes into account the impedance of the matching network to more accurately calculate Gm*R. equivalent or provide a constant gain for the RF amplifier across the entire RFIC. In a fourth method (240), a combination of a constant G calibration procedure (e.g., Method 1 or Method 2) and a constant gain closed loop circuit (e.g., Method 3) can be designed for the RF amplifier.

[0021] FIG. 3 illustrates a first method for providing a precise transistor size ratio K to a bias generator using a calibration circuit 301. In the embodiment of FIG. 3, calibration circuit 301 is used to select (K+1) identical transistors from N transistors in an RFIC, where N>(K+1). Each RFIC contains N identical transistors with sizes (W / L), and each transistor is tested using calibration circuit 301. The testing and selection steps are as follows: Step 1) Cycle through each of the N transistors for a gate voltage Vm and measure the drain current due to the voltage drop across an accurate precision resistor Rm. 2) For each transistor, obtain multiple points on its IV characteristic curve by varying Vm and measuring the corresponding drain current. Step 3) From the IV characteristic curves of the N transistors, obtain the same operating point for all transistors that is close to the desired Gm on the IV characteristic curve. Step 4) Select (K+1) transistors with closely matching Gm on the IV characteristic curve. Step 5) The best match is used as M1 and M2 in the constant Gm bias generator 201 of FIG. ratio Selecting 1 and K transistors with K. In one example, selecting (K+1) transistors from N transistors is done by ABS

number

[0022] 4 shows the improvement of the first method for the maximum error due to the transistor size calibration error of the bias generator 401. The first method uses 1) the transistor size ratio K (i.e., Δ) after selecting (K+1) transistors from N transistors, 2) the threshold voltage V th There is a maximum error, ε, in the error in Δ. For example, the calibrated transistor size of M2 may be (K+Δ)*(W / L). Further improvement can then be obtained by adjusting the transistor sizes in the current mirror to correct for the error caused by Δ in the size ratio K. Both Δ and ε can be obtained from IV measurements. In FIG. 4, a circuit 410 containing multiple small transistors and switches in a constant Gm bias generator 401 can be used to adjust the current mirror size to compensate for the mismatch Δ.

[0023] FIG. 5 is a flow diagram of a first method for maintaining a constant transconductance (Gm) bias in a radio frequency integrated circuit (RFIC) according to an embodiment. In step 501, a bias generator generates a bias current or voltage. The bias generator includes a first transistor (M1) and a second transistor (M2). M2 is formed by replicating the same M1 based on a size ratio K, where K is a positive integer. In step 502, the bias generator is calibrated using a calibration circuit and N transistors in the RFIC. N is a positive integer greater than (K+1), and the calibration includes selecting one transistor to be used as M1 and selecting K transistors to be used as M2. In step 503, the calibrated bias generator maintains a constant Gm bias in the RFIC.

[0024] 6 illustrates a second method that uses time-domain averaging during operation to provide a bias generator 601 with a constant Gm. The bias generator 601 includes (K+1) transistors located on either the left or right side of the bias generator. By the second method, for example, every clock cycle (e.g., 1 millisecond), one of the (K+1) transistors (M i ) is selected to operate on the left side of bias generator 601, and the remaining K transistors are selected to operate on the right side of bias generator 601, and so on, in a round-robin fashion using a precision clock. For example, in clock cycle 1, M1 is on the left side, in clock cycle 2, M2 is on the left side, and similarly, in clock cycle K+1, M K+1 is on the left side. An averaging circuit 610 is then used to calculate the gate voltage (Vref i ) is averaged. Vref average is the reference voltage resulting from averaging the constant Gm bias. Note that switches S1 through S4 are used to position each of the (K+1) transistors to operate on either the left or right side of the bias generator, for example, under the control of the bias generator's calibration engine. The second method can introduce switching noise due to time-domain averaging.

[0025] FIG. 7 illustrates an improvement to the constant Gm bias generator by reducing Gm interpolation errors due to nonlinearities in the IV characteristic curves. As depicted by the IV characteristic curve 710 of the amplifier transistor, the operating point of the desired Gm value lies between points P1 and P2. In Methods 1 and 2 described above, the same operating point (same Vm and Io) is assumed for all transistors, and the (K+1) transistors with the best matching ratios are selected, or time-domain averaging is performed. The size (W / L) of transistor M1 is equal to the size of the amplifier transistor, and the size of transistor M2 is K*(W / L). Therefore, the constant Gm circuit obtains an approximate value of Gm based on the different M1 and M2 transistor sizes, which results in an interpolation error. According to one embodiment, the Vbias voltage is used to generate offset gate voltages between the two transistors M1 and M2 by tapping a specific resistor Rext to compensate for the nonlinearities in the IV characteristic curves due to different bias voltage points. In the example of Figure 7, Vbias is used to convert the resistor Rext into two series-connected resistors, the ratio of which has an optimal value to compensate for the nonlinearity of the IV characteristic curve of the amplifier transistor.

[0026] 8 is a flow diagram of a second method for maintaining a constant transconductance (Gm) bias in a radio frequency integrated circuit (RFIC) according to one embodiment. In step 801, a bias generator generates a bias current or voltage. The bias generator includes a first transistor (M1) and a second transistor (M2), where M2 is formed by replicating the same M1 based on a size ratio K, where K is a positive integer. In step 802, a high-precision clock is used to select one transistor from the (K+1) transistors to be used as M1 and the remaining K transistors to be used as M2 every clock cycle. In step 803, an averaging circuit is used to average the bias generator bias current or voltage over (K+1) clock cycles to maintain a constant Gm bias.

[0027] FIG. 9 illustrates a constant Gm*R RF amplifier according to one embodiment. equivalent A third method of providing constant gain is shown. The RF amplifier is connected to a matching network. Note that the RF amplifier gain is determined by the product of Gm and the parallel combination of the impedance of the matching network and the output impedance of the two transistors in the RF amplifier. In Figure 9, a matching network 901 is depicted that is part of an RF amplifier 910, and Vref is supplied by a constant gain bias generator. At the center frequency of the amplifier frequency response, the reactive elements in the matching network cancel each other, leaving an equivalent load resistance Rz in the matching network. As a result, the equivalent resistance R equivalent = equivalent load resistance of the matching network (Rz) / / transistor output Rout / / other R (e.g., from the input to the next stage). For simplicity, we have assumed that the other Rs are zero, but in a practical implementation, they need to be considered in a similar manner to Rout and Rz. Therefore, the amplifier gain at the center frequency of the amplifier frequency response is Gm*R equivalent In one embodiment, compared to controlling the Gm of the RF amplifier, the Gm*R of the RF amplifier equivalent The control is more precise.

[0028] FIG. 10 shows a simplified block diagram of a constant-gain bias generator 1001 according to a third method. In one example, the constant-gain bias generator 1001 provides a constant gain to the RF amplifier 910, maintaining the drain voltage while adjusting the bias current and corresponding gate voltage until the amplifier gain is equal to a preset value. The bias generator 1001 must utilize a drain load identical to the drain load of the RF amplifier 910, e.g., the real resistance (Rz) of the LC matching network 901 in FIG. 9. The RF amplifier gain is determined by the drain load, which is composed of the amplifier transistor's output impedance Zout and the impedance of the output matching network. Ideally, the imaginary part of the drain load (composed of the output matching network impedance and the transistor output impedance) should be equal to zero at the RF amplifier tuning frequency, and only the real part of the matching network (i.e., Rz) and the real part of the transistor output impedance (i.e., Rout) are seen by the RF transistor.

[0029] Two error amplifiers using closed-loop feedback are used: 1) the upper one to generate the desired differential-mode drain voltage difference (differential gain), and 2) the lower one to generate the appropriate common-mode drain voltage. The lower common-mode feedback loop adjusts the common-mode gate bias voltage (i.e., the common-mode of Vi+, Vi-) to make the common-mode voltage of output nodes Vo+, Vo- equal to VDD. The upper differential-mode feedback loop adjusts the bias current until the differential output voltage (Vo+, Vo-) equals 2*Iref*Rout. For stability, the time constant of the upper differential loop should be 10 times slower than the time constant of the lower loop.

[0030] The differential inputs (Vi+, Vi-) are equal to a voltage of 2*Iref*Rin. The upper differential error amplifier compares (Vo+, Vo-) with 2*Iref*Rout and attempts to make them equal by adjusting the PMOS current. At balance, the differential transistor pair M1 and M2 has a differential gain equal to (Vo+ - Vo-) / (Vi+ - Vi-) = (2*Iref*Rout) / (2*Iref*Rin) = Rout / Rin. The same bias currents from M1 and M2 feed an RF differential amplifier with the same transistor sizes, i.e., the same Zo as M1 and M2, providing the same RF gain with Rz equal to the real part of the output matching network and the exact same drain load. Note that the bias currents from M1 and M2 keep the RF gain constant.

[0031] The amplifier gain is defined solely by the ratio of Rout to Rin. The resistor ratio is insensitive to wafer process, power supply voltage, and temperature. To reduce amplifier tracking error during closed-loop operation, it is desirable to use a larger differential voltage (Vi+, Vi-), but avoid a differential voltage that is so large that significant signal distortion at (Vo+, Vo-) begins to affect operation. The absolute values ​​and temperature coefficients of Iref, Rin, and Rout do not affect the accuracy of the constant gain bias; only the ratio of Rout to Rin affects the amplifier gain. This bias provides very precise gain tracking performance without requiring any high-precision elements, only matching of Rout to Rin is required.

[0032] Rz (equal to the real part of the amplifier output matching network) typically varies little across process, supply voltage, and temperature. In addition, Rz can be much larger than Rout and therefore contributes less to Requivalent. Therefore, if an external precision resistor is used for a constant-gain bias generator, the corresponding RF amplifier gain can be expected to change little with process variations, supply voltage, and temperature changes. Rz can be implemented with a precision external resistor or an on-chip poly resistor and can be fine-tuned during wafer calibration to compensate for poly sheet resistance variations and matching network variations. The optimal Rz fine-tuning setting for a particular lot can be calculated or simulated using wafer test data, such as metal sheet resistance (meaning metal thickness), poly sheet resistance, measured capacitance deviation, and measured inductance deviation.

[0033] A fourth method combines the constant Gm calibration procedure with a constant gain closed-loop circuit; for example, the constant Gm calibration circuit and the constant gain circuit can be merged by adding more switches. A fourth implementation is a combination of first using a transistor selection method such as Method 1 to select (K+1) transistors with good and consistent matching characteristics from a population of N transistors, and then using Method 3 to maintain a constant gain of the RF amplifier. The selection method can also be applied to other elements such as Rz and Rout used in the bias generator to increase accuracy.

[0034] While the present invention has been described in conjunction with specific embodiments for purposes of illustration, the invention is not limited to these descriptions. Accordingly, various modifications, adaptations, and combinations of the various features of the described embodiments may be made without departing from the scope of the invention as set forth in the claims.

Claims

1. 1. A method for maintaining constant amplifier gain in a radio frequency integrated circuit (RFIC), comprising: generating a bias current or a bias voltage by a bias generator including a first transistor (M1) and a second transistor (M2) whose size is K times the size of the first transistor (M1), where K is a positive integer, and wherein a gate of the first transistor (M1) and a gate of the second transistor (M2) are connected to an external resistor that is a high-precision resistor having a zero temperature coefficient; a high-precision clock that controls a plurality of switches included in the radio frequency integrated circuit (RFIC) and connected to N transistors, respectively, and generates a timing reference for switching, in a round-robin manner, between a transistor to be used as a first transistor and a transistor to be used as a second transistor among the N transistors, and selects one transistor to be used as the first transistor (M1) and K remaining transistors to be used as the second transistors (M2) from (K+1) transistors that are less than N, for each clock cycle for switching, in a round-robin manner, the transistors to be used, thereby making the size ratio of the first transistor (M1) to the second transistor (M2) K times; switching the first transistor over (K+1) clock cycles to average the bias current or bias voltage of the bias generator and maintain a constant amplifier gain; A method comprising:

2. 2. The method of claim 1, wherein a transconductance Gm of the radio frequency integrated circuit (RFIC) is determined by the size ratio K between the first transistor (M1) and the second transistor (M2).

3. 3. The method of claim 1 or 2, wherein the plurality of switches are switched on or off such that any one of the (K+1) transistors can be used as the first transistor (M1) and the remaining K transistors can be used as the second transistors (M2).

4. The external resistor is two resistors connected in series, 3. The method of claim 2, further comprising generating an offset gate voltage between the first transistor (M1) and the second transistor (M2) between the two series-connected resistors to compensate for an interpolation error of the transconductance Gm of the I-V characteristic curves of N transistors included in the radio frequency integrated circuit (RFIC).

5. 1. A radio frequency integrated circuit (RFIC), comprising: a bias generator, a high-precision clock, and an averaging circuit; The bias generator includes a first transistor (M1) and a second transistor (M2) whose size is K times the size of the first transistor (M1), where K is a positive integer, and the gate of the first transistor (M1) and the gate of the second transistor (M2) are connected to an external resistor that is a high-precision resistor having a zero temperature coefficient; the bias generator generates a bias current or a bias voltage; the averaging circuit is included in the radio frequency integrated circuit (RFIC), controls a plurality of switches connected to the N transistors, and switches between transistors to be used as first transistors and transistors to be used as second transistors in a round robin manner among the N transistors; the averaging circuit selects, for each clock cycle using the high-precision clock, one transistor to be used as the first transistor (M1) and the remaining K transistors to be used as the second transistor (M2) from among (K+1) transistors that are less than N, and sets a size ratio between the first transistor (M1) and the second transistor (M2) K times; The averaging circuit switches the first transistor over (K+1) clock cycles to average the bias current or bias voltage of the bias generator to maintain a constant amplifier gain of the radio frequency integrated circuit (RFIC).

6. A base station comprising a radio frequency integrated circuit according to claim 5.

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