Swapping and restoring context-specific branch predictor state on context switch in a processor

Abstract

A method for swapping and restoring context-specific branch predictor states upon a context switch within a processor includes: a branch prediction circuit within an instruction processing circuit of the processor includes a private branch prediction memory configured to store branch prediction states for the context of an executing process; the branch prediction states are accessed by the branch prediction circuit to predict the outcome of that branch instruction of the process; in certain aspects, when a context switch occurs within the processor, branch prediction states stored in the private branch prediction memory and associated with the current context to be swapped out are swapped out from the private branch prediction memory to a shared branch prediction memory; and branch prediction states previously stored (i.e., swapped out) in the shared branch prediction memory associated with the context to be swapped in for execution are restored within the private branch prediction memory for use in branch prediction.

Description

[Technical Field]

[0001] The techniques of this disclosure relate to processing instructions for execution in a computer processor ("processor"), and more particularly to branch prediction of branch instructions in a processor. [Background technology]

[0002] Microprocessors, also known as "processors," perform computational tasks for a wide range of applications. A conventional microprocessor includes a central processing unit (CPU) that includes one or more processor cores, also known as "CPU cores." The CPU executes computer program instructions ("instructions"), also known as "software instructions," to perform operations on data and generate results, which are generated values. An instruction that generates a generated value is a "producer" instruction. The generated value may then be, for example, stored in memory, provided as output to an input / output ("I / O") device, or made available (i.e., communicated) as an input value to another "consumer" instruction executed by the CPU. Thus, a consumer instruction relies on the generated value generated by the producer instruction as an input value to the consumer instruction for execution.

[0003] A processor may use instruction pipelining as a processing technique, whereby the throughput of executed computer instructions can be increased by dividing the processing of each instruction into a series of steps. These steps are performed in an execution pipeline consisting of multiple stages. Optimal processor performance may be achieved when all stages in the execution pipeline process instructions concurrently and sequentially, just as the instructions are ordered within the instruction pipeline(s). However, structural hazards may occur, preventing the next instruction from executing without leading to erroneous computational results. For example, a control hazard may occur as a result of the execution of a control flow instruction that causes a precise interrupt within the processor. One example of a control flow instruction that can cause a control hazard is a conditional branch instruction. A conditional branch instruction can redirect the flow path of instruction execution based on the result evaluated when the control branch instruction is executed. As a result, the processor must stop fetching additional instructions until the conditional control instruction is executed, resulting in reduced processor performance and increased power consumption.

[0004] One approach to maximizing processor performance involves utilizing prediction circuitry to speculatively predict the outcome of conditional branch instructions. For example, the taken path of a conditional branch instruction can be based on program history stored in a private branch prediction memory (e.g., a private branch prediction table) within the instruction pipeline. The program history can include the branch prediction history of previously executed conditional branch instructions. When the conditional branch instruction eventually reaches the execute stage of the instruction pipeline and is executed, the resulting target address of the conditional branch instruction is verified by comparing it with the target address previously predicted when the conditional branch instruction was fetched. If the predicted and actual target addresses match—that is, a correct prediction—there is no delay in instruction execution because the subsequent instructions at the target address have been correctly fetched and are already in the instruction pipeline when the conditional branch instruction reaches the execute stage of the instruction pipeline. Power consumption is also reduced because the processor does not need to stall the processing instructions following the conditional branch instruction until the conditional branch instruction is executed. Thus, performance and power consumption can be improved by employing accurate branch prediction in a processor. However, if the predicted target address and the actual target address do not match, a mispredicted branch hazard occurs in the instruction pipeline that causes a precise interrupt. As a result, a misprediction recovery process is performed, which flushes the instruction pipeline and redirects the instruction pipeline fetch unit to fetch new instructions from the target address, resulting in delays and performance degradation. Mispredictions in the processing of instructions in a processor are costly in terms of resulting delays and reduced performance. Therefore, the more accurate the branch prediction, the greater the performance and power savings that can be achieved, offsetting any performance degradation and power consumption incurred in misprediction recovery.

[0005] Generally, a branch predictor with a larger branch prediction table is more accurate because the branch predictor can store more program history for branch prediction. However, processor design and performance constraints, such as cycle time and area constraints, can limit the size of a branch predictor's branch prediction table. One way to scale up the memory size of the branch prediction table without having to allocate additional storage in the branch predictor in the instruction pipeline is to allocate additional memory for storing branch prediction history in a separate, shared, lower-level memory outside the fetch stage of the instruction pipeline. For example, a larger branch prediction memory can be allocated in the main memory or a lower-level cache memory serving the processor. A smaller branch prediction table in the instruction pipeline can serve as a cache for the branch prediction memory. The branch prediction memory is shared among different contexts for processes (e.g., threads) executing in the processor to store and access branch prediction history. Branch prediction state can be swapped in and out between the smaller branch prediction table in the branch predictor in the instruction pipeline and the branch prediction memory, such as a cache memory. Therefore, it is possible to increase the effective capacity of the branch prediction table in the branch predictor in the instruction pipeline, and to increase the branch prediction accuracy without the need to increase the branch prediction table in the branch predictor.

[0006] However, providing a larger shared branch prediction memory capacity exposes the applications to security vulnerabilities because it can be a source of leaked information about applications running in the processor. For example, a malicious attacker application running in the processor can prime the branch predictor and set the branch prediction history to a predefined state. Later, when a victim application is executed, the predefined branch prediction history state primed by the attacker application in the shared branch prediction memory is cached in the branch prediction table of the branch predictor, affecting the victim application's speculative execution path. The victim application then causes some of the branch prediction entries in the branch prediction table to be updated and / or evicted to the shared branch prediction memory. Thus, when the attacker application resumes execution, it can access the shared branch prediction memory to detect changes in the branch prediction state as a result of the victim application's execution and extract this information about the victim application. Branch prediction can be disabled to avoid such security vulnerabilities, but this prevents the performance benefits of branch prediction. An alternative solution to prevent this security vulnerability could be to flush the branch prediction memory upon each context switch, thereby preventing the leakage of branch prediction history updates caused by the executing application. However, this means that the branch predictor must be retrained after each context switch, resulting in a decrease in branch prediction accuracy during training. Summary of the Invention [Means for solving the problem]

[0007] Aspects disclosed herein include swapping and restoring context-specific branch predictor state upon a context switch within a processor. A context is a minimal set of data used by a process of an application ("process") executing within a processor of a central processing unit (CPU) that is saved so that the task can be interrupted and later executed from the same interruption point. A context switch stores the state of the context for the interrupted process so that it can be later restored, allowing execution of the process to resume from the same point in the processor. Context switching allows multiple processes to share a single processor. In this regard, the processor includes an instruction processing circuit including several instruction processing stages configured to pipeline the processing and execution of fetched instructions according to dataflow execution. The instruction processing circuit includes a fetch circuit within a fetch stage configured to fetch instructions from an instruction memory to be inserted into the instruction pipeline for execution. The branch prediction circuit is configured to speculatively predict the outcome of a fetched branch instruction (e.g., a conditional branch instruction, an indirect branch instruction, or a return branch instruction), which is used to determine the next instruction to be fetched into the instruction pipeline by the fetch circuit. The branch prediction circuitry is configured to access the branch prediction state to speculatively predict the outcome of a branch instruction.

[0008] In example aspects disclosed herein, the branch prediction circuitry includes a private branch prediction memory (e.g., a branch prediction table circuit) configured to store branch prediction state for the context of a currently executing process (the “current context”), which is used to predict the outcome of branch instructions in the current context being executed. The private branch prediction memory is affected only by the current context, not the contexts of other processes not currently executing. When a context switch occurs in the processor, the branch prediction state stored in the private branch prediction memory and associated with the current context to be swapped out is swapped out from the private branch prediction memory to the shared branch prediction memory. The shared branch prediction memory is a shared structure configured to store branch prediction state for multiple contexts for multiple executing processes. For example, the shared branch prediction memory may be outside the instruction processing circuitry, such as in a cache memory or main memory associated with the processor. The branch prediction state previously stored (i.e., swapped out) in the shared branch prediction memory associated with the context to be swapped in is restored in the private branch prediction memory used for branch prediction during execution of the process associated with the context being swapped in. Upon further context changes, the associated branch prediction state in the shared branch prediction memory for the newly swapped-in context is restored into the private branch prediction memory, and the branch prediction state in the private branch prediction memory for the currently swapped-out context is stored into the shared branch prediction memory.

[0009] In this way, the branch prediction history for a process's current context is preserved and not lost when that context is swapped out of the instruction processing circuitry and later swapped back in for use in the execution of its associated process. The size of the private branch prediction memory can be used only to store the branch prediction state of the current context, effectively increasing the size of the branch predictor circuitry for more accurate branch predictions, rather than sharing the private branch prediction memory among multiple different contexts. Also, because the shared branch prediction memory can store branch prediction state for multiple specific shared contexts, flushing of the shared branch prediction memory is not required upon context switching to avoid leaking information about the victim process context by the attacker process. Thus, for example, if an attacker process primes branch prediction state in the private branch prediction memory and then a victim process is swapped in for execution on behalf of the attacker process, the primed branch prediction state is not used to predict branch instructions in the victim process. The branch prediction state for the attacker process is swapped out to the shared branch prediction memory, and the previously stored branch prediction state for the victim process is swapped in to the private branch prediction memory. Thus, when the attacker process is swapped in, the previously primed branch prediction history is restored in the private branch prediction memory instead of the victim process's context branch prediction history, and the victim application is not affected by the primed branch prediction state associated with the attacker process. Thus, the attacker process cannot detect how the victim process was executed based on how its execution affected the primed branch prediction state by the victim process execution.

[0010] In this regard, one exemplary aspect provides a branch prediction circuit having a private branch prediction memory configured to store at least one branch prediction state for a current context of a current process executing in an instruction processing circuit of a processor. The branch prediction circuit is configured to speculatively predict an outcome of a branch instruction in the current process executing in the instruction processing circuit based on a branch prediction state among the at least one branch prediction state for the current context in the private branch prediction memory associated with the branch instruction. The branch prediction circuit is also configured to receive a process identifier identifying a new context swapped into the instruction processing circuit. In response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuit, the branch prediction circuit is also configured to store at least one branch prediction state associated with the new context as the at least one branch prediction state in the private branch prediction memory.

[0011] In another exemplary aspect, a method for predicting a branch outcome of a branch instruction for a context executed within an instruction processing circuit of a processor is provided. The method includes speculatively predicting an outcome of a branch instruction in a current process executed within the instruction processing circuit based on a branch prediction state among at least one branch prediction state of a current context of the current process in a private branch prediction memory associated with the branch instruction, the private branch prediction memory being configured to store at least one branch prediction state for the context of the current process to be executed within the instruction processing circuit of the processor. The method also includes receiving a process identifier identifying a new context swapped into the instruction processing circuit. The method also includes determining whether the process identifier indicates a new context that is different from the current context swapped into the instruction processing circuit. The method also includes storing at least one branch prediction state associated with the new context as at least one branch prediction state in the private branch prediction memory in response to the process identifier indicating a new context that is different from the current context swapped into the instruction processing circuit.

[0012] In another exemplary aspect, a processor-based system is disclosed. The processor-based system includes a processor. The processor has an instruction processing circuit including one or more instruction pipelines, each including a fetch circuit, a branch prediction circuit, and an execution circuit. The fetch circuit is configured to fetch a plurality of instructions from a memory into an instruction pipeline of the one or more instruction pipelines executed by the execution circuit. The instruction processing circuit also includes a branch prediction circuit having a private branch prediction memory configured to store at least one branch prediction state for a current context to be executed in the instruction processing circuit of the processor. The branch prediction circuit is configured to speculatively predict the outcome of a branch instruction in a current process executed by the instruction processing circuit based on a branch prediction state in the at least one branch prediction state in the current context in the private branch prediction memory associated with the branch instruction. The instruction processing circuit is configured to receive a process identifier identifying a new context swapped into the instruction processing circuit, and, in response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuit, store at least one branch prediction state associated with the new context as at least one branch prediction state in the private branch prediction memory. The processor also has a shared branch prediction memory configured to store at least one branch prediction state associated with a context among each of a plurality of contexts associated with each process configured to execute in the instruction processing circuitry.

[0013] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in connection with the accompanying drawings. [Brief explanation of the drawings]

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0015] [Figure 1] 1 is a diagram of an exemplary processor-based system including a processor having instruction processing circuitry including one or more instruction pipelines for processing computer instructions for execution, the instruction processing circuitry configured to retrieve branch prediction state associated with a context being swapped in from a shared branch prediction memory, and swap in and restore the retrieved branch prediction state into a private branch prediction memory for the branch prediction circuitry for use for branch prediction in execution of a process associated with the swapped-in context.

[0016] [Figure 2] 2 is a flowchart illustrating exemplary processing of the instruction processing circuit of FIG. 1;

[0017] [Figure 3] FIG. 1 illustrates a branch prediction memory including a statically partitioned memory configured to store branch prediction state for each context and a non-partitioned memory configured to store branch prediction state for a current context of a currently executing process.

[0018] [Figure 4] 10 is a flowchart illustrating an alternative exemplary operation of the instruction processing circuit of FIG. 1 in response to a context switch, where the branch prediction state associated with the swapped-in context is partially swapped from a shared branch prediction memory to a private branch prediction memory for use for branch prediction in the execution of a process associated with the swapped-in context.

[0019] [Figure 5]1 is a diagram of an alternative processor-based system including instruction processing circuitry configured to, in response to a context switch, temporarily use an alternative branch prediction scheme until a swap of the swapped-in context has completed swapping in and restoring retrieved branch prediction state from a shared branch prediction memory to a private branch prediction memory for use in branch prediction in the execution of a process associated with the swapped-in context.

[0020] [Figure 6] 6 is a flowchart illustrating exemplary processing of the instruction processing circuit of FIG. 5.

[0021] [Figure 7] FIG. 10 is a diagram of another alternative exemplary processor-based system including a processor having instruction processing circuitry including one or more instruction pipelines for processing computer instructions for execution, the instruction processing circuitry including primary and secondary branch prediction circuits configured to store respective branch prediction states for a current context and a branch prediction state for another next context that is likely to be swapped in after the current context, the instruction processing circuitry configured to retrieve branch prediction states associated with the next context from a shared branch prediction memory and swap in and restore the retrieved branch prediction states in a private branch prediction memory of the secondary branch prediction circuit so that when swapped in for the current context, they are ready for use for branch prediction in execution of a process associated with the next context.

[0022] [Figure 8A] 8 is a first half of a flowchart illustrating exemplary processing of the instruction processing circuit of FIG. 7. [Figure 8B] 8 is a second half of a flowchart illustrating exemplary processing of the instruction processing circuit of FIG. 7.

[0023] [Figure 9]1 is a block diagram of an exemplary processor-based system including a processor having instruction processing circuitry including branch prediction circuitry for predicting outcomes of branch instructions, the instruction processing circuitry configured to retrieve branch prediction state associated with a context being swapped in from a shared branch prediction memory and swap in and restore the retrieved branch prediction state to a private branch prediction memory for the branch prediction circuitry to be used for branch prediction in execution of the context being swapped in, including but not limited to the instruction processing circuits of FIGS. 1, 5, and 7. DETAILED DESCRIPTION OF THE INVENTION

[0024] Aspects disclosed herein include swapping and restoring context-specific branch predictor state upon a context switch within a processor. A context is a minimal set of data used by a process of an application ("process") executing within a processor of a central processing unit (CPU) that is saved so that the task can be interrupted and later executed from the same interruption point. A context switch stores the state of the context for the interrupted process so that it can be later restored, allowing execution of the process to resume from the same point in the processor. Context switching allows multiple processes to share a single processor. In this regard, the processor includes an instruction processing circuit including several instruction processing stages configured to pipeline the processing and execution of fetched instructions according to dataflow execution. The instruction processing circuit includes a fetch circuit within a fetch stage configured to fetch instructions from an instruction memory to be inserted into the instruction pipeline for execution. The branch prediction circuit is configured to speculatively predict the outcome of a fetched branch instruction (e.g., a conditional branch instruction, an indirect branch instruction, or a return branch instruction), which is used to determine the next instruction to be fetched into the instruction pipeline by the fetch circuit. The branch prediction circuitry is configured to access the branch prediction state to speculatively predict the outcome of a branch instruction.

[0025] In example aspects disclosed herein, the branch prediction circuitry includes a private branch prediction memory (e.g., a branch prediction table circuit) configured to store branch prediction state for the context of a currently executing process (the “current context”), which is used to predict the outcome of branch instructions in the current context being executed. The private branch prediction memory is affected only by the current context, not the contexts of other processes not currently executing. When a context switch occurs in the processor, the branch prediction state stored in the private branch prediction memory and associated with the current context to be swapped out is swapped out from the private branch prediction memory to the shared branch prediction memory. The shared branch prediction memory is a shared structure configured to store branch prediction state for multiple contexts for multiple executing processes. For example, the shared branch prediction memory may be outside the instruction processing circuitry, such as in a cache memory or main memory associated with the processor. The branch prediction state previously stored (i.e., swapped out) in the shared branch prediction memory associated with the context to be swapped in is restored in the private branch prediction memory used for branch prediction during execution of the process associated with the context being swapped in. Upon further context changes, the associated branch prediction state in the shared branch prediction memory for the newly swapped-in context is restored into the private branch prediction memory, and the branch prediction state in the private branch prediction memory for the currently swapped-out context is stored into the shared branch prediction memory.

[0026] In this way, the branch prediction history for a process's current context is preserved and not lost when that context is swapped out of the instruction processing circuitry and later swapped in for use in the execution of its associated process. The size of the private branch prediction memory can be used only to store the branch prediction state for the current context, effectively increasing the size of the branch predictor circuitry for more accurate branch predictions, rather than sharing the private branch prediction memory among multiple different contexts. Also, because the shared branch prediction memory can store branch prediction state for multiple specific shared contexts, flushing of the shared branch prediction memory upon context switching is not required to avoid the attacker process leaking information about the victim process context. Thus, for example, if an attacker process primes branch prediction state in the private branch prediction memory and then a victim process is swapped in for execution on behalf of the attacker process, the primed branch prediction state is not used to predict branch instructions in the victim process. The branch prediction state for the attacker process is swapped out to the shared branch prediction memory, and the previously stored branch prediction state for the victim process is swapped in to the private branch prediction memory. Thus, when the attacker process is swapped back in, the previously primed branch prediction history is restored in the private branch prediction memory instead of the victim process's context branch prediction history, and the victim process is not affected by the primed branch prediction state associated with the attacker process. Thus, the attacker process cannot detect how the victim process has executed based on how its execution has affected the primed branch prediction state.

[0027] In this regard, FIG. 1 is a diagram of an exemplary processor-based system 100 including a processor 102. The processor 102 may be an in-order or out-of-order processor (OoP). The processor 102 may also be referred to as a "processor core" or a "central processing unit (CPU) core," and the processor-based system 100 may include multiple processors 102. In this example, the processor 102 includes one or more instruction pipelines I0-I1 for processing fetched computer instructions 106F fetched by a fetch circuit 108 for execution. N The processor 102 includes an instruction processing circuit 104 including a fetch circuit 108 configured to fetch instructions 106 from an instruction memory 110. The instruction memory 110 may, by way of example, be provided within or as part of a system memory within the processor-based system 100. To reduce latency in the fetch circuit 108, an instruction cache 112 may also be provided within the processor 102 for caching instructions 106 fetched from the instruction memory 110. The fetch circuit 108 in this example passes instructions 106 as fetched instructions 106F down one or more instruction pipelines I0-I1 as an instruction stream 114 within the instruction processing circuit 104 to be pre-processed before the fetched instructions 106F reach the execution circuit 116 for execution. N The fetched instructions 106F in the instruction stream 114 include producer instructions and consumer instructions that consume values ​​generated as a result of the instruction processing circuit 104 executing the producer instructions. N are provided through various processing circuits or stages of the instruction processing circuitry 104 to pre-process and process the fetched instructions 106F in a series of steps that can be performed in parallel to increase throughput, prior to execution of the fetched instructions 106F by the execution circuitry 116.

[0028] 1, instruction processing circuitry 104 includes decode circuitry 118 configured to decode fetched instruction 106F, fetched by fetch circuitry 108, into decoded instruction 106D to determine the instruction type and required action. The instruction type and required action encoded in decoded instruction 106D determine which instruction pipeline 100-1000 the decoded instruction 106D is to be sent to. N In this example, the decoded instruction 106D is placed in the instruction pipeline I0-I1. N , ..., PRF) 126. The renaming circuit 120 is configured to determine whether any registers in the decoded instruction 106D need to be renamed to break register dependencies that prevent parallel or out-of-order processing. The renaming circuit 120 renames logical source register operands and / or destination register operands of the decoded instruction 106D to available physical registers 124(1) through 124(X) (P0, P1, ..., PRF) in a physical register file (PRF) 126. X ), the RMT 122 includes a plurality of mapping entries, each of which corresponds to a respective logical register R0-R1. P The mapping entries are configured to store information in the form of address pointers that point to physical registers 124(1)-124(X) in physical register file (PRF) 126. Each physical register 124(1)-124(X) in PRF 126 includes a data entry configured to store data for source and / or destination register operands of decoded instruction 106D.

[0029] 1 also includes a register access (RACC) circuit 128. The register access circuit 128 accesses the logical registers R0-R1 in the RMT 122 of the source register operands of the decoded instruction 106D. P The register access circuit 128 is also configured to provide the retrieved generated value from the executed decoded instruction 106E as a source register operand of the decoded instruction 106D to be executed. Also, in the instruction processing circuit 104, the scheduler circuit 130 schedules the instruction pipelines I0 to I1. N The scheduler circuit 130 may be configured to store the decoded instruction 106D in a reservation entry until all source register operands for the decoded instruction 106D are available. For example, the scheduler circuit 130 may schedule the decoded consumer instruction 106D to be sent to issue lanes L0-L1 of the "K" issue lanes. K-1 The scheduler circuit 130 is responsible for determining that required values ​​for operands of the decoded consumer instruction 106D are available before issuing the decoded instruction 106D to the execution circuit 116 for execution in the PRF 126. The scheduler circuit 130 issues the decoded instruction 106D that is ready to be executed to the execution circuit 116. A write circuit 132 is also provided within the instruction processing circuit 104 for writing back or committing generated values ​​from the executed instruction 106E to memory, such as the PRF 126, cache memory, or system memory.

[0030] 1, instruction processing circuitry 104 also includes branch prediction circuitry 134. Branch prediction circuitry 134 is configured to speculatively predict the outcome of fetched branch instructions 106F, which determines whether a taken or not taken path within the instruction control flow path of instruction stream 114 will be selected for execution in instruction pipelines I0-I1. N For example, branch instruction 106F may be a conditional branch instruction that includes a condition to be resolved by instruction processing circuitry 104 to determine which control flow path within instruction stream 114 to take. Thus, in this example, the outcome of fetched branch instruction 106F as a conditional branch instruction does not need to be resolved in execution by execution circuitry 116 before instruction processing circuitry 104 can continue processing fetched instruction 106F. The prediction made by branch prediction circuitry 134 can be provided as prediction information 135 by fetch circuitry 108 to be used by fetch circuitry 108 to determine the next instruction 106 to fetch as fetched instruction 106F. Other examples of branch instructions 106F that may be fetched include indirect branch instructions and return branch instructions. In this example, branch prediction circuitry 134 makes speculative predictions for branch instructions 106F based on branch prediction states stored in private branch prediction memory 136. As explained in more detail below, private branch prediction memory 136 is affected only by the context of the current process executing in instruction processing circuitry 104, and not by the context of other processes that are not currently executing.

[0031] Private branch prediction memory 136 is configured to store branch prediction states 138(0)-138(B), which in this example are "B+1" branch prediction states. For example, private branch prediction memory 136 may be a branch prediction table circuit 140 including a plurality of indexable entries 141(0)-141(B) configured to store corresponding branch prediction states 138(0)-138(B). Branch prediction circuit 134 is configured to speculatively predict the outcome of fetched branch instruction 106F based on the retrieved branch prediction states 138(0)-138(B) from private branch prediction memory 136. Fetch circuit 108 fetches instruction pipelines I0-I1. N For example, if the outcome prediction for branch instruction 106F made by branch prediction circuit 134 is that branch instruction 106F will resolve to a taken instruction flow path, branch prediction circuit 134 provides this prediction information 135 to fetch circuit 108, which in turn fetches instructions 106 from the branched instruction flow path into instruction pipelines I0-I1. N However, if the prediction made by branch prediction circuit 134 is that branch instruction 106F will resolve to a branched instruction flow path, branch prediction circuit 134 still provides this prediction information 135 to fetch circuit 108, which then fetches instructions 106 from the branched instruction flow path into instruction pipelines I0-I1. N If the prediction is determined to be a misprediction once the branch instruction 106F is executed in the execution circuitry 116 to resolve the condition, the instructions 106 fetched into the instruction processing circuitry 104 from the incorrect instruction flow path can be flushed and instructions 106 from the correct instruction flow path can be fetched.

[0032] As an example, branch prediction states 138(0)-138(B) may include bits that use a logic state '0' to indicate a not-taken branch state and a logic state '1' to indicate a taken branch state. Branch prediction table circuit 134 may be configured to store static states as branch prediction states 138(0)-138(B) in branch prediction table circuit 140 that are not dynamically changed based on the execution of instruction 106F. Alternatively, branch prediction circuit 134 may be configured to update branch prediction states 138(0)-138(B) in branch prediction circuit 140 based on the history of the execution of instruction 106F. For example, branch prediction states 138(0)-138(B) may be updated based on the history of resolved states of branch instruction 106F executed in execution circuit 116. Thus, with a larger number of branch prediction states 138(0)-138(B), more specific historical information about branch instructions can be stored, thereby improving branch prediction accuracy.

[0033] The processor 102 of FIG. 1 may be a multitasking processor capable of swapping in and out running processes (e.g., threads) executing in the instruction processing circuit 104. Context information, referred to as a “context,” is information used and updated by the instruction processing circuit 104 during process execution. For example, the context may include data stored in the RMT 122 and / or PRF 126, the state of flags, and the branch prediction states 138(0) through 138(B) stored in the branch prediction table circuit 140 when a process executes in the instruction processing circuit 104. The context in the processor 102 is a minimal set of data used by a process executing in the processor 102 that is saved to allow a task to be interrupted and later executed from the same interruption point. Thus, a context switch is performed by the processor 102 when a new next process is swapped into the instruction processing circuit 104 to execute in place of the currently executing process. Context switching allows multiple processes to share the processor 102. A context switch is when the processor stores the context for a suspended current process that is swapped out of the instruction processing circuitry 104 to make way for a new next process, the context is restored, and execution of the previous current process can resume within the processor 102 from the same suspension point. Thus, a context switch involves restoring the context of the next process that was swapped in to the instruction processing circuitry 104 to be executed, and then swapping in the next process itself.

[0034] In this example of processor 102 of FIG. 1 , private branch prediction memory 136 of branch prediction circuit 134 is desirably sized to store a desired number of branch prediction states 138(0) through 138(B) to provide a desired level of prediction accuracy, within the design and performance constraints of processor 102. For example, processor 102 may be constrained by cycle time and area constraints that may limit the size of private branch prediction memory 136 within branch prediction circuit 134. One way to scale up the memory size of private branch prediction memory 136 to improve branch prediction accuracy without having to increase storage within branch prediction circuit 134 is to allocate additional memory for storing branch prediction states in a separate, shared memory. In this regard, as shown in FIG. 1 , processor-based system 100 includes shared branch prediction memory 142. In this example, shared branch prediction memory 142 is external to branch prediction circuit 134 so as not to consume area of ​​branch prediction circuit 134 and / or its private branch prediction memory 136. The shared branch prediction memory 142 may be located external to the instruction processing circuitry 104. For example, the shared branch prediction memory 142 may be located within a cache memory (e.g., an L1 cache) including, but not limited to, within the processor 102, a cache (e.g., an L3 cache) external to the processor 102, or main memory (e.g., double data rate random access memory (RAM) (DDRAM)) of the processor-based system 100. The shared branch prediction memory 142 is sized to store multiple contexts 144(0)-144(C) for different processes that executed within the processor 102 but may be swapped into the instruction processing circuitry 104 for further execution. Each context 144(0)-144(C) is configured to store a plurality of branch prediction states 146(0)(0)-146(C)(B) in a corresponding plurality of entries 148, where 'S' may be equal to 'B' due to the capacity of the branch prediction states 138(0)-138(B) in the private branch prediction memory 136.

[0035] In this example, when a process swap occurs, the instruction processing circuit 104 receives a process identifier (ID) 150 that identifies a new context for a new process swapped into the instruction processing circuit 104 for execution. By way of example, the process ID 150 identifies the next context to be swapped into the instruction processing circuit 104, where the process ID 150 identifies a process that can be associated with that context, or the process ID 150 can be used to identify the context. For example, an operating system (OS) executing on the processor 102 can control the process swap and generate the process ID 150. The process ID 150 indicates a process swap if the process ID is different from the process currently executing in the instruction processing circuit 104. In this example, when a context switch occurs within processor 102 in response to process ID 150 indicating a new swapped-in process that is different from the current process executing in instruction processing circuitry 104, instruction processing circuitry 104 is configured to swap in branch prediction state 146(0) through 146(0)(B) from shared branch prediction memory 142 into private branch prediction memory 136 for the context associated with the swapped-in process to be executed. Similarly, to preserve current branch prediction state 138(0) through 138(B) in private branch prediction memory 136 for the swapped-out process, instruction processing circuitry 104 is configured to first swap out branch prediction state 138(0) through 138(B) from private branch prediction memory 136 into its reserved context 144(0) through 144(C) in shared branch prediction memory 142. In this manner, the branch prediction circuitry 134 uses the restored branch condition state 146()(0) through 146()(B) for the new process being swapped in for execution to speculatively predict branch instruction 106F.However, the previous branch condition states 138(0)-138(B) for the swapped-out process are not lost but are stored in its reserved context 144(0)-144(C) in the shared branch prediction memory 142. When a swapped-out process is swapped back into the instruction processing circuit 104, the stored branch condition states 146()(0)-146()(B) for the previously swapped-out process can be swapped back in as the current branch prediction states 138(0)-138(B) in the private branch prediction memory 136 for use by the branch prediction circuit 134 in its execution. This is in contrast to flushing the branch prediction states 138(0)-138(B) in the private branch prediction memory 136, which deletes the branch prediction history for the swapped-in context and causes the branch prediction circuit 134 to retrain its branch predictions for the swapped-in process through updates to the flushed private branch prediction memory 136.

[0036] In this way, the size of the private branch prediction memory 136 is The shared branch prediction memory 142 can be used only to store branch prediction state 138(0)-138(B) of the current context for the currently executing process, effectively increasing the size of the branch predictor circuit 134 for more accurate branch predictions, rather than sharing private branch prediction memory 136 among multiple different contexts. Also, because the shared branch prediction memory 142 can store branch prediction state 144(0)(0)-144(C)(B) for multiple specific shared contexts 144(0)-144(C), flushing of the shared branch prediction memory 142 upon context switching is not required to avoid leaking information about the victim process context by the attacker process. Thus, for example, if an attacker process primes branch prediction state 138(0)-138(B) in private branch prediction memory 136 and then a victim process is swapped into instruction processing circuit 104 for execution on behalf of the attacker process, the primed branch prediction state 138(0)-138(B) will not be used to predict branch instructions in the victim process. Branch prediction state 138(0)-138(B) for the attacker process is swapped out to shared branch prediction memory 142, and previously stored branch prediction state 146(0)(0)-146(C)(B) of the victim process's specific context 144(0)-144(C) is swapped back into private branch prediction memory 136. Thus, when the attacker process is swapped back in, the previously primed branch prediction history 138(0)-138(B) is restored in private branch prediction memory 136 instead of the branch predictions of the victim process, and the victim application is not affected by the primed branch prediction state 138(0)-138(B) associated with the attacker process. Thus, the attacker process cannot detect how the victim process will execute based on how its execution has affected the primed branch prediction state 138(0)-138(B) by the victim process execution.

[0037] 2 is a flowchart illustrating an example process 200 of the branch prediction circuit 134 in the instruction processing circuit 104 of FIG. 1 configured to swap in a context from the shared branch prediction memory 142 to the private branch prediction memory 136 in lieu of swapping out a context from the private branch prediction memory 136 to the shared branch prediction memory 142. This process 200 of FIG. 2 is described below in connection with the instruction processing circuit 104 of FIG. 1. In this regard, the branch prediction circuit 134 speculatively predicts the outcome of a branch instruction 106F in a current process executing in the instruction processing circuit 104 (block 202 of FIG. 2). The speculative prediction is based on the accessed associated branch prediction state 138(0)-138(B) in the private branch prediction memory 136 for the context associated with the branch instruction 106F in the current process executing in the instruction processing circuit 104 (block 202 of FIG. 2). As previously mentioned, the private branch prediction memory 136 is configured to store branch prediction states 138(0)-138(B) for the current context of the current process executing on the instruction processing circuitry 104 of the processor 102.

[0038] Continuing with FIG. 2 , the branch prediction circuit 134 receives a process ID 150 identifying a new context that has been or will be swapped into the instruction processing circuit 104 (block 204 of FIG. 2 ). This indicates a context switch. The branch prediction circuit 134 determines whether the process ID 150 indicates a new context that is different from the current context swapped into the instruction processing circuit 104 (block 206 of FIG. 2 ). In response to the process ID 150 indicating a new context that is different from the current context swapped into the instruction processing circuit 104 (block 208 of FIG. 2 ), the branch prediction circuit 134 stores branch prediction states 146()(0) through 146()(B) associated with the new contexts 144(0) through 144(C) in branch prediction states 138(0) through 138(B) of the private branch prediction memory 136 (block 210). Also, in response to process ID 150 indicating a new context that is different from the current context swapped in to instruction processing circuitry 104, branch prediction circuitry 134 swaps out branch prediction states 138(0)-138(B) in private branch prediction memory 136 for the current context and stores them as branch prediction states 146()(0)-146()(B) for that context 144(0)-144(C) in shared branch prediction memory 142 (block 212 of FIG. 2).

[0039] In this way, as described above, the branch prediction circuitry 134 for the process does not need to be retrained. Branch prediction circuit 134 can access branch prediction state 138(0)-138(B) in private branch prediction memory 136 for the context of the currently executing process. Also, shared branch prediction memory 142 is sized to store branch prediction state 146(0)(0)-146(C)(B) for a specific, different context, eliminating the need to flush shared branch prediction memory 142 after a context switch because a process cannot affect the context and associated branch prediction state of another process. For comparison, FIG. 3 illustrates branch prediction memory 302, which stores branch prediction state used for branch prediction by branch prediction circuit 300. Branch prediction memory 302 is divided into two categories of memory: statically partitioned branch prediction memory 304 and dynamic branch prediction memory 306. Static partitioned branch prediction memory 304 may be local to branch prediction circuit 300, while dynamic branch prediction memory 306 may be stored in a separate memory. The statically partitioned branch prediction memory 304 includes one or more branch prediction tables 307(0)-307(T), which are partitioned into memory segments 308(1)-308(X), providing isolation between the contexts of running processes and preventing one process from affecting the context of another, as discussed above for security reasons. The dynamic branch prediction memory 306 includes one or more unpartitioned branch prediction tables 310(0)-310(T), which are used and available to store and update prediction state for currently running processes to provide additional branch prediction state capacity to the statically partitioned branch prediction memory 304. However, the dynamic branch prediction memory 306 is not partitioned and is flushed upon context switch to prevent leakage. The statically partitioned branch prediction memory 304 is a smaller memory structure that prevents leakage by being partitioned by context, but with reduced prediction accuracy without the use of the dynamic branch prediction memory 306.However, the dynamic branch prediction memory 306 being flushed upon a context switch causes the branch prediction training (i.e., history) for the context of the process being swapped out to be lost.

[0040] Referring back to FIG. 1 , in response to a context switch, the instruction processing circuitry 104 and the branch prediction circuitry 134 may be configured to swap out each branch prediction state 138(0)-138(B) in the private branch prediction memory 136 to the shared branch prediction memory 142 and swap in each branch prediction state 146()(0)-146()(B) for the context being swapped in from the shared branch prediction memory 142 to the private branch prediction memory 136 before making a speculative prediction for the branch instruction 106F. However, this may delay instruction processing because the swap-in procedure of the new context into the private branch prediction memory 136 may not be completed before the branch instruction 106F is fetched for the process associated with that context. In this regard, to avoid delaying the processing of branch instructions 106F that may follow a context switch, a “lazy” swapping procedure may be employed such that the outcome of the branch instruction 106F can be speculatively predicted before the swap-in of the new context is completed.

[0041] For example, FIG. 4 is a flowchart illustrating an alternative exemplary process 400 for partially swapping in and restoring branch prediction states 138(0)-138(B) from shared branch prediction memory 142 to private branch prediction memory 136, while still allowing branch prediction circuit 134 to make branch predictions based on the partial restoration of branch prediction states 138(0)-138(B). Process 400 of FIG. 4 may continue from process 200 of FIG. 2, for example, and may begin after the process of swapping in and out branch prediction states in blocks 210 and 212 of FIG. 2 has begun. In this regard, as shown in FIG. 4, branch prediction circuit 134 is configured to determine whether the swapping-in and storing of branch prediction states 146()(0)-146()(B) in shared branch prediction memory 142 for the context being swapped in to private branch prediction memory 136 is complete (block 402 of FIG. 4). In response to determining that the storage of branch prediction states 146()(0)-146()(B) from the shared branch prediction memory 142 to the private branch prediction memory 136 is not complete (block 404 of FIG. 4), the branch prediction circuit 134 is configured to speculatively predict the outcome of the branch instruction 106F in the swapped-in current process executing in the instruction processing circuit 104 based on the alternative branch prediction state (block 406 of FIG. 4). For example, the branch prediction circuit 134 can be configured to speculatively predict the outcome of the fetched branch instruction 106F in the swapped-in current process executing in the instruction processing circuit 104 before the storage of branch prediction states 146()(0)-146()(B) from the shared branch prediction memory 142 to the private branch prediction memory 136 is complete based on a static branch prediction state, such as always taken or not taken.

[0042] However, in response to determining that the storage of branch prediction states 146()(0)-146()(B) from the shared branch prediction memory 142 to the private branch prediction memory 136 is complete (block 408 of FIG. 4), the branch prediction circuitry 134 may be configured to speculatively predict the outcome of branch instruction 106F in the swapped-in current process being executed in the instruction processing circuitry 104 using the branch prediction states 146()(0)-146()(B) from the shared branch prediction memory 142, which are stored as branch prediction states 138(0)-138(B) in the private branch prediction memory 136 as described above (block 410 of FIG. 4).

[0043] 4, in another "lazy" swapping method, branch prediction circuit 134 stores only a subset or less than all of the prediction states 146()(0) through 146()(B) associated with new context 144(0) through 144(C) in branch prediction states 138(0) through 138(B) in private branch prediction memory 136, rather than completely storing all of the branch prediction states 146()(0) through 146()(B) in private branch prediction memory 136. Branch prediction circuit 134 can also be configured to store only a subset or less than all of the prediction states 138(0) through 138(B) associated with the current context in shared branch prediction memory 142. This allows branch prediction circuit 134 to speculatively predict the outcome of branch instruction 106F without having to swap in and out all branch prediction states for the current and new contexts. The branch prediction circuitry 134 may be configured to swap in branch prediction states 146()(0) through 146()(B) from a private branch prediction memory 136 that is more likely to provide an accurate branch prediction for the branch instruction 106F.

[0044] Alternatively, the branch prediction circuitry 134 can be configured to speculatively predict the outcome of a branch instruction 106F in a swapped-in current process being executed within the instruction processing circuitry 104 based on the branch prediction state in a separate, dedicated branch prediction memory before the branch prediction states 146()(0) through 146()(B) from the shared branch prediction memory 142 have been stored in the private branch prediction memory 136. This is illustrated in the processor-based system 500 of FIG. 5. The processor-based system 500 of FIG. 5 includes the same processor 102 as the processor-based system 100 of FIG. 1, and like components between the processor-based system 100 of FIG. 1 and the processor-based system 500 of FIG. 5 are indicated with common element numbers. The previous description of these elements with respect to FIG. 1 is applicable to FIG. 5 and will not be described again.

[0045] As shown in FIG. 5, the processor-based system 500 includes a shared branch prediction memory 542 similar to the shared branch prediction memory 142 of FIG. 1. The shared branch prediction memory 542 is sized to store multiple contexts 544(0)-544(C) for different processes executed within the processor 102, which may be swapped into the instruction processing circuit 104 for further execution. Each context 544(0)-544(C) is configured to store multiple branch prediction states 546(0)-546(B) within a corresponding number of entries 148, due to the capacity of the branch prediction states 138(0)-138(B) within the private branch prediction memory 136. The shared branch prediction memory 542 also includes a dedicated branch prediction memory 502 configured to store multiple branch prediction states 546(0)-546(B) in respective entries 548(0)-548(B) for a single context 544. In this example, the size "S" of entries 548(0) through 548(B) in dedicated branch prediction memory 502 is the same as the number of entries in a single context 544(0) through 544(C) in shared branch prediction memory 542. Thus, until the swap-in of branch prediction states 546(0) through 546(B) from shared branch prediction memory 542 to private branch prediction memory 136 is complete, branch prediction circuitry 134 can access branch prediction states 546(0) through 546(B) in dedicated branch prediction memory 502 to speculatively predict the outcome of branch instruction 106F.

[0046] Figure 6 is a flow chart illustrating an example process 600 of the branch prediction circuit 134 in the instruction processing circuit 104 of Figure 1. The branch prediction circuit is configured to swap in contexts from the shared branch prediction memory 542 to the private branch prediction memory 136, instead of swapping out contexts from the private branch prediction memory 136 to the shared branch prediction memory 542, and to use the prediction states 546(0) through 546(B) in the dedicated branch prediction memory 502 to make predictions until the swap-in process is complete. This process 600 of Figure 6 is described below in connection with the instruction processing circuit 104 of Figure 5. In this regard, the branch prediction circuit 134 speculatively predicts the outcome of a fetched branch instruction 106F in a current process being executed in the instruction processing circuit 104 (block 602 of Figure 6). The speculative prediction may be based on the accessed associated branch prediction states 138(0)-138(B) in the private branch prediction memory 136 for a context associated with the fetched branch instruction 106F of the current process executing in the instruction processing circuitry 104 (block 602 of FIG. 6). As previously described, the private branch prediction memory 136 is configured to store the branch prediction states 138(0)-138(B) for the current context of the current process executing in the instruction processing circuitry 104 of the processor 102.

[0047] Continuing with FIG. 6 , the branch prediction circuit 134 receives a process ID 150 identifying a new context that has been or will be swapped into the instruction processing circuit 104, which indicates a context switch (FIG. 6 , block 604). The branch prediction circuit 134 determines whether the process ID 150 indicates a new context that is different from the current context that has been swapped into the instruction processing circuit 104 (FIG. 6 , block 606). In response to the process ID 150 indicating a new context that is different from the current context that has been swapped into the instruction processing circuit 104 (FIG. 6 , block 608), the branch prediction circuit 134 stores branch prediction states 546()(0) through 546()(B) associated with the new contexts 544(0) through 544(C) in branch prediction states 138(0) through 138(B) of the private branch prediction memory 136 (FIG. 6 , block 610). Also, in response to process ID 150 indicating a new context that is different from the current context swapped in to instruction processing circuitry 104, branch prediction circuitry 134 swaps out branch prediction state 138(0)-138(B) in private branch prediction memory 136 for the current context to be stored as branch prediction state 546()(0)-546()(B) for that context 544(0)-544(C) in shared branch prediction memory 542 (block 612 of FIG. 6).

[0048] 6, the branch prediction circuit 134 is configured to determine whether the swap-in and storage of the branch prediction states 546()(0) through 546()(B) in the shared branch prediction memory 542 for the swapped-in context into the private branch prediction memory 136 is complete (block 614 of FIG. 6). In response to determining that the storage of the branch prediction states 546()(0) through 546()(B) from the shared branch prediction memory 542 into the private branch prediction memory 136 is not complete (block 616 of FIG. 6), the branch prediction circuit 134 is still configured to speculatively predict the outcome of the branch instruction 106F in the swapped-in current process executing in the instruction processing circuit 104 based on the branch prediction states 546(0) through 546(B) in the dedicated branch prediction memory 502 associated with the branch instruction 106F (block 618 of FIG. 6). However, in response to determining that the storage of branch prediction states 546()(0) through 546()(B) from the shared branch prediction memory 542 to the private branch prediction memory 136 is complete (block 620 of FIG. 6), the branch prediction circuitry 134 may be configured to speculatively predict the outcome of branch instruction 106F in the swapped-in current process executing within instruction processing circuitry 104 using the branch prediction states 546()(0) through 546()(B) from the shared branch prediction memory 542 stored as branch prediction states 138(0) through 138(B) in the private branch prediction memory 136, as described above (block 622 of FIG. 6).

[0049] Another alternative branch prediction circuit that speculatively predicts the outcome of branch instruction 106F based on branch condition state swapped into a private branch prediction memory in response to a context switch is shown in Figure 7. Figure 7 shows a processor-based system 700 that includes a processor 702 and instruction processing circuitry 704 similar to processor 102 and instruction processing circuitry 104 in processor-based system 100 of Figure 1. Identical components between processor-based system 100 of Figure 1 and processor-based system 700 of Figure 7 are indicated with common element numbers. The previous descriptions of these elements with respect to Figure 1 are applicable to Figure 7 and will not be described again.

[0050] In the processor-based system 700 of Figure 7, the instruction processing circuit 704 includes two identical branch prediction circuits: the branch prediction circuit 134 from the instruction processing circuit 104 of Figure 1, and a second branch prediction circuit 734. As described in further detail below, one branch prediction circuit 134, 734 is configured to hold a current-context branch prediction state 138(0)-138(B), 738(0)-738(B) for the current process being executed, and the other branch prediction circuit 734, 134 is configured to hold a next-context branch prediction state 738(0)-738(B), 138(0)-138(B) for the next process that is more likely to be swapped into the instruction processing circuit 704 for execution. In this way, when a context switch occurs, if the process ID 150 identifying the process to be swapped is associated with the context currently stored in the second branch prediction circuit 734, 134, the second branch prediction circuit 734, 134 can take over making speculative predictions in the instruction processing circuit 704 without delay. The first branch prediction circuit 134, 734 can be disabled, and a new context for the process predicted to be more likely to be swapped in next can be loaded into its entries 140(0)-140(B), 740(0)-740(B) as its branch prediction state 138(0)-138(B), 738(0)-738(B). The branch prediction states 138(0)-138(B) in the first branch prediction circuit 134 can be swapped out to the shared branch prediction memory 142, and new contexts associated with new processes predicted to be swapped into the instruction processing circuit 104 can then be swapped from the shared branch prediction memory 142 to the branch prediction memory 136, as described above.However, if a context switch occurs and the process ID 150 identifying the process to be swapped is not associated with the context currently stored in the second branch prediction circuit 734, 134, the branch prediction state 138(0)-138(B), 738(0)-738(B) in the second branch prediction circuit 734, 134 can be flushed, and the branch prediction state 144()(0)-144()(B) for the new context stored in the shared branch prediction memory 142 can be swapped in to the first branch prediction circuit 134, 734. This includes according to any of the techniques described above.

[0051] 8A and 8B are flowcharts illustrating an example process 800 for the instruction processing circuit 704 of FIG. 7, which includes two branch prediction circuits 134, 734 and is configured to switch between the branch prediction circuits 134, 734 to speculatively predict the outcome of a branch instruction 106F. In this regard, assuming that the branch prediction circuit 134 is configured to perform speculative prediction in the instruction processing circuit 704, the branch prediction circuit 134 speculatively predicts the outcome of a fetched branch instruction 106F in a current process executing in the instruction processing circuit 104 (block 802 of FIG. 8A). The speculative prediction may be based on accessed associated branch prediction states 138(0)-138(B) in the private branch prediction memory 136 for a context associated with the fetched branch instruction 106F of the current process executing in the instruction processing circuit 104 (block 802 of FIG. 8A). As mentioned above, the first private branch prediction memory 136 is configured to store branch prediction states 138(0)-138(B) for the current context of the current process executing in the instruction processing circuitry 104 of the processor 102.

[0052] Continuing with reference to FIG. 8A , the instruction processing circuit 704 receives a process ID 150 identifying a new context that has been or will be swapped into the instruction processing circuit 104, which indicates a context switch (block 804 of FIG. 8A ). The instruction processing circuit 704 determines whether the process ID 150 indicates a new context that is different from the current context swapped into the instruction processing circuit 104 (block 806 of FIG. 8A ). In response to the process ID 150 indicating a new context that is different from the current context swapped into the instruction processing circuit 104 (block 808 of FIG. 8A ), the instruction processing circuit 704 is further configured to determine whether the new context is associated with a branch prediction state 738(0)-738(B) stored in the second private branch prediction memory 736 of the second branch prediction circuit 734 (block 810 of FIG. 8A ). If so, the instruction processing circuit 704 is configured to switch from the first branch prediction circuit 134 to the second branch prediction circuit 734 and cause the second branch prediction circuit 734 to speculatively predict the outcome of the branch instruction 106F in the next process executed in the instruction processing circuit 704 based on the branch prediction states 738(0)-738(B) for the next context in the second private branch prediction memory 736 associated with the branch instruction 106F (block 812 of FIG. 8A ). Thus, the second private branch prediction memory 736 can start speculatively predicting the outcome of the branch instruction 106F for the next process without having to wait for the branch prediction states for the next context to be swapped into the second private branch prediction memory 736. Also, if the new context is associated with the branch prediction state 738(0)-738(B) stored in the second private branch prediction memory 736 of the second branch prediction circuit (block 810 of FIG. 8A), the branch prediction circuit 134 is further configured to cease speculatively predicting the outcome of the branch instruction 106F in the next process executed in the instruction processing circuit 104 (block 814 of FIG. 8B).The instruction processing circuit 704 is further configured to swap out the branch prediction states 138(0)-138(B) in the branch prediction memory 136 for the branch prediction states 146(0)-146(B) for the current contexts 144(0)-144(C) in the shared branch prediction memory 142, as previously described (block 816 in FIG. 8B). The instruction processing circuit 704 is also further configured to swap in the branch prediction states 146(0)-146(B) for the contexts 144(0)-144(C) of the next speculatively-speculated context to be swapped in to the instruction processing circuit 704 from the shared branch prediction memory 142 to the private branch prediction memory 136 (block 818 in FIG. 8B).

[0053] However, if the new context is not associated with a branch prediction state 738(0)-738(B) stored in the second private branch prediction memory 736 of the second branch prediction circuit 734 (block 810 of FIG. 8A), the instruction processing circuit 704 is configured to flush the branch prediction state 738(0)-738(B) associated with the next context in the second private branch prediction memory 736 (block 820 of FIG. 8B). This allows the branch prediction state 146(0)-146(B) of the next speculatively-speculated context 144(0)-144(C) to be swapped in to be loaded into the second private branch prediction memory 736. The branch prediction circuit 134 continues to speculatively predict the outcome of the branch instruction 106F for the new process being swapped in to the instruction processing circuit 704 (block 822 of FIG. 8B). The instruction processing circuit 704 is configured to swap out the branch prediction states 738(0) through 738(B) in the private branch prediction memory 136 to the shared branch prediction memory 142 (block 816 of FIG. 8B), as previously described. The instruction processing circuit 704 is further configured to swap in the branch prediction states 146(0) through 146(B) for the contexts 144(0) through 144(C) of the new contexts swapped into the instruction processing circuit 704 from the shared branch prediction memory 142 to the private branch prediction memory 136 (block 818 of FIG. 8B).

[0054] It should be noted that any of the operations described above regarding swapping out contexts from the private branch prediction memory 136, 736 to the shared branch prediction memory 142, 542, 742, and swapping in contexts from the shared branch prediction memory 142, 542, 742 to the private branch prediction memory 136, 736 may be performed elsewhere within the instruction processing circuitry 104 and / or processor 102, 702.

[0055] 9 is a block diagram of an exemplary processor-based system 900 including a processor 902 (e.g., a microprocessor) that includes an instruction processing circuit 904. The instruction processing circuit 904 may, for example, be any of the instruction processing circuits 104 in the processor 102 of FIGS. 1, 5, and 7, and may include a branch prediction circuit 906 configured to speculatively predict the outcome of a branch instruction to be executed, and a private branch prediction memory configured to store branch prediction states accessed to make such predictions. The processor-based system 900 may, for example, be any of the processor-based systems 100, 500, and 700 of FIGS. 1, 5, and 7, and may include a shared branch prediction memory used to swap in and out contexts in response to context switches of the processor 902, for example, the shared branch prediction memories 142, 542, and 742 of FIGS. 1, 5, and 7. The processor-based system 900 may represent one or more circuits contained in an electronic board card, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing pad, mobile device, or any other device, such as a server or a user's computer. In this example, the processor-based system 900 includes a processor 902. The processor 902 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. More specifically, the processor 902 may be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for communicating product values ​​resulting from the execution of producer instructions. The processor 902 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, the processor 902 includes an instruction cache 908 for temporary, fast-access memory storage of instructions accessible by the instruction processing circuit 904.Instructions fetched or prefetched from memory, such as from system memory 910 via system bus 912, are stored in instruction cache 908. Instruction processing circuitry 904 is configured to process instructions fetched into instruction cache 908 and prepare the instructions for execution. System memory 910 may include a shared branch prediction memory 911, such as shared branch prediction memory 142, 542, 742 in FIGS. 1, 5, and 7.

[0056] The processor 902 and the system memory 910 are coupled to a system bus 912, which may interconnect peripheral devices included in the processor-based system 900. As is well known, the processor 900 communicates with these other devices by exchanging address, control, and data information over the system bus 912. For example, the processor 902, as an example of a slave device, may communicate bus transaction requests to a memory controller 914 within the system memory 910. Although not shown in FIG. 9, multiple system buses 912 may be provided, with each system bus constituting a different fabric. In this example, the memory controller 914 is configured to provide memory access requests to a memory array 916 within the system memory 910. The memory array 916 comprises an array of storage bit cells for storing data. The system memory 910 may be, by way of non-limiting example, read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0057] Other devices may be connected to the system bus 912. As shown in FIG. 9, these devices may include, by way of example, a system memory 910, one or more input devices 918, one or more output devices 920, a modem 922, and one or more display controllers 924. The input devices 918 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output devices 920 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem 922 may be any device configured to enable the exchange of data with a network 926. The network 926 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The modem 922 may be configured to support any type of communication protocol desired. The processor 902 may also be configured to access a display controller 924 through the system bus 912 to control information sent to one or more displays 928. The display 928 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0058] 9 may include a set of instructions 930 that are executed by the processor 902 for any desired application in accordance with the instructions. The instructions 930 may be stored in the system memory 910, the processor 902, and / or the instruction cache 908 as examples of non-transitory computer-readable media 932. The instructions 930 may also reside, completely or at least partially, within the system memory 910 and / or the processor 902 during their execution. The instructions 930 may further be transmitted or received over a network 926 via the modem 922, whereby the network 926 includes the computer-readable medium 932.

[0059] Although the computer-readable medium 932 is shown in the exemplary embodiment to be a single medium, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., centralized or distributed databases, and / or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium that can store, encode, or carry a set of instructions for execution by a processing device that causes the processing device to perform any one or more of the methods of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0060] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied by machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0061] The embodiments disclosed herein may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, and may be provided as a computer program product or software that can be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), etc.

[0062] Unless otherwise specifically stated, and as is clear from the preceding discussion, discussions throughout this document using terms such as "processing," "computing," "determining," "displaying," and the like are understood to refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display devices.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Further, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​may be used to implement the teachings of the embodiments described herein.

[0064] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or other computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip, by way of example. The memory disclosed herein may be any type and size of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

[0065] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0066] The embodiments disclosed herein may be embodied in hardware and instructions stored on the hardware, which may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0067] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described as a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps described in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, light fields or particles, or any combination thereof.

[0068] Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a particular order. Thus, unless a method claim actually recites the order in which its steps should be followed, or unless the claim or specification otherwise expressly states that the steps are to be limited to a particular order, no particular order is intended to be inferred.

[0069] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations, and variations of the disclosed embodiments that incorporate the spirit and content of the present invention may occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and their equivalents.

Claims

1. 1. A branch prediction circuit having a private branch prediction memory configured to store at least one branch prediction state for a current context of a current process executing in an instruction processing circuit of a processor, the branch prediction memory comprising: The branch prediction circuit: speculatively predicting an outcome of a branch instruction in a current process being executed in the instruction processing circuit based on a branch prediction state of the at least one branch prediction state in a current context in the private branch prediction memory associated with the branch instruction; receiving a process identifier identifying a new context swapped into the instruction processing circuit; In response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuit: swapping out at least one branch prediction state from the private branch prediction memory to a shared branch prediction memory by storing the at least one branch prediction state in the private branch prediction memory as at least one branch prediction state in a shared branch prediction memory, the shared branch prediction memory being configured to store at least one branch prediction state associated with each of a plurality of contexts; and storing at least one branch prediction state associated with the new context as the at least one branch prediction state in the private branch prediction memory. and configured to perform the steps The branch prediction circuitry, in response to the process identifier indicating a new context different from the current context swapped into the instruction processing circuitry, performs: storing at least one branch prediction state associated with the new context in the shared branch prediction memory, the shared branch prediction memory being configured to store at least one branch prediction state associated with a context among each of a plurality of contexts, as at least one branch prediction state in the private branch prediction memory; The branch prediction circuitry, in response to the process identifier indicating a new context different from a current context swapped into the instruction processing circuitry: determining whether storing the at least one branch prediction state in the shared branch prediction memory into the private branch prediction memory is complete; In response to determining that storing the at least one branch prediction state from the shared branch prediction memory to the private branch prediction memory is not complete: further configured to speculatively predict an outcome of a branch instruction in a current process executed within the instruction processing circuit based on the branch prediction state of the at least one branch prediction state in a dedicated branch prediction memory associated with the branch instruction, the dedicated branch prediction memory configured to store at least one branch prediction state associated with a context including a current context; Branch prediction circuitry.

2. In response to determining that storing the at least one branch prediction state from the shared branch prediction memory to the private branch prediction memory is complete: configured to speculatively predict the outcome of a branch instruction in a current process being executed in the instruction processing circuitry based on the branch prediction state of the at least one branch prediction state in the private branch prediction memory associated with the branch instruction.

2. The branch prediction circuit according to claim 1.

3. a processor; an instruction processing circuit including one or more instruction pipelines including a fetch circuit, a branch prediction circuit according to claim 1 or 2, and an execution circuit; Shared Branch Prediction Memory 1. A processor-based system having: the fetch circuitry is configured to fetch a plurality of instructions from memory into an instruction pipeline of the one or more instruction pipelines for execution by the execution circuitry; the shared branch prediction memory is configured to store at least one branch prediction state associated with a respective one of a plurality of contexts associated with each process configured to execute within the instruction processing circuit; Processor-based systems.

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