MEMORY DEVICE AND METHOD FOR PROGRAMMING THE SAME - Patent application

Abstract

To provide a memory device and a programming method that eliminate programming disturb.SOLUTION: A programming method for a multi-plane type memory device includes: starting programming a first plane and a second plane simultaneously; and bypassing the first plane, continuing to program the second plane, and disabling the first plane, when the first plane has been successfully programmed and the second plane has not been successfully programmed yet.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a memory device and a programming method thereof, and more particularly to a memory device and a programming method thereof for eliminating programming disturbance. [Background technology]

[0002] In recent years, the field of semiconductor memory has received increasing attention. Semiconductor memory can be volatile or non-volatile. Non-volatile semiconductor memory devices can retain data even when not powered and have therefore been widely used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.

[0003] Memory devices can be classified into single-plane and multi-plane types according to the structural configuration of the memory array. A single-plane memory device includes a memory array arranged in a single plane, while a multi-plane memory device includes a memory array arranged in multiple planes. When programming a multi-plane memory device, two or more planes can be simultaneously programmed and verified according to a multi-plane programming scheme to improve programming efficiency. However, when a multi-plane memory device includes a faulty plane (or a corrupted plane), both the normal plane and the faulty plane (or the corrupted plane) are repeatedly programmed when attempting to program data into the faulty plane (or the corrupted plane), thereby reducing programming speed, reducing programming efficiency, and causing programming disturbance to the normal plane.

[0004] Therefore, there is a need to provide a memory device and programming method that bypasses certain planes, such as normal planes, so that the normal planes are not subjected to the programming stress of unnecessary programming pulses. Summary of the Invention [Problem to be solved by the invention]

[0005] It is therefore an object of the present invention to provide a memory device and associated programming method that eliminates programming disturb. [Means for solving the problem]

[0006] The present invention discloses a programming method for a memory device, which includes the steps of: starting to program a first plane and a second plane simultaneously; and, if the first plane has been successfully programmed and the second plane has not yet been successfully programmed, bypassing the first plane and continuing to program the second plane.

[0007] The present invention further discloses a memory device comprising a first plane, a second plane, and a control circuit configured to control the first plane and the second plane according to a programming method including: starting to program the first plane and the second plane simultaneously; and, if the first plane has been successfully programmed but the second plane has not yet been successfully programmed, bypassing the first plane and continuing to program the second plane.

[0008] These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram of a memory device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a schematic diagram of a plane of the memory device illustrated in FIG. 1. [Figure 3] 2 is a flowchart of a programming method for programming the memory device illustrated in FIG. 1 according to one embodiment of the present invention. [Figure 4] FIG. 2 is a schematic diagram illustrating a waveform of a programming voltage according to one embodiment of the present invention. [Figure 5] 2 is a flowchart of a programming method for programming the memory device illustrated in FIG. 1 according to one embodiment of the present invention. [Figure 6] FIG. 2 is a schematic diagram of selected circuitry in the control circuit shown in FIG. 1 according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] 1 is a block diagram of a memory device 10 according to one embodiment of the present invention. The memory device 10 may have a dual-plane structure and may include a control circuit 100, a word line driver 120, multiple bit line drivers 131, 132, and multiple planes (also referred to as memory planes) 141, 142.

[0011] Briefly, planes 141 and 142 may be programmed and verified simultaneously. If plane 141 (also referred to as the first plane) has been successfully programmed but plane 142 has not yet been successfully programmed, then plane 141 may be bypassed and plane 142 (also referred to as the second plane) may still be programmed. Bypassing plane 141 from subsequent programming once plane 141 passes all verifications reduces the time spent trying to apply unnecessary programming pulses to plane 141 and eliminates programming disturb in plane 141.

[0012] See also FIG. 2, which is a schematic diagram of planes 141 and 142 of memory device 10 shown in FIG. 1. Plane 141 may be divided into multiple blocks 141B1-141Bi. Each of blocks 141B1-141Bi includes multiple strings, which may be NAND strings. Each string may include, but is not limited to, two select cells and multiple memory cells, each connected in series. The select cell located at the top of a string is configured to connect the string to multiple bit lines BL11-BL1m and may be controlled by applying an appropriate voltage to a string select line SSL1. The select cell located at the bottom of a string is configured to connect the string to a common source line CSL1 and may be controlled by applying an appropriate voltage to a ground select line GSL1. The control gates of the memory cells in the strings are connected to multiple word lines WL11-WL1n, respectively.

[0013] Similarly, the plane 142 may be divided into multiple blocks 142B1 to 142Bi. Each of the blocks 142B1 to 142Bi includes multiple strings, which may be NAND strings. Each string may include, but is not limited to, two select cells and multiple memory cells, each connected in series. The select cell located at the top of a string is configured to connect the string to multiple bit lines BL21 to BL2m and may be controlled by applying an appropriate voltage to a string select line SSL2. The select cell located at the bottom of a string is configured to connect the string to a common source line CSL2 and may be controlled by applying an appropriate voltage to a ground select line GSL2. The control gates of the memory cells in the strings are connected to multiple word lines WL21 to WL2n, respectively.

[0014] As shown in FIG. 2, planes 141 and 142 have an identical structure (or a mirror structure). While a dual-plane structure is used in this embodiment, it should be recognized that other numbers of planes may also be employed within the scope of the present invention. Furthermore, any of a two-dimensional planar memory structure, a three-dimensional stacked structure, a NAND flash memory structure, and / or a NOR flash memory structure may be implemented in planes 141 and 142. Each of blocks 141B1-141Bi and 142B1-142Bi may be divided into multiple pages, as indicated by the dashed lines. In some embodiments, a block is a conventional unit of erase, and a page is a conventional unit of program. However, other units of erase / program may also be used. Typically, bit lines BL11-BL1m or BL21-BL2m extend above the strings in a direction perpendicular to word lines WL11-WL1n or WL21-WL2n, respectively, where i, m, and n are integers greater than 1, but are not limited thereto.

[0015] Those skilled in the art will recognize that the number of memory cells in a string does not limit the scope of the present invention. In addition, the memory cells in a string can be floating gate transistors or charge trapping transistors. Each memory cell may store one bit of data or more than one bit of data and therefore may be of a single-level cell (SLC) type, a multi-level cell (MLC) type, a triple-level cell (TLC) type, a quad-level cell (QLC) type, or a higher level type. Each memory cell can have one of Q possible programming states, where Q is a positive integer greater than or equal to 2, typically Q=2 for SLC, Q=4 for MLC, Q=8 for TLC, and Q=16 for QLC.

[0016] The control circuit 100 may be coupled to a word line driver 120 and bit line drivers 131 and 132. The word line driver 120 may be coupled to a plane 141 via a string select line SSL1, word lines WL11 to WL1n, and a ground select line GSL1. The word line driver 120 may be coupled to a plane 142 via a string select line SSL2, word lines WL21 to WL2n, and a ground select line GSL2. The bit line driver 131 may be coupled to the plane 141 via bit lines BL11 to BL1m. The bit line driver 132 may be coupled to the plane 142 via bit lines BL21 to BL2m. The array of memory cells in the plane 141 may be addressed by the word lines WL11 to WL1n and bit lines BL11 to BL1m, and the array of memory cells in the plane 142 may be addressed by the word lines WL21 to WL2n and bit lines BL21 to BL2m.

[0017] The control circuit 100 may be a controller, an embedded microprocessor, a microcontroller, or the like. The control circuit 100 may communicate with an external host to receive data for storage in the planes 141 and 142 and to transmit data retrieved from the planes 141 and 142. The control circuit 100 may receive commands, addresses, or data from the external host and generate bit line address signals Scadr1 and Scadr2 and word line address signal Sradr. The word line driver 120 may operate in response to the word line address signal Sradr from the control circuit 100 to select word lines for read, program, erase, and verify operations. The bit line drivers 131 and 132 may operate in response to the bit line address signals Scadr1 and Scadr2 from the control circuit 100 to generate bit line signals that select bit lines for read, program, erase, and verify operations. In some embodiments, control circuit 100 includes voltage reference circuits for providing voltages for read, program, erase, and verify operations, and bit line drivers 131, 132 and word line driver 120 include switches for selecting the voltages. In other embodiments, bit line drivers 131, 132 and word line driver 120 include voltage generation circuitry, and control circuit 100 provides digital control information to instruct bit line drivers 131, 132 and word line driver 120 to drive various voltages onto bit lines BL11-BL1m, BL21-BL2m and word lines WL11-WL1n, WL21-WL2n. However, the manner in which voltages are generated or delivered to bit lines BL11-BL1m, BL21-BL2m and word lines WL11-WL1n, WL21-WL2n does not limit the scope of the present invention.

[0018] 3 is a flowchart of a programming method 30 for programming the memory device 10 shown in FIG. 1 according to one embodiment of the present invention. The programming method 30 may be compiled into program code. The method 30 is performed by the control circuit 100 and may include the following steps: Step S300: Start. Step S302: Start to program the first plane and the second plane simultaneously. Step S304: If the first plane has been successfully programmed and the second plane has not yet been successfully programmed, bypass the first plane and continue to program the second plane. Step S306: End.

[0019] In step S302, control circuit 100 begins simultaneously programming two planes (e.g., planes 141 and 142) or three or more planes of memory device 10 to achieve a multi-plane programming scheme in which two or more planes can be programmed and verified simultaneously. However, in step S302, if plane 141 is successfully programmed but plane 142 is not yet successfully programmed, plane 141 is bypassed and plane 142 is still programmed. Once plane 141 passes all verifications, bypassing plane 141 can eliminate programming disturbance.

[0020] For example, the control circuit 100 may employ an incremental step pulse programming (ISPP) scheme to program the planes 141 and 142. See FIG. 4, which is a schematic diagram illustrating the waveforms of programming voltages according to one embodiment of the present invention. Multiple programming pulses Vpp1-Vpp6 may be applied to the blocks with increasing amplitudes, and each successive programming pulse (e.g., programming pulse Vpp2) may exceed the previous programming pulse (e.g., programming pulse Vpp1) by a programming step size. The programming step size may vary according to the programming state or other requirements. The programming pulse Vpp1 may be applied to both planes 141 and 142 to begin programming them simultaneously. On the other hand, if the block 141B1 has been successfully programmed before the programming pulse Vpp5 is applied, the block 141B1 may bypass the subsequent programming pulses Vpp5 and Vpp6 by simply following the programming pulses Vpp1-Vpp4. As a result, while block 142B1 needs to be programmed with additional programming pulses (i.e., programming pulses Vpp5, Vpp6) for a longer time (due to the greater number of programming pulses), block 141B1 will not be subjected to the programming stress of subsequent unnecessary programming pulses Vpp5, Vpp6, thereby eliminating or at least reducing programming disturbance in block 141B1.

[0021] Block 141B1 may be programmed up to a first programming pulse count (equal to 4) corresponding to programming pulses Vpp1-Vpp4, and block 142B1 may be programmed up to a second programming pulse count (equal to 6) corresponding to programming pulses Vpp1-Vpp6. The first programming pulse count is less than the second programming pulse count. Block 142B1 may be programmed until a maximum programming pulse count Cpmax (also referred to as a predetermined programming pulse count) (e.g., equal to 6) is reached. If block 142B1 is still not successfully programmed, block 142B1 may be identified as a bad block. Because programming pulse Vpp6 is the last programming pulse corresponding to the maximum programming pulse count Cpmax, control circuit 100 may stop programming block 142B1. Although the control circuit 100 finishes programming blocks 141B1 and 142B1 (which were either unsuccessfully programmed or successfully programmed) asynchronously, the control circuit 100 begins programming (the first memory cell of) block 141B2 followed by (the third memory cell of) block 141B1 and (the second memory cell of) block 142B2 followed by (the fourth memory cell of) block 142B2 simultaneously. The length of time from the start of programming block 141B1 to the start of programming block 141B2 depends on the length of time from the start of programming block 142B1 to the start of programming block 142B2. In other words, the length of time to program two blocks (e.g., blocks 141B1 and 142B1) is determined based on the block with the higher programming pulse count, which may be a bad or deteriorated block, rather than the block with the lower programming pulse count, which may be a good block.

[0022] 5 is a flowchart of a programming method 50 for programming the memory device 10 shown in FIG. 1 according to one embodiment of the present invention. The programming method 50 may be compiled into program code. The method 50 is performed by the control circuitry 100 and may include the following steps: Step S500: Start. Step S502: Apply a programming pulse. Step S504: Increment the programming pulse count Cp. Step S506: Bypass at least one plane that has been successfully programmed. Step S508: Determine whether all planes are bypassed. If yes, proceed to step S514; if not, proceed to step S510. Step S510: Determine whether the programming pulse count Cp is less than the maximum programming pulse count Cpmax. If yes, proceed to step S502; if not, proceed to step S512. Step S512: Indicates programming failure. Step S514: End.

[0023] In response to the start of multi-plane programming, the planes 141 and 142 are initialized for programming in step S500. The control circuit 100 sets a programming pulse count Cp and a verify count Cvf to values ​​such as 0 (i.e., Cp=0, Cvf=0). In step S502, the control circuit 100 begins simultaneously programming a first memory cell in (a block 141B1 or page of) the plane 141 and a second memory cell in (a block 142B1 or page of) the second plane 142. The word line driver 120 may apply a programming pulse (e.g., programming pulse Vpp1) to a selected word line of the planes 141 and 142. In step S504, the control circuit 100 increments the programming pulse count Cp by 1 (Cp=1).

[0024] The control circuit 100 may then verify whether the first memory cell in plane 141 and the second memory cell in plane 142 were successfully programmed. In some embodiments, a verify pulse may be applied after each program pulse illustrated in FIG. 4 to verify the threshold voltage of each memory cell. In some embodiments, the control circuit 100 may verify whether the first memory cell and the second memory cell have reached one or more programming states. In some embodiments, data may be read from the first memory cell and the second memory cell on the selected bit line, respectively. If the read data is incorrect, the control circuit 100 may verify the respective first memory cell or the respective second memory cell as failed. If the read data is correct, the control circuit 100 may verify the respective first memory cell or the respective second memory cell as passed. After verifying the first memory cell and the second memory cell, the control circuit 100 increments the verify count Cvf by one (Cvf=1). In some embodiments, if more than a respective preset number of first memory cells or second memory cells fail to reach one of the programming states, control circuit 100 will verify the first memory cells or second memory cells as failing. If fewer than a respective preset number of first memory cells or second memory cells fail to reach a programming state, control circuit 100 will verify planes 141, 142 as passing. In some embodiments, if the number of first memory cells or second memory cells that fail to be successfully programmed to each of the programming states is less than a respective preset number, the first memory cells or second memory cells are determined to pass.

[0025] To reduce programming disturbance, if any plane is successfully programmed (and verified as passing), the control circuit 100 bypasses the (successfully programmed) plane in subsequent programming in step S506. However, the control circuit 100 continues programming the other planes that have not yet been successfully programmed in step S506. The control circuit 100 sets the pause signal Sss1 to logic low while maintaining the main signal Smn at logic high to bypass plane 141 and continue programming plane 142. By pausing plane 141 once plane 141 passes all verifications, programming disturbance can be eliminated. In some embodiments, if fewer than a predetermined number of first memory cells have not yet verified as passing but more than a predetermined number of second memory cells have yet to be verified as failing, plane 141 is paused and plane 142 is still programmed. The first memory cells of plane 141 will be bypassed and saved in the next programming, while the second memory cells of plane 142 will still be programmed in the next programming. In other words, a first programming process for a first memory cell in plane 141 and a second programming process for a second memory cell in plane 142 start simultaneously but end asynchronously. By pausing plane 141 when the first memory cell in plane 141 is bypassed, programming disturb in plane 141 can be eliminated.

[0026] In step S508, the control circuit 100 determines whether all of the planes 141 and 142 for the multi-plane programming scheme are bypassed. If all of the planes 141 and 142 are bypassed, the multi-plane programming scheme is completed. If any of the planes 141 and 142 are not yet paused, the control circuit 100 determines in step S510 whether the programming pulse count Cp is less than the maximum programming pulse count Cpmax. If the programming pulse count Cp (e.g., Cp=1) is less than the maximum programming pulse count Cpmax (e.g., Cpmax=6), the control circuit 100 repeats steps S502 through S508 until the programming pulse count Cp reaches the maximum programming pulse count Cpmax. For example, another programming pulse (e.g., programming pulses Vpp2, Vpp3, ..., or Vpp6 in sequence) is applied to the selected word line of the non-bypass plane in step S502, and the control circuit 100 again increments the programming pulse count Cp by 1 in step S504.

[0027] If the first memory cell of plane 141 is bypassed after programming pulse Vpp4 is applied, the programming pulse count Cp increases to 4 and serves as the first programming pulse count. Additionally, the verify count Cvf may be 4 or greater and serve as the first number of times for the first memory cell to be verified. Similarly, if the second memory cell of plane 142 is bypassed after programming pulse Vpp6 is applied, the programming pulse count Cp increases to 6 and serves as the second programming pulse count. Alternatively, if the second memory cell of plane 142 cannot be successfully programmed (and therefore may be unusable) after the last programming pulse (i.e., programming pulse Vpp6) is applied, the programming pulse count Cp also increases to 6 and becomes equal to the maximum programming pulse count Cpmax. In these cases, the verify count Cvf is 6 or greater and serves as the second number of times for the second memory cell to be verified. The first programming pulse count corresponding to the first memory cell is less than the second programming pulse count corresponding to the second memory cell. The first number of times for the first memory cell to be verified is less than the second number of times for the second memory cell to be verified.

[0028] Because the first memory cell was successfully programmed before programming pulse Vpp5 was applied, the first memory cell may bypass the subsequent programming pulses Vpp5, Vpp6 by only following programming pulses Vpp1-Vpp4. Thus, while the second memory cell needs to be programmed for a longer time by the additional programming pulses Vpp5, Vpp6, the first memory cell will not be subjected to the programming stress of the subsequent programming pulses Vpp5, Vpp6, thereby eliminating or at least reducing programming disturb in block 141B1.

[0029] If the programming pulse count Cp (or the second programming pulse count) is greater than or equal to the maximum programming pulse count Cpmax, a programming failure report is sent to the control circuit 100 in step S512 to report a programming failure for the non-bypass plane (e.g., plane 142), if any. In other words, the second memory cell may be programmed until the maximum programming pulse count Cpmax is reached. In some embodiments, the control circuit 100 may stop programming the second memory cell when the programming pulse count Cp (or the second programming pulse count) is equal to the maximum programming pulse count Cpmax.

[0030] It is worth noting that various modifications and alterations can be readily made by those skilled in the art. For example, to bypass (the first memory cell of) plane 141, the plane select signal or block select signal can be interrupted. Alternatively, to bypass (the first memory cell of) plane 141, all word lines WL11-WL1n or all bit lines BL11-BL1m of plane 141 can be deselected. FIG. 6 is a schematic diagram of selected circuits in the control circuit 100 shown in FIG. 1 according to an embodiment of the present invention. The control circuit 100 can include AND gates 101 and 102 that control access to planes 141 and 142, respectively. The AND gate 101 can receive a plane address signal Spr1, a disable signal Sdb1, a main signal Smn, or a pause signal Sss1 and generate a plane select signal Ssp1. The AND gate 102 can receive a plane address signal Spr2, a disable signal Sdb2, a main signal Smn, or a pause signal Sss2 and generate a plane select signal Ssp2. In some embodiments, control circuitry 100 may set primary signal Smn to logic high to continue programming memory device 10 or set primary signal Smn to logic low to stop programming memory device 10. In some embodiments, control circuitry 100 may generate disable signals Sdb1, Sdb2 when a programming failure report is received, which may indicate the programming result upon exiting the program verify operation. In some embodiments, pause signals Sss1, Sss2 may indicate whether the verify result is pass or fail.

[0031] In some embodiments, the disable signals Sdb1 and Sdb2 may be associated with a programming state counter, a verify count Cvf, a programming pulse count Cp, or a maximum programming pulse count Cpmax. The maximum programming pulse count Cpmax may define the maximum number of times programming pulses are applied to the planes 141 and 142. The programming state counter may be associated with a target programming state or a current programming state. Specifically, the first and second memory cells may be initially set to an erased state, and later, a series of program verify operations may be performed on the first and second memory cells to program the first and second memory cells to their respective target programming states. The series of program verify operations may start from a lowest programming state and progress to higher programming states until the threshold voltages of the selected memory cells reach the respective verify voltage levels of their respective target programming states. In some embodiments, the verify voltages may be selected as the lowest threshold voltages of the threshold voltage distribution curves of the respective programming states. Each program verify operation may include a programming operation and a next verify operation.

[0032] The control circuit 100 may generate a bit line address signal Scadr1 according to the plane select signal Ssp1, may generate a bit line address signal Scadr2 according to the plane select signal Ssp2, and may generate a word line address signal Sradr according to the plane select signals Ssp1 and Ssp2. In some embodiments, when it is determined to suspend the plane 141, the control circuit 100 may set the suspend signal Sss1 to logic low. Even if the AND gate 101 blocks the plane select signal Ssp1 in response to the suspend signal Sss1 by setting the plane select signal Ssp1 to logic low, the control circuit 100 may still generate the word line address signal Sradr and the bit line address signal Scadr1 that deselect the word lines WL11-WL1n and bit lines BL11-BL1m of the plane 141. Similarly, when it is determined to pause plane 142, control circuit 100 may set pause signal Sss2 to logic low, and AND gate 102 may interrupt plane select signal Ssp2 in response to the pause signal Sss2 by setting plane select signal Ssp2 to logic low, and control circuit 100 may generate word line address signal Sradr and bit line address signal Scadr2 to deselect word lines WL21-WL2n and bit lines BL21-BL2m of plane 142. For example, word lines WL11-WL1n, WL21-WL2n or bit lines BL11-BL1m, BL21-BL2m may be floated, exposed to a low voltage, or grounded to deselect word lines WL11-WL1n, WL21-WL2n or bit lines BL11-BL1m, BL21-BL2m.

[0033] In some embodiments, the AND gate 101 may receive a first block address signal instead of the plane address signal Spr1 to generate a first block select signal (replacing the plane select signal Ssp1), and the AND gate 102 may receive a second block address signal instead of the plane address signal Spr2 to generate a second block select signal (replacing the plane select signal Ssp2). The control circuit 100 may generate a bit line address signal Scadr1 according to the first block select signal, generate a bit line address signal Scadr2 according to the second block select signal, and generate a word line address signal Sradr according to the first block select signal and the second block select signal. In some embodiments, when it is determined to pause block 141B1, control circuit 100 may set pause signal Sss1 to logic low, AND gate 101 may interrupt the first block select signal in response to pause signal Sss1 by setting the first block select signal to logic low, and control circuit 100 may generate word line address signal Sradr and bit line address signal Scadr1 to deselect word lines WL11 to WL1n and bit lines BL11 to BL1m of plane 141. Similarly, when it is determined to pause block 142B1, control circuit 100 may set pause signal Sss2 to logic low, and AND gate 102 may interrupt the second block select signal in response to pause signal Sss2 by setting the second block select signal to logic low, and control circuit 100 may generate word line address signal Sradr and bit line address signal Scadr2 to deselect word lines WL21 to WL2n and bit lines BL21 to BL2m of plane 142.

[0034] In summary, the present invention simultaneously programs at least two planes of a memory device to achieve a multi-plane programming scheme. When at least one plane has been successfully programmed but the other planes have not yet been successfully programmed, at least one plane is bypassed and the other planes are still programmed. By bypassing at least one plane once it passes all verifications, programming disturb in at least one plane can be eliminated.

[0035] Those skilled in the art will immediately recognize that numerous modifications and variations of the devices and methods may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. [Explanation of symbols]

[0036] 10 Memory Devices 100 control circuit 101, 102 AND gate 120 Word Line Driver 131, 132 Bit Line Driver 141, 142 Plain 141B1~141Bi, 142B1~142Bi blocks BL11~BL1m, BL21~BL2m bit lines CSL1, CSL2 common source line GSL1, GSL2 Ground selection lines Scadr1, Scadr2 bit line address signals Sdb1, Sdb2 disable signals Smn main signal Spr1, Spr2 plane address signals Sradr Word line address signal SSL1, SSL2 string selection line Ssp1, Ssp2 plane selection signals Sss1, Sss2 Pause signal Vpp1~Vpp6 programming pulse WL11~WL1n, WL21~WL2n word lines

Claims

1. The first plane and The second plane, coupled to the first plane and the second plane; beginning to program the first plane and the second plane simultaneously; if the first plane is successfully programmed, the second plane is not successfully programmed, and the programming pulse count of the second plane is less than a predetermined programming pulse count value; adjusting programming control signals of the first plane; configured to continue programming the second plane and bypass the first plane by maintaining the main signals of the first plane and the second plane; Control circuit and A memory device comprising:

2. The control circuit bypassing the first plane if the first plane is successfully programmed; further configured to continue programming the second plane if the first plane is bypassed, the second plane is not successfully programmed, and the programming pulse count of the second plane is less than the predetermined programming pulse count value.

10. The memory device of claim 1.

3. To bypass the first plane, the control circuitry interrupting a plane select signal associated with the first plane; interrupting a block select signal associated with the first plane; deselecting all word lines of the first plane; or deselecting all bit lines of the first plane; further configured to perform at least one of 3. The memory device of claim 2.

4. The control circuit bypassing the first plane if the first plane is successfully programmed; further configured to bypass the second plane if the programming pulse count of the second plane is greater than or equal to the predetermined programming pulse count value.

3. The memory device of claim 2.

5. The control circuit applying a programming pulse to at least a first word line coupled to one or more first memory cells in the first plane and to at least a second word line coupled to one or more second memory cells in the second plane; Increasing the programming pulse count of the first plane and the programming pulse count of the second plane Further configured as follows:

10. The memory device of claim 1.

6. The control circuit 6. The memory device of claim 5, further configured to determine that the first plane was successfully programmed and the second plane was not successfully programmed if a first number of the first memory cells that were not successfully programmed is less than a preset number and a second number of the second memory cells that were not successfully programmed is greater than the preset number.

7. The control circuit applying a programming pulse to the second plane: increasing the programming pulse count of the second plane; Further comprised of:

10. The memory device of claim 1.

8. The control circuit further configured to adjust a programming status signal of the second plane if the programming pulse count of the second plane is greater than or equal to the predetermined programming pulse count value.

5. The memory device of claim 4.

9. The control circuit further configured to verify whether the first memory cell and the second memory cell are successfully programmed, and a third number of times the first memory cell is to be verified is less than a fourth number of times the second memory cell is to be verified.

6. The memory device of claim 5.

10. 1. A method of programming a memory device, comprising: beginning to program the first plane and the second plane simultaneously; if the first plane is successfully programmed and the second plane is not successfully programmed and the programming pulse count of the second plane is less than a predetermined programming pulse count value, continuing to program the second plane and bypassing the first plane; adjusting programming control signals of the first plane; maintaining a main signal of the first plane and the second plane; A method comprising:

11. Continuing to program the second plane and bypassing the first plane includes: if the first plane is successfully programmed, bypassing the first plane; and continuing to program the second plane if the first plane is bypassed, the second plane is not successfully programmed, and the programming pulse count of the second plane is less than the predetermined programming pulse count value. The method of claim 10.

12. The step of bypassing the first plane includes: interrupting a plane select signal associated with the first plane; interrupting a block select signal associated with the first plane; deselecting all word lines of the first plane; or deselecting all bit lines of the first plane; at least one of: The method of claim 11.

13. if the second plane is successfully programmed, bypassing the first plane; and bypassing the second plane if the programming pulse count of the second plane is equal to or greater than the predetermined programming pulse count value. The method of claim 11.

14. applying a programming pulse to at least a first word line coupled to one or more first memory cells in the first plane and to at least a second word line coupled to one or more second memory cells in the second plane; and increasing the programming pulse count of the first plane and the programming pulse count of the second plane. The method of claim 10.

15. determining that the first plane was successfully programmed and that the second plane was not successfully programmed includes: determining that the first plane is successfully programmed and the second plane is not successfully programmed if a first number of the first memory cells that are not successfully programmed is less than a preset number and a second number of the second memory cells that are not successfully programmed is greater than the preset number; The method of claim 14.

16. Continuing to program the second plane includes: applying a next programming pulse to the second plane; increasing the programming pulse count of the second plane; 11. The method of claim 10, further comprising:

17. 14. The method of claim 13, further comprising adjusting a programming state signal of the second plane if the programming pulse count of the second plane is greater than or equal to the predetermined programming pulse count value.

18. 15. The method of claim 14, further comprising verifying whether the first memory cell and the second memory cell are successfully programmed, wherein a third number of times the first memory cell is to be verified is less than a fourth number of times the second memory cell is to be verified.

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