Display device with pixel dimming hardware

Abstract

The electronic device comprises a display device including a plurality of pixels forming an active area of ​​the display device, the active area of ​​the display device defining a curved edge portion, some pixels forming at least a part of the curved edge portion having graduated relative luminance levels determined by a hardware structure of the some pixels, such that a first pixel located at a first position of the curved edge portion of the some pixels has a first relative luminance level defined by the first pixel hardware structure and a second pixel located at a second position of the some pixels has a second relative luminance level defined by the second pixel hardware structure, the first relative luminance level being different from the second relative luminance level and the first pixel hardware structure being different from the second pixel hardware structure.

Description

[Technical Field]

[0001] Technical Field The present specification relates generally to electronic devices having display panels. [Background technology]

[0002] background An electronic device may include a display panel capable of displaying visual images. For example, a user of an electronic device may view visual images on a flat panel display while watching a movie or playing a video game. Many electronic devices include a large display that covers most of the front of the device. The electronic device may include a bezel that surrounds an active area of ​​the display. The active area of ​​the display may have rounded corners such that the boundary between the active area and the bezel is rounded. Summary of the Invention [Means for solving the problem]

[0003] overview Techniques are disclosed for dimming pixels, for example, pixels at curved display corners. The electronic device can include a display panel including a pixel array of light-emitting pixels. The array of light-emitting pixels can include an active area defined by an outline. In some examples, the outline has rounded corners. The electronic device can include an internal window, for example, for a sensor located below the display.

[0004] For displays with rounded corners, internal windows, or both, pixels on the outer edges of the curved boundary can be partially dimmed to approximate a smooth curve using square or rectangular pixels. The pixel circuits of the dimmed pixels include a diode-connected transistor connected to the anode electrode of the respective pixel OLED such that a portion of the current bypasses the OLED to achieve dimming.

[0005] The dimming level of a pixel can be controlled in design by adjusting the aspect ratio of the diode-connected transistor, by adjusting the bias voltage (VBIAS) of the diode-connected transistor during runtime, or both. In some examples, the aspect ratio and / or VBIAS of the diode-connected transistor can be varied for different subpixels of a pixel. In some examples, the VBIAS of the diode-connected transistor can be varied with different display brightness settings.

[0006] As additional explanation to the embodiments described below, the present disclosure describes the following embodiments.

[0007] Embodiment 1 is directed to an electronic device comprising a display device including a plurality of pixels forming an active area of ​​the display device, the active area of ​​the display device defining a curved edge portion, some pixels forming at least a part of the curved edge portion having graduated relative luminance levels determined by a hardware structure of the some pixels, such that a first pixel of the some pixels located at a first position of the curved edge portion has a first relative luminance level defined by the first pixel hardware structure, and a second pixel of the some pixels located at a second position of the curved edge portion has a second relative luminance level defined by the second pixel hardware structure, the first relative luminance level being different from the second relative luminance level, and the first pixel hardware structure being different from the second pixel hardware structure.

[0008] Embodiment 2 is the electronic device of embodiment 1, wherein the first pixel is adjacent to the second pixel in the display device.

[0009] Embodiment 3 is an electronic device described in any one of embodiments 1 to 2, wherein the first relative luminance level comprises a first default dimmed luminance level that is dimmed relative to a first programmed luminance level programmed into the first pixel, and the second relative luminance level comprises a second default dimmed luminance level that is dimmed relative to a second programmed luminance level programmed into the second pixel.

[0010] Embodiment 4 is the electronic device of embodiment 3, wherein the display device includes a plurality of central pixels forming a central region of the display device offset from the curved edge portion, and each central pixel of the plurality of central pixels forming the central region of the display device is configured to emit a brightness level programmed therefor.

[0011] Embodiment 5 is the electronic device of embodiment 4, wherein the central pixels form a contiguous block of at least 100 pixels offset from the curved edge portion.

[0012] Embodiment 6 is the electronic device of any one of embodiments 1 to 5, wherein the first pixel comprises a first organic light-emitting diode (OLED) and the second pixel comprises a second OLED.

[0013] Embodiment 7 is the electronic device of any one of embodiments 1 to 6, wherein the first pixel includes a first light-emitting diode (LED), a first resistive element, and a first drive transistor configured to drive current in parallel through the first LED and the first resistive element during light emission by the first LED, and the second pixel includes a second LED, a second resistive element, and a second drive transistor configured to drive current in parallel through the second LED and the second resistive element during light emission by the second LED.

[0014] Embodiment 8 is the electronic device of embodiment 7, wherein the first resistive element has a first resistance that is a first ratio to the resistance of the first LED, and the second resistive element has a second resistance that is a second ratio to the resistance of the second LED, the first ratio being different from the second ratio.

[0015] Embodiment 9 is an electronic device described in any one of embodiments 7 to 8, wherein the display device includes a plurality of central pixels forming a central region of the display device offset from the curved edge portion, and each central pixel of the plurality of central pixels forming the central region of the display device includes a corresponding central pixel LED and a corresponding central pixel drive transistor, and the corresponding central pixel drive transistor is configured to drive current through the corresponding central pixel LED without driving current through a corresponding resistive element in parallel with the corresponding central pixel LED.

[0016] Embodiment 10 is the electronic device of any one of embodiments 7 to 9, wherein the first resistive element comprises a first diode-connected transistor, the first diode-connected transistor including a first diode-connected transistor gate terminal and a first diode-connected transistor drain terminal connected to the first diode-connected transistor gate terminal; and the second resistive element comprises a second diode-connected transistor, the second diode-connected transistor including a second diode-connected transistor gate terminal and a second diode-connected transistor drain terminal connected to the second diode-connected transistor gate terminal.

[0017] Embodiment 11 is the electronic device of embodiment 10, wherein the first diode-connected transistor has a first resistance that is a first ratio to a resistance of the first LED, and the second diode-connected transistor has a second resistance that is a second ratio to a resistance of the second LED, the first ratio being different from the second ratio.

[0018] Example 12 is the electronic device of Example 11, wherein the first diode-connected transistor has a first resistance due to the first diode-connected transistor having physical dimensions with a first aspect ratio, and the second diode-connected transistor has a second resistance due to the second diode-connected transistor having physical dimensions with a second aspect ratio, and the first aspect ratio is different from the second aspect ratio.

[0019] Embodiment 13 is an electronic device described in any one of embodiments 10 to 12, wherein the first pixel is a subpixel of a first composite pixel in a display device, the second pixel is a subpixel of a second composite pixel in the display device, and the first LED of the first pixel emits the same color as the second LED of the second pixel, such that the first pixel and the second pixel represent subpixels of the same color.

[0020] Embodiment 14 is the electronic device of embodiment 13, wherein the drain terminal of the first diode-connected transistor is connected to a first bias voltage and the drain terminal of the second diode-connected transistor is connected to the first bias voltage.

[0021] Example 15 is the electronic device of example 14, wherein the display device is configured such that increasing the first bias voltage increases the first resistance of the first diode-connected transistor and increases the second resistance of the second diode-connected transistor.

[0022] Embodiment 16 is a display device including a third pixel, the third pixel including a third LED, a third resistive element comprising a third diode-connected transistor including a third diode-connected transistor gate terminal and a third diode-connected transistor drain terminal connected to the third diode-connected transistor gate terminal, and a third drive transistor configured to drive current in parallel through the third LED and the third diode-connected transistor during emission of light by the third LED; and the display device further includes a fourth pixel, the fourth pixel including a fourth LED, a fourth diode-connected transistor connected to the fourth diode-connected transistor gate terminal and the fourth diode-connected transistor drain terminal. 16. The electronic device of any one of embodiments 14 to 15, further comprising: a fourth resistive element comprising a fourth diode-connected transistor including a diode-connected transistor drain terminal; and a fourth drive transistor configured to drive current in parallel through the fourth LED and the fourth diode-connected transistor during emission of light by the fourth LED; wherein the third pixel is a subpixel of a first composite pixel, the fourth pixel is a subpixel of a second composite pixel, the third LED of the third pixel emits the same color as the fourth LED of the fourth pixel, and therefore the third pixel and the fourth pixel represent subpixels of the same color, and the color emitted by the first pixel and the second pixel is different from the color emitted by the third pixel and the fourth pixel.

[0023] Embodiment 17 is the electronic device of embodiment 16, wherein the drain terminal of the third diode-connected transistor is connected to a second bias voltage and the drain terminal of the fourth diode-connected transistor is connected to a second bias voltage, the second bias voltage being different from the first bias voltage.

[0024] Embodiment 18 is the electronic device of embodiment 7, wherein the first drive transistor is connected to the first LED through a first intermediate transistor in series between the first drive transistor and the first LED, and the second drive transistor is connected to the second LED through a second intermediate transistor in series between the second drive transistor and the second LED.

[0025] Embodiment 19 is a display device including a number of light emitting diodes (LEDs), the number of LEDs including a first LED of the number of LEDs including a first LED anode terminal and a first LED cathode terminal; a first drive transistor including a first drive transistor source terminal, a first drive transistor gate terminal, and a first drive transistor drain terminal, the first drive transistor drain terminal being connected to the first LED anode terminal; and a first resistive element connected to the first drive transistor drain terminal, wherein the display device is configured such that a current flows through the first LED and the first resistive element during emission of the first LED. a second LED of the number of LEDs, the number of LEDs further including a second LED anode terminal and a second LED cathode terminal; a second drive transistor including a second drive transistor source terminal, a second drive transistor gate terminal, and a second drive transistor drain terminal, the second drive transistor drain terminal connected to the second LED anode terminal; and a second resistive element connected to the second drive transistor drain terminal, wherein the display device is configured such that current flows through the second LED and the second resistive element during emission of the second LED.

[0026] Embodiment 20 is a display device as described in embodiment 19, wherein the first resistive element has a first resistance that is a first ratio to the resistance of the first LED, and the second resistive element has a second resistance that is a second ratio to the resistance of the second LED, and the first ratio is different from the second ratio.

[0027] Embodiment 21 is a display device as described in embodiment 20, in which several LEDs form a pixel array, a first LED is at least part of a first pixel that is part of an edge of the active display area of ​​the pixel array, a second LED is at least part of a second pixel that is part of the edge of the active display area of ​​the pixel array, and the first pixel is adjacent to the second pixel.

[0028] Embodiment 22 is a display device as described in embodiment 21, comprising: a group of third LEDs among the number of LEDs, wherein each respective third LED in the group of third LEDs includes a third LED anode terminal and a third LED cathode terminal; and a group of third drive transistors corresponding to the group of third LEDs, wherein each respective third drive transistor in the group of third drive transistors includes a third drive transistor source terminal, a third drive transistor gate terminal, and a third drive transistor drain terminal, wherein the third drive transistor drain terminal of each respective third drive transistor is connected to the third LED anode terminal of the corresponding third LED in the group of third LEDs, and the third drive transistor drain terminal of each respective third drive transistor is not connected to a group of source terminals of a resistive element through which current flows during emission of the corresponding third LED.

[0029] Embodiment 23 is a display device as described in embodiment 22, wherein the display device is configured such that (i) a current flows through the first resistive element during emission of the first LED, (ii) a current flows through the second resistive element during emission of the second LED, and (iii) each respective third drive transistor has no connection to the source terminal of the resistive element through which current flows during emission of the corresponding third LED, such that (i) the first LED emits a first default dim level for the group of third LEDs, and (ii) the second LED emits a second default dim level for the group of third LEDs.

[0030] Embodiment 24 is the display device of embodiment 22, wherein the third group of LEDs forms a contiguous block of at least 100 pixels offset from an edge of the active display area of ​​the pixel array.

[0031] Embodiment 25 is a display device as described in embodiment 24, wherein the edges of the active display area of ​​the pixel array are curved edges of the active display area of ​​the pixel array.

[0032] Embodiment 26 is the display device of any one of embodiments 19 to 25, wherein the first LED is an organic LED (OLED) and the second LED is an OLED.

[0033] Embodiment 27 is a display device described in any one of embodiments 19 to 26, wherein the first resistive element comprises a first diode-connected transistor, the first diode-connected transistor including a first diode-connected transistor source terminal, a first diode-connected transistor gate terminal, and a first diode-connected transistor drain terminal, the first diode-connected transistor gate terminal being connected to the first diode-connected transistor drain terminal; and the second resistive element comprises a second diode-connected transistor, the second diode-connected transistor including a second diode-connected transistor source terminal, a second diode-connected transistor gate terminal, and a second diode-connected transistor drain terminal, the second diode-connected transistor gate terminal being connected to the second diode-connected transistor drain terminal.

[0034] Embodiment 28 is the display device of embodiment 27, wherein the first diode-connected transistor has a first resistance that is a first ratio to the resistance of the first LED, and the second diode-connected transistor has a second resistance that is a second ratio to the resistance of the second LED, the first ratio being different from the second ratio.

[0035] Embodiment 29 is the display device of embodiment 28, wherein the first diode-connected transistor has a first resistance due to the first diode-connected transistor having physical dimensions with a first aspect ratio, and the second diode-connected transistor has a second resistance due to the second diode-connected transistor having physical dimensions with a second aspect ratio, and the first aspect ratio is different from the second aspect ratio.

[0036] Embodiment 30 is a display device as described in embodiment 28, wherein the first LED is a subpixel of a first pixel in a pixel array, the second LED is a subpixel of a second pixel in the pixel array, and the first LED emits the same color as the second LED, such that the first LED and the second LED represent subpixels of the same color.

[0037] Embodiment 31 is a display device as described in embodiment 30, wherein the drain terminal of the first diode-connected transistor is connected to a first bias voltage and the drain terminal of the second diode-connected transistor is connected to the first bias voltage.

[0038] Embodiment 32 is the display device of embodiment 31, wherein the display device is configured such that increasing the first bias voltage increases the first resistance of the first diode-connected transistor and increases the second resistance of the second diode-connected transistor.

[0039] Embodiment 33 is a display device comprising: a third LED of the number of LEDs, the third LED including a third LED anode terminal and a third LED cathode terminal; a third drive transistor including a third drive transistor source terminal, a third drive transistor gate terminal, and a third drive transistor drain terminal, the third drive transistor drain terminal being connected to the third LED anode terminal; and a third resistive element connected to the third drive transistor drain terminal, wherein the display device is configured such that a current flows through the third LED and the third resistive element during emission of the third LED; and the display device further comprises a fourth LED of the number of LEDs, the fourth LED including a fourth LED anode terminal and a fourth LED cathode terminal; and a fourth drive transistor source terminal, a third drive transistor gate terminal, and a third drive transistor drain terminal. a fourth drive transistor including a fourth drive transistor drain terminal, the fourth drive transistor drain terminal being connected to the fourth LED anode terminal, and a fourth resistive element connected to the fourth drive transistor drain terminal; wherein the display device is configured such that current flows through the fourth LED and the fourth resistive element during emission of the fourth LED; the third LED is a subpixel of a first pixel in the pixel array, the fourth LED is a subpixel of a second pixel in the pixel array, the third LED emits the same color as the fourth LED, such that the first LED and the second LED represent subpixels of the same color, and the color emitted by the first LED and the second LED is different from the color emitted by the third LED and the fourth LED.

[0040] Embodiment 34 is the display device of embodiment 33, wherein the drain terminal of the third diode-connected transistor is connected to a second bias voltage, and the drain terminal of the fourth diode-connected transistor is connected to a second bias voltage, and the second bias voltage is different from the first bias voltage.

[0041] Embodiment 35 is a display device described in any one of embodiments 19 to 34, wherein the drain terminal of the first drive transistor is connected to the anode terminal of the first LED via the source terminal and drain terminal of the first intermediate transistor, respectively, and the drain terminal of the second drive transistor is connected to the anode terminal of the second LED via the source terminal and drain terminal of the second intermediate transistor, respectively.

[0042] Embodiment 36 is a display device including a number of light emitting diodes (LEDs) forming a pixel array, the LED being a first LED of the number of LEDs, the first LED including a first LED anode terminal and a first LED cathode terminal, and being at least part of a first pixel that is part of an edge of an active display area of ​​the pixel array; a first drive transistor including a first drive transistor source terminal, a first drive transistor gate terminal, and a first drive transistor drain terminal, the first drive transistor drain terminal being connected to the first LED anode terminal; and a first diode-connected transistor connected to the first drive transistor drain terminal, wherein the display device drives the first LED and the first diode-connected transistor during emission of the first LED. a second LED of the number of LEDs, the second LED including a second LED anode terminal and a second LED cathode terminal, the second LED being at least part of a second pixel at an edge of an active display area of ​​the pixel array; a second drive transistor including a second drive transistor source terminal, a second drive transistor gate terminal, and a second drive transistor drain terminal, the second drive transistor drain terminal connected to the second LED anode terminal; and a second diode-connected transistor connected to the second drive transistor drain terminal, wherein the display device is configured to cause current to flow through the second LED and the second diode-connected transistor during emission of the second LED.

[0043] Embodiment 37 is the display device of embodiment 36, wherein the first diode-connected transistor has a first resistance that is a first ratio to the resistance of the first LED, and the second diode-connected transistor has a second resistance that is a second ratio to the resistance of the second LED, the first ratio being different from the second ratio, the drain terminal of the first diode-connected transistor is connected to a first bias voltage, and the drain terminal of the second diode-connected transistor is connected to the first bias voltage, and the display device is configured such that increasing the first bias voltage increases the first resistance of the first diode-connected transistor and increases the second resistance of the second diode-connected transistor.

[0044] Embodiment 38 is a display device described in any one of embodiments 36 or 37, comprising: a group of third LEDs among the number of LEDs, wherein each respective third LED in the group of third LEDs includes a third LED anode terminal and a third LED cathode terminal; and a group of third drive transistors corresponding to the group of third LEDs, wherein each respective third drive transistor in the group of third drive transistors includes a third drive transistor source terminal, a third drive transistor gate terminal, and a third drive transistor drain terminal, wherein the third drive transistor drain terminal of each respective third drive transistor is connected to the third LED anode terminal of the corresponding third LED in the group of third LEDs, and the third drive transistor drain terminal of each respective third drive transistor is not connected to the source terminal of a diode-connected transistor through which LED current will flow during the corresponding third emission. [Effects of the Invention]

[0045] The disclosed techniques can be used to improve the smoothness of curved display corners in the active display area by dimming pixels located at or near the corners. The disclosed techniques can reduce power consumption of the display SoC and DDIC compared to other techniques for dimming pixels. The disclosed techniques can also improve the smooth appearance of curved corners.

[0046] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0047] [Figure 1] FIG. 1 is a diagram of an exemplary electronic device having a display panel and a bezel. [Figure 2] FIG. 1 is a diagram of a display system of an electronic device. [Figure 3] 3A and 3B are diagrams illustrating an example of a pixel in a curved display corner. [Figure 4] FIG. 1 shows an example of dimming pixels in a curved display corner. [Figure 5] 5A and 5B are an exemplary circuit diagram of a pixel and a timing diagram of the pixel. [Figure 6] FIG. 10 illustrates an example circuit for dimmed pixels in curved display corners. [Figure 7] 7A and 7B are diagrams illustrating exemplary transistors for a dimmed pixel in a curved display corner. [Figure 8] 1 is a table showing the relationship between pixel brightness and changes in bias voltage and transistor width-to-length ratio. DETAILED DESCRIPTION OF THE INVENTION

[0048] Like reference numbers and designations in the various drawings refer to like elements. Detailed Description FIG. 1 is a diagram of an exemplary display panel 100 having a display active area 104 and a bezel 108. The display panel 100 can be incorporated into an electronic device, such as a smartphone, a television, a smartwatch, or a handheld game console. The display panel 100 includes an array of several light-emitting pixels. The display panel 100 can be, for example, an active matrix organic light-emitting diode (OLED) panel or a light-emitting diode (LED) liquid crystal display (LCD) panel. The display panel 100 can be contained in a housing. The housing is sometimes referred to as a housing.

[0049] The display panel 100 includes a top edge 112, left and right side edges 118, and a bottom edge 114. The display panel 100 includes a bezel 108. The area between the edges of the display panel 100 and the edges of the display active area 104 is the bezel 108. The bezel 108 surrounds the array of light-emitting pixels of the display panel 100. The bezel 108 may include driver circuitry for the display panel 100, power supply lines, and signal lines between the display control circuitry and the integrated driver circuitry or pixels. The active area 104 is bounded by an outline 120. The outline 120 separates the active area 104 from a bezel 122.

[0050] The display panel 100 includes a sensor window, for example, the display panel 100 defines a camera window 130. The camera window 130 is an area of ​​the display panel 100 that corresponds to the location of a sensor of an electronic device. The sensor may be, for example, a camera. The camera window 130 is an area of ​​the display panel 100 where no pixels are active. The camera window 130 is bounded by a camera outline 140. The camera outline 140 separates the camera window 130 from the active area 104. The camera outline 140 may be referred to as an interior edge of the active area 104.

[0051] The light intensity of a pixel can be determined by a grayscale value. The light intensity of a pixel can be represented as a grayscale value that includes integers from zero to 255, representing an exemplary 8-bit grayscale display. Other grayscale value ranges can be used. For example, grayscale values ​​can range from zero to 1023 for a 10-bit display or from zero to 65535 for a 16-bit display. Other possible grayscale value ranges can include the range from zero to 1 with fractional values ​​in between, and the range from zero percent (%) to 100%.

[0052] In a full-color display that spatially combines colors, each pixel can include several color channels or subpixels. In some examples, each pixel can include red, green, and blue subpixels. In some examples, each pixel can include cyan, magenta, and yellow subpixels. The light intensity of each subpixel can be represented using grayscale values ​​as described above, e.g., integers between 0 and 255 for an 8-bit display.

[0053] FIG. 2 is a diagram of an exemplary display system 200 of a display panel. For example, FIG. 2 can show the display system 200 of the display panel 100. The display system 200 is an OLED display system including an array 212 of light-emitting pixels. Each light-emitting pixel includes an OLED. The OLED display is driven by a driver including a scan / emission driver 208 and a data driver 210. Generally, the scan / emission driver 208 selects a row of pixels in the display, and the data driver 210 provides data signals (e.g., voltage data) to the pixels in the selected row according to image data to illuminate the selected OLED. Signal lines, such as scan lines, emission lines, and data lines, can be used to control the pixels to display an image on the display. Although FIG. 2 shows the display system 200 with the scan / emission driver 208 on one side, the scan / emission driver 208 can be located on both the left and right sides of the display to improve driving performance (e.g., speed).

[0054] The display system 200 includes a pixel array 212 that includes a plurality of light-emitting pixels, e.g., pixels P11 through P43. A pixel is a small element on a display that can change color based on image data provided to it. Each pixel in the pixel array 212 can be separately addressed to produce various intensities of color. The pixel array 212 extends in a plane and includes rows and columns. The rows extend horizontally across the array. For example, the first row of the pixel array 212 includes pixels P11, P12, and P13. The columns extend vertically down the display. For example, the first column of the pixel array 212 includes pixels P11, P21, P31, and P41. For simplicity, only a few pixels are shown in FIG. 2 . In reality, the pixel array 212 may include millions of pixels. A larger number of pixels allows for higher image resolution.

[0055] The display system 200 includes a scan / emission driver 208 and a data driver 210. The scan / emission driver 208 is an integrated, or stacked, row line driver that provides signals to rows of a pixel array 212. For example, the scan / emission driver 208 provides scan signals S1 through S4 and emission signals E1 through E4 to the row pixels. The data driver 210 provides signals to columns of the pixel array 212. For example, the data driver 210 provides data signals D1 through D4 to the column pixels.

[0056] Each pixel in pixel array 212 is addressable by horizontal scan lines and emission lines and vertical data lines. For example, pixel P11 is addressable by scan line S1, emission line E1, and data line D1. In another example, pixel P32 is addressable by scan line S3, emission line E3, and data line D2.

[0057] The display system 200 includes a controller 206 that receives display input data 202. The controller 206 may include a graphics controller and a timing controller. The controller generates timing signals for sending to the display. The controller 206 provides input signals (e.g., clock signals, start pulses) to a scan / emission driver 208 and image data to a data driver 210.

[0058] The scan / emission driver 208 and the data driver 210 provide signals to the pixels so that the pixels can reproduce images on the display. The scan / emission driver 208 and the data driver 210 provide signals to the pixels via scan lines, emission lines, and data lines. To provide signals to the pixels, the scan / emission driver 208 selects a scan line and controls the emission operation of the pixel. The data driver 210 provides data signals to the pixels addressable by the selected scan line according to image data to light up the selected OLED.

[0059] While Figure 2 shows an OLED display, the technique for reducing the corner bezel size of a display can be used for any flat panel display that contains an array of pixels. For example, the technique for reducing the corner bezel size of a display can be used for light-emitting diode (LED) liquid crystal displays (LCDs) and plasma display panels (PDPs).

[0060] Figures 3A and 3B show examples of pixels in curved display corners. Figure 3A shows a display panel 300 having a display system that dims pixels in curved display corners. Display panel 300 includes a pixel array 302. Figure 3B shows a detailed view of the upper right corner 132 of display panel 300, including an upper right portion of pixel array 302.

[0061] 3A and 3B show the top right corner of the display panel 300, the techniques for reducing the bezel size at the corners of the display can also be used in other corner areas of the display panel 300, such as the top left corner. FIG. 3B shows a top right portion 320 of the pixel array 302 in the top corner of the display panel 300.

[0062] Pixels often have a square or rectangular shape. Therefore, when a display has a curved outline, the shape of the outline of the active area is not strictly curved. Rather, the outline has a jagged shape similar to a staircase. This makes the curved edges of the display screen less smooth. To achieve a perceived smoother curved shape, the luminance of individual pixels at the curved edge is gradually reduced depending on the amount of overlap of the active area of ​​the pixel.

[0063] Outline 120 is a target outline that follows a smooth curve. Using square or rectangular pixels, the disclosed techniques can be used to light up pixels to approximate outline 120. Outline 120 is approached by progressively dimming pixels at or near outline 120.

[0064] Pixels are progressively dimmed from inside outline 120 to outside outline 120. With reference to FIG. 4 , the directions of "inside" and "outside" are represented by arrows 420. Generally, "inside" refers to a direction away from outline 120 toward the brightest pixels of the active area. "Outside" refers to a direction away from outline 120 toward an edge of the display panel, e.g., edge 118. While FIG. 4 illustrates a corner of an exemplary display, e.g., corner 132, the pixel dimming techniques described with reference to FIG. 4 can also be applied to an internal window of the display, e.g., camera window 130. Thus, the disclosed techniques can be applied to both the external and internal edges of the active area of ​​a display.

[0065] In some examples, all pixels within the outline are at full brightness, all pixels outside the outline are at full dimming, and pixels along the outline are dimmed in small increments in a gradual pattern. The pixels shown in Figure 4 are dimmed to various dimming levels, and each such pixel is dimmed using a current divider in the corresponding pixel circuit that reduces the amount of current flowing through the OLED. The current divider includes a resistive element, such as a diode-connected transistor. The current divider is described in further detail with reference to Figure 6.

[0066] In some examples, not all pixels of a display include a current divider. For example, pixels that are not on or near a curved edge may not include a current divider. Referring to FIG. 4, pixel 401 is located inside outline 120 away from the edge. In some examples, pixel 401 is one of a group of pixels that do not include a current divider with a diode-connected transistor. In some examples, pixel 401 is part of a contiguous block of at least 100 pixels offset from an edge of pixel array 302. When pixel 401 is “on,” e.g., emitting light, pixel 401 is not dimmed because it does not include a current divider. Thus, pixel 401 may be referred to as a maximum brightness pixel (notwithstanding the ability of a computing device having the display of FIG. 4 to dim pixel 401 by changing the duty cycle at which pixel 401 emits light and / or the amount of current sourced to pixel 401 by the pixel drive transistor).

[0067] Similarly, pixel 430 is located outside of outline 120, away from the edge. In some embodiments, pixel 430 does not include a current divider. When pixel 430 is “on,” e.g., emitting light, pixel 430 is not dimmed because it does not include a current divider. Thus, pixel 430 may be referred to as a maximum brightness pixel. However, because it is located outside outline 120, pixel 430 is generally “off,” e.g., does not emit light. Because pixel 430 is generally “off” during normal operation of the display device, it cannot be considered part of the active display area of ​​the display. In some implementations, a display device can be constructed having a design similar to that of FIG. 4, except that the display does not include pixels that are “outside” ideal outline 120.

[0068] The edge of pixel array 302 is a curved edge defined by outline 120. In the example of Figure 4, pixels 403, 404, 406, 408, and 412 are located at or near the edge defined by outline 120 (e.g., an ideal outline would pass through the pixel). The pixel circuits of pixels 403, 404, 406, 408, and 412 each include a current divider that includes a diode-connected transistor. Differences in the physical properties of the diode-connected resistors result in differences in the dimming levels of pixels 403, 404, 406, 408, and 412 when compared to one another.

[0069] Pixels 403, 404, 406, 408, and 412 exhibit gradual dimming from inside to outside. Pixel 406 is split approximately evenly between inside and outside outline 120 and is dimmed 50%. Pixels 403 and 404 are mostly inside outline 120 and are dimmed 10% and 30%, respectively. Pixels 408 and 412 are mostly outside outline 120 and are dimmed 70% and 90%, respectively.

[0070] 4 as having five dim levels (e.g., 10%, 30%, 50%, 70%, and 100%), other dim levels are possible. For example, pixel array 302 can have any suitable number of dim levels, such as 6 dim levels, 8 dim levels, 10 dim levels, etc.

[0071] 4 illustrates the dimming level for each pixel based on the percentage of the pixel's area that is inside or outside the outline. For example, the percentage of pixel 404 that is inside outline 120 is smaller than the percentage of pixel 403 that is inside outline 120. Thus, pixel 404, which is dimmed by 30%, is more dimmed than pixel 403, which is dimmed by 10%. Similarly, the percentage of pixel 408 that is outside outline 120 is smaller than the percentage of pixel 412 that is outside outline 120. Thus, pixel 408, which is dimmed by 70%, is less dimmed than pixel 412, which is dimmed by 90%.

[0072] In some examples, the dimming level for each pixel can be based on the pixel's proximity to the outline. For example, pixels that overlap the outline can have a first dimming level. Pixels that are inside the outline but one pixel away from the outline can have a second dimming level, pixels that are inside the outline but two pixels away from the outline can have a third dimming level, and so on. Similarly, pixels that are outside the outline but one pixel away from the outline can have a fourth dimming level, pixels that are outside the outline but two pixels away from the outline can have a fifth dimming level, and so on.

[0073] 5A and 5B show exemplary circuitry and pixel timing diagrams for a full-brightness pixel. Figure 5A is a diagram 500 of an LED and corresponding drive circuitry for a display system (although diagram 500 could also represent an LED and corresponding drive circuitry for a subpixel, for simplicity, sometimes referred to hereinafter as pixel 500). For example, Figure 5A can show a more detailed diagram of a pixel of display system 200.

[0074] The pixel 500 is an active matrix OLED (AMOLED) pixel. The pixel 500 receives a scan signal "GW(N)" and a reset scan signal "GI(N)". The pixel 500 receives a data voltage "DATA(k)" and an emission signal "EM(N)". The pixel 500 receives a first supply voltage ELVDD and an initial reference voltage VINIT. The pixel 500 is connected to a common ground ELVSS.

[0075] The pixel 500 includes an organic light-emitting diode (OLED) 520. The OLED 520 includes a layer of organic compounds that emits light in response to a current IOLED. The organic layer is positioned between two electrodes, an anode and a cathode, such that the OLED includes an anode terminal A and a cathode terminal C. The OLED 520 is driven by a current source circuit that receives a supply voltage ELVDD. The current source circuit drives the OLED 520 to emit light.

[0076] The pixel 500 includes a storage capacitor CST, transistors T2 through T7, and an OLED drive transistor T1. The drive transistor T1 includes a source terminal S and a drain terminal D. The drain terminal D is connected to the anode terminal A of the OLED 520 (e.g., through an intermediate transistor such that the drain terminal D of T1 is connected directly by a conductor to the source terminal of the intermediate transistor, and the drain terminal of the intermediate transistor is connected directly to the anode terminal A of the OLED 520). The pixel 500 is programmed by control signals, namely, SCAN, EM, and DATA(k). The OLED current, namely, IOLED, varies based on the voltage present between the LED and the drive transistor T1.

[0077] FIG. 5B shows an example timing diagram of pixel circuit operation for pixel 500. The voltages shown in FIG. 5B are referenced to ground. During operation, pixel 500 goes through an initialization stage, a programming stage, and an emission stage. During the initialization stage, OLED 520 is turned off in preparation for programming. OLED 520 is turned off by switching off 501 the EM signal (e.g., by setting it to a high level), which turns off T5 and T6 and stops current flow through OLED 520. The pixel enters the initialization stage by receiving 502 a reset signal GI(N), which turns on T4 and sets G to VINIT.

[0078] The pixel then enters the programming stage by receiving 503 a scan signal GW(N). During the programming stage, the GW(N) signal turns on, which turns on T2, T3, and T7. Voltage data DATA(k) passes through T2, T1, and T3 to set G to DATA(k) minus at least the threshold voltage of T1. Thus, when pixel 500 receives data voltage DATA(k) during the programming stage of a frame, that voltage is programmed to the “G” node of T1.

[0079] During the emission stage, the EM(N) signal is turned on 504, which turns on T5 and T6. Current from ELVDD flows through T1 and T6 to the OLED 520, and the current level of the OLED 520 is determined by G. Thus, after the pixel 500 changes to the emission stage of a frame, a current IOLED flows through the OLED 520 based on the voltage setting at the “G” node of the drive transistor (e.g., based on the received data voltage DATA(k)), so that the OLED 520 emits light when the current IOLED flows through the OLED 520. The light intensity or brightness varies depending on the amount of applied current IOLED. When a maximum current level, e.g., 100% IOLED, flows through the OLED 520, the OLED 520 lights up at its “maximum” brightness.

[0080] Higher current generally results in brighter light. Thus, the intensity of light emitted from the OLED 520 is based on DATA(k), which is programmed into the "G" node and corresponds to the image data for the individual pixel. The storage capacitor CST maintains the state of the pixel 500 so that it remains illuminated at approximately the programmed level during the emission stage that follows the programming / addressing stage.

[0081] 6 shows an exemplary pixel circuit 600 for a dimmed pixel in a curved display corner. The circuit 600 includes a current divider. The current divider includes a resistive element, e.g., diode-connected transistor T8. Diode-connected transistor T8 is connected to the drain terminal D of the drive transistor T1 (e.g., via intermediate transistor T6). The current divider divides a current IOLED between transistor T8 and the OLED 620. Thus, during emission of the OLED 620, current flows through the OLED and diode-connected transistor T8.

[0082] The gate electrode of transistor T8 is electrically shorted to the drain electrode. Diode-connected transistor T8 is in parallel with the OLED diode. The gate and drain electrodes are connected to a bias voltage VBIAS. The OLED emission current IOLED from the pixel circuit is split into IOLED1 and IOLED2. IOLED1 flows through OLED 620, lighting the pixel. IOLED2 flows through transistor T8. For a given input current IOLED, the greater the amount of current flowing through transistor T8, the smaller the amount of current flowing through OLED 620.

[0083] The resistance of transistor T8 affects the amount of current IOLED2 flowing through transistor T8 and therefore the amount of current IOLED1 flowing through OLED 620. In one example, the resistance of transistor T8 is equal to the resistance of the OLED, and IOLED1 is equal to IOLED2. In another example, the resistance of transistor T8 is twice the resistance of OLED 620, and IOLED2 is half IOLED1. Reducing IOLED1 from maximum brightness causes OLED 620 to dim. In some examples, the OLED can be adjusted from a high brightness of about 500 nits to a low brightness of about 10 nits.

[0084] The resistance of transistor T8 can be controlled and / or adjusted using several techniques. The first technique is to control the resistance of transistor T8 based on the design of the hardware features of transistor T8. For example, transistor T8 can be designed to have a resistance that is a predetermined percentage of the resistance of the OLED. Transistor T8 is connected to the drain terminal of drive transistor T1, which reduces the brightness of the OLED according to the predetermined percentage of the resistance. The OLED is dimmed to a default dim level by the hardware features of transistor T8. The default dim level can be expressed as the dimness compared to a maximum brightness OLED with the same VBIAS.

[0085] The brightest OLED can be, for example, the OLED in a pixel where the drain terminal of the drive transistor T1 is not connected to the source terminal of the diode-connected transistor, such as the OLED in pixel 500. The brightest OLED can also be the OLED in a pixel where the drain terminal of the drive transistor T1 is connected to the source terminal of the diode-connected transistor, but where the current divider is turned off, such as the OLED in pixel 600. For example, the current divider can be turned off by VBIAS being set to a high value so that all of the current IOLED flows through OLED 620.

[0086] A computing device sending image data to a display panel can change the intensity of any given pixel by sending programming that causes a voltage difference to that respective pixel's G node. Thus, the computing device can also vary pixel intensities in software, as shown in FIG. 4. However, because the image displayed on the display panel can change from frame to frame, dimming pixels at the edge of the display in software involves recalculating the intensity level for each such pixel for each frame. For example, for each frame, the computing device must first identify the intended intensity of the edge pixel (e.g., 80%) and then reduce the intensity of that pixel to achieve the effect of a soft, "curved" edge on the display (e.g., dimming the initial 80% intensity value by 50% to achieve a final resulting intensity value of 40% written to the G node). These repeated calculations consume energy and computing bandwidth. The techniques described in this disclosure allow the percentage of dimming due to a pixel being at a curved edge to be implemented in hardware, for example, using the characteristics of a diode-connected transistor T8. Thus, the computing device simply needs to program the original image data into the pixels of the display panel, and any dimming at the edges is handled by the hardware.

[0087] In one example, transistor T8 can be designed to have a resistance that is two-thirds that of the OLED. Hardware characteristics of transistor T8 can include the aspect ratio of transistor T8. The aspect ratio is the ratio of the transistor's width to its length ("W / L ratio"). In some examples, the aspect ratio can be adjusted separately for each pixel color. For example, pixel circuit 600 can be the circuit for a subpixel, such as a red, green, or blue subpixel of a pixel. Transistor T8 of the red subpixel can have an aspect ratio that is different from the aspect ratio of the green subpixel, the blue subpixel, or both. Figures 7A and 7B show transistors with different aspect ratios.

[0088] A second technique for controlling the resistance of transistor T8 is to adjust the bias voltage VBIAS. The higher VBIAS, the smaller IOLED2 and, consequently, the larger the emission current IOLED1 through the OLED. Adjusting VBIAS causes a change in the brightness of the pixel when compared to the default dim level. In other words, adjusting VBIAS allows a computing device to change the default dim level determined by the aspect ratio of the T8 transistor.

[0089] In some examples, the subpixels of a pixel can have different bias voltages. For example, a red subpixel can have a different VBIAS than a green subpixel, a blue subpixel, or both. In some examples, VBIAS can be adjusted between a high level of about 2V and a low value of about −5V. In some examples, VBIAS can be adjusted during operation of the pixel.

[0090] To adjust the dimming level of a pixel during operation, VBIAS can be adjusted based on the brightness setting of the display. For example, a DDIC in a display system can override the dimming of pixel 600 by increasing VBIAS. VBIAS can be increased so that no current flows through transistor T8. Thus, T8 is turned off and the OLED current flows entirely through OLED 620, so that IOLED equals IOLED1. In some examples, VBIAS is a global parameter. For example, adjusting VBIAS for a red subpixel can adjust VBIAS for all red subpixels in a display panel. All subpixels in a display can receive the same VBIAS, so there can be a first VBIAS for all red subpixels, a second VBIAS for all green subpixels, and a third VBIAS for all blue subpixels.

[0091] 7A and 7B show exemplary transistors 700, 750 for dimmed pixels in curved display corners. The physical dimensions of the transistors can be adjusted from default ratios to achieve a constant resistance of the transistor. The physical dimensions can include the width and length of the transistor, which affect the aspect ratio, or W / L ratio, of the transistor.

[0092] Transistor 700 includes a drain 702, a source 704, and a gate 710. Transistor 700 also includes a substrate 706 and an oxide 708. Gate 710 has a width W1 and a length L1. The aspect ratio of transistor 700 is W1 / L1.

[0093] Transistor 750 includes a drain 712, a source 714, and a gate 720. Transistor 750 also includes a substrate 716 and an oxide 718. Gate 720 has a width W2 and a length L2. The aspect ratio of transistor 750 is W2 / L2. Width W2 is the same as width W1. Length L2 is longer than length L1. Therefore, aspect ratio W2 / L2 is less than aspect ratio W1 / L1.

[0094] Transistor 700 and transistor 750 can each be used in a current divider of a dimmed pixel. For example, transistors 700 and 750 can each be used as transistor T8 in pixel circuit 600 (e.g., for subpixels of the same color in two adjacent pixels at the edge of the active area of ​​a display). The smaller aspect ratio W2 / L2 than aspect ratio W1 / L1 causes transistor 750 to have a higher resistance than transistor 700. Thus, a first pixel circuit including transistor 700 as transistor T8 will have a higher current flow through transistor T8 than an equivalent second pixel circuit including transistor 750 as transistor T8. As a result, the first pixel circuit including transistor 700 will have a lower current flow through the OLED and will be dimmed by a greater amount than a second pixel circuit including transistor 750. Therefore, the default dimming level of the first pixel circuit will be dimmer, i.e., less bright, than the default dimming level of the second pixel circuit.

[0095] 8 is a table 800 illustrating the change in pixel brightness caused by changing the bias voltage and the transistor width-to-length ratio. As discussed above, the resistance of transistor T8 can be adjusted using two techniques. The first technique is to adjust the physical dimensions, including the W / L ratio, of the transistor. The second technique is to adjust the bias voltage VBIAS.

[0096] Configuration 801 in table 800 includes a large W / L ratio and the same VBIAS. A large W / L ratio results in a smaller resistance through transistor T8, which results in a larger IOLED2 and a smaller IOLED1. Therefore, if a first pixel has a larger W / L ratio than a second pixel and the same VBIAS as the second pixel, the first pixel will have a lower OLED brightness. For example, returning to FIG. 4, pixel 406 will have a lower brightness (50% dimming) than pixel 404 (30% dimming). This can occur because pixel 406 with a current divider has a diode-connected transistor T8 with a larger W / L ratio than the diode-connected transistor T8 in the current divider of pixel 404.

[0097] Configuration 802 in table 800 includes a small W / L ratio and the same VBIAS. A small W / L ratio results in a larger resistance through transistor T8, which results in a smaller IOLED2 and a larger IOLED1. Therefore, if a first pixel has a smaller W / L ratio than a second pixel and the same VBIAS as the second pixel, the first pixel will have a higher OLED brightness. For example, returning to FIG. 4, pixel 406 will have a higher brightness (50% dimming) than pixel 408 (70% dimming). This can occur because pixel 406 with the current divider has a diode-connected transistor T8 with a lower W / L ratio than the diode-connected transistor T8 of the current divider of pixel 408.

[0098] Configuration 803 in table 800 includes a high VBIAS and the same W / L ratio. A higher VBIAS results in a higher resistance through transistor T8, which results in a smaller IOLED2 and a larger IOLED1. Therefore, if a first pixel has a higher VBIAS than a second pixel and the same W / L ratio as the second pixel, the first pixel will have a higher OLED brightness.

[0099] Configuration 804 of table 800 includes a lower VBIAS and the same W / L ratio. A lower VBIAS results in a lower resistance through transistor T8, which results in a larger IOLED2 and a smaller IOLED1. Thus, if a first pixel has a lower VBIAS than a second pixel and the same W / L ratio as the second pixel, the first pixel will have a lower OLED brightness.

[0100] Embodiments of the present subject matter and operation of the features described herein may be implemented in any suitable electronic device, such as a personal computer, a mobile phone, a smartphone, a smart watch, a smart TV, a portable audio or video player, a gaming console, or a combination of one or more of these devices.

[0101] The electronic device may include various components, such as a memory, a processor, a display, and an input / output unit. The input / output unit may include, for example, a transceiver capable of communicating with one or more networks to transmit and receive data. The display may be any suitable display, including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), or a light emitting diode (LED) display, for displaying images.

[0102] Various implementations of the systems and techniques described herein may be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application-specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs executable and / or interpretable on a programmable system including at least one programmable processor, which may be dedicated or general-purpose coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device.

[0103] Embodiments may be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer-readable medium for execution by or to control the operation of a data processing apparatus. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter affecting a machine-readable propagated signal, or one or more combinations thereof. The term "data processing apparatus" encompasses all apparatuses, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or a multiprocessor or multicomputer. In addition to hardware, an apparatus may include code that creates an execution environment for a subject computer program, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof. A propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal that encodes information for transmission to an appropriate receiver apparatus.

[0104] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including a standalone program or modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple associated files (e.g., files storing one or more modules, subprograms, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communications network.

[0105] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor receives instructions and data from a read-only memory or a random-access memory or both.

[0106] The elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also includes one or more mass storage devices, such as magnetic, magneto-optical, or optical disks, for storing data, or is operatively coupled to receive data from, transmit data to, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data include, by way of example, all types of non-volatile memory, media, and memory devices, including semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices, magnetic disks, e.g., internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0107] While this specification contains details of many specific implementations, these should not be construed as limitations on the scope of the claims, but rather as descriptions of features that may be unique to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, while each feature is described above as operative in a certain combination and may initially be claimed by itself, in some cases, one or more features of a claimed combination can be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

Claims

1. a display device including a plurality of pixels forming an active area of ​​the display device, the active area of ​​the display device defining a curved edge portion, some pixels forming at least a part of the curved edge portion having graduated relative luminance levels determined by a hardware structure of the some pixels, such that a first pixel of the some pixels located at a first position of the curved edge portion has a first relative luminance level defined by a first pixel hardware structure, and a second pixel of the some pixels located at a second position of the curved edge portion has a second relative luminance level defined by a second pixel hardware structure, the first relative luminance level being different from the second relative luminance level, and the first pixels a first light emitting diode (LED); a first resistive element having a first adjustable resistance; a first drive transistor configured to drive current in parallel through the first LED and the first resistive element having the first adjustable resistance during light emission by the first LED; and Including, the first resistive element comprises a first diode-connected transistor including a first diode-connected transistor gate terminal and a first diode-connected transistor drain terminal connected to the first diode-connected transistor gate terminal; the first diode-connected transistor drain terminal is connected to a first bias voltage; The display device is configured such that increasing the first bias voltage increases the first adjustable resistance of the first resistive element.

2. The electronic device of claim 1 , wherein the first pixel is adjacent to the second pixel in the display device.

3. the first relative brightness level comprises a first default dimmed brightness level that is dimmed relative to a first programmed brightness level programmed into the first pixel; the second relative brightness level comprises a second default dimmed brightness level that is dimmed relative to a second programmed brightness level programmed into the second pixel; The electronic device according to any one of claims 1 to 2.

4. the display device includes a plurality of central pixels forming a central region of the display device offset from the curved edge portion; each central pixel of the plurality of central pixels forming the central region of the display device is configured to emit a brightness level programmed therefor; The electronic device according to claim 3 .

5. the plurality of central pixels form a contiguous block of at least 100 pixels offset from the curved edge portion; The electronic device according to claim 4 .

6. the first pixel comprises a first organic light emitting diode (OLED); the second pixel comprises a second OLED; The electronic device according to any one of claims 1 to 5.

7. The second pixel is a second LED; and a second resistive element having a second adjustable resistance; a second drive transistor configured to drive current in parallel through the second LED and the second resistive element having the second adjustable resistance during light emission by the second LED; and Including, The electronic device according to any one of claims 1 to 6.

8. the display device includes a plurality of central pixels forming a central region of the display device offset from the curved edge portion; each central pixel of the plurality of central pixels forming the central region of the display device includes a corresponding central pixel LED and a corresponding central pixel drive transistor, the corresponding central pixel drive transistor configured to drive current through the corresponding central pixel LED without driving current through a corresponding resistive element in parallel with the corresponding central pixel LED; The electronic device according to any one of claims 1 to 3.

9. The second resistive element comprises a second diode-connected transistor, the second diode-connected transistor including a second diode-connected transistor gate terminal and a second diode-connected transistor drain terminal connected to the second diode-connected transistor gate terminal. The electronic device of claim 7.

10. the first diode-connected transistor has a first resistance that is a first ratio to a resistance of the first LED; the second diode-connected transistor has a second resistance that is a second ratio to a resistance of the second LED; the first ratio is different from the second ratio; 10. The electronic device of claim 9.

11. the first diode-connected transistor has the first resistance by virtue of the first diode-connected transistor having physical dimensions with a first aspect ratio; the second diode-connected transistor has the second resistance by virtue of the second diode-connected transistor having physical dimensions with a second aspect ratio; the first aspect ratio is different from the second aspect ratio; The electronic device of claim 10.

12. the first pixel is a subpixel of a first composite pixel in the display device; the second pixel is a subpixel of a second composite pixel in the display device; 12. The electronic device of claim 1, wherein the first LED of the first pixel emits the same color as the second LED of the second pixel, such that the first pixel and the second pixel represent subpixels of the same color.

13. The second diode-connected transistor drain terminal is connected to the first bias voltage. The electronic device according to any one of claims 9 to 11.

14. The display device comprises: a third pixel, the third pixel comprising: a third LED; and a third resistive element having a third adjustable resistance; a third drive transistor configured to drive current in parallel through the third LED and the third resistive element having the third adjustable resistance during light emission by the third LED; and Including, The display device further comprises: a fourth pixel, the fourth pixel comprising: a fourth LED; and a fourth resistive element having a fourth adjustable resistance; a fourth drive transistor configured to drive current in parallel through the fourth LED and the fourth resistive element having the fourth adjustable resistance during light emission by the fourth LED; and Including, the third pixel is a subpixel of the first composite pixel; the fourth pixel is a subpixel of a second composite pixel; the third LED of the third pixel emits the same color as the fourth LED of the fourth pixel, so that the third pixel and the fourth pixel represent subpixels of the same color; the colors emitted by the first pixel and the second pixel are different from the colors emitted by the third pixel and the fourth pixel; The electronic device according to any one of claims 7, 9 to 11, and 13.

15. the third resistive element comprises a third diode-connected transistor including a third diode-connected transistor gate terminal and a third diode-connected transistor drain terminal connected to the third diode-connected transistor gate terminal and to a second bias voltage; the fourth resistive element comprises a fourth diode-connected transistor including a fourth diode-connected transistor gate terminal and a fourth diode-connected transistor drain terminal connected to the fourth diode-connected transistor gate terminal and to the second bias voltage; the second bias voltage is different from the first bias voltage; 15. The electronic device of claim 14.

16. 16. The electronic device of claim 1, wherein the first drive transistor is connected to the first LED via a first intermediate transistor in series between the first drive transistor and the first LED.

Images