Display devices and electronic devices

Abstract

To improve the display quality of a display.SOLUTION: A display includes a first display area, a second display area that has a lower pixel density than that of the first display area, a first metal layer, a second metal layer that is an upper layer of the first metal layer, and a third metal layer that is an upper layer of the first metal layer and the second metal layer. The occupation ratio of the third metal layer in the second display area is smaller than the occupation ratio of the third metal layer in the first display area. The first metal layer includes a first electrode that controls the amount of current in a channel of a transistor in each first pixel part. The second metal layer includes a second electrode part and a third electrode part that apply current to a channel of a drive transistor in each first pixel part. The third metal layer includes a main part that constitutes a capacity included in a first capacitive element that holds voltage for controlling the drive transistor, and an island part that is surrounded by the main part with an interval therebetween and interconnected with a lower electrode part of a light emitting device with a via part.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] OLED (Organic Light-Emitting Diode) elements are current-driven, self-emitting elements that do not require a backlight, and have the advantages of low power consumption, a wide viewing angle, and a high contrast ratio, making them promising for the development of flat panel displays.

[0003] The display area of ​​an OLED display device may include areas with different pixel densities. For example, in some mobile devices such as smartphones and tablet computers, a light-receiving element such as a camera for capturing images may be located below the display area. To receive external light, the camera is located below an area with a lower pixel density than the surrounding area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0312941 [Patent Document 2] U.S. Patent Application Publication No. 2019 / 0393294 Summary of the Invention [Problem to be solved by the invention]

[0005] The increased density of pixel circuits associated with higher resolution can cause the following problems, for example. One is that power supply wiring becomes thinner and more resistive, which can cause in-plane non-uniformity of the anode power supply voltage (Ir-drop). Another is that when the storage capacitor and wiring come close to each other, crosstalk occurs due to capacitive coupling, which can cause the voltage of the storage capacitor to deviate from the desired voltage. Furthermore, in a configuration in which a photosensor is located behind the display area as described above, the required transmittance differs between the area of ​​the display area that overlaps with the photosensor and other areas. [Means for solving the problem]

[0006] A display device according to one embodiment of the present disclosure includes a first display region for displaying an image, a second display region for displaying an image and having a lower pixel density than the first display region, a first metal layer, a second metal layer above the first metal layer, and a third metal layer above the first and second metal layers. The third metal layer has a smaller occupancy rate in the second display region than the third metal layer in the first display region. The first display region includes a plurality of first pixel units, each of which includes a light-emitting element including an upper electrode unit, a lower electrode unit, and a light-emitting layer between the upper electrode unit and the lower electrode unit, and a drive transistor for controlling light emission of the light-emitting element. The first metal layer, the second metal layer, and the third metal layer are located below the lower electrode unit. The first metal layer includes a first electrode for controlling the amount of current in the channel of the drive transistor in each of the plurality of first pixel units. The second metal layer includes a second electrode portion and a third electrode portion that provide a current to the channel of the drive transistor in each of the first pixel portions of the plurality of first pixel portions. The third metal layer includes a main portion to which a power supply potential is applied and which constitutes, between the third metal layer and the second metal layer, a capacitance included in a first capacitive element that holds a voltage that controls the drive transistor, and an island portion that is separated from the main portion, is surrounded by a gap by the main portion, and is interconnected to the lower electrode portion by a via portion.

[0007] A display device according to one embodiment of the present disclosure includes a first display region for displaying an image, a second display region for displaying an image and having a lower pixel density than the first display region, a first metal layer, a second metal layer above the first metal layer, and a third metal layer above the first and second metal layers. The pattern of the third metal layer in the second display region is different from the pattern of the third metal layer in the first display region. The first display region includes a plurality of first pixel units. Each first pixel unit includes a light-emitting element including an upper electrode unit, a lower electrode unit, and a light-emitting layer between the upper electrode unit and the lower electrode unit, and a drive transistor for controlling light emission of the light-emitting element. The first metal layer, the second metal layer, and the third metal layer are located below the lower electrode unit. The first metal layer includes a first electrode for controlling the amount of current in the channel of the drive transistor in each of the plurality of first pixel units. The second metal layer includes a second electrode portion and a third electrode portion that provide a current to the channel of the drive transistor in each of the first pixel portions of the plurality of first pixel portions. The third metal layer includes a main portion to which a power supply potential is applied and which constitutes, between the third metal layer and the second metal layer, a capacitance included in a first capacitive element that holds a voltage that controls the drive transistor, and an island portion that is separated from the main portion, is surrounded by a gap by the main portion, and is interconnected to the lower electrode portion by a via portion. [Effects of the Invention]

[0008] According to one aspect of the present disclosure, the display quality of a display device can be improved. [Brief explanation of the drawings]

[0009] [Figure 1] 1 shows a schematic configuration example of an OLED display device. [Figure 2] 1 illustrates an example of the configuration of a pixel circuit and a control signal according to an embodiment of the present specification. [Figure 3] FIG. 2 is a plan view schematically showing the device structure of one pixel portion. [Figure 4] 4 shows a schematic cross-sectional structure taken along line IV-IV' in FIG. [Figure 5A]1 shows the pattern of layers included in the laminated structure of a TFT substrate. [Figure 5B] 1 shows the pattern of layers included in the laminated structure of a TFT substrate. [Figure 5C] 1 shows the pattern of layers included in the laminated structure of a TFT substrate. [Figure 5D] 1 shows the pattern of layers included in the laminated structure of a TFT substrate. [Figure 5E] 1 shows the pattern of layers included in the laminated structure of a TFT substrate. [Figure 5F] 1 shows the pattern of layers included in the laminated structure of a TFT substrate. [Figure 5G] 1 shows the pattern of layers included in the laminated structure of a TFT substrate. [Figure 6] 10A and 10B show schematic configuration examples of a display area. [Figure 7] Schematic diagram of the layout of control wiring on a TFT substrate. [Figure 8A] 10 shows a first metal layer pattern, an intermediate conductor layer pattern, and a third metal layer pattern in another example structure of a pixel section including a third metal layer. [Figure 8B] 8B shows an intermediate conductor layer pattern and a third metal layer pattern in the structural example shown in FIG. 8A. [Figure 8C] In addition to the layer structure shown in FIG. 8A, a second metal layer pattern is shown. [Figure 9] FIG. 10 is a cross-sectional view schematically showing a cross-sectional structure of another example of the pixel portion. [Figure 10] 10 is a cross-sectional view schematically showing the cross-sectional structure of a low-density region including another example pattern of the third metal layer. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present embodiment is merely an example for realizing the present disclosure and does not limit the technical scope of the present disclosure.

[0011] In the following description, a pixel is the smallest unit in a display area, and refers to an element that emits light of a single color, and may also be called a subpixel. A set of pixels of multiple different colors, for example, red, blue, and green pixels, constitutes an element that displays one color dot, and may also be called a main pixel. In the following description, when distinguishing between elements that display a single color and elements that display a color for clarity, they will be called subpixels and main pixels, respectively. Note that the features of this specification can be applied to a display device that displays monochrome, and its display area is composed of monochrome pixels.

[0012] An example of the configuration of a display device will be described below. The display area of ​​the display device includes an area with a relatively low pixel density (also referred to as a low-density or low-resolution area) and an area with a relatively high pixel density (also referred to as a normal area or normal-resolution area). A plurality of low-density areas with a pixel density lower than that of the normal area may be arranged, and these pixel densities may be different. In the example described below, the light-emitting elements of the pixels are current-driven elements, such as OLED (Organic Light-Emitting Diode) elements.

[0013] The increased density of pixel circuits associated with higher resolution can cause the following problems, for example. One is that power supply wiring becomes thinner and more resistive, which can lead to in-plane non-uniformity of the anode power supply voltage (Ir-drop). Another is that when the storage capacitor and wiring come close to each other, crosstalk occurs due to capacitive coupling, which can prevent the storage capacitor from maintaining an accurate potential (leading to the desired light emission from the light-emitting element). Another is that when metal wiring is formed on an insulating layer or polysilicon in a flexible display device, if the wiring becomes thinner, the wiring is more likely to break when the substrate is bent.

[0014] The pixel portion of the display device according to one embodiment of the present specification includes a first metal layer including a gate electrode portion, a second metal layer including a source / drain electrode portion, and a third metal layer above these. The gate electrode portion is a first electrode portion that controls the amount of current in the channel of the transistor. The source / drain electrode portion is a second electrode portion or a third electrode portion that provides current to the channel of the transistor.

[0015] The third metal layer is given the power supply potential of the light-emitting element, and forms a storage capacitor for the driving field-effect transistor between it and the second metal layer. The display area includes a normal area and a low-density area, and the pattern of the third metal layer differs between them. This configuration reduces the Ir-Drop of the power supply potential and also provides the pixel section with characteristics suitable for the display area.

[0016] [Display device configuration] The overall configuration of a display device according to one embodiment of the present specification will be described with reference to Figure 1. Note that for clarity of explanation, the dimensions and shapes of the objects shown in the figures may be exaggerated. In the following, an OLED display device will be described as an example of the display device.

[0017] 1 schematically shows an example of the configuration of an OLED display device 10. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which OLED elements (light-emitting elements) are formed, and a sealing structure 150 that seals the OLED elements. A control circuit is arranged around a cathode electrode formation region 114 outside a display region 125 of the TFT substrate 100. Specifically, a scan driver 131, an emission driver 132, an electrostatic discharge protection circuit 133, a driver IC 134, and a demultiplexer 136 are arranged.

[0018] The driver IC 134 is connected to external devices via an FPC (Flexible Printed Circuit) 135. The scan driver 131 drives the scan lines of the TFT substrate 100. The emission driver 132 drives the emission control lines to control the light emission of each pixel. The electrostatic discharge protection circuit 133 prevents electrostatic damage to elements on the TFT substrate. The driver IC 134 is mounted using, for example, an anisotropic conductive film (ACF).

[0019] The driver IC 134 supplies power and control signals including timing signals to the scan driver 131 and the emission driver 132. Furthermore, the driver IC 134 supplies power and data signals to the demultiplexer 136. The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer equal to or greater than 2). The demultiplexer 136 switches the output data line of the data signal from the driver IC 134 d times within the scanning period, thereby driving d times as many data lines as the number of output pins of the driver IC 134.

[0020] [Pixel circuit] 2 shows an example of the configuration of a pixel circuit 200 and control signals according to an embodiment of the present specification. The pixel circuit 200 is included in an Nth (N is an integer) pixel circuit row. The pixel circuit 200 includes six transistors (TFTs) P1 to P6, each having a gate, a source, and a drain. In this example, all of the transistors P1 to P6 are P-type TFTs.

[0021] The transistor P1 is a drive transistor that controls the amount of current to the OLED element E1. The source of the drive transistor P1 is connected to a power supply line 241 that transmits a power supply potential VDD. The drive transistor P1 controls the amount of current provided to the OLED element E1 from the power supply line 241 according to the voltage held by the holding capacitance element C0. The holding capacitance element C0 holds the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to a power supply line 204 that transmits a power supply potential VEE from a cathode power supply.

[0022] 2, the capacitance element C0 is composed of a first capacitance element C1 and a second capacitance element C2 connected in series. An anode power supply potential VDD is applied to one end of the capacitance element C0, and the other end is connected to the gate of the driving transistor P1.

[0023] The storage capacitor C0 is composed of capacitors C1 and C2 connected in series between a power supply line 241 transmitting the anode power supply potential VDD and the gate of the drive transistor P1. One end of the capacitor C1 is connected to the power supply line 241. One end of the capacitor C2 is connected to the other end of the capacitor C1. The gate of the drive transistor P1 is connected to the other end of the capacitor C2. The source / drain of the transistor P4 and the source / drain of the transistor P2 are connected to the intermediate node between the capacitors C1 and C2.

[0024] The voltage of the storage capacitor element C0 is the voltage between the gate of the driving transistor P1 and the VDD power supply line 241. The source of the driving transistor P1 is connected to the VDD power supply line 241, and the source potential is the anode power supply potential VDD. Therefore, the storage capacitor element C0 holds the gate-source voltage of the driving transistor P1.

[0025] The transistor P5 is a light-emission control switch transistor that controls the supply of drive current to the OLED element E1 and the resulting ON / OFF control of light emission. The source of the transistor P5 is connected to the drain of the drive transistor P1. The transistor P5 turns ON / OFF the supply of current to the OLED element E1 connected to its drain. The gate of the transistor P5 is connected to a control signal line 232A, and the transistor P5 is controlled by a light-emission control signal Em from the emission driver 132. The light-emission control signal is a selection signal that controls the light emission of the OLED element E1.

[0026] The transistor P6 operates to supply a reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor P6 is connected to a power supply line 242 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0027] The gate of the transistor P6 is connected to the control signal line 231A, and the transistor P6 is controlled by the selection signal S1. When the transistor P6 is turned on by the selection signal S1 from the scan driver 131, it supplies the reset potential Vrst transmitted by the power supply line 242 to the anode of the OLED element E1. In addition, the transistors P5 and P6 supply the reset potential Vrst to the gate of the drive transistor P1 via the transistor P3.

[0028] The transistor P3 is a switch transistor (threshold compensation transistor) for writing a voltage for threshold correction (threshold compensation) of the driving transistor P1 to the holding capacitance element C0, and is a transistor for resetting the gate potential of the driving transistor P1. The source and drain of the transistor P3 are connected to the gate and drain of the driving transistor P1. Therefore, when the transistor P3 is ON, the driving transistor P1 is in a diode-connected state.

[0029] The transistor P4 is a switch transistor (threshold compensation transistor) for writing a voltage for threshold compensation of the drive transistor P1 to the holding capacitance element C0. The transistor P4 controls whether or not a reference potential Vref is supplied to the holding capacitance element C0. One end of the source / drain of the transistor P4 is connected to a power supply line 202 that transmits the reference potential Vref, and the other end is connected to an intermediate node between the capacitance elements C1 and C2. The gate of the transistor P4 is connected to a control signal line 231B, and the transistor P4 is controlled by a selection signal S1 input to the gate from the scanning driver 131.

[0030] The transistors P3, P6, and P4 are controlled by a selection signal S1. Therefore, these transistors P3, P6, and P4 are simultaneously turned ON / OFF. While these transistors are ON, the transistor P5 is turned ON to reset the gate potential of the driving transistor P1, and then the transistor P5 is turned OFF. When the transistors P3 and P4 are ON, the transistor P1 forms a diode-connected transistor. A threshold compensation voltage is written to the holding capacitance element C0 based on the power supply potential VDD and the reference potential Vref.

[0031] The transistor P2 is a switch transistor for selecting a pixel circuit to which a data signal is supplied and writing a data signal (data signal voltage) Vdata to the storage capacitor C0. One end of the source / drain of the transistor P2 is connected to the storage capacitor C0. The other end Connected to the data line 237 that transmits the data signal Vdata R .

[0032] The gate of the transistor P2 is connected to a control signal line 231C that transmits a selection signal S2 from the scan driver 131. The transistor P2 is controlled by the selection signal S2. The selection signal S2 is a selection signal different from the selection signal S1. In the pixel circuit 200, the selection signal S2 is used to transmit a data signal Vdat to the storage capacitor element C0. a When the transistor P2 is ON, the transistor P2 supplies the data signal Vdata supplied from the driver IC 134 via the data line 237 to the storage capacitor element C0.

[0033] [Pixel structure] The structure of the pixel unit in the display region 125 will be described below. FIG. 3 is a plan view schematically showing the device structure of one pixel unit 300. FIG. 3 also shows the entire pixel unit 300 and part of an adjacent pixel unit. The pixel unit 300 is also called a pixel region. The pixel unit 300 has the circuit configuration described with reference to FIG. 2. That is, as shown in FIG. 3, the pixel unit 300 includes six thin-film transistors P1 to P6 and two capacitive elements C1 and C2. In FIG. 3, the light-emitting element E1 is omitted for simplicity of illustration.

[0034] 3 further shows a VDD power supply line 241 that transmits a power supply potential VDD, and a power supply line 242 that transmits a reset potential Vrst. The reference potential Vref is, for example, the same as the anode power supply potential VDD. Also shown are control signal lines 231A and 231B that transmit a selection signal S1, a control signal line 231C that transmits a selection signal S2, and a control signal line 232A that transmits a light-emission control signal Em. Also shown is a data line 237 that transmits a data signal Vdata.

[0035] In FIG. 3, for the sake of illustration, the metal layer (the second metal layer described below) including the power line 241 is shown with a dashed line. Portions of the same layer are represented by the same pattern. A layer is formed of the same material and by the same process. A layer may be composed of a single component layer of a single material, or may have a stacked structure consisting of multiple component layers of different materials. In FIG. 3, via portions (also called contact portions), which are conductor portions formed in vertical holes in an insulator to interconnect different layers, are represented by solid black rectangles or rectangles enclosing an X.

[0036] The rectangles surrounding Xs represent vias between the third metal layer (described later) and other conductor layers, and the black rectangles represent vias between the second metal layer and other conductor layers. For example, via 301 is a via that interconnects the third metal layer and the VDD power supply line 241, and via 311 is a via that interconnects the third metal layer and the anode electrode of OLED element E1.

[0037] The third metal layer includes a main portion 361 that occupies most of the area of ​​the pixel portion 300, and an island portion 362 that exists within an opening formed in the main portion 361. The main portion 361 fills the entire area around the opening in the pixel portion 300, for example, filling more than half of the area of ​​the pixel portion 300. The entire periphery of the island portion 362 is surrounded by a gap, and is physically and electrically isolated from the main portion 361.

[0038] Fig. 4 shows a schematic cross-sectional structure taken along line IV-IV' in Fig. 3. Fig. 4 shows a schematic cross-sectional structure of a configuration including a flexible substrate, a driving TFT and an OLED element, and a sealing structure of the TFT substrate 100. In the following description, up and down refer to up and down in the drawing.

[0039] The TFT substrate 100 includes a flexible substrate, and pixel circuits (TFT arrays) and OLED elements formed on the flexible substrate. The flexible substrate includes, from bottom to top, a polyimide layer 402, a silicon oxide layer (SiOx layer) 403, an amorphous silicon layer (a-Si layer) 404, and a polyimide layer 405. The silicon oxide layer 403 is formed on and in direct contact with the polyimide layer 402. The amorphous silicon layer 404 is formed on and in direct contact with the silicon oxide layer 403. The polyimide layer 405 is formed on and in direct contact with the amorphous silicon layer 404.

[0040] The TFT substrate 100 includes, from bottom to top, a silicon oxide layer 406, a transparent conductive layer 407, a silicon oxide layer 408, a silicon nitride layer (SiNx layer) 409, and a silicon oxide layer 410 on a flexible substrate (polyimide layer 405). The transparent conductive layer 407 is formed of, for example, an amorphous oxide such as ITO or IZO, or an amorphous silicon layer (a-Si layer). A pixel circuit (TFT array) and an OLED element are formed on the silicon oxide layer 410.

[0041] The silicon oxide layer 406 is formed between the polyimide layer 405 and the transparent conductive layer 407 and in direct contact with them. The silicon oxide layer 406 covers the entire surface of the polyimide layer 405. The silicon oxide layer 408 is formed on and in direct contact with the transparent conductive layer 407. The silicon nitride layer 409 is formed on and in direct contact with the silicon oxide layer 408. The silicon oxide layer 410 is formed on and in direct contact with the silicon nitride layer 409.

[0042] An OLED element is formed on a flexible substrate including the above-mentioned multiple layers. The OLED element includes a lower electrode portion (e.g., an anode electrode 438), an upper electrode portion (e.g., a cathode electrode 432), and an organic light-emitting multilayer film 434. The organic light-emitting multilayer film 434 is disposed between the cathode electrode 432 and the anode electrode 438. The multiple anode electrodes 438 are disposed on the same surface (e.g., on the planarization film 431), and one organic light-emitting multilayer film 434 is disposed on one anode electrode 438. In the example of FIG. 4, the cathode electrode 432 of one pixel is part of a continuous conductor film that covers the entire surface of the display region 125.

[0043] FIG. 4 shows an example of a pixel structure of a top-emission type (OLED element). In a top-emission type pixel structure, a cathode electrode 432 common to multiple pixels is arranged on the light-emitting side (upper side of the drawing). The cathode electrode 432 has a shape that covers the entire display area 125. In a top-emission type pixel structure, the anode electrode 438 reflects light, and the cathode electrode 432 is optically transparent. This results in a configuration in which light from the organic light-emitting multilayer film 434 is emitted toward the sealing structure 150. A semi-transparent film can be used for the cathode electrode 432 to optically optimize the distance from the anode electrode 438 to form a resonant structure.

[0044] The bottom-emission pixel structure has a transparent anode electrode and a reflective cathode electrode, and emits light to the outside through the flexible substrate. A transparent display device can also be realized by forming both the anode electrode and the cathode electrode from a light-transmitting material. The flexible substrate structure of the present disclosure can be applied to any of these types of OLED display devices, and can also be applied to display devices that include light-emitting elements other than OLEDs.

[0045] In a full-color OLED display, subpixels typically display one of three colors: red, green, or blue. The red, green, and blue subpixels make up a single main pixel. A pixel circuit containing multiple thin-film transistors controls the emission of a corresponding OLED element. An OLED element consists of an anode electrode (lower electrode), an organic light-emitting layer, and a cathode electrode (upper electrode).

[0046] Each pixel unit 300 includes a pixel circuit including a plurality of switch transistors and a drive transistor. The pixel circuit is formed between the silicon oxide layer 410 and the anode electrode 438 and controls the current supplied to the anode electrode 438. The transistor P3 shown in FIG. 4 has a top-gate structure. The other transistors also have a top-gate structure.

[0047] A polysilicon layer lies on and in direct contact with silicon oxide layer 410. The polysilicon layer includes a channel 413 that provides the transistor characteristics of transistor P3, located between gate electrode portion 411 and gate electrode portion 412. 7 At either end are heavily doped source / drain regions 414, 415 for electrical connection to the upper wiring layer. Figure 4 also shows the source / drain region 412 of transistor P5 in the polysilicon layer.

[0048] An LDD (Lightly Doped Drain) doped with a low concentration of impurities may be formed between the channel 413 and the source / drain regions 414, 415. The LDD is not shown in the figure to avoid complication. The polysilicon layer further includes portions used as wiring and electrodes.

[0049] A first metal layer including a gate electrode portion 417 and electrode portions 418 and 419 is formed on the polysilicon layer via a gate insulating layer 416. The electrode portion 418 includes the gate electrode portion of the driving transistor P1 (not shown). The first metal layer can be formed of, for example, a high-melting-point metal such as W, Mo, or Ta, or an alloy thereof.

[0050] An interlayer insulating film 420 is formed to cover the first metal layer. The interlayer insulating film 420 can be made of, for example, silicon oxide or silicon nitride. An intermediate conductor layer including electrode portions 421 and 422 is formed on and in direct contact with the interlayer insulating film 420. The intermediate conductor layer can be made of, for example, a low-resistance semiconductor, a high-melting-point metal such as W, Mo, or Ta, or an alloy thereof. The intermediate conductor layer can increase the capacitance value of the storage capacitor element C0 using a smaller area.

[0051] 4, the electrode portion 421 overlaps with the electrode portion 419 of the first metal layer in the stacking direction, with the interlayer insulating film 420 sandwiched therebetween. The electrode portion 422 overlaps with the electrode portion 418 of the first metal layer in the stacking direction, with the interlayer insulating film 420 sandwiched therebetween. A portion of the storage capacitance element C1 is formed between the electrode portion 421 and the electrode portion 419. An anode power supply potential VDD is applied to the electrode portion 419. In addition, a portion of the storage capacitance element C2 is formed between the electrode portion 422 and the electrode portion 418.

[0052] A planarization film 424 is formed so as to cover the intermediate conductor layer and the interlayer insulating film 420. The planarization film 424 can be formed of an organic or inorganic insulator, and is in direct contact with the intermediate conductor layer and the interlayer insulating film 420.

[0053] A second metal layer including source / drain electrode portions 425 is formed on the planarization film 424. The second metal layer may have, for example, a single Al layer or a Ti / Al / Ti laminated structure. The source / drain electrode portions 425 are connected to the source / drain regions 414 of the polysilicon layer by via portions formed in holes that penetrate the interlayer insulating film 420 and the gate insulating layer 416 in the stacking direction.

[0054] The second metal layer further includes an electrode portion 426. The electrode portion 426 is connected to the electrode portion 422 of the intermediate conductor layer by a via portion formed in a hole that penetrates the planarization film 424 in the stacking direction. These are at the same potential.

[0055] The second metal layer further includes an electrode portion 427. The electrode portion 427 faces the electrode portion 421 of the intermediate conductor layer in the stacking direction, with an interlayer insulating film 420 interposed therebetween. A portion of the storage capacitance element C1 is formed between the electrode portion 427 and the electrode portion 421.

[0056] The second metal layer further includes an electrode portion 428. The electrode portion 428 extends directly downward and is connected to the source / drain region 412 of the transistor P5 by a via portion formed in a hole penetrating the planarization film 424, the interlayer insulating film 420, and the gate insulating layer 416.

[0057] A planarization film 430 is formed to cover the second metal layer and the planarization film 424. The planarization film 430 can be made of an organic or inorganic insulator, and is in direct contact with the second metal layer and the planarization film 424.

[0058] Planarization film 4 30 A third metal layer including a main portion 361 and an island portion 362 is formed on the planarization film 4. The third metal layer may have, for example, a single Al layer or a laminated structure of Ti / Al / Ti. 30As described above, the island portion 362 is separated from the main portion 361 and is surrounded by the main portion 361 via a gap. The main portion 361 surrounds the island portion 362, and a gap exists around the island portion 362.

[0059] The main portion 361 is connected to an electrode portion 427 of the second metal layer by a via portion 301 that extends directly below a hole in the planarization film 430. The main portion 361 is supplied with an anode power supply potential VDD via the electrode portion 427.

[0060] In this example, the main portion 361 covers the entire intermediate conductor layer when viewed in the stacking direction (viewed vertically in FIG. 4). A portion of the main portion 361 faces a portion of the electrode portions 421 and 422 of the third metal layer, with planarization films 430 and 424 sandwiched therebetween. A portion of the capacitance element C1 is formed between the electrode portions 421 and 422 and the main portion 361. Furthermore, a portion of the main portion 361 faces an electrode portion 426 of the second metal layer, with the planarization film 430 sandwiched therebetween. A portion of the capacitance element C1 is formed between the main portion 361 and the electrode portion 426.

[0061] In this example, as described above, the capacitance element C1 includes a capacitance between the electrode portion 421 of the intermediate conductor layer and the electrode portion 419 of the first metal layer, a capacitance between the electrode portion 421 and the electrode portion 427 of the second metal layer, a capacitance between the electrode portions 421, 422 of the intermediate conductor layer and the main portion 361 of the third metal layer, and a capacitance between the electrode portion 426 of the second metal layer and the main portion 361 of the third metal layer.

[0062] The electrode portion 427 of the second metal layer and the main portion 361 of the third metal layer are at the same potential. The electrode portion 427 of the second metal layer and the electrode portions 421 and 422 of the intermediate conductor layer are at the same potential. The anode power supply potential VDD is applied to the electrode portions 419 and 427 and the main portion 361. In this way, the storage capacitance element C1 includes the capacitance between the intermediate conductor layer and the third metal layer in addition to the capacitance between the third metal layer and the first metal layer.

[0063] The storage capacitor element C2 is composed of a capacitance between the electrode portion 422 of the intermediate conductor layer and the electrode portion 418 of the first metal layer. The electrode portion 418 is connected to the gate electrode of the driving transistor P1. In this way, the storage capacitor element C2 is composed only of a capacitance between the intermediate conductor layer and the first metal layer.

[0064] As described above, the intermediate conductor layer forms a capacitance included in the capacitive element C2 between itself and the first metal layer, and forms a capacitance included in the capacitive element C1 between itself and the main portion 361.

[0065] The main portion 361 of the third metal layer occupies a large area of ​​the pixel portion 300 and covers the entire intermediate conductor layer, including the electrode portions 421 and 422, which form the storage capacitor element C0. A constant anode power supply potential VDD is applied to the main portion 361, which can suppress voltage fluctuations in the storage capacitor due to crosstalk. In addition, the main portion 361 increases the area of ​​the power supply line, which can reduce the possibility of the power supply line being disconnected due to bending and Ir-Drop.

[0066] The island portion 362 is connected to the electrode portion 428 of the second metal layer by the via portion 312 directly below it. The via portion 312 penetrates the planarizing film 430 in the stacking direction and is in direct contact with the electrode portion 428.

[0067] A planarization film 431 is formed so as to cover the third metal layer and the planarization film 430. The planarization film 431 can be formed of an organic or inorganic insulating material. 3 Metal layer and planarization film 4 30 is in direct contact with

[0068] An anode electrode 438 is formed on the planarization film 431. The anode electrode 438 is in direct contact with the planarization film 431. The anode electrode 438 is connected to the source / drain region 412 via a contact hole in the planarization film 431. A TFT of the pixel circuit is formed below the anode electrode 438. The anode electrode 438 is composed of, for example, a central reflective metal layer and transparent conductive layers sandwiching the reflective metal layer. The anode electrode 438 has, for example, an ITO / Ag / ITO structure or an IZO / Ag / IZO structure.

[0069] The anode electrode 438 is connected to the island portion 362 of the third metal layer through a via portion directly below the anode electrode 438. The via portion penetrates the planarization film 431 in the stacking direction and is in direct contact with the island portion 362. The source / drain region 412, the electrode portion 428 of the second metal layer, and the island portion 362 apply to the anode electrode 438 a driving potential (anode potential) that determines the luminance (amount of light emitted) of the light-emitting element. The island portion 362 is located outside and away from the main portion 361 to which the power supply potential VDD is applied. This allows a driving potential to be applied to the anode electrode 438.

[0070] An insulating pixel defining layer (PDL) 437 is formed on the anode electrode 438 to separate the OLED elements. The OLED elements are formed in openings 436 in the pixel defining layer 437.

[0071] An organic light-emitting multilayer film 434 is formed on the anode electrode 438. The organic light-emitting multilayer film 434 is attached to the pixel definition layer 437 at and around an opening 436 in the pixel definition layer 437. The organic light-emitting multilayer film 434 is formed on the anode electrode 438 by depositing an organic light-emitting material for each of the RGB colors.

[0072] The organic light-emitting multilayer film 434 is formed by depositing an organic light-emitting material at positions corresponding to the pixels using a metal mask. The organic light-emitting multilayer film 434 is composed of, from the bottom up, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The layered structure of the organic light-emitting multilayer film 434 is determined by the design.

[0073] A cathode electrode 432 is formed on the organic light-emitting multilayer film 434. The cathode electrode 432 is an electrode having optical transparency. The cathode electrode 432 transmits a portion of visible light from the organic light-emitting multilayer film 434. The layer of the cathode electrode 432 is formed by vapor deposition of a metal such as Ag or Mg, or an alloy containing these metals. If the resistance of the cathode electrode 432 is high and the uniformity of the light emission brightness is impaired, an auxiliary electrode layer is further added using a material for forming a transparent electrode, such as ITO, IZO, ZnO, or In2O3.

[0074] The stacked film of the anode electrode 438, organic light-emitting multilayer film 434, and cathode electrode 432 formed in the opening 436 of the pixel definition layer 437 constitutes an OLED element. A sealing structure is formed on and in direct contact with the cathode electrode 432. The sealing structure (thin film sealing portion) includes, from the bottom up, an inorganic insulator (e.g., SiNx, AlOx) layer 433, an organic planarizing film 439, and an inorganic insulator (e.g., SiNx, AlOx) layer 435.

[0075] On the sealing structure, from bottom to top, a touchscreen film 453, a λ / 4 plate 454, a polarizer 455, and a resin cover lens 456 are laminated. The λ / 4 plate 454 and the polarizer 455 suppress reflection of light incident from the outside. Note that the laminated structure of the OLED display device described with reference to FIG. 4 is an example, and some of the layers shown in FIG. 4 may be omitted, or layers not shown in FIG. 4 may be added. For example, the intermediate conductor layer may be omitted. When the intermediate conductor layer is omitted, a storage capacitor is formed between the gate electrode and the polysilicon layer doped with a high concentration of impurities, for example, via the gate insulating layer 416.

[0076] 5A to 5G respectively show the patterns of several layers included in the laminated structure of the TFT substrate 100. 5A to 5G show the layers formed in this order from the flexible substrate side (bottom side).

[0077] 5A schematically shows a semiconductor layer (e.g., polysilicon layer) pattern 501. The semiconductor layer pattern 501 includes a high-resistance channel region. Furthermore, impurities are doped into parts of the semiconductor layer pattern 501, and these parts become low-resistance parts with lower resistance than the channel.

[0078] FIG. 5B schematically shows a first metal layer pattern 503. As described above, the first metal layer includes, in addition to the gate electrodes of the transistors, wiring portions or electrode portions that transmit power supply potential or signal potential. FIG. 5C schematically shows an intermediate conductor layer pattern 505. The intermediate conductor layer includes electrode portions 421 and 422 and a connecting portion 423 that connects these electrode portions. Electrode portions 421 and 422 are the fifth electrode portion and the fourth electrode portion, respectively.

[0079] The width of the connecting portion 423 (the length in the left-right direction in FIG. 5C) is smaller than the width of the electrode portions 421 and 422. The narrower the width of the connecting portion 423, the better, in order to minimize the influence on the two storage capacitors due to misalignment and processing variations, and the minimum value allowed in the manufacturing process is used. For example, it is 1 / 10 or less of the width of the electrode portions 421 and 422. As described above, the intermediate conductor layer is a component of the storage capacitor.

[0080] 5D schematically shows the stacked structure of semiconductor layer pattern 501, first metal layer pattern 503, and intermediate conductor layer pattern 505. FIG. 5D also shows, with black rectangles, via portions that interconnect the second metal layer and the underlying conductor layer. Via portion 531 interconnects the first metal layer and the second metal layer. Via portion 551 interconnects the intermediate conductor layer and the second metal layer.

[0081] 5E is a schematic diagram of a second metal layer pattern 507. FIG. 5E further shows vias 301 and 302 interconnecting the second metal layer and the third metal layer. 12. As described above, via portion 301 interconnects main portion 361 of the third metal layer with the second metal layer. Via portion 312 interconnects island portion 362 of the third metal layer with the second metal layer. FIG. 5F schematically illustrates third metal layer pattern 509. FIG. 5F further illustrates: The anode electrode of the OLED element E1 Via portion 3 interconnecting with the third metal layer 11 5F, the main portion 361 fills the area of ​​the pixel portion other than the island portion 362 and the gap between the main portion 361 and the island portion 362.

[0082] The main portion 361 of one pixel portion 300 is part of one continuous metal sheet. This metal sheet includes the main portions 361 of multiple pixel portions 300. One island portion 362 exists in one pixel portion 300. The island portion 362 exists within the opening 363 of the main portion 361, and all outer peripheral edges of the island portion 362 are spaced apart from the inner edge of the opening 363 of the main portion 361.

[0083] 5G schematically shows an anode electrode 438 and an opening 436 in a PDL layer 437. A light-emitting region is present within the opening 436. As described above, a driving potential is applied to the anode electrode 438 via an island 362 in the third metal layer.

[0084] [Display area configuration] An example of the configuration of the display area 125 according to an embodiment of the present specification will be described below. FIG. 6 schematically shows an example of the configuration of the display area 125. The OLED display device 10 is implemented in a mobile terminal such as a smartphone or a tablet terminal. The display area 125 includes a normal area 461 having a normal pixel density and a low-density area 463 having a pixel density lower than the pixel density of the normal area 461. The normal area 461 is a first display area, and the low-density area 463 is a second display area.

[0085] One or more cameras 465 are disposed below (behind) the low-density region 463. The camera 465 is an example of an optical sensor, and other optical sensors may be disposed below the low-density region 463. In Figure 6, one of the multiple cameras is indicated by the reference numeral 465 as an example.

[0086] The low-density region 463 is disposed on the viewing side of the camera 465, and the camera 465 photographs an object on the viewing side using light that passes through the low-density region 463. In order not to interfere with the photographing by the camera 465, the density of the pixel portion (including the light-emitting element and the pixel circuit) in the low-density region 463 is lower than the density of the pixel portion in the surrounding normal region 461.

[0087] A control device (not shown) transmits data of an image captured by, for example, a camera 465 to the OLED display device 10. Note that while Fig. 6 shows an area under which a camera is disposed as an example of a low-density area, the features described herein can be applied to display devices including areas with a relatively low pixel density for other purposes. The frequency of light sensed by the optical sensor is not limited.

[0088] [Wiring and third metal layer layout] An example of the wiring layout of the OLED display device 10 will be described below. Fig. 7 schematically shows the layout of control wiring on the TFT substrate 100. In the configuration example of Fig. 7, the low-density region 463 is a region that includes an edge of the display region 125, and one side of the low-density region 463 is part of one side of the display region 125. The other part of the periphery of the low-density region 463 exists within the display region 125 and forms the boundary with the normal region 461.

[0089] In the configuration example of FIG. 7, the pixel circuits in the normal region 461 are laid out in a stripe arrangement. Specifically, pixel columns (sub-pixel columns) extending along the Y axis are made up of pixels (sub-pixels) of the same color. Pixel rows extending along the X axis are made up of cyclically arranged red, green, and blue pixels. The low-density region 463 has a configuration in which some pixels are thinned out from the pixel layout of the normal region 461. In the blank areas of the low-density region 463, pixel circuits including OLED elements are not formed, and only wiring passes through.

[0090] A plurality of scanning lines 106 extend from the scanning driver 131 along the X-axis. A plurality of emission control lines 107 extend from the emission driver 132 along the X-axis. In FIG. 7, for example, one scanning line and one emission control line are indicated by reference numerals 106 and 107, respectively. In the configuration example shown in FIG. 7, the scanning line 106 transmits selection signals for pixels in the normal region 461 and the low-density region 463. The emission control line 107 transmits emission control signals for the normal region 461 and the low-density region 463.

[0091] The driver IC 134 transmits a control signal to the scan driver 131 via a wiring 711, and transmits a control signal to the emission driver 132 via a wiring 713. The driver IC 134 controls the timing of the scan signal (selection pulse) from the scan driver 131 and the emission control signal of the emission driver 132 based on image data (image signal) from the outside.

[0092] The driver IC 134 supplies the data signals of the sub-pixels in the normal region 461 and the low-density region 463 to the demultiplexer 136 via wiring 705. In Fig. 7, one wiring is shown by the reference symbol 705. The driver IC 134 determines the data signals of each sub-pixel in the normal region 461 and the low-density region 463 from the gradation levels of one or more sub-pixels in the image data (frame) from the outside.

[0093] The demultiplexer 136 sequentially outputs one output of the driver IC 134 to N (N is an integer equal to or greater than 2) data lines 105 within a scanning period. In Fig. 7, one data line among the multiple data lines extending along the Y axis is indicated by the reference numeral 105 as an example.

[0094] 7 schematically shows the layout of an anode power supply line pattern on the TFT substrate 100. As shown in Fig. 7, the TFT substrate 100 includes an anode power supply line pattern 801. The power supply line pattern 801 applies an anode power supply potential to pixel circuits in the normal region 461 and the low-density region 463.

[0095] The anode power supply line pattern 801 includes a rectangular periphery and line portions that extend along the Y-axis within the periphery and are arranged along the X-axis. Some of the line portions pass through the normal region 461 and the low-density region 463. The anode power supply line pattern 801 transmits an anode power supply potential VDD to the pixel circuits of each subpixel in the normal region 461 and the low-density region 463. Note that the anode power supply line pattern 801 may be different from the example in FIG. 7. For example, the anode power supply line pattern 801 may be mesh-shaped and include line portions that extend along the Y-axis as well as multiple line portions that extend along the X-axis.

[0096] 7 further schematically shows third metal layer 591. Anode power supply potential VDD is applied to a main portion of third metal layer 591 from anode power supply line pattern 801. In this example, third metal layer 591 is not present in low-density region 463, but is present in normal region 461. Because third metal layer 591 is removed in low-density region 463 and is present only outside low-density region 463, it is possible to reduce the reduction in light that passes through low-density region 463 and reaches rear camera 465.

[0097] Unlike the configuration in which the low-density region 463 exists within one opening of the third metal layer 591, a part of the third metal layer 591 may exist within the low-density region 463. The pattern of the third metal layer 591 in the low-density region 463 is different from the pattern of the third metal layer 591 in the normal region 461.

[0098] The occupancy rate of the third metal layer 591 in the low-density region 463 is smaller than the occupancy rate in the normal region 461. This reduces the reduction in light reaching the camera 465. The occupancy rate in a region is the value obtained by dividing the region filled with the third metal layer 591 in that region by the area of ​​that region.

[0099] For example, the pixel circuits and pixel units in the normal display region 461 have the same outer size as those in the low-density region 463. The pixel unit in the normal region 461 has the structure described with reference to FIGS. 3 to 5G.

[0100] On the other hand, since the third metal layer 591 is not present in the low-density region 463, the pixel portion in the low-density region 463 has a structure in which the third metal layer is removed from the structure described with reference to FIGS. 3 to 5G. Therefore, the via portion 311 shown in FIG. 4 directly contacts the electrode portion 428 of the second metal layer. In other words, the anode electrode 438 is connected to the second metal layer by a via portion extending directly downward, without going through the third metal layer. The third metal layer may also be present in the pixel portion in the low-density region 463. For example, an island pattern of the third electrode may be disposed only in the via portion 311. In this case, the contact resistance from the driving TFT to the anode electrode can be made the same in the low-density region and the high-density region. The occupancy rate of the third metal layer in the pixel portion (pixel region) in the low-density region 463 is smaller than that in the normal region 461.

[0101] The driver IC 134 includes a DC-DC converter, generates a plurality of power supply potentials, and supplies them to the OLED display panel. The driver IC 134 outputs an anode power supply potential VDD to the anode power supply line pattern 801, and outputs a cathode power supply potential VSS to the cathode electrode 432.

[0102] 7 is in the form of a single sheet, and covers the entire normal region 461 and the low-density region 463. The cathode electrodes of the pixels in these regions 461 and 463 are part of the single sheet-like cathode electrode layer.

[0103] [Other configuration examples] Other structural examples of the pixel section in the normal display region 461 are described below. In the structural examples described with reference to FIGS. 3 to 5G, the main portion of the third metal layer covers the entire area of ​​the intermediate conductor layer in the pixel section when viewed in the stacking direction. In other configuration examples, only a portion of the intermediate conductor layer in the pixel section may be covered by the main portion. By adjusting the area where the main portion covers the intermediate conductor layer, the capacitance value of the capacitive element C1 can be adjusted.

[0104] 8A shows a first metal layer pattern 503, an intermediate conductor layer pattern 505, and a third metal layer pattern 820 in another example structure of a pixel unit including a third metal layer. Compared to the structures described with reference to FIGS. 3 to 5G, the first metal layer pattern 503 and the intermediate conductor layer pattern 505 are similar, but the third metal layer pattern 820 is different.

[0105] 8B shows the intermediate conductor layer pattern 505 and the third metal layer pattern 820 in the structural example shown in FIG. 8A. The third metal layer pattern 820 is composed of a main portion 821 and an island portion 822 in the pixel portion. The island portion 822 is present within the opening of the main portion 821.

[0106] A gap exists around the island portion 822, separating the island portion 822 from the main portion 821. The area of ​​this gap is wider than in the above structural example. Therefore, the occupancy rate of the third metal layer in the pixel portion is smaller than in the above structural example. The electrode portion 421 of the intermediate conductor layer exists in the gap between the main portion 821 and the island portion 822, and is located closer to the third metal layer 822 in the stacking direction. 2 On the other hand, the entire electrode portion 422 of the intermediate conductor layer does not overlap with the third metal layer 80 in the stacking direction. 2 It overlaps (is covered by) 0.

[0107] Intermediate conductor layer pattern 505 includes a connecting portion 423 that connects two electrode portions 421 and 422 in the Y-axis direction (first direction). The narrower the width of connecting portion 423 (the length in the X-axis direction (second direction) in FIG. 8B ) is compared to the widths of electrode portions 421 and 422, the better, and the minimum line width allowed in the manufacturing process is used. This makes it possible to reduce changes in storage capacitance due to alignment errors of the intermediate conductor layer in the Y-axis direction.

[0108] 8B, distances L1 and L2 are defined along the X-axis between the edge of the electrode portion 421 of the intermediate conductor layer and the edge (the inner edge of the opening) of the main portion 821 of the third metal layer. In one example, these distances L1 and L2 are the same. This reduces the effects of alignment errors.

[0109] 8A, in addition to the layer structure shown in FIG. 8C, a second metal layer pattern 850 is shown. In this embodiment, the third metal layer does not overlap the electrode portion 421 of the intermediate conductor layer, and therefore the position of the via portion 825 connecting the second metal layer pattern 850 and the third metal layer pattern 820 is different from that of the other structural examples described above. Similar to the via portion 301 of the other structural examples described above, the via portion 825 interconnects the main portion 821 of the third metal layer and the electrode (wiring) that transmits the anode power supply potential VDD of the second metal layer.

[0110] 9 is a cross-sectional view schematically illustrating the cross-sectional structure of this pixel portion structure example. Differences from the structure example of FIG. 4 will be mainly explained. Electrode portion 421 of the intermediate conductor layer is not covered by the third metal layer pattern, but exists within the opening. Furthermore, since the position of the via portion connecting the second metal layer and the third metal layer is different, the via portion 301 and electrode portion 427 of the second metal layer shown in FIG. 4 do not exist in this example.

[0111] 4, a portion of the capacitance element C1 is formed between the main portion 821 of the third metal layer and the electrode portion 426 of the second metal layer, and a portion of the capacitance element C1 is formed between the main portion 821 and the electrode portion 422 of the intermediate conductor layer. The capacitance element C2 is formed only between the intermediate conductor layer and the first metal layer.

[0112] Next, we will explain another example of using the third metal layer. In the example described below, the third metal layer is used as a pinhole matrix layer. The pinhole matrix layer includes a pinhole array consisting of multiple pinholes arranged two-dimensionally. The pinholes allow only light from a point on an object to pass through in a specific direction.

[0113] 10 is a cross-sectional view schematically showing the cross-sectional structure of the low-density region 463. In the low-density region 463, the third metal layer functions as a MAPIS (Matrix Pinhole Image Sensing) layer 593. The MAPIS layer 593 is a pinhole matrix layer.

[0114] An encapsulating structure 471 is laminated to cover the OLED element E1. A touchscreen film 453, a polarizing plate 455, and a cover lens 456 are sequentially laminated on the encapsulating structure 471. The pattern of the third metal layer in the normal region 461 is as described with reference to FIGS. 3 to 5G or 8A to 9. As such, the pattern of the third metal layer in the low-density region 463 is different from the pattern of the third metal layer in the normal region 461.

[0115] 10, a CMOS sensor 901, which is an optical sensor, is disposed below (behind) the MAPIS layer 593. The configuration example shown in FIG. 10 can function as, for example, a fingerprint sensor. A finger 902 to be imaged reflects light from the OLED element E1. The light from the finger 902 passes through the pinhole array in the MAPIS layer 593 and forms an image on the CMOS sensor 901. The fingerprint image captured by the CMOS sensor 901 is transferred to a control device (not shown). The control device compares the fingerprint data of a registered user with the captured fingerprint image to perform user authentication.

[0116] The MAPIS layer 593 is supplied with an anode power supply potential VDD. AA portion of the PIS 593 constitutes a portion of the storage capacitor. The portions of the MAPIS layer 593 other than the pinholes are filled with metal. In one example, the occupancy rate of the MAPIS layer 593 in the pixel portion is greater than the occupancy rate of the third metal layer in the normal region 461 in the pixel portion. As shown in this and other configuration examples, the third metal layer has different patterns in different regions of the display region 125, allowing light appropriate for the purpose of each region to reach the photosensor on the back side.

[0117] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments. Those skilled in the art can easily modify, add, or convert each element of the above embodiments within the scope of the present disclosure. It is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0118] 100 TFT substrates 106 scan lines 107 Emission Control Line 131 Scan Driver 132 Emission Driver 134 Driver IC 361, 801 3rd metal layer main part 362, 802 Third metal layer island 421, 422 Intermediate conductor layer electrode part 425-428 Second metal layer electrode part 461 Normal area 463 Low density area 465 Camera

Claims

1. A display device, a first display area for displaying an image; a second display area having a lower pixel density than the first display area and displaying an image; a first metal layer; a second metal layer above the first metal layer; a third metal layer above the first metal layer and the second metal layer; Including, an occupancy rate of the third metal layer in the second display region is smaller than an occupancy rate of the third metal layer in the first display region; The first display region includes a plurality of first pixel units, each of which includes: a light emitting device including an upper electrode portion, a lower electrode portion, and a light emitting layer between the upper electrode portion and the lower electrode portion; a driving transistor for controlling the light emission of the light emitting element; Including, the first metal layer, the second metal layer, and the third metal layer are layers below the lower electrode portion, the first metal layer includes a first electrode portion that controls the amount of current in a channel of the driving transistor in each of the first pixel portions of the plurality of first pixel portions; the second metal layer includes a second electrode portion and a third electrode portion that supply a current to a channel of the driving transistor in each of the first pixel portions of the plurality of first pixel portions; The third metal layer is a main portion that is supplied with a power supply potential and that constitutes, between the main portion and the second metal layer, a capacitance included in a first capacitance element that holds a voltage that controls the drive transistor; an island portion separated from the main portion, surrounded by the main portion with a gap therebetween, and interconnected with the lower electrode portion by a via portion; Including, Display device.

2. The display device according to claim 1 , an intermediate conductor layer between the first metal layer and the second metal layer; The intermediate conductor layer is a capacitance included in a second capacitance element different from the first capacitance element is formed between the first metal layer and the second metal layer; A capacitance included in the first capacitive element is formed between the main portion and the first capacitive element. Display device.

3. The display device according to claim 2, the main portion covers the entire area of ​​the intermediate conductor layer when viewed in the stacking direction; Display device.

4. The display device according to claim 2, the intermediate conductor layer includes a fourth electrode portion, a fifth electrode portion, and a connecting portion that connects the fourth electrode portion and the fifth electrode portion in a first direction; the third metal layer covers the entire fourth electrode portion when viewed in the stacking direction, the fifth electrode portion is present in a gap between the main portion and the island portion as viewed in the stacking direction, a length of the connecting portion in a second direction perpendicular to the first direction is smaller than lengths of the fourth electrode portion and the fifth electrode portion in the second direction; Display device.

5. The display device according to claim 2, the intermediate conductor layer includes a fourth electrode portion and a fifth electrode portion, the third metal layer covers the entire fourth electrode portion when viewed in the stacking direction, the fifth electrode portion is present in a gap between the main portion and the island portion as viewed in the stacking direction, The distances from each of the two sides of the fifth electrode portion to the main portion are the same. Display device.

6. The display device according to claim 1 , the main portion fills the area of ​​the pixel portion other than the island portion and the gap; Display device.

7. The display device according to claim 1 , In the second display area, the third metal layer is removed. Display device.

8. A display device, a first display area for displaying an image; a second display area having a lower pixel density than the first display area and displaying an image; a first metal layer; a second metal layer above the first metal layer; a third metal layer above the first metal layer and the second metal layer; Including, an occupancy rate of the third metal layer relative to an area of ​​the second display region is smaller than an occupancy rate of the third metal layer relative to an area of ​​the first display region; The first display region includes a plurality of first pixel units, each of which includes: a light emitting device including an upper electrode portion, a lower electrode portion, and a light emitting layer between the upper electrode portion and the lower electrode portion; a driving transistor for controlling the light emission of the light emitting element; Including, the first metal layer, the second metal layer, and the third metal layer are layers below the lower electrode portion, the first metal layer includes a first electrode portion that controls the amount of current in a channel of the driving transistor in each of the first pixel portions of the plurality of first pixel portions; the second metal layer includes a second electrode portion and a third electrode portion that supply a current to a channel of the driving transistor in each of the first pixel portions of the plurality of first pixel portions; The third metal layer is a main portion that is supplied with a power supply potential and that constitutes, between the main portion and the second metal layer, a capacitance included in a first capacitance element that holds a voltage that controls the drive transistor; an island portion separated from the main portion, surrounded by the main portion with a gap therebetween, and interconnected with the lower electrode portion by a via portion; Including, Display device.

9. The display device according to claim 8, the third metal layer has a pinhole array in the second display area; Display device.

10. The display device according to claim 1 or 8; a photosensor disposed below the second display area; Electronic devices, including:

Images