Master Transform Architecture for Deep Learning

Abstract

Apparatus, systems, and techniques for transforming input data for training a neural network, in at least one embodiment, wherein one or more data transformations are identified and combined in a sequence of data transformations to become one or more master data transformations used by one or more parallel processing units to prepare data for training an untrained neural network.

Description

[Technical Field]

[0001] This application claims priority to U.S. patent application Ser. No. 16 / 719,883, filed Dec. 18, 2019, entitled "MASTER TRANSFORM ARCHITECTURE FOR DEEP LEARNING," the entire contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] At least one embodiment relates to processing resources used to implement and facilitate artificial intelligence, for example, a processor or computing system used to transform input data for training neural networks and for inference using neural networks in accordance with various novel techniques described herein. [Background technology]

[0003] Training neural networks so that they can be used to perform inference often requires large amounts of data. This data is often available in various formats or must be modified before it can be used to train a neural network. Pre- and post-transformations that prepare data for training and inference are an important part of training neural networks and performing deep learning inference. Preparing input data for training neural networks often requires applying transformations to the input data, which can be expensive due to both technical limitations (e.g., memory requirements) and limitations based on formatting. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 illustrates a system for training and inference using neural networks, according to at least one embodiment. [Figure 2]FIG. 1 illustrates a system for training and inference using neural networks with acceleration by one or more parallel processing units (PPUs), according to at least one embodiment. [Figure 3] FIG. 10 illustrates an example sequence of transformations that prepare data for training and inference using a neural network, according to at least one embodiment. [Figure 4] FIG. 10 illustrates the percentage of time for each transformation of an example of processing data for use in training and inference using a neural network, according to at least one embodiment. [Figure 5] FIG. 1 illustrates a sequence of example transformations that prepare data for training and inference using a neural network, in which a subset of the example transformations are performed by one or more graphics processing units (GPUs) and the remaining example transformations are performed by one or more central processing units (CPUs), according to at least one embodiment. [Figure 6] FIG. 10 illustrates a sequence of example transformations that prepare data for training and inference using a neural network, in which a subset of the example transformations are combined into a master transform performed by one or more GPUs, and the remaining example transformations are performed individually by one or more CPUs, according to at least one embodiment. [Figure 7] FIG. 1 illustrates a system for determining one or more master transforms, each encompassing two or more data transforms, from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment. [Figure 8]FIG. 1 illustrates a process for determining one or more master transforms, each encompassing two or more data transforms, from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment. [Figure 9A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 9B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 10] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 11] FIG. 1 illustrates an example data center system in accordance with at least one embodiment. [Figure 12A] FIG. 1 illustrates an example of an autonomous vehicle in accordance with at least one embodiment. [Figure 12B] 12B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 12A, according to at least one embodiment. [Figure 12C] FIG. 12B is a block diagram illustrating a system architecture of the autonomous vehicle example of FIG. 12A, according to at least one embodiment. [Figure 12D] FIG. 12B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 12A, according to at least one embodiment. [Figure 13] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 14] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 15] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 16] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17E] FIG. 1 illustrates a shared programming model according to at least one embodiment. [Figure 17F] FIG. 1 illustrates a shared programming model according to at least one embodiment. [Figure 18] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 19A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 19B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 20A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 20B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 21] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 22A] FIG. 1 illustrates a parallel processor in accordance with at least one embodiment. [Figure 22B] FIG. 1 illustrates a partition unit according to at least one embodiment. [Figure 22C] FIG. 1 illustrates a processing cluster according to at least one embodiment. [Figure 22D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 23] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 24] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 25] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 26] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 27] FIG. 1 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment. [Figure 28] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 29] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 30] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 31] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor, according to at least one embodiment. [Figure 32] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 33A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 33B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 34] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 35] FIG. 1 illustrates a general processing cluster (“GPC”), according to at least one embodiment. [Figure 36] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 37]FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] FIG. 1 illustrates a system for training and inference using one or more neural networks 110, 112, according to at least one embodiment. In at least one embodiment, a training framework 108 is used to train an untrained neural network 110 to perform operations such as classification. In at least one embodiment, the training framework 108 is a group of software modules whose instructions, when executed, perform operations to train the neural network 110, including performing calculations and backpropagating or updating weight values ​​for the nodes of the neural network 110. In at least one embodiment, the untrained neural network 110 is a forward propagation neural network. In at least one embodiment, the untrained neural network 110 is a radial basis function neural network. In at least one embodiment, the untrained neural network 110 is a recurrent neural network. In at least one embodiment, the untrained neural network 110 is a convolutional neural network. In at least one embodiment, the untrained neural network 110 is a modular neural network. In at least one embodiment, untrained neural network 110 is any other type of neural network suitable for training to perform inference and other deep learning operations.

[0006] In at least one embodiment, the training framework 108 trains an untrained neural network 110, which includes trainable logic, to determine a logit value. In at least one embodiment, the logit value is a raw prediction value. In at least one embodiment, the logit value may be a numeric, Boolean, or other value. In at least one embodiment, the training framework 108 trains an untrained neural network 110, such as those described herein, to perform an operation such as classification. In at least one embodiment, the training framework 108 trains the untrained neural network 110 based on training data 102. In at least one embodiment, the training data 102 includes images. In at least one embodiment, the training data 102 includes text. In at least one embodiment, the training data 102 includes raw data. In at least one embodiment, the training data 102 is any other type of data suitable for training an untrained neural network 110 using the training framework 108. In at least one embodiment, the training data 102 is supervised training data. In at least one embodiment, training data 102 is unsupervised training data. In at least one embodiment, training data 102 is a mixture of supervised and unsupervised training data. In at least one embodiment, training data 102 is any other type of supervised or unsupervised data suitable for training an untrained neural network 110.

[0007] In at least one embodiment, the training data 102 must be prepared and / or transformed 106, as described herein, for use by the training framework 108 to train the untrained neural network 110. In at least one embodiment, the training data 102 is unformatted. In at least one embodiment, the training data 102 includes a variable format that is not suitable for training the untrained neural network 110. In at least one embodiment, the data preparation and transformation 106 prepares the data for use in training the untrained neural network 110. In at least one embodiment, the data preparation and transformation 106 applies one or more transformations or calculations to the training data 102 to put it in a format suitable for training the untrained neural network 110 by the training framework 108. In at least one embodiment, the one or more transformations or calculations applied by the data preparation and transformation 106 are unordered. In at least one embodiment, the one or more transformations or calculations applied by the data preparation and transformation 106 must be specifically ordered. In at least one embodiment, one or more transformations or calculations applied by data preparation and transformation 106 are reordered to optimize the transformation of training data 102 .

[0008] In at least one embodiment, the training framework 108 trains an untrained neural network 110 using training data 102 that has been prepared and transformed 106 to facilitate neural network training. In at least one embodiment, the training framework 108 generates a trained neural network 112. In at least one embodiment, the trained neural network 112 determines one or more outcomes 114 based on new data 104 through deep learning inference or other inference. In at least one embodiment, the new data 104 is prepared and transformed 106 using techniques described herein to perform deep learning inference and other inference using the trained neural network 112.

[0009] 2 illustrates a system for training and inference using neural networks with acceleration 216 by one or more parallel processing units (PPUs) 218, according to at least one embodiment. In at least one embodiment, a training framework 208 is used to train an untrained neural network 210 as described herein to perform one or more operations, such as classification, as described herein. In at least one embodiment, the training framework 208 further trains the untrained neural network 210 using training data 202 to perform operations based on information learned from the training data 202, as described herein.

[0010] In at least one embodiment, before training framework 208 can train untrained neural network 210, input training data 202 is prepared and transformed 206 to ensure that the input training data 202 is in a format usable by training framework 208 to train untrained neural network 210. In at least one embodiment, one or more transforms 206 are applied to prepare training data 202 for use by training framework 208 to train untrained neural network 210. In at least one embodiment, it may not be necessary to apply transforms 206 to prepare training data 202 for use by training framework 208 to train untrained neural network 210. In at least one embodiment, one or more transforms used in data preparation and transformation 206 apply arithmetic and other arithmetic operations to training data 202, as further described herein. In at least one embodiment, one or more transforms used in data preparation and transformation 206 apply operations other than arithmetic operations to training data 202, as further described herein.

[0011] In at least one embodiment, one or more transforms used in data preparation and transformation 206 are accelerated by one or more PPUs 218, including graphics processing units (GPUs), as described further herein. In at least one embodiment, one or more PPUs 218, such as GPUs, implement 216 all of the transforms described herein used to perform data preparation and transformation 206. In at least one embodiment, one or more PPUs 218, such as GPUs, implement 216 a portion of the transforms described herein used to perform data preparation and transformation 206. In at least one embodiment, one or more PPUs 218, such as GPUs, implement 216 a portion of the training framework 208 for training untrained neural network 210, as described herein. In at least one embodiment, one or more PPUs 218, such as GPUs, work in conjunction with one or more central processing units (CPUs) to prepare and transform 206 training data 202 for use by training framework 208 to train untrained neural networks 210 as described herein, applying one or more transformations as described herein.

[0012] 3 illustrates a sequence of exemplary transformations 308, 310, 312, 314, 316, 318, and 320 that prepare input data 302 for training and inference using a neural network, according to at least one embodiment. In at least one embodiment, the input data 302 described above is prepared and transformed 304 to create transformed data 306 suitable for training an untrained neural network by a training framework, as described herein. In at least one embodiment, data preparation and transformation 304 is a collection of transformations 308, 310, 312, 314, 316, 318, and 320 that prepare the input data 302 for use by the training framework to train an untrained neural network. In at least one embodiment, data preparation and transformation 304 is a collection of transformations 308, 310, 312, 314, 316, 318, and 320 that prepare the input data 302 for use in inference using a trained neural network.

[0013] In at least one embodiment, the example transformations 308, 310, 312, 314, 316, 318, 320 demonstrate that a sequence of data transformations is applied to input data 302 to generate transformed data 306 suitable for training an untrained neural network. In at least one embodiment, the sequence of data transformations 308, 310, 312, 314, 316, 318, 320 has a particular order. In at least one embodiment, the sequence of data transformations 308, 310, 312, 314, 316, 318, 320 is unordered.

[0014] In at least one embodiment, the example transformations include data transformations for medical imaging. In at least one embodiment, the example transformations include data transformations capable of handling 2D, 3D, and 4D medical data, including raw and reconstructed data volumes. In at least one embodiment, the example transformations include general transformations as well as modality-specific transformations, such as imaging modalities and associated data types. In at least one embodiment, the example transformations include data transformations that are not specific to an application space. In at least one embodiment, the example transformations include transformations that load specific values ​​for input data 308. In at least one embodiment, the example transformations include transformations that convert 310 3D values ​​to a 4D array. In at least one embodiment, the example transformations include transformations that adjust 312 intensity values ​​for input data 302, such as an image. In at least one embodiment, the example transformations include transformations that extract 314 rectangular subvolumes from input data 302, such as an image. In at least one embodiment, the example transformations include transformations that randomly flip 316 input data 302, such as an image, either horizontally or vertically. In at least one embodiment, the example transformations include transformations that randomly rotate 318 points on the X,Y plane of input data 302, such as an image. In at least one embodiment, the example transformations include transformations that scale intensity oscillations 320 of input data 302.

[0015] In at least one embodiment, the dimensionality of the data input and output between each data transformation in the sequence of data transformations 308, 310, 312, 314, 316, 318, 320 is variable. In at least one embodiment, the dimensionality of the data input and output between each data transformation in the sequence of data transformations 308, 310, 312, 314, 316, 318, 320 is fixed. In at least one embodiment, each data transformation in the sequence of data transformations 308, 310, 312, 314, 316, 318, 320 has variable memory and compute time requirements.

[0016] 4 illustrates the percentage of time for each example transform for processing data for use in training an untrained neural network and in inference using a trained neural network, according to at least one embodiment. In at least one embodiment, data transforms described herein, such as example transforms 402, 404, 406, 408, 410, 412, and 414, have variable memory and compute time requirements when performed by a central processing unit (CPU) or a parallel processing unit (PPU), such as a graphics processing unit (GPU). In at least one embodiment, some transforms 402, 408, 410, and 414 have high memory or compute time requirements. In at least one embodiment, some transforms 404, 406, and 412 have low memory or compute time requirements.

[0017] In at least one embodiment, data transforms having high memory or compute time requirements 402, 408, 410, 414 can be accelerated by implementation on a PPU, such as a GPU. In at least one embodiment, data transforms that are accelerated by implementation on a PPU, such as a GPU, are limited by memory requirements. In at least one embodiment, data transforms are selected for implementation on a PPU, such as a GPU, based on whether their memory requirements exceed the available memory in one or more PPUs, including a GPU. In at least one embodiment, one or more data transforms are selected based on their aggregate memory requirements as well as other considerations described below for implementation on a PPU, including a GPU, performed in conjunction with other transforms performed by one or more CPUs.

[0018] 5 illustrates a sequence of example transformations to prepare data for neural network training and inference using the trained neural network, where a subset of the example transforms 512, 516, 522 are performed by a graphics processing unit (GPU) and the remaining example transforms are performed by a central processing unit (CPU), according to at least one embodiment. In at least one embodiment, input data 502 is prepared and transformed 504 using a sequence of transforms implemented partially in a CPU and partially in one or more parallel processing units (PPUs), such as a GPU, to create transformed data 506 used by the training framework to train an untrained neural network. In at least one embodiment, one or more of the transforms 512, 516, 522 are implemented for acceleration by one or more PPUs, such as one or more GPUs.

[0019] In at least one embodiment, the transforms implemented on one or more PPUs, such as one or more GPUs, are selected based on compute time and memory requirements. In at least one embodiment, the transforms must have memory requirements that can be satisfied by the available memory of one or more PPUs, including one or more GPUs. In at least one embodiment, further considerations, such as those described below, determine whether a transform is implemented on one or more PPUs, such as one or more GPUs.

[0020] In at least one embodiment, some data transforms must be performed sequentially, with the output from one input matching the dimensions of the input of the next transform in the sequence of transforms. In at least one embodiment, an example transform converting 3D data points to a 4D array 508 includes a data output having dimensions supported by a subsequent transform 512. In at least one embodiment, the subsequent transform 512 is implemented for acceleration by one or more PPUs, including GPUs, such that data is copied from memory associated with one or more CPUs implementing the previous transform 508 to memory associated with one or more PPUs, including GPUs, implementing the subsequent transform 512. In at least one embodiment, once the accelerated data transform 512 completes its operation, the data is copied back to memory associated with one or more CPUs 510.

[0021] In at least one embodiment, if the subsequent transform 516 after the data has been copied to memory associated with one or more CPUs is accelerated or performed by one or more PPUs, such as a GPU, then a further copy 510 of the results from the previous data transform 512 to memory associated with the one or more PPUs, such as a GPU, must be performed in order to perform the subsequent accelerated transform 516. In at least one embodiment, the results from the subsequent accelerated transform 516 are then copied 514 back to memory associated with the one or more CPUs for use by further data transforms in the sequence of data transformations.

[0022] In at least one embodiment, further individual data transforms 522 may be accelerated by one or more PPUs, such as GPUs, after the sequence of data transforms has been performed by one or more CPUs. In at least one embodiment, at any point in the sequence of data transforms where a subsequent individual transform 522 is performed or accelerated by one or more PPUs, such as one or more GPUs, data must be copied from memory storing the results of the previous sequence of transforms 518 to memory associated with one or more PPUs, such as one or more GPUs, for use by the further individual accelerated transform 522. In at least one embodiment, after the further individual accelerated transform 522 completes processing, the results are then copied 520 from memory associated with one or more PPUs, including GPUs, to memory associated with one or more CPUs. In at least one embodiment, once the sequence of ordered or unordered transforms is complete, the transformed data 506 is ready for use by the training framework to train an untrained neural network.

[0023] 6 illustrates a sequence of example transformations for preparing data for neural network training and inference using the trained neural network, where a subset of the example transformations are combined into a master transform 610 performed by one or more parallel processing units (PPUs), such as one or more graphics processing units (GPUs), and the remaining example transformations are performed individually by one or more central processing units (CPUs), according to at least one embodiment. In at least one embodiment, input data 602 is prepared and transformed 604 using a sequence of data transformations implemented in part on one or more CPUs and in part on one or more PPUs, such as one or more GPUs, to create transformed data 606 used by the training framework to train an untrained neural network. In at least one embodiment, one or more transforms, including transforms that meet certain requirements described herein, when combined for serial processing by one or more PPUs, including GPUs, without transferring execution back to one or more CPUs and without copying intermediate data from memory associated with the one or more PPUs, such as GPUs, to memory associated with one or more CPUs, are combined into a master transform 610. In at least one embodiment, transforms 616 that are implemented for acceleration or processing by one or more PPUs, including one or more GPUs, but that are not included in the master transform 610, are processed individually by one or more PPUs, such as one or more GPUs.

[0024] In at least one embodiment, multiple transforms in a sequence of transforms that meet memory and data requirements are aggregated to become a master transform 610 to be accelerated or processed by one or more PPUs, such as one or more GPUs. In at least one embodiment, the transforms to be aggregated to become the master transform 610, when aggregated, must have memory requirements that fall within the constraints imposed by the one or more PPUs, such as GPUs. In at least one embodiment, the master transform 610 of the aggregated transforms must not require more memory than is available in the one or more PPUs, such as GPUs.

[0025] In at least one embodiment, transforms that are to be aggregated to become a master transform 610 must have compatible data inputs and outputs. In at least one embodiment, data inputs and outputs are compatible if they have dimensions and types that allow the transforms to be performed one after the other without further modification of the data dimensions or data types. In at least one embodiment, for example, a data transform that outputs an N×N matrix cannot provide its output to a subsequent data transform that requires K×K inputs without further data processing, such as padding or trimming. In at least one embodiment, only data transforms that output K×K outputs will match subsequent data transforms that require K×K data inputs.

[0026] In at least one embodiment, the master transform 610 includes two or more data transforms from a sequence of data transforms that include compatible data inputs and outputs. In at least one embodiment, the master transform 610 includes two or more data transforms that, in the aggregate, have memory requirements that can be satisfied by one or more PPUs, such as GPUs. In at least one embodiment, data outputs from individual data transforms in the sequence of data transforms performed on one or more CPUs will be transferred 608 from memory associated with one or more CPUs to memory associated with one or more PPUs, such as one or more GPUs, where the data outputs will be used as input to the master transform 610. In at least one embodiment, the master transform 610 will perform two or more aggregated data transform operations using one or more PPUs, such as one or more GPUs. In at least one embodiment, data outputs from the master transform 610 will be transferred 612 from memory associated with one or more PPUs, such as one or more GPUs, to memory associated with one or more CPUs. In at least one embodiment, the data output 612 from the master transform 610 is then used by the remaining data transforms in the sequence of data transforms.

[0027] In at least one embodiment, additional individual data transforms 616 not included in the master transform 610 may also be accelerated by one or more PPUs, such as one or more GPUs. In at least one embodiment, at any point in a sequence of data transformations where a subsequent individual transform 616 not included in the master transform 610 is performed or accelerated by one or more PPUs, such as one or more GPUs, the data must be copied or transferred 614 from memory storing the results of the previous sequence of transforms to memory associated with one or more PPUs, such as one or more GPUs, for use by the additional individual accelerated transform 616. In at least one embodiment, after the additional individual accelerated transform 616 completes processing, the results are then copied 618 from memory associated with one or more PPUs, such as one or more GPUs, to memory associated with one or more CPUs. In at least one embodiment, once a sequence of ordered or unordered transforms, including one or more master transforms 610, is complete, the transformed data 606 is ready for use by the training framework to train an untrained neural network.

[0028] 7 illustrates a system for determining one or more master transforms, each comprising two or more data transforms, from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment. In at least one embodiment, a system configuration 702, as described above, is understood to indicate the computing and memory resources in a system implementing the one or more master transforms. In at least one embodiment, the system configuration 702 and input data 704 described above are used by a component, such as a system profiler 708, to determine compute and resource availability for a system implementing the one or more master transforms to prepare data for training one or more untrained neural networks.

[0029] In at least one embodiment, input data 704, as described above and further herein, is used by an input transformation designer 710. In at least one embodiment, input transformation designer 710 is a group of software modules that include instructions that, when executed, perform operations to determine information related to data transformations. In at least one embodiment, input transformation designer 710 determines the total computational and memory requirements for transforming input data 704 for use in training an untrained neural network, as described herein. In at least one embodiment, input transformation designer 710 determines a predetermined sequence of data transformations for transforming input data 704 to be used in training an untrained neural network.

[0030] In at least one embodiment, transform controller 712 controls the determination of one or more master transforms given a profile of available computing and memory resources and the transforms 706 to be applied, such as those determined by system profiler 708 and input transform designer 710. In at least one embodiment, transform controller 712 includes a transform profiler 714 or other component or method to determine the compute requirements of each transform implementation or kernel for particular input data 704. In at least one embodiment, transform controller 712 uses transform profiler 714 or other component or method to determine the internal PPU (or GPU) memory requirements when the transforms are being processed. In at least one embodiment, transform controller 712 uses transform profiler 714 or other component or method to determine the dimensions of the input and output data for each transform in a sequence of transforms to be applied, such as those determined by input transform designer 710.

[0031] In at least one embodiment, the resource monitoring engine 716 monitors the available memory used during transform profiling 714 for particular input data 704. In at least one embodiment, the resource monitoring engine 716 imposes constraints on transform resource usage to determine the impact of the constraints on transform profiling 714 on compute and memory performance. In at least one embodiment, the resource monitoring engine 716 provides other resource usage information that is utilized by the transform controller to determine the resource consumption profile for individual and sequences of data transforms when applied to particular input data 704.

[0032] In at least one embodiment, the master transformation framework 718 utilizes information from the system profiler 708, the input transformation designer 710, and the transformation controller 712 to determine an optimized transformation configuration or sequence of transformations given a set of transformations, system resource availability, and input data. In at least one embodiment, the master transformation designer 720 combines two or more transformations in the sequence of transformations determined by the master transformation framework 718 into one or more master transformations. In at least one embodiment, two or more master transformations are created when multiple groups of two or more transforms are combined independently in the sequence of transformations determined by the master transformation framework 718. In at least one embodiment, a user explicitly allocates additional memory in one or more parallel processing units to specify two or more data transformations with mismatched input and output dimensions. In at least one embodiment, considering combining two or more data transformations with mismatched input and output dimensions when it is not possible to match the transforms based on the input and output dimensions enables optimized utilization of PPU resources and efficient use of PPU memory registers.

[0033] In at least one embodiment, the master transform designer 720 creates updated implementations or kernels for one or more master transforms, each containing two or more data transforms to be processed or executed by one or more PPUs, such as one or more GPUs. In at least one embodiment, the master transform designer 720 provides an efficient memory allocation mechanism for implementing several transforms running in parallel through multi-threaded CPU calls using a single GPU. In at least one embodiment, the master transform designer 720 merges two or more transforms into a single master transform. In at least one embodiment, the master transform designer 720 merges one or more groups of two or more transforms into multiple master transforms based on input and output data compatibility and memory and compute time requirements in the sequence of transforms, as described above. In at least one embodiment, the master transform designer 720 outputs an updated pre-transform and post-transform sequence 722 containing one or more master transforms for use in training an untrained neural network, as described herein.

[0034] 8 illustrates a process for determining one or more master transforms, each comprising two or more data transforms, from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment. In at least one embodiment, the process for determining a pre-transform and post-transform sequence comprising one or more master transforms begins 802 by determining a system configuration 804, including available processing and memory resources on a system implementing the data transforms to train an untrained neural network, as described above. In at least one embodiment, the available data transforms are configured 806, as described above, to determine a sequence of data transforms to apply to input data in preparation for training the untrained neural network.

[0035] In at least one embodiment, the transform controller profiles 808 the transforms in the set of data transforms against the input data to determine the compute time and memory resource requirements for each transform, as well as the dimensions of the transformed data inputs and outputs, as described above. In at least one embodiment, the transforms in the transform sequence are optimized 810 according to the techniques and information described above. Once the sequence of transforms is optimized, in at least one embodiment, one or more master transforms are designed 812 from the optimized sequence of transforms, and an optimized software implementation or kernel is generated, as described above. In at least one embodiment, after one or more master transforms, each encompassing two or more data transforms, are generated by the master transform designer 812, optimized pre-transform and post-transform sequences encompassing the one or more master transforms are output 814, completing the process of generating an optimized transform sequence encompassing the one or more master transforms 816.

[0036] Logic of inference and training 9A illustrates inference and / or training logic 915 used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided below in conjunction with FIG. 9A and / or FIG. 9B.

[0037] In at least one embodiment, the inference and / or training logic 915 may include, without limitation, code and / or data storage 901 that stores forward and / or output weights, and / or input / output data, and / or other parameters that configure neurons or layers of a neural network to be trained and / or used to infer, in one or more embodiments. In at least one embodiment, the training logic 915 may include or be coupled to code and / or data storage 901 that stores graph code or other software that controls the timing and / or ordering of logic loaded with weights and / or other parameter information, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may be included with other on-chip or off-chip data storage, including L1, L2, or L3 cache or system memory of a processor.

[0038] In at least one embodiment, any portion of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 901 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or code and / or data storage 901 is internal or external to the processor, or comprised of DRAM, SRAM, flash, or some other type of storage, may depend on, for example, available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in neural network inference and / or training, or any combination of these factors.

[0039] In at least one embodiment, the inference and / or training logic 915 may include, without limitation, code and / or data storage 905 that stores backpropagated and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that is trained and / or used to infer in accordance with aspects of one or more embodiments. In at least one embodiment, the code and / or data storage 905 stores weight parameters and / or input / output data for each layer of a neural network that is trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, the training logic 915 may include or be coupled to code and / or data storage 905 that stores graph code or other software that controls the timing and / or order into which weights and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 905 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage.In at least one embodiment, the choice of whether code and / or data storage 905 is internal or external to the processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, for example, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inferencing and / or training of the neural network, or any combination of these factors.

[0040] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0041] In at least one embodiment, the inference and / or training logic 915 may include one or more arithmetic logic units (“ALUs”) 910, including, without limitation, integer and / or floating point units, that perform logical and / or arithmetic operations based at least in part on or indicated by the training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) that are stored in activation storage 920 and are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, the activations stored in activation storage 920 are generated according to linear algebra and / or matrix-based calculations performed by ALU 910 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 905 and / or data 901 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 905, or code and / or data storage 901, or in another storage, on-chip or off-chip.

[0042] In at least one embodiment, ALU 910 is included within one or more processors or other hardware logic devices or circuits, although in other embodiments, ALU 910 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 910 may be included within an execution unit of a processor or may otherwise be included within an ALU bank accessible by an execution unit of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, data storage 901, code and / or data storage 905, and activation storage 920 may be on the same processor or other hardware logic device or circuit, although in other embodiments, they may be in different processors or other hardware logic devices or circuits, or some combination of the same processor or other hardware logic device or circuit and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, the inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0043] In at least one embodiment, activation storage 920 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 920 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 920 is internal or external to a processor, or comprised of DRAM, SRAM, flash, or some other type of storage, for example, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or any combination of these factors. In at least one embodiment, the inference and / or training logic 915 shown in Figure 9A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 915 shown in Figure 9A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0044] FIG. 9B illustrates inference and / or training logic 915 according to at least one various embodiment. In at least one embodiment, the inference and / or training logic 915 may include, without limitation, hardware logic in which computational resources are dedicated to or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 915 illustrated in FIG. 9B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 915 illustrated in FIG. 9B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, inference and / or training logic 915 includes, without limitation, code and / or data storage 901 and code and / or data storage 905, which may be used to store code (e.g., graph code), weight and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 9B , code and / or data storage 901 and code and / or data storage 905 are each associated with respective dedicated computational resources, such as computation hardware 902 and computation hardware 906. In at least one embodiment, computation hardware 902 and computation hardware 906 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 901 and code and / or data storage 905, respectively, with the results stored in activation storage 920.

[0045] In at least one embodiment, each of code and / or data storage 901 and 905 and corresponding computational hardware 902 and 906 corresponds to a different layer of a neural network, such that activations resulting from one "storage / computation pair 901 / 902" of code and / or data storage 901 and computational hardware 902 are provided as input to the next "storage / computation pair 905 / 906" of code and / or data storage 905 and computational hardware 906 to reflect the conceptual organization of the neural network. In at least one embodiment, storage / computation pairs 901 / 902 and 905 / 906 may each correspond to two or more neural network layers. In at least one embodiment, additional storage / computation pairs (not shown) may be included in inference and / or training logic 915 after or in parallel with storage / computation pairs 901 / 902 and 905 / 906.

[0046] Neural network training and deployment FIG. 10 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 91006 is trained using a training data set 1002. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0047] In at least one embodiment, the untrained neural network 1006 is trained using supervised learning, where the training data set 1002 includes inputs paired with desired outputs for those inputs, or the training data set 1002 includes inputs with known outputs, and the outputs of the neural network 1006 are manually scored. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner, processing inputs from the training data set 1002 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts the weights that control the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools to monitor how well the untrained neural network 1006 is converging toward a model, such as a trained neural network 1008, that is suitable for generating correct answers, such as results 1014, based on known input data, such as new data 1012. In at least one embodiment, the training framework 1004 iteratively trains the untrained neural network 1006 while adjusting weights to refine the output of the untrained neural network 1006 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until it reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0048] In at least one embodiment, the untrained neural network 1006 is trained using unsupervised learning, where the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 1002 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training data set 1002 and determine how individual inputs relate to the untrained data set 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 1008 that can perform operations useful for reducing the dimensionality of the new data set 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identifying data points in the new data set 1012 that deviate from the normal patterns of the new data set 1012.

[0049] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 1002. In at least one embodiment, the training framework 1004 may be used to implement incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 1008 to adapt to new data sets 1012 without forgetting the knowledge instilled in the network during initial training.

[0050] Data Center 11 illustrates an example data center 1100 in which at least one embodiment may be used. In at least one embodiment, data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0051] 11, data center infrastructure layer 1110 may include a resource orchestrator 1112, grouped computing resources 1114, and node computing resources (“node CRs”) 1116(1) through 1116(N), where “N” represents any positive integer. In at least one embodiment, node CRs 1116(1) through 1116(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power supply modules, cooling modules, etc. In at least one embodiment, one or more of the nodes CR 1116(1)-1116(N) may be a server having one or more of the computing resources described above.

[0052] In at least one embodiment, grouped computing resources 1114 may include separate groups of node CRs housed within one or more racks (not shown) or multiple racks housed in a data center in various graphical locations (also not shown). Separate groups of node CRs within grouped computing resources 1114 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources that support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0053] In at least one embodiment, resource orchestrator 1112 may configure or otherwise control one or more nodes CR 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource orchestrator 1112 may include a software design infrastructure (“SDI”) management entity for data center 1100. In at least one embodiment, resource orchestrator may include hardware, software, or some combination thereof.

[0054] As shown in FIG. 11 , in at least one embodiment, framework layer 1120 includes a job scheduler 1132, a configuration manager 1134, a resource manager 1136, and a distributed file system 1138. In at least one embodiment, framework layer 1120 may include frameworks supporting software 1132 in software layer 1130 and / or one or more applications 1142 in application layer 1140. In at least one embodiment, software 1132 or applications 1142 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter, “Spark”), which may utilize distributed file system 1138 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1132 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 1100. In at least one embodiment, configuration manager 1134 may be capable of configuring different tiers, such as software tier 1130 and framework tier 1120, which includes Spark and distributed file system 1138 to support large-scale data processing. In at least one embodiment, resource manager 1136 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 1138 and job scheduler 1132. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 in data center infrastructure tier 1110.In at least one embodiment, resource manager 1136 may work in conjunction with resource orchestrator 1112 to manage these mappings or allocated computing resources.

[0055] In at least one embodiment, software 1132 included in software layer 1130 may include software used by nodes CR 1116(1)-1116(N), grouped computing resources 1114, and / or at least a portion of distributed file system 1138 of framework layer 1120. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0056] In at least one embodiment, the applications 1142 included in the application layer 1140 may include one or more types of applications used by at least a portion of the nodes CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1138 of the framework layer 1120. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and machine learning applications including training or inference software, machine learning framework software (e.g., PyTorch, Tensorflow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0057] In at least one embodiment, any of configuration manager 1134, resource manager 1136, and resource orchestrator 1112 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable a data center operator of data center 1100 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0058] In at least one embodiment, data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1100 by using the weight parameters calculated by one or more training techniques described herein.

[0059] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service that allows a user to perform training or inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0060] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 11 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0061] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 11 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0062] Autonomous Vehicles 12A illustrates an example of an autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as “vehicle 1200”) may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-tractor trailer truck used for hauling cargo. In at least one embodiment, vehicle 1200 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0063] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In one or more embodiments, vehicle 1200 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1200 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0064] In at least one embodiment, vehicle 1200 may include components such as, without limitation, a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1200 may include a propulsion system 1250 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to a drive train of vehicle 1200, which may include, without limitation, a transmission that enables propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving a signal from throttle / accelerator 1252.

[0065] In at least one embodiment, steering system 1254, which may include without limitation a steering wheel, is used to steer vehicle 1200 (e.g., along a desired path or route) when propulsion system 1250 is operating (e.g., when the vehicle is moving). In at least one embodiment, steering system 1254 may receive signals from steering actuator 1256. The steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1246 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1248 and / or brake sensor.

[0066] In at least one embodiment, controller 1236, which may include, without limitation, one or more systems on chip (“SoC”) (not shown in FIG. 12A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, controller 1236 may send signals to operate vehicle brakes via brake actuator 1248, steering system 1254 via steering actuator 1256, and propulsion system 1250 via throttle / accelerator 1252. Controller 1236 may also include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1200. In at least one embodiment, the controllers 1236 may include a first controller 1236 for autonomous driving functions, a second controller 1236 for functional safety functions, a third controller 1236 for artificial intelligence functions (e.g., computer vision), a fourth controller 1236 for infotainment functions, a fifth controller 1236 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1236 may handle two or more of the above functionalities, two or more controllers 1236 may handle a single functionality, and / or any combination thereof.

[0067] In at least one embodiment, controller 1236 provides signals to control one or more components and / or systems of vehicle 1200 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system (“GNSS”) sensors 1258 (e.g., global positioning system sensors), RADAR sensors 1260, ultrasonic sensors 1262, LIDAR sensors 1264, inertial measurement units (“IMUs”), and the like. 12A ), a speed sensor 1244 (e.g., for measuring the speed of the vehicle 1200), a vibration sensor 1242, a steering sensor 1240, a brake sensor (e.g., as part of a brake sensor system 1246), and / or other types of sensors.

[0068] In at least one embodiment, one or more of the controllers 1236 may receive input (e.g., represented by input data) from the instrument cluster 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 12A )), location data (e.g., the location of vehicle 1200 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object states as perceived by controller 1236, etc. For example, in at least one embodiment, HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0069] In at least one embodiment, vehicle 1200 further includes network interface 1224, which may use a wireless antenna 1226 and / or a modem to communicate over one or more networks. For example, in at least one embodiment, network interface 1224 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. In at least one embodiment, the wireless antenna 1226 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and / or low power wide-area networks (“LPWAN”) such as LoRaWAN, SigFox, etc.

[0070] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 12A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0071] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 12A for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0072] 12B illustrates example camera locations and fields of view for autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on vehicle 1200.

[0073] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1200. The camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0074] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0075] In at least one embodiment, one or more of the cameras may be mounted in a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from the interior of the vehicle (e.g., reflections reflected from the dashboard onto the front mirror) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate matches the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. With respect to side view cameras, in at least one embodiment, the camera may also be integrated into the four pillars at each corner of the cabin.

[0076] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 1200 may be used for a surroundings view to facilitate identification of the path and obstacles ahead, and may be used in conjunction with controller 1236 and / or one or more of the control SoCs to assist in generating an occupancy grid and / or providing information essential for determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings (“LDW”), autonomous cruise control (“ACC”), and / or traffic sign recognition.

[0077] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1270 may be used to perceive objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While only one wide-angle camera 1270 is shown in FIG. 12B , in other embodiments, there may be any number (including zero) of wide-angle cameras 1270 on the vehicle 1200. In at least one embodiment, any number of long-range cameras 1298 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera 1298 may also be used for object detection and classification, as well as basic object tracking.

[0078] In at least one embodiment, any number of stereo cameras 1268 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit with a scalable processing unit, which may provide programmable logic ("FPGA") and a multi-core microprocessor with an integrated Controller Area Network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1200 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1268 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that measures the distance from the vehicle 1200 to target objects and may use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1268 may be used in addition to or instead of those described herein.

[0079] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of vehicle 1200 (e.g., side view cameras) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1274 (e.g., four surrounding cameras 1274 as shown in FIG. 12B ) may be disposed on vehicle 1200. Surrounding cameras 1274 may include, without limitation, any number and combination of wide-angle cameras 1270, fisheye cameras, and / or 360-degree cameras. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of vehicle 1200. In at least one embodiment, vehicle 1200 may use three surrounding cameras 1274 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0080] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1200 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as front cameras described herein (e.g., long-range camera 1298, and / or mid-range camera 1276, stereo camera 1268, infrared camera 1272, etc.).

[0081] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 12B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0082] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 12B for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0083] FIG. 12C is a block diagram illustrating a system architecture for the example autonomous vehicle 1200 of FIG. 12A , according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1200 of FIG. 12C is shown as connected via a bus 1202. In at least one embodiment, the bus 1202 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, the CAN may be a network internal to the vehicle 1200 used to help control various features and functions of the vehicle 1200, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1202 may be configured with tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1202 may be read to determine steering angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be an ASIL B compliant CAN bus.

[0084] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or instead of CAN. In at least one embodiment, any number of buses 1202 may be present, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1202 may be used to perform different functions and / or to provide redundancy. For example, a first bus 1202 may be used for collision avoidance functions, and a second bus 1202 may be used for actuation control. In at least one embodiment, each bus 1202 may communicate with any of the components of vehicle 1200, or two or more buses 1202 may communicate with the same component. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1204, each of controllers 1236, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0085] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to FIG. 12A. Controller 1236 may be used for a variety of functions. In at least one embodiment, controller 1236 may be coupled to any of a variety of other components and systems of vehicle 1200 and may be used for control of vehicle 1200, artificial intelligence of vehicle 1200, and / or infotainment of vehicle 1200.

[0086] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. Each SoC 1204 may include, without limitation, a central processing unit ("CPU") 1206, a graphics processing unit ("GPU") 1208, a processor 1210, a cache 1212, an accelerator 1214, a data store 1216, and / or other components and features not shown. In at least one embodiment, SoC 1204 may be used to control vehicle 1200 in various platforms and systems. For example, in at least one embodiment, SoC 1204 may be incorporated into a system (e.g., that of vehicle 1200) having a high definition ("HD") map 1222 that may obtain map refreshes and / or updates via a network interface 1224 from one or more servers (not shown in FIG. 12C ).

[0087] In at least one embodiment, CPU 1206 may include a CPU cluster or CPU complex (also referred to herein as a “CCPLEX”). In at least one embodiment, CPU 1206 may include multiple cores and / or level 2 (“L2”) caches. For example, in at least one embodiment, CPU 1206 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1206 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 MB of L2 cache). In at least one embodiment, CPU 1206 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPU 1206 to be active at any given time.

[0088] In at least one embodiment, one or more of the CPUs 1206 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPU 1206 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines the best power state for cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0089] In at least one embodiment, GPU 1208 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1208 may use an extended tensor instruction set. In one embodiment, GPU 1208 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1208 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1208 may use a compute application programming interface (API). In at least one embodiment, GPU 1208 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA).

[0090] In at least one embodiment, one or more of GPUs 1208 may be power-optimized for best performance in automotive and embedded use cases. For example, in one embodiment, GPU 1208 may be fabricated on fin field-effect transistors ("FinFETs"). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to allow finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0091] In at least one embodiment, one or more of GPUs 1208 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, providing, in some instances, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or instead of the HBM memory.

[0092] In at least one embodiment, GPU 1208 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU 1208 to directly access the page tables of CPU 1206. In at least one embodiment, when the memory management unit (“MMU”) of GPU 1208 encounters a miss, an address translation request may be sent to CPU 1206. In at least one embodiment, in response, CPU 1206 may look up the virtual-to-physical address mapping in its page tables and send the translation back to GPU 1208. In at least one embodiment, unified memory technology may enable a single, unified virtual address space for both CPU 1206 and GPU 1208 memory, thereby simplifying programming of GPU 1208 and porting applications to GPU 1208.

[0093] In at least one embodiment, GPU 1208 may include any number of access counters that may record the frequency of GPU 1208's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0094] In at least one embodiment, one or more of SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, cache 1212 may include a level 3 (“L3”) cache available to both CPU 1206 and GPU 1208 (e.g., connected to both CPU 1206 and GPU 1208). In at least one embodiment, cache 1212 may include a write-back cache capable of recording line state, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may also be used.

[0095] In at least one embodiment, one or more of the SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1208 and offload some of the GPU 1208's tasks (e.g., freeing up more cycles of the GPU 1208 to perform other tasks). In at least one embodiment, accelerator 1214 can be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0096] In at least one embodiment, accelerator 1214 (e.g., a hardware-accelerated cluster) may include a deep learning accelerator (“DLA”). The DLA may include, without limitation, one or more tensor processing units (“TPUs”), which may be further configured to provide tens of trillions of operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). The DLA may further be optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the DLA's design may provide improved performance per millimeter over a typical general-purpose GPU, typically significantly exceeding the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, a CNN for object identification and detection using data from a camera sensor, a CNN for distance estimation using data from a camera sensor, a CNN for emergency vehicle detection and identification using data from microphone 1296, a CNN for face recognition and vehicle owner identification using data from a camera sensor, and / or a CNN for security and / or safety events.

[0097] In at least one embodiment, the DLA may perform any function of the GPU 1208, and a designer may target either the DLA or the GPU 1208 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1208 and / or other accelerators 1214.

[0098] In at least one embodiment, accelerator 1214 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. The PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0099] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any of the cameras described herein), an image signal processor, and / or the like. In at least one embodiment, the RISC cores may each include any amount of memory. In at least one embodiment, the RISC cores may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0100] In at least one embodiment, the DMA may allow components of the PVA to access system memory independently of the CPU 1206. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0101] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0102] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, a PVA may include additional error correcting code ("ECC") memory to enhance overall system security.

[0103] In at least one embodiment, the accelerator 1214 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1214. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM consisting of eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0104] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0105] In at least one embodiment, one or more of SoCs 1204 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0106] In at least one embodiment, accelerator 1214 (e.g., a hardware accelerator cluster) has diverse uses for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that require low-latency, low-power, and predictable run-times, even with small data sets. In at least one embodiment, in an autonomous vehicle such as vehicle 1200, the PVA is designed to run traditional computer vision algorithms because they are effective for object detection and integer arithmetic.

[0107] For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, algorithms based on semi-global matching may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0108] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0109] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence allows the system to make further decisions regarding which detections should be considered positive detections rather than false detections. For example, in at least one embodiment, the system may set a threshold for confidence and consider only detections that exceed the threshold to be positive detections. In embodiments where an automatic emergency braking (“AEB”) system is used, a false detection may cause the vehicle to automatically apply emergency braking, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as, among others, the dimensions of the bounding box, a ground surface estimate obtained (e.g., from another subsystem), an output from the IMU sensor 1266 that correlates with the orientation of the vehicle 1200, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., the LIDAR sensor 1264 or the RADAR sensor 1260).

[0110] In at least one embodiment, one or more of the SoCs 1204 may include a data store 1216 (e.g., memory). In at least one embodiment, the data store 1216 may be on-chip memory of the SoC 1204, which may store neural networks running on the GPU 1208 and / or DLA. In at least one embodiment, the capacity of the data store 1216 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1216 may comprise an L2 or L3 cache.

[0111] In at least one embodiment, one or more of the SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). The processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 1204, and / or manage the power state of the SoC 1204. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1204 may use the ring oscillator to detect the temperature of the CPU 1206, the GPU 1208, and / or the accelerator 1214. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1204 in a low power state, and / or place the vehicle 1200 in a driver-safety shutdown mode (e.g., bring the vehicle 1200 to a safety shutdown).

[0112] In at least one embodiment, processor 1210 may further include a set of embedded processors that may act as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that includes a digital signal processor with dedicated RAM.

[0113] In at least one embodiment, processor 1210 may further include an always-on processor engine that may provide the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0114] In at least one embodiment, the processor 1210 may further include a safety cluster engine, which may include, without limitation, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 1210 may further include a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor 1210 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0115] In at least one embodiment, processor 1210 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 1270, surrounding camera 1274, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 1204 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0116] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0117] In at least one embodiment, the video image composer may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image composer may also be used to composite the user interface when the operating system desktop is in use, eliminating the need for GPU 1208 to continually render new surfaces. In at least one embodiment, the video image composer may be used to offload GPU 1208 when GPU 1208 is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0118] In at least one embodiment, one or more of the SoCs 1204 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0119] In at least one embodiment, one or more of the SoCs 1204 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces that allow communication with other devices. The SoCs 1204 may be used to process data from cameras (e.g., connected via gigabit multimedia serial links and Ethernet), data from sensors (e.g., LIDAR sensors 1264, RADAR sensors 1260, etc., which may be connected via Ethernet), data from bus 1202 (e.g., vehicle 1200 speed, steering wheel position, etc.), data from GNSS sensors 1258 (e.g., connected via Ethernet or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1204 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 1206.

[0120] In at least one embodiment, SoC 1204 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible and reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC 1204 is faster, more reliable, and more energy- and space-efficient than traditional systems. For example, in at least one embodiment, accelerator 1214, when combined with CPU 1206, GPU 1208, and data store 1216, may provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0121] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language, such as the C programming language, to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0122] Embodiments described herein allow multiple neural networks to be implemented simultaneously and / or sequentially, and the results can be combined to enable Levels 3-5 autonomous driving capabilities. For example, in at least one embodiment, the CNN running on the DLA or a separate GPU (e.g., GPU 1220) may include text and word recognition, enabling the supercomputer to read and understand traffic signs, including signs for which the neural network was not specifically trained. In at least one embodiment, the DLA may further include a neural network capable of identifying and interpreting signs and providing a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0123] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Icy" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Icy" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1208.

[0124] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC 1204 provides security against theft and / or carjacking.

[0125] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1204 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1258. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in the United States, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program to execute an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1262 until the emergency vehicle has passed.

[0126] In at least one embodiment, vehicle 1200 may include a CPU 1218 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 1218 may include, for example, an X86 processor. CPU 1218 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 1204 and / or monitoring the status and health of controller 1236 and / or infotainment system on a chip (“infotainment SoC”) 1230.

[0127] In at least one embodiment, vehicle 1200 may include GPU 1220 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, GPU 1220 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1200.

[0128] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, without limitation, a wireless antenna 1226 (e.g., one or more wireless antennas 1226 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity over the Internet with the cloud (e.g., servers and / or other network devices), other vehicles, and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and the other vehicles and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1200). In at least one embodiment, the above-described features may be part of a cooperative adaptive cruise control feature of the vehicle 1200.

[0129] In at least one embodiment, network interface 1224 may include an SoC that provides modulation and demodulation functionality and enables controller 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0130] In at least one embodiment, vehicle 1200 may further include a data store 1228, which may include, without limitation, off-chip (e.g., not on SoC 1204) storage. In at least one embodiment, data store 1228 may include, without limitation, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash, a hard disk, and / or other components and / or devices that may store at least one bit of data.

[0131] In at least one embodiment, vehicle 1200 may further include GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) that assist with mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example and without limitation, a GPS that uses a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0132] In at least one embodiment, vehicle 1200 may further include a RADAR sensor 1260. The RADAR sensor 1260 may be used by vehicle 1200 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. The RADAR sensor 1260 may use CAN and / or bus 1202 for control (e.g., to transmit data generated by the RADAR sensor 1260) and to access object tracking data, and in some instances may have Ethernet access to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, the RADAR sensor 1260 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of the RADAR sensors 1260 are pulse-Doppler RADAR sensors.

[0133] In at least one embodiment, the RADAR sensor 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 meter range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1260 may help distinguish between static and moving objects and may be used by the ADAS system 1238 to provide emergency braking assistance and forward collision warning. The sensors 1260 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1200 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting vehicle 1200's lane.

[0134] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1260 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1238 to provide blind spot detection and / or lane change assistance.

[0135] In at least one embodiment, vehicle 1200 may further include ultrasonic sensors 1262. Ultrasonic sensors 1262 may be located at the front, rear, and / or sides of vehicle 1200 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1262 may operate at functional safety level ASIL B.

[0136] In at least one embodiment, vehicle 1200 may include a LIDAR sensor 1264. The LIDAR sensor 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor 1264 may be functional safety level ASIL B. In at least one embodiment, vehicle 1200 may include multiple LIDAR sensors 1264 (e.g., two, four, six, etc.), which may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0137] In at least one embodiment, the LIDAR sensor 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1264 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors 1264 may be used. In such embodiments, the LIDAR sensor 1264 may be implemented as a small device that may be integrated into the front, rear, sides, and / or corners of the vehicle 1200. In at least one embodiment, the LIDAR sensor 1264 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 m, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1264 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0138] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1200 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1200 to the object. In at least one embodiment, flash LIDAR allows a highly accurate, undistorted image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be installed, one on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0139] In at least one embodiment, the vehicle may further include an IMU sensor 1266. In at least one embodiment, the IMU sensor 1266 may be positioned at the center of the rear axle of the vehicle 1200 in at least one embodiment. In at least one embodiment, the IMU sensor 1266 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, the IMU sensor 1266 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, the IMU sensor 1266 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0140] In at least one embodiment, the IMU sensor 1266 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical system ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1266 may enable the vehicle 1200 to estimate its orientation by directly observing velocity changes and correlating them from the GPS to the IMU sensor 1266, without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1266 and the GNSS sensor 1258 may be combined into a single integrated unit.

[0141] In at least one embodiment, vehicle 1200 may include microphones 1296 located in and / or around vehicle 1200. In at least one embodiment, microphones 1296 may be used for, among other things, emergency vehicle detection and identification.

[0142] In at least one embodiment, vehicle 1200 may further include any number of camera types, including stereo camera 1268, wide-angle camera 1270, infrared camera 1272, perimeter camera 1274, long-range camera 1298, mid-range camera 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1200. In at least one embodiment, the types of cameras used vary depending on vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1200. In at least one embodiment, the number of cameras may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. The cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera is described in further detail herein above with respect to Figures 12A and 12B.

[0143] In at least one embodiment, vehicle 1200 may further include a vibration sensor 1242. Vibration sensor 1242 may measure vibrations of components of vehicle 1200, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 1242 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0144] In at least one embodiment, vehicle 1200 may include an ADAS system 1238. ADAS system 1238 may include, without limitation, an SoC in some instances. In at least one embodiment, the ADAS systems 1238 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0145] In at least one embodiment, the ACC system may use a RADAR sensor 1260, a LIDAR sensor 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately preceding the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1200 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0146] In at least one embodiment, the CACC system uses information from other vehicles, which may be received via a wireless link or indirectly via a network connection (e.g., via the Internet) from other vehicles via network interface 1224 and / or wireless antenna 1226. In at least one embodiment, a direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while an indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, the V2V communication concept provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of vehicle 1200 and in the same lane), while the I2V communication concept provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 1200 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0147] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0148] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0149] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1200 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. The LKA system provides steering input or braking control to correct the vehicle 1200 if the vehicle 1200 begins to drift out of its lane.

[0150] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1260 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0151] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1200. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration component.

[0152] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1200 itself determines whether to follow the results from the primary computer (e.g., first controller 1236) or the secondary computer (e.g., second controller 1236). For example, in at least one embodiment, the ADAS system 1238 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on various hardware components to detect perception errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1238 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0153] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0154] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary and secondary computers. In at least one embodiment, the monitoring MCU's neural network may learn when the secondary computer's output may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the monitoring MCU's neural network may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the monitoring MCU's neural network may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of SoC 1204.

[0155] In at least one embodiment, the ADAS system 1238 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides the same overall result, the supervisory MCU may have greater confidence that the overall result is correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0156] In at least one embodiment, the output of the ADAS system 1238 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0157] In at least one embodiment, vehicle 1200 may further include infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1230 is shown and described as an SoC, in at least one embodiment, it need not be an SoC and may include, without limitation, two or more individual components. In at least one embodiment, infotainment SoC 1230 may include, without limitation, a combination of hardware and software that may be used to provide vehicle 1200 with audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, rear park assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.). For example, infotainment SoC 1230 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1234, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1230 may also be used to provide information (e.g., visual and / or auditory) to a vehicle user, such as information from ADAS system 1238, autonomous driving information such as vehicle maneuver plans, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0158] In at least one embodiment, infotainment SoC 1230 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1230 may communicate with other devices, systems, and / or components of vehicle 1200 through bus 1202 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, infotainment SoC 1230 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 1236 (e.g., vehicle 1200's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1230 may place vehicle 1200 in a driver-safety shutdown mode, as described herein.

[0159] In at least one embodiment, vehicle 1200 may further include an instrument cluster 1232 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). Instrument cluster 1232 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, instrument cluster 1232 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some instances, information may be displayed and / or shared between infotainment SoC 1230 and instrument cluster 1232. In at least one embodiment, instrument cluster 1232 may be included as part of infotainment SoC 1230, or vice versa.

[0160] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 12C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0161] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 12C for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0162] 12D is a diagram of a system 1276 for communicating between a cloud-based server and the autonomous vehicle 1200 of FIG. 12A , according to at least one embodiment. In at least one embodiment, the system 1276 may include, without limitation, a server 1278, a network 1290, and any number and type of vehicles, including the vehicle 1200. The server 1278 may include, without limitation, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(H) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1288 developed by NVIDIA, and / or a PCIe connection 1286. In at least one embodiment, GPUs 1284 are connected to each other via an NVLink and / or an NVSwitch SoC, and GPUs 1284 and PCIe switches 1282 are connected via a PCIe interconnect. In at least one embodiment, eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are illustrated, but this is not intended to be limiting. In at least one embodiment, servers 1278 may each include any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination, without limitation. For example, in at least one embodiment, the servers 1278 may each include 8, 16, 32, and / or more GPUs 1284.

[0163] In at least one embodiment, server 1278 may receive image data from the vehicle over network 1290 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1278 may transmit neural network 1292, updated neural network 1292, and / or map information 1294, including, without limitation, information regarding traffic and road conditions, to the vehicle over network 1290. In at least one embodiment, updates to map information 1294 may include, without limitation, updates to HD map 1222, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1292, updated neural network 1292, and / or map information 1294 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1278 and / or other servers).

[0164] In at least one embodiment, server 1278 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. The training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1290) and / or used by server 1278 to remotely monitor the vehicle.

[0165] In at least one embodiment, server 1278 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1278 may include a deep learning supercomputer and / or dedicated AI computer powered by GPU 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1278 may also include a deep learning infrastructure using a CPU-powered data center.

[0166] In at least one embodiment, the deep learning infrastructure of server 1278 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as a series of images and / or objects that vehicle 1200 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1200; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1200 has failed, server 1278 may send a signal to vehicle 1200 to command its fail-safe computer to assume control, notify the occupants, and complete a safe stopping maneuver.

[0167] In at least one embodiment, server 1278 may include a GPU 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 915 is used to implement one or more embodiments. Details regarding hardware structure 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B.

[0168] Computer Systems 13 is a block diagram illustrating an example computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof 1300 formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1300 may include components such as, without limitation, processor 1302 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1300 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1300 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0169] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0170] In at least one embodiment, computer system 1300 may include, without limitation, a processor 1302, which may include, without limitation, one or more execution units 1308 that perform training and / or inference of machine learning models according to the techniques described herein. In at least one embodiment, system 13 is a single-processor desktop or server system, while in other embodiments, system 13 may be a multiprocessor system. In at least one embodiment, processor 1302 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310, which may transmit data signals between processor 1302 and other components within computer system 1300.

[0171] In at least one embodiment, processor 1302 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1302. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1306 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0172] In at least one embodiment, processor 1302 also includes an execution unit 1308, including, without limitation, logic to perform integer and floating-point operations. Processor 1302 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1308 may include logic to accommodate a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309, along with associated circuitry to execute the instructions, in the instruction set of general-purpose processor 1302, operations used by many multimedia applications may be performed using packed data in general-purpose processor 1302. In one or more embodiments, many multimedia applications may be accelerated and run more efficiently by performing operations on packed data using the full width of the processor's data bus, which may eliminate the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0173] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, without limitation, memory 1320. In at least one embodiment, memory 1320 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. Memory 1320 may store instructions 1319 and / or data 1321, represented by data signals, that may be executed by processor 1302.

[0174] In at least one embodiment, a system logic chip may be coupled to processor bus 1310 and memory 1320. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1316, and processor 1302 may communicate with MCH 1316 via processor bus 1310. In at least one embodiment, MCH 1316 may provide a high-bandwidth memory path 1318 to memory 1320 for storing instructions and data, as well as for storing graphics commands, data, and textures. In at least one embodiment, MCH 1316 may route data signals between processor 1302, memory 1320, and other components of computer system 1300, and may bridge data signals between processor bus 1310, memory 1320, and system I / O 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1316 may be coupled to memory 1320 via a high-bandwidth memory path 1318, and graphics / video card 1312 may be coupled to MCH 1316 via an Accelerated Graphics Port (“AGP”) interconnect 1314.

[0175] In at least one embodiment, computer system 1300 may use system I / O 1322, a proprietary hub interface bus that couples MCH 1316 to I / O controller hub (“ICH”) 1330. In at least one embodiment, ICH 1330 may directly connect to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1320, a chipset, and processor 1302. Examples may include, without limitation, an audio controller 1329, a firmware hub ("flash BIOS") 1328, a wireless transceiver 1326, data storage 1324, a legacy I / O controller 1323 including a user input and keyboard interface, a serial expansion port 1327 such as a Universal Serial Bus ("USB"), and a network controller 1334. Data storage 1324 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0176] In at least one embodiment, Figure 13 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 13 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in Figure cc may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 may be interconnected using a compute express link (CXL) interconnect.

[0177] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 13 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0178] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 13 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0179] 14 is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410, according to at least one embodiment. In at least one embodiment, electronic device 1400 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0180] In at least one embodiment, system 1400 may include a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, including, without limitation, processor 1410 coupled using a bus or interface, such as an I / O bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 14 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, FIG. 14 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in FIG. 14 are interconnected with proprietary interconnects and standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 14 are interconnected using Compute Express Link (CXL).

[0181] In at least one embodiment, FIG. 14 illustrates a display 1424, a touch screen 1425, a touch pad 1430, a Near Field Communications unit ("NFC") 1445, a sensor hub 1440, a thermal sensor 1446, an Express Chipset ("EC") 1435, a Trusted Platform Module ("TPM") 1438, a BIOS / firmware / flash memory ("BIOS,FW flash") 1422, a DSP 1460, a drive ("SSD or HDD") 1420, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1440, a wireless local area network ("WLAN") 1450, a wireless local area network ("WLAN") 1460, a wireless local area network ("WLAN") 1470, a wireless local area network ("WLAN") 1480, a wireless local area network ("WLAN") 1490, a wireless local area network ("WLAN") 1500, a wireless local area network ("WLAN") 1510, a wireless local area network ("WLAN") 1520, a wireless local area network ("WLAN") 1530, a wireless local area network ("WLAN") 1540, a wireless local area network ("WLAN") 1550, a wireless local area network ("WLAN") 1560, a wireless local area network ("SSD") 1520, a wireless local area network ("HDD") 1520, a wireless local area network ("SSD") 1540, a wireless local area network ("HDD") 1520, a wireless local area network ("SSD") 1520, a wireless local area network ("HDD") 1540, a wireless local area network ("SSD") 1520, a wireless local area network ("HDD") 1540, a The memory may include a Bluetooth unit 1450, a Bluetooth unit 1452, a Wireless Wide Area Network unit (“WWAN”) 1456, a Global Positioning System (GPS) 1455, a camera such as a USB 3.0 camera (“USB 3.0 camera”) 1454, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1415, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0182] In at least one embodiment, other components may be communicatively coupled to processor 1410 through the aforementioned components. In at least one embodiment, an accelerometer 1441, an ambient light sensor (“ALS”) 1442, a compass 1443, and a gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1446, and a touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, a speaker 1463, headphones 1464, and a microphone (“mic”) 1465 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1464, which may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1464 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, SIM card ("SIM") 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as WLAN unit 1450 and Bluetooth unit 1452, as well as WWAN unit 1456, may be implemented in a Next Generation Form Factor ("NGFF").

[0183] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 14 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0184] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 14 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0185] 15 illustrates a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0186] In at least one embodiment, computer system 1500 includes at least one central processing unit ("CPU") 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as, but not limited to, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1504, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1522 provides an interface with other computing devices and networks to receive data from other systems and transmit data from computer system 1500 to other systems.

[0187] In at least one embodiment, computer system 1500 includes, without limitation, input device(s) 1508, a parallel processing system 1512, and a display device 1506, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1508, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

[0188] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 15 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0189] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 15 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0190] 16 illustrates a computer system 1600 according to at least one embodiment. In at least one embodiment, computer system 1600 may include, without limitation, a computer 1610 and a USB stick 1620. In at least one embodiment, computer system 1610 may include, without limitation, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1610 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0191] In at least one embodiment, USB stick 1620 includes, without limitation, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, processing unit 1630 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1630 may include, without limitation, any number and types of processing cores (not shown). In at least one embodiment, processing core 1630 comprises an application specific integrated circuit ("ASIC") optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, processing core 1630 is a tensor processing unit ("TPC") optimized to perform machine learning inference operations. In at least one embodiment, processing core 1630 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0192] In at least one embodiment, USB interface 1640 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 may include any amount and type of logic that enables processing unit 1630 to interface with a device (e.g., computer 1610) via USB connector 1640.

[0193] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 16 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0194] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 16 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0195] 17A illustrates an exemplary architecture in which multiple GPUs 1710-1713 are communicatively coupled to multiple multi-core processors 1705-1706 through high-speed links 1740-1743 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 1740-1743 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. Various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0196] Additionally, in one embodiment, two or more of GPUs 1710-1713 may be interconnected through high-speed links 1729-1730, which may be implemented using the same or different protocol / links as used for high-speed links 1740-1743. Similarly, two or more of multi-core processors 1705-1706 may be connected through high-speed link 1728, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 17A may be achieved using the same protocol / links (e.g., through a common interconnect fabric).

[0197] In one embodiment, each multi-core processor 1705-1706 is communicatively coupled to processor memory 1701-1702 through a memory interconnect 1726-1727, respectively, and each GPU 1710-1713 is communicatively coupled to GPU memory 1720-1723 through a GPU memory interconnect 1750-1753, respectively. Memory interconnects 1726-1727 and 1750-1753 may utilize the same or different memory access technologies. By way of example, and not limitation, processor memory 1701-1702 and GPU memory 1720-1723 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or non-volatile memory such as 3D XPoint or Nano-RAM. In one embodiment, some portions of processor memory 1701-1702 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0198] As described herein, the various processors 1705-1706 and GPUs 1710-1713 may each be physically coupled to a particular memory 1701-1702, 1720-1723, but a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among the various physical memories. For example, the processor memories 1701-1702 may each have 64 GB of system memory address space, and the GPU memories 1720-1723 may each have 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0199] 17B shows further details of the interconnection between multi-core processor 1707 and graphics acceleration module 1746 according to one example embodiment. Graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to processor 1707 via high-speed link 1740. Alternatively, graphics acceleration module 1746 may be integrated in the same package or chip as processor 1707.

[0200] In at least one embodiment, the illustrated processor 1707 includes multiple cores 1760A-1760D, each having a translation lookaside buffer 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components, not shown, for executing instructions and processing data. The caches 1762A-1762D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included in the caches 1762A-1762D and shared by the set of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. The processor 1707 and graphics acceleration module 1746 are coupled to system memory 1714, which may include processor memory 1701-1702 of FIG. 17A.

[0201] Coherence is maintained for data and instructions stored in the various caches 1762A-1762D, 1756, and system memory 1714 through inter-core communication via a coherence bus 1764. For example, each cache may have associated cache coherence logic / circuitry that communicates over the coherence bus 1764 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 1764 to monitor cache accesses.

[0202] In one embodiment, proxy circuit 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764 to enable graphics acceleration module 1746 to participate in cache coherence protocols as a peer of cores 1760A-1760D. In particular, interface 1735 provides a connection to proxy circuit 1725 over high-speed link 1740 (e.g., PCIe bus, NVLink, etc.), and interface 1737 connects graphics acceleration module 1746 to link 1740.

[0203] In one implementation, the accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1731, 1732, N of the graphics acceleration module 1746. The graphics processing engines 1731, 1732, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1731, 1732, N may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731-1732, N, or the graphics processing engines 1731-1732, N may be individual GPUs integrated into a common package, line card, or chip.

[0204] In one embodiment, accelerator integrated circuitry 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1714. MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, cache 1738 stores commands and data for efficient access by graphics processing engines 1731-1732, N. In one embodiment, data stored in cache 1738 and graphics memory 1733-1734, M is kept coherent with core caches 1762A-1762D, 1756, and system memory 1714. As noted above, this may be accomplished via the proxy circuit 1725 on behalf of the cache 1738 and memory 1733-1734, M (e.g., sending updates regarding modifications / accesses of cache lines in the processor caches 1762A-1762D, 1756 to the cache 1738 and receiving updates from the cache 1738).

[0205] A set of registers 1745 stores context data for threads executed by the graphics processing engines 1731-1732, and a context management circuit 1748 manages thread contexts. For example, the context management circuit 1748 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1748 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 1748 may restore the register values. In one embodiment, the interrupt management circuit 1747 receives and processes interrupts received from system devices.

[0206] In one implementation, virtual / effective addresses from the graphics processing engine 1731 are translated to real / physical addresses in the system memory 1714 by the MMU 1739. One embodiment of the accelerator integration circuit 1736 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1746 and / or other accelerator devices. The graphics accelerator modules 1746 may be dedicated to a single application running on the processor 1707 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1731-1732, N, are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0207] In at least one embodiment, the accelerator integrated circuitry 1736 acts as a bridge to the system for the graphics acceleration module 1746, providing address translation and system memory caching services. Additionally, the accelerator integrated circuitry 1736 may provide a virtualization facility for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1731-1732.

[0208] The hardware resources of the graphics processing engines 1731-1732, N are explicitly mapped into the real address space seen by the host processor 1707, so that any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 1736 is to physically separate the graphics processing engines 1731-1732, N so that they appear as independent units to the system.

[0209] In at least one embodiment, one or more graphics memories 1733-1734, M are respectively coupled to each of the graphics processing engines 1731-1732, N. The graphics memories 1733-1734, M store instructions and data that are processed by the respective graphics processing engines 1731-1732, N. The graphics memories 1733-1734, M may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0210] In one embodiment, to reduce data traffic over link 1740, a biasing technique is used to ensure that the data stored in graphics memory 1733-1734, M is data that will be most frequently used by graphics processing engines 1731-1732, N, and preferably is data that is not used (or at least not frequently used) by cores 1760A-1760D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and therefore preferably not needed by graphics processing engines 1731-1732, N) in the cores' caches 1762A-1762D, 1756 and system memory 1714.

[0211] FIG. 17C shows another exemplary embodiment in which the accelerator integration circuitry 1736 is integrated within the processor 1707. In at least this embodiment, the graphics processing engines 1731-1732, N communicate directly with the accelerator integration circuitry 1736 via high-speed link 1740 via interface 1737 and interface 1735 (again, any form of bus or interface protocol can be utilized). The accelerator integration circuitry 1736 may perform the same operations as described with respect to FIG. 17B, but may potentially operate at a higher throughput given its proximity to the coherence bus 1764 and caches 1762A-1762D, 1756. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integration circuitry 1736 and a programming model controlled by the graphics acceleration module 1746.

[0212] In at least one embodiment, graphics processing engines 1731-1732, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1731-1732, N, achieving virtualization within a VM / partition.

[0213] In at least one embodiment, graphics processing engines 1731-1732, N may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1731-1732, N and allow access by each operating system. In a single-partition system without a hypervisor, graphics processing engines 1731-1732, N are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1731-1732, N and provide access to each process or application.

[0214] In at least one embodiment, the graphics acceleration module 1746 or the individual graphics processing engines 1731-1732,N selects a process element using a process handle. In one embodiment, the process element is stored in system memory 1714 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engines 1731-1732,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0215] FIG. 17D illustrates an exemplary accelerator integration slice 1790. As used herein, a "slice" comprises a designated portion of the processing resources of the accelerator integration circuitry 1736. An application effective address space 1782 in system memory 1714 stores a process element 1783. In one embodiment, the process element 1783 is stored in response to a GPU call 1781 from an application 1780 running on the processor 1707. The process element 1783 contains the process state of the corresponding application 1780. A work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the application's address space 1782.

[0216] The graphics acceleration module 1746 and / or the individual graphics processing engines 1731-1732, N may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0217] In at least one embodiment, the dedicated process programming model is implementation specific, in which a single process owns the graphics acceleration module 1746 or an individual graphics processing engine 1731. Because the graphics acceleration module 1746 is owned by a single process, when the graphics acceleration module 1746 is allocated, the hypervisor initializes the accelerator integration circuitry 1736 for the owning partition, and the operating system initializes the accelerator integration circuitry 1736 for the owning process.

[0218] In operation, WD fetch unit 1791 in accelerator integrated slice 1790 fetches the next WD 1784, which contains an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 1746. As shown, data from WD 1784 may be stored in register 1745 and used by MMU 1739, interrupt management circuit 1747, and / or context management circuit 1748. For example, one embodiment of MMU 1739 includes segment / page walk circuitry for accessing segment / page table 1786 within OS virtual address space 1785. Interrupt management circuit 1747 may process interrupt events 1792 received from graphics acceleration module 1746. When performing graphics operations, effective addresses 1793 generated by graphics processing engines 1731-1732, N are translated into real addresses by MMU 1739.

[0219] In one embodiment, the same set of registers 1745 may be replicated for each graphics processing engine 1731-1732, N, and / or graphics acceleration module 1746 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 1790. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0220] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0221] In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731-1732, N. It contains all the information the graphics processing engine 1731-1732, N needs to do its work, or it can be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0222] 17E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1798 in which a process element list 1799 is stored. The hypervisor real address space 1798 is accessible through a hypervisor 1796 that virtualizes the graphics acceleration module engine of an operating system 1795.

[0223] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1746. There are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0224] In this model, the system hypervisor 1796 owns the graphics acceleration module 1746 and makes its functions available to all operating systems 1795. In order for the graphics acceleration module 1746 to support virtualization by the system hypervisor 1796, the graphics acceleration module 1746 may comply with the following: 1) an application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1746 must provide a mechanism for saving and restoring context. 2) the application's job request must be guaranteed by the graphics acceleration module 1746 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 1746 must provide the ability to preempt job processing. 3) the graphics acceleration module 1746 must ensure fairness between processes when operating in a specified shared programming model.

[0225] In at least one embodiment, the application 1780 must make a system call to the operating system 1795 with the graphics acceleration module 1746 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module 1746 type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module 1746 type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and may take the form of a graphics acceleration module 1746 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by the graphics acceleration module 1746. In one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. If the implementation of the accelerator integrated circuit 1736 and the graphics acceleration module 1746 does not support a User Permission Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. The hypervisor 1796 may optionally apply the current Permission Mask Override Register (AMOR) value before placing the AMR in the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the effective address of an area in the application's address space 1782 for the graphics acceleration module 1746 to save and restore context state. This pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0226] Upon receiving the system call, the operating system 1795 may verify that the application 1780 is registered and authorized to use the graphics acceleration module 1746. The operating system 1795 then calls the hypervisor 1796 with the information shown in Table 3. [Table 3]

[0227] Upon receiving the hypervisor call, the hypervisor 1796 verifies that the operating system 1795 is registered and authorized to use the graphics acceleration module 1746. The hypervisor 1796 then places the process element 1783 into the process element linked list of the corresponding graphics acceleration module 1746 type. The process element may include the information shown in Table 4. [Table 4]

[0228] In at least one embodiment, the hypervisor initializes registers 1745 of multiple accelerator integrated slices 1790.

[0229] As shown in FIG. 17F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memories 1701-1702 and GPU memories 1720-1723. In this implementation, operations performed on GPUs 1710-1713 utilize the same virtual / effective memory address space as those used to access processor memories 1701-1702, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701, a second portion is allocated to second processor memory 1702, a third portion is allocated to GPU memory 1720, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memories 1701-1702 and GPU memories 1720-1723, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0230] In one embodiment, bias / coherence management circuits 1794A-1794E in one or more of MMUs 1739A-1739E ensure cache coherence between caches of one or more host processors (e.g., 1705) and caches of GPUs 1710-1713 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. Although multiple instances of bias / coherence management circuits 1794A-1794E are shown in FIG. 17F, the bias / coherence circuits may also be implemented within the MMUs of one or more host processors 1705 and / or within the accelerator integration circuit 1736.

[0231] One embodiment allows the GPU-attached memory 1720-1723 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, the GPU-attached memory 1720-1723 can be accessed as system memory without cumbersome cache coherence overhead, providing a beneficial operating environment for GPU offload. This configuration allows the host processor 1705 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access the GPU-attached memory 1720-1723 without cache coherence overhead can be critical to the execution time of the offloaded computation. For example, in cases where there is significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1710-1713. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0232] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. For example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (i.e., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU-attached memories 1720-1723, with or without a bias cache in the GPUs 1710-1713 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, the bias table may be maintained entirely within the GPU.

[0233] In at least one embodiment, the bias table entry associated with each access to GPU-biased memory 1720-1723 is accessed prior to the actual access to the GPU memory, resulting in the following actions: First, a local request from a GPU 1710-1713 that finds its page in the GPU bias is forwarded directly to the corresponding GPU memory 1720-1723. A local request from a GPU that finds its page in the host bias is forwarded to the processor 1705 (e.g., via the high-speed link described above). In one embodiment, a request from the processor 1705 that finds the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1710-1713. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, solely by a hardware-based mechanism.

[0234] One mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1705 bias to GPU bias, but not for transitions in the opposite direction.

[0235] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 1705. To access these pages, the processor 1705 may request access from the GPU 1710, which may or may not immediately grant the access. Therefore, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 1705, or vice versa.

[0236] A hardware structure 915 is used to implement one or more embodiments. Details regarding the hardware structure (x) 915 are provided herein in conjunction with Figures 9A and / or 9B.

[0237] 18 illustrates an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0238] 18 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1800 that may be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may further include an image processor 1815 and / or a video processor 1820, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I.sup.2S / I.sup.2C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a high-definition multimedia interface (HDMI®) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1865 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 1870.

[0239] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in integrated circuit 1800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0240] In at least one embodiment, inference and / or training logic 2 may be used in integrated circuit 1800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0241] 19A-19B illustrate an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0242] 19A-19B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 19A illustrates an exemplary graphics processor 1910 of a system-on-chip integrated circuit, which may be fabricated using one or more IP cores according to at least one embodiment. FIG. 19B illustrates a further exemplary graphics processor 1940 of a system-on-chip integrated circuit, which may be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the graphics processor 1910 of FIG. 19A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1940 of FIG. 19B is a high-performance graphics processor core. In at least one embodiment, the graphics processors 1910, 1940 may each be a variation of the graphics processor 1810 of FIG. 18.

[0243] In at least one embodiment, graphics processor 1910 includes vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D-1915N-1, and 1915N). In at least one embodiment, graphics processor 1910 can execute different shader programs through separate logic, whereby vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1905 implements the vertex processing stage of a 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processors 1915A-1915N use the primitive and vertex data generated by vertex processor 1905 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processors 1915A-1915N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0244] In at least one embodiment, graphics processor 1910 further includes one or more memory management units (MMUs) 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide virtual-to-physical address mapping for graphics processor 1910, including vertex processor 1905 and / or fragment processors 1915A-1915N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1805, image processor 1815, and / or video processor 1820 of Figure 18, allowing each processor 1805-1820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable graphics processor 1910 to interface with other IP cores in the SoC via the SoC's internal bus or via a direct connection.

[0245] In at least one embodiment, graphics processor 1940 includes one or more MMUs 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B of graphics processor 1910 of FIG. 19A. In at least one embodiment, graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F-1955N-1, and 1955N), which provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1955A-1955N, and a tiling unit 1958 for accelerating tiling operations for tile-based rendering, where rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0246] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in integrated circuits 19A and / or 19B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0247] In at least one embodiment, inference and / or training logic 2 may be used in integrated circuit 19A and / or 19B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0248] 20A-20B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 20A illustrates a graphics core 2000, which, in at least one embodiment, may be included in graphics processor 1810 of Figure 18, or, in at least one embodiment, may be integrated shader cores 1955A-1955N, as in Figure 19B. Figure 20B illustrates a highly parallel, general-purpose graphics processing unit 2030 suitable for incorporation into a multi-chip module in at least one embodiment.

[0249] In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020, which are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A-2001N, or partitions per core, and a graphics processor may include multiple instances of graphics core 2000. Slices 2001A-2001N may include supporting logic, including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and sets of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N may include a set of additional functional units (AFUs 2012A-2012N), floating point units (FPUs 2014A-2014N), integer arithmetic logic units (ALUs 2016-2016N), address calculation units (ACUs 2013A-2013N), double precision floating point units (DPFPUs 2015A-2015N), and matrix processing units (MPUs 2017A-2017N).

[0250] In at least one embodiment, the FPUs 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 2015A-2015N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 2017A-2017N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication (GEMM) acceleration. In at least one embodiment, AFUs 2012A-2012N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric functions (e.g., sine, cosine, etc.).

[0251] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in graphics core 2000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0252] In at least one embodiment, inference and / or training logic 2 may be used in graphics core 2000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0253] FIG. 20B illustrates a general-purpose processing unit (GPGPU) 2030, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 for enabling connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and, using a global scheduler 2034, distributes execution threads associated with these commands to a set of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share cache memory 2038. In at least one embodiment, cache memory 2038 can act as a higher level cache for cache memories within compute clusters 2036A-2036H.

[0254] In at least one embodiment, GPGPU 2030 includes memory 2044A-2044B coupled to compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, memory 2044A-2044B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0255] In at least one embodiment, compute clusters 2036A-2036H each include a set of graphics cores, such as graphics core 2000 of FIG. 20A, that may include multiple types of integer and floating-point logic units capable of performing computational operations at various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 2036A-2036H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0256] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2036A-2036H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate via host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to a GPU link 2040 that allows direct connection to other instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that allows communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU link 2040 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via a network device accessible via host interface 2032. In at least one embodiment, GPU link 2040 can be configured to allow connection to a host processor in addition to, or instead of, host interface 2032.

[0257] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, when the GPGPU 2030 is used for inference, the GPGPU may include fewer compute clusters 2036A-2036H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2044A-2044B may be different for the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0258] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in GPGPU 2030 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0259] In at least one embodiment, inference and / or training logic 2 may be used in GPGPU 2030 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0260] 21 is a block diagram illustrating a computing system 2100, according to at least one embodiment. In at least one embodiment, the computing system 2100 includes a processing subsystem 2101 having one or more processors 2102 and a system memory 2104 that communicate via an interconnection path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or may be integrated within the one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that can enable the computing system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 can enable a display controller, which may be included in one or more processors 2102 and provide output to one or more display devices 2110A. In at least one embodiment, the one or more display devices 2110A coupled to the I / O hub 2107 can include local, internal, or embedded display devices.

[0261] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to a memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 may be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, the one or more parallel processors 2112 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2112 form a graphics processing subsystem that can output pixels to one of one or more display devices 2110A coupled via the I / O hub 2107. In at least one embodiment, the one or more parallel processors 2112 may also include a display controller and display interface (not shown) that allows direct connection to one or more display devices 2110B.

[0262] In at least one embodiment, a system storage unit 2114 may be connected to an I / O hub 2107 to provide a storage mechanism for the computing system 2100. In at least one embodiment, an I / O switch 2116 may be used to provide an interface mechanism to enable communication between the I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 2120. In at least one embodiment, the network adapter 2118 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0263] In at least one embodiment, computing system 2100 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2107. In at least one embodiment, the communication paths interconnecting the various components of FIG. 21 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface, such as an NV-Link high-speed interconnect, or other interconnection protocol.

[0264] In at least one embodiment, one or more parallel processors 2112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2112 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, memory hub 2105, processor 2102, and I / O hub 2107 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2100 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0265] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 2100 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0266] In at least one embodiment, inference and / or training logic 2 may be used in the system of FIG. 2100 for inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0267] Processor 22A illustrates a parallel processor 2200 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2200 is a variation of one or more parallel processors 2112 shown in FIG. 21 according to an example embodiment.

[0268] In at least one embodiment, parallel processor 2200 includes parallel processing units 2202. In at least one embodiment, parallel processing units 2202 include I / O units 2204 that enable communication with other devices, including other instances of parallel processing units 2202. In at least one embodiment, I / O units 2204 may be directly connected to other devices. In at least one embodiment, I / O units 2204 are connected to other devices through the use of a hub or switch interface, such as memory hub 2105. In at least one embodiment, the connection between memory hub 2105 and I / O units 2204 forms communication link 2113. In at least one embodiment, I / O units 2204 are connected to host interface 2206 and memory crossbar 2216, where host interface 2206 receives commands directed to the execution of processing operations and memory crossbar 2216 receives commands directed to the execution of memory operations.

[0269] In at least one embodiment, when host interface 2206 receives command buffers via I / O unit 2204, host interface 2206 can direct work operations to implement these commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to distribute commands or other work items to processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is properly configured and in a valid state before tasks are distributed to processing cluster array 2212 of processing cluster array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, allowing rapid preemption and context switching of threads executing in the processing array 2212. In at least one embodiment, host software can signal the scheduling workload in the processing array 2212 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 2212 by scheduler 2210 logic in the microcontroller that includes the scheduler 2210.

[0270] In at least one embodiment, processing cluster array 2212 can include up to “N” processing clusters (e.g., cluster 2214A, cluster 2214B through cluster 2214N). In at least one embodiment, each cluster 2214A through 2214N of processing cluster array 2212 can execute a large number of simultaneous threads. In at least one embodiment, scheduler 2210 can allocate work to clusters 2214A through 2214N of processing cluster array 2212 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2210 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2212. In at least one embodiment, different clusters 2214A through 2214N of processing cluster array 2212 can be allocated to process different types of programs or perform different types of computations.

[0271] In at least one embodiment, processing cluster array 2212 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2212 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0272] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from system memory via the I / O unit 2204 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) during processing and then written back to system memory.

[0273] In at least one embodiment, when graphics processing is performed using parallel processing unit 2202, scheduler 2210 can be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2214A-2214N of processing cluster array 2212. In at least one embodiment, portions of processing cluster array 2212 can be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2214A-2214N may be buffered so that the intermediate data can be transmitted between clusters 2214A-2214N for further processing.

[0274] In at least one embodiment, processing cluster array 2212 can receive processing tasks to be performed via scheduler 2210, which receives commands defining the processing tasks from front end 2208. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, scheduler 2210 can be configured to fetch the index corresponding to the task or can receive the index from front end 2208. In at least one embodiment, front end 2208 can be configured to ensure that processing cluster array 2212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0275] In at least one embodiment, each of one or more instances of parallel processing unit 2202 can be coupled to parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 can be accessed via memory crossbar 2216, which can receive memory requests from processing cluster array 2212 as well as I / O unit 2204. In at least one embodiment, memory crossbar 2216 can access parallel processor memory 2222 via memory interface 2218. In at least one embodiment, memory interface 2218 can include multiple partition units (e.g., partition unit 2220A, partition unit 2220B through partition unit 2220N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 2222. In at least one embodiment, the number of partition units 2220A-2220N is configured to be equal to the number of memory units, such that a first partition unit 2220A has a corresponding first memory unit 2224A, a second partition unit 2220B has a corresponding memory unit 2224B, and an Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N does not have to be equal to the number of memory devices.

[0276] In at least one embodiment, the memory units 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2224A-2224N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2222, render targets, such as frame buffers or texture maps, may be stored across the memory units 2224A-2224N, allowing the partition units 2220A-2220N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2222 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0277] In at least one embodiment, any one of the clusters 2214A-2214N in the processing cluster array 2212 can process data that is to be written to any one of the memory units 2224A-2224N in the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 can be configured to forward the output of each cluster 2214A-2214N to any partition unit 2220A-2220N or to another cluster 2214A-2214N that can perform further processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with a memory interface 2218 through the memory crossbar 2216 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2216 has connections to memory interface 2218 for communicating with I / O unit 2204, as well as connections to local instances of parallel processor memory 2222, allowing processing units in different processing clusters 2214A-2214N to communicate with system memory or other memory not local to parallel processing unit 2202. In at least one embodiment, memory crossbar 2216 can use virtual channels to separate traffic streams between clusters 2214A-2214N and partition units 2220A-2220N.

[0278] In at least one embodiment, multiple instances of parallel processing unit 2202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2202 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2202 or parallel processor 2200 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0279] FIG. 22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, partition unit 2220 is an instance of one of partition units 2220A-2220N of FIG. 22A. In at least one embodiment, partition unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a raster operations unit (ROP) 2226. L2 cache 2221 is a read / write cache configured to execute load and store operations received from memory crossbar 2216 and ROP 2226. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 2221 to frame buffer interface 2225 for processing. In at least one embodiment, updates are also sent to the frame buffer via frame buffer interface 2225 for processing. In at least one embodiment, frame buffer interface 2225 interfaces with one of the memory units of a parallel processor memory, such as memory units 2224A-2224N (eg, within parallel processor memory 2222) of FIG.

[0280] In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP 2226 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a number of compression algorithms. The type of compression performed by ROP 2226 can be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0281] In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., clusters 2214A-2214N of FIG. 22 ) rather than within partition unit 2220. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2216. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2110 of FIG. 21 , may be routed for further processing by processor 2102, or may be routed for further processing by one of the processing entities in parallel processor 2200 of FIG. 22A.

[0282] FIG. 22C is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of processing clusters 2214A-2214N of FIG. 22. In at least one embodiment, processing cluster 2214 may be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0283] In at least one embodiment, operation of processing cluster 2214 may be controlled via a pipeline manager 2232, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, pipeline manager 2232 receives instructions from scheduler 2210 of FIG. 22 and manages the execution of those instructions via graphics multiprocessor 2234 and / or texture unit 2236. In at least one embodiment, graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 2214. In at least one embodiment, one or more instances of graphics multiprocessor 2234 may be included within processing cluster 2214. In at least one embodiment, graphics multiprocessor 2234 may process data, and data crossbar 2240 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2232 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed via data crossbar 2240.

[0284] In at least one embodiment, each graphics multiprocessor 2234 in a processing cluster 2214 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0285] In at least one embodiment, instructions sent to processing cluster 2214 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in graphics multiprocessor 2234. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 2234. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 2234. In at least one embodiment, if a thread group includes more threads than the number of processing engines in graphics multiprocessor 2234, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on graphics multiprocessor 2234.

[0286] In at least one embodiment, the graphics multiprocessor 2234 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 can forgo the internal cache and use cache memory (e.g., L1 cache 2248) within the processing cluster 2214. In at least one embodiment, each graphics multiprocessor 2234 can also access an L2 cache within a partition unit (e.g., partition units 2220A-2220N in FIG. 22 ), which may be shared among all processing clusters 2214 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 can also access off-chip global memory, which may include one or more of local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2202 may be used as global memory. In at least one embodiment, processing cluster 2214 includes multiple instances of graphics multiprocessor 2234 that can share common instructions and data, which may be stored in L1 cache 2248.

[0287] In at least one embodiment, each processing cluster 2214 may include an MMU 2245 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2245 may reside within memory interface 2218 of FIG. 22. In at least one embodiment, MMU 2245 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses for tiles (tiling is described in more detail) and optionally cache line indices. In at least one embodiment, MMU 2245 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 2234 or an L1 cache, or processing cluster 2214. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0288] In at least one embodiment, processing cluster 2214 may be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2234 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2234 outputs processed tasks to data crossbar 2240 to provide the processed tasks to another processing cluster 2214 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2216. In at least one embodiment, a pre-ROP 2242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2234 and direct the data to the ROP units, which may be located within partition units (e.g., partition units 2220A-2220N of FIG. 22) as described herein. In at least one embodiment, the pre-ROP 2242 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0289] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in graphics processing cluster 2214 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0290] In at least one embodiment, inference and / or training logic 2 may be used in graphics processing cluster 2214 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0291] 22D illustrates a graphics multiprocessor 2234 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2234 couples with a pipeline manager 2232 of a processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 has an execution pipeline including, but not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general-purpose graphics processing unit (GPGPU) cores 2262, and one or more load / store units 2266. The GPGPU cores 2262 and the load / store units 2266 are coupled to a cache memory 2272 and a shared memory 2270 via a memory and cache interconnect 2268.

[0292] In at least one embodiment, instruction cache 2252 receives a stream of instructions to execute from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched for execution by instruction unit 2254. In at least one embodiment, instruction unit 2254 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group being assigned to a different execution unit within GPGPU core 2262. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2256 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2266.

[0293] In at least one embodiment, register file 2258 provides a set of registers to the functional units of graphics multiprocessor 2234. In at least one embodiment, register file 2258 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU core 2262, load / store unit 2266) of graphics multiprocessor 2234. In at least one embodiment, register file 2258 is partitioned among the respective functional units, such that each functional unit is allocated a dedicated portion of register file 2258. In one embodiment, register file 2258 is partitioned among the different warps being executed by graphics multiprocessor 2234.

[0294] In at least one embodiment, GPGPU cores 2262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for graphics multiprocessor 2234. GPGPU cores 2262 may have similar or different architectures. In at least one embodiment, a first portion of GPGPU core 2262 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or may enable variable-precision floating-point operations. In at least one embodiment, graphics multiprocessor 2234 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0295] In at least one embodiment, GPGPU core 2262 includes SIMD logic capable of performing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can execute in parallel via a single SIMD8 logical unit.

[0296] In at least one embodiment, memory and cache interconnect 2268 is an interconnect network connecting each functional unit of graphics multiprocessor 2234 to register file 2258 and shared memory 2270. In at least one embodiment, memory and cache interconnect 2268 is a crossbar interconnect that allows load / store unit 2266 to implement load and store operations between shared memory 2270 and register file 2258. In at least one embodiment, register file 2258 can operate at the same frequency as GPGPU cores 2262, and therefore data transfers between GPGPU cores 2262 and register file 2258 have very low latency. In at least one embodiment, shared memory 2270 can be used to enable communication between threads executing in functional units within graphics multiprocessor 2234. In at least one embodiment, cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 2236. In at least one embodiment, shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 2262 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 2272.

[0297] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into the same package or chip as the core or may be communicatively coupled to the core via an internal (i.e., internal to the package or chip) processor bus / interconnect. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0298] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in graphics multiprocessor 2234 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0299] In at least one embodiment, inference and / or training logic 2 may be used in graphics multiprocessor 2234 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0300] FIG. 23 illustrates a multi-GPU computing system 2300, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2300 may include a processor 2302 coupled to multiple general-purpose graphics processing units (GPGPUs) 2306A-D via a host interface switch 2304. In at least one embodiment, the host interface switch 2304 is a PCI Express switch device that couples the processor 2302 to a PCI Express bus, via which the processor 2302 can communicate with the GPGPUs 2306A-D. The GPGPUs 2306A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2316. In at least one embodiment, the GPU-to-GPU links 2316 are connected to each of the GPGPUs 2306A-D via dedicated GPU links. In at least one embodiment, P2P GPU link 2316 enables direct communication between each of GPGPUs 2306A-D without requiring communication via host interface bus 2304 to which processor 2302 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to P2P GPU link 2316, host interface bus 2304 remains available for access to system memory or for communication with other instances of multi-GPU computing system 2300, for example, via one or more network devices. In at least one embodiment, GPGPUs 2306A-D are connected to processor 2302 via host interface switch 2304, and in at least one embodiment, processor 2302 includes direct support for P2P GPU link 2316 and can be directly connected to GPGPUs 2306A-D.

[0301] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the multi-GPU computing system 2300 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0302] In at least one embodiment, inference and / or training logic 2 may be used in multi-GPU computing system 2300 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0303] 24 is a block diagram of a graphics processor 2400, according to at least one embodiment. In at least one embodiment, graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, ring interconnect 2402 couples graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0304] In at least one embodiment, graphics processor 2400 receives batches of commands via ring interconnect 2402. In at least one embodiment, the incoming commands are interpreted by command streamer 2403 of pipeline front end 2404. In at least one embodiment, graphics processor 2400 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, command streamer 2403 supplies the commands to geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, command streamer 2403 supplies the commands to video front end 2434, which is coupled to media engine 2437. In at least one embodiment, the media engine 2437 includes a Video Quality Engine (VQE) 2430 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 2433 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each spawn execution threads for thread execution resources provided by at least one graphics core 2480A.

[0305] In at least one embodiment, graphics processor 2400 includes scalable thread execution resources characterized by modular cores 2480A-2480N (sometimes referred to as core slices), each having multiple sub-cores 2450A-2450N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2400 can have any number of graphics cores 2480A-2480N. In at least one embodiment, graphics processor 2400 includes graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, graphics processor 2400 is a low-power processor having a single sub-core (e.g., 2450A). In at least one embodiment, graphics processor 2400 includes multiple graphics cores 2480A-2480N, each including a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each of first sub-cores 2450A-2450N includes at least a first set of execution units 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each sub-core 2450A-2450N, 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0306] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in graphics processor 2400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0307] In at least one embodiment, inference and / or training logic 2 may be used in graphics processor 2400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0308] FIG. 25 is a block diagram illustrating the micro-architecture of a processor 2500 that may include logic circuits for implementing instructions, according to at least one embodiment. In at least one embodiment, the processor 2500 may implement instructions including x86 instructions, ARM instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2510 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2510 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0309] In at least one embodiment, processor 2500 includes an in-order front end (“front end”) 2501 that fetches instructions to be executed and prepares instructions for later use in the processor pipeline. In at least one embodiment, front end 2501 may include several units. In at least one embodiment, an instruction prefetcher 2526 fetches instructions from memory and provides the instructions to an instruction decoder 2528, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2528 decodes received instructions into one or more operations called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”) that the machine may execute. In at least one embodiment, instruction decoder 2528 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2530 may assemble the decoded uops into program-order sequences, or traces, in uop queue 2534 for execution. In at least one embodiment, when trace cache 2530 encounters a complex instruction, microcode ROM 2532 provides the uops necessary to complete the operation.

[0310] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 2528 may access the microcode ROM 2532 to implement the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 2528. In at least one embodiment, if an operation requires a large number of micro-ops to complete, the instruction may be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2532, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2532 has finished sequencing micro-ops for an instruction, the machine front end 2501 may resume fetching micro-ops from the trace cache 2530.

[0311] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2503 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions, optimizing performance as instructions are scheduled for execution down the pipeline. Out-of-order execution engine 2503 includes, without limitation, allocator / register renamer 2540, memory uop queue 2542, integer / floating point uop queue 2544, memory scheduler 2546, fast scheduler 2502, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2504, and simple floating point scheduler ("simple FP scheduler") 2506. In at least one embodiment, fast scheduler 2502, slow / general purpose floating point scheduler 2504, and simple floating point scheduler 2506 are also collectively referred to herein as "uop schedulers 2502, 2504, 2506." Allocator / register renamer 2540 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2540 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2540 also allocates each uop's entry to one of two uop queues: memory uop queue 2542 for memory operations and integer / floating point uop queue 2544 for non-memory operations, before memory scheduler 2546 and uop schedulers 2502, 2504, 2506. In at least one embodiment, uop schedulers 2502, 2504, 2506 determine when uops are ready to execute based on the readiness of the sources of their dependent input register operands and the availability of the execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 2502 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2504 and simple floating point scheduler 2506 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2502, 2504, 2506 arbitrate for dispatch ports to schedule uops for execution.

[0312] In at least one embodiment, execution block b11 includes, without limitation, integer register file / bypass network 2508, floating point register file / bypass network (“FP register file / bypass network”) 2510, address generation units (“AGUs”) 2512 and 2514, fast arithmetic logic units (ALUs) (“fast ALUs”) 2516 and 2518, slower arithmetic logic unit (“slower ALU”) 2520, floating point ALU (“FP”) 2522, and floating point move unit (“FP move”) 2524. In at least one embodiment, integer register file / bypass network 2508 and floating point register file / bypass network 2510 are also referred to herein as “register files 2508, 2510.” In at least one embodiment, AGUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating-point ALU 2522, and floating-point move unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524." In at least one embodiment, execution block b11 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0313] In at least one embodiment, register files 2508, 2510 may be located between uop schedulers 2502, 2504, 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file / bypass network 2508 performs integer operations. In at least one embodiment, floating point register file / bypass network 2510 performs floating point operations. In at least one embodiment, register files 2508, 2510 may each include, without limitation, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 2508, 2510 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2508 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 2510 may include, without limitation, 128-bit wide entries.

[0314] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524 may execute instructions. In at least one embodiment, register files 2508 and 2510 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 2500 may include any number and combination of execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524, without limitation. In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 may execute floating-point, MMX, SIMD, AVX, and other operations, including SEE, or special machine learning instructions. In at least one embodiment, the floating-point ALU 2522 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the fast ALUs 2516, 2518. In at least one embodiment, the fast ALUs 2516, 2518 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the slow ALU 2520 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, with most complex integer operations proceeding to the slow ALU 2520. In at least one embodiment, memory load / store operations may be performed by the AGUS 2512, 2514. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 may be implemented to support wide operands having various bit widths.In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0315] In at least one embodiment, the uop schedulers 2502, 2504, 2506 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2500, the processor 2500 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0316] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0317] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B . In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the EXE block 2511 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the EXE block 2511. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the EXE block 2511 to implement one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0318] In at least one embodiment, some or all of the inference and / or training logic 2 may be incorporated into EXE block 2511 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in EXE block 2511. Additionally, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of EXE block 2511 to implement one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0319] 26 illustrates a deep learning application processor 2600, according to at least one embodiment. In at least one embodiment, the deep learning application processor 2600 uses instructions that, when executed by the deep learning application processor 2600, cause the deep learning application processor 2600 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2600 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2600 performs matrix multiplication operations, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2600 includes, without limitation, processing clusters 2610(1)-2610(12), inter-chip links (“ICLs”) 2620(1)-2620(12), inter-chip controllers (“ICCs”) 2630(1)-2630(2), high-bandwidth memory second generation (“HBM2”) 2640(1)-2640(4), memory controllers (“Mem Ctrlrs”) 2642(1)-2642(4), high-bandwidth memory physical layers (“HBM 2644(1)-2644(4), a management-controller central processing unit ("management-controller CPU") 2650, a serial peripheral interface, inter-integrated circuit, and general-purpose input / output block ("SPI, I2C, GPIO") 2660, a peripheral component interconnect express controller and direct memory access block ("PCIe controller and DMA") 2670, and a 16-lane peripheral component interconnect express port ("PCI Express x16") 2680.

[0320] In at least one embodiment, the processing clusters 2610 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2610 may include any number and types of processors, without limitation. In at least one embodiment, the deep learning application processor 2600 may include any number and types of processing clusters 2600. In at least one embodiment, the inter-chip link 2620 is bidirectional. In at least one embodiment, the inter-chip link 2620 and the inter-chip controller 2630 enable multiple deep learning application processors 2600 to exchange information, including activation information resulting from the implementation of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2600 may include any number and types (including zero) of ICLs 2620 and ICCs 2630.

[0321] In at least one embodiment, the HBM2 2640 provides a total of 32 Gigabytes (GB) of memory. Each HBM2 2640(i) is associated with both a memory controller 2642(i) and an HBM PHY 2644(i). In at least one embodiment, any number of HBM2s 2640 may provide any type and total amount of high-bandwidth memory and may be associated with any number and types of memory controllers 2642 and HBM PHYs 2644 (including zero). In at least one embodiment, the SPI, I2C, GPIO 2660, PCIe controller and DMA 2670, and / or PCIe 2680 may be replaced with any number and types of blocks enabling any number and types of communication standards in any technically feasible manner.

[0322] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B . In at least one embodiment, the deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 2600. In at least one embodiment, the deep learning application processor 2600 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2600. In at least one embodiment, the processor 2600 may be used to implement one or more neural network use cases described herein.

[0323] FIG. 27 is a block diagram of a neuromorphic processor 2700, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2700 receives one or more inputs from sources external to the neuromorphic processor 2700. In at least one embodiment, these inputs may be sent to one or more neurons 2702 within the neuromorphic processor 2700. In at least one embodiment, the neurons 2702 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2700 may include, without limitation, thousands or millions of instances of neurons 2702, although any suitable number of neurons 2702 may be used. In at least one embodiment, each instance of a neuron 2702 may include a neuron input 2704 and a neuron output 2706. In at least one embodiment, the neuron 2702 may generate an output, which may be sent to an input of another instance of the neuron 2702. For example, in at least one embodiment, neuron input 2704 and neuron output 2706 may be interconnected via synapse 2708 .

[0324] In at least one embodiment, neurons 2702 and synapses 2708 may be interconnected such that neuromorphic processor 2700 operates to process or analyze information received by neuromorphic processor 2700. In at least one embodiment, neuron 2702 may send an output pulse (or "fire" or "spike") when input received via neuron input 2704 exceeds a threshold. In at least one embodiment, neuron 2702 may sum or integrate signals received at neuron input 2704. For example, in at least one embodiment, neuron 2702 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 2702 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 2704 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 2704 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to cause firing). In at least one embodiment, neuron 2702 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 2702 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron output 2706 when the result of applying the transfer function to neuron input 2704 exceeds a threshold. In at least one embodiment, neuron 2702 may ignore previously received input information when firing, for example, by resetting the membrane potential to 0 or another suitable default value.In at least one embodiment, once the membrane potential is reset to zero, neuron 2702 may resume normal operation after a suitable period (or refractory period).

[0325] In at least one embodiment, neurons 2702 may be interconnected through synapses 2708. In at least one embodiment, synapses 2708 may operate to transmit a signal from an output of a first neuron 2702 to an input of a second neuron 2702. In at least one embodiment, neurons 2702 may transmit information through two or more instances of synapses 2708. In at least one embodiment, one or more instances of neuron outputs 2706 may be connected to instances of neuron inputs 2704 of the same neuron 2702 through instances of synapses 2708. In at least one embodiment, an instance of neuron 2702 that generates an output to be transmitted through an instance of synapse 2708 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 2708. In at least one embodiment, an instance of neuron 2702 that receives an input to be transmitted through an instance of synapse 2708 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 2708. In at least one embodiment, an instance of neuron 2702 may receive input from one or more instances of synapse 2708 and may send output through one or more instances of synapse 2708, so that a single instance of neuron 2702 may therefore be both a “pre-synaptic neuron” and a “post-synaptic neuron” with respect to various instances of synapse 2708.

[0326] In at least one embodiment, neurons 2702 may be organized into one or more layers. Each instance of a neuron 2702 may have one neuron output 2706 that may fan out to one or more neuron inputs 2704 through one or more synapses 2708. In at least one embodiment, a neuron output 2706 of a neuron 2702 in a first layer 2710 may be connected to a neuron input 2704 of a neuron 2702 in a second layer 2712. In at least one embodiment, layer 2710 may be referred to as a "feed-forward" layer. In at least one embodiment, each instance of a neuron 2702 in an instance of a first layer 2710 may fan out to each instance of a neuron 2702 in a second layer 2712. In at least one embodiment, first layer 2710 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of neuron 2702 in the second layer 2712 may fan out to fewer than all instances of neuron 2702 in the third layer 2714. In at least one embodiment, the second layer 2712 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, the neurons 2702 in the second layer 2712 may fan out to neurons 2702 in multiple other layers, including neurons 2702 in the same second layer 2712. In at least one embodiment, the second layer 2712 may be referred to as a "recurrent layer." The neuromorphic processor 2700 may include any suitable combination of recurrent and feed-forward layers, including, without limitation, both sparsely connected feed-forward layers and fully connected feed-forward layers.

[0327] In at least one embodiment, neuromorphic processor 2700 may include, without limitation, a reconfigurable interconnect architecture or dedicated hardwired interconnects for connecting synapses 2708 to neurons 2702. In at least one embodiment, neuromorphic processor 2700 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2702 as needed based on the neural network topology and the fan-in / fan-out of the neurons. For example, in at least one embodiment, synapses 2708 may be connected to neurons 2702 using an interconnect fabric, such as a network-on-chip, or using dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0328] 28 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808 and may be a single-processor desktop system, a multi-processor workstation system, or a server system having multiple processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0329] In at least one embodiment, system 2800 may include or be incorporated into a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2800 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 2800 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2800 is a television or set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

[0330] In at least one embodiment, the one or more processors 2802 each include one or more processor cores 2807 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, the one or more processor cores 2807 are each configured to process a particular instruction set 2809. In at least one embodiment, the instruction set 2809 may facilitate computing via complex instruction set computing (CISC), reduced instruction set computing (RISC), or very long instruction word (VLIW). In at least one embodiment, the processor cores 2807 may each process a different instruction set 2809, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 2807 may also include other processing devices, such as a digital signal processor (DSP).

[0331] In at least one embodiment, processor 2802 includes cache memory 2804. In at least one embodiment, processor 2802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2802. In at least one embodiment, processor 2802 also uses an external cache (e.g., a level 3 (L3) cache or last level cache (LLC)) (not shown), which may be shared among processor cores 2807 using known cache coherence techniques. In at least one embodiment, processor 2802 further includes register file 2806, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2806 may include general-purpose registers or other registers.

[0332] In at least one embodiment, the one or more processors 2802 are coupled to one or more interface buses 2810 to transmit communication signals, such as address, data, or control signals, between the processors 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 may be a processor bus, such as, in one embodiment, a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2810 is not limited to a DMI bus, but may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, the memory controller 2816 facilitates communication between memory devices and other components of the system 2800, while the platform controller hub (PCH) 2830 provides connectivity to I / O devices via a local I / O bus.

[0333] In at least one embodiment, memory device 2820 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device with performance suitable for serving as process memory. In at least one embodiment, memory device 2820 may operate as system memory for system 2800, storing data 2822 and instructions 2821 for use by one or more processors 2802 when executing applications or processes. In at least one embodiment, memory controller 2816 also couples to an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 within processor 2802 to perform graphics and media operations. In at least one embodiment, a display device 2811 may be connected to processor 2802. In at least one embodiment, display device 2811 may include one or more of an internal display device, such as a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). In at least one embodiment, display device 2811 may include a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0334] In at least one embodiment, platform controller hub 2830 allows peripheral devices to connect to memory device 2820 and processor 2802 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, and a data storage device 2824 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 2824 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensor 2825 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 2826 may be a WiFi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2828 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2834 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high-definition audio controller. In at least one embodiment, system 2800 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.In at least one embodiment, platform controller hub 2830 can also connect to one or more universal serial bus (USB) controller 2842 connected input devices, such as a keyboard and mouse 2843 combination, a camera 2844, or other USB input devices.

[0335] In at least one embodiment, instances of memory controller 2816 and platform controller hub 2830 may be integrated into a separate external graphics processor, such as external graphics processor 2812. In at least one embodiment, platform controller hub 2830 and / or memory controller 2816 may be external to one or more processors 2802. For example, in at least one embodiment, system 2800 may include external memory controller 2816 and platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with processor 2802.

[0336] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B . In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into graphics processor 2800. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in 3D pipeline 2812. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 9A or FIG. 9B . In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of graphics processor 2800 to implement one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0337] In at least one embodiment, some or all of the inference and / or training logic 2 may be incorporated into graphics processor 2800. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in 3D pipeline 2812. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 1 or 2. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of graphics processor 2800 to implement one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0338] 29 is a block diagram of a processor 2900 having one or more processor cores 2902A-2902N, an integrated memory controller 2914, and an integrated graphics processor 2908, according to at least one embodiment. In at least one embodiment, processor 2900 may include a smaller number of additional cores, including additional core 2902N, represented by a dashed box. In at least one embodiment, processor cores 2902A-2902N each include one or more internal cache units 2904A-2904N. In at least one embodiment, each processor core also has access to one or more shared cache units 2906.

[0339] In at least one embodiment, internal cache units 2904A-2904N and shared cache unit 2906 represent a cache memory hierarchy within processor 2900. In at least one embodiment, cache memory units 2904A-2904N may include at least one level of instruction and data cache within each processor core, as well as one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherency between the various cache units 2906 and 2904A-2904N.

[0340] In at least one embodiment, processor 2900 may also include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, one or more bus controller units 2916 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2910 provides management functions for various processor components. In at least one embodiment, system agent core 2910 includes one or more integrated memory controllers 2914 for managing access to various external memory devices (not shown).

[0341] In at least one embodiment, one or more of processor cores 2902A-2902N include support for simultaneous multithreading. In at least one embodiment, system agent core 2910 includes components for coordinating and operating cores 2902A-2902N during multithreaded processing. In at least one embodiment, system agent core 2910 may further include a power control unit (PCU), which includes logic and components for coordinating the power state of one or more of processor cores 2902A-2902N and graphics processor 2908.

[0342] In at least one embodiment, processor 2900 further includes a graphics processor 2908 for performing graphics processing operations. In at least one embodiment, graphics processor 2908 couples to a shared cache unit 2906 and to a system agent core 2910 that includes one or more integrated memory controllers 2914. In at least one embodiment, system agent core 2910 also includes a display controller 2911 for directing output of the graphics processor to one or more coupled displays. In at least one embodiment, display controller 2911 may also be a separate module coupled to graphics processor 2908 via at least one interconnect or may be integrated within graphics processor 2908.

[0343] In at least one embodiment, a ring-based interconnect unit 2912 is used to couple the internal components of processor 2900. In at least one embodiment, alternative interconnect units such as a point-to-point interconnect, a switched interconnect, or other techniques may be used. In at least one embodiment, graphics processor 2908 couples to ring interconnect 2912 via I / O link 2913.

[0344] In at least one embodiment, I / O link 2913 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2918, such as an eDRAM module. In at least one embodiment, each of processor cores 2902A-2902N and graphics processor 2908 use embedded memory module 2918 as a shared last-level cache.

[0345] In at least one embodiment, processor cores 2902A-2902N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores 2902A-2902N execute a common instruction set, while one or more other of processor cores 2902A-2902N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of microarchitecture, where one or more cores with relatively higher power consumption are combined with one or more cores with lower power consumption. In at least one embodiment, processor 2900 can be implemented on one or more chips or as an SoC integrated circuit.

[0346] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B . In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into graphics processor 2910. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of 3D pipeline 2812, graphics core 2915A, shared function logic 2916, graphics core 2915B, shared function logic 2920, or an ALU embodied in other logic of FIG. 29 . Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 9A or FIG. 9B . In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that comprise the ALU of the graphics processor 2910 for implementing one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0347] In at least one embodiment, some or all of the inference and / or training logic 2 may be incorporated into graphics processor 2910. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of ALUs embodied in 3D pipeline 2812, graphics core 2915A, shared function logic 2916, graphics core 2915B, shared function logic 2920, or other logic of FIG. 29. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 1 or 2. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of graphics processor 2910 to implement one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0348] 30 is a block diagram of a graphics processor 3000, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 3000 communicates with registers of the graphics processor 3000 via a memory-mapped I / O interface using commands placed in memory. In at least one embodiment, the graphics processor 3000 includes a memory interface 3014 for accessing memory. In at least one embodiment, the memory interface 3014 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0349] In at least one embodiment, graphics processor 3000 also includes a display controller 3002 for driving display output data to display device 3020. In at least one embodiment, display controller 3002 includes one or more overlapping planes for display device 3020 and hardware for compositing multi-layered video or user interface elements. In at least one embodiment, display device 3020 can be an internal or external display device. In at least one embodiment, display device 3020 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, graphics processor 3000 includes a video codec engine 3006 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including, but not limited to, Motion Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and Joint Photographic Experts Group (JPEG) formats such as Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and JPEG, and Motion JPEG (MJPEG) formats. 【035...

Claims

1. one or more circuits that implement a data transformation comprising a combination of two or more data transformations, the two or more data transformations being combined based at least in part on input and output data sizes of the two or more data transformations; A processor, wherein the data transformations are performed by one or more parallel processing units, and wherein the combining of two or more data transformations is based at least in part on a resource requirement profile for each of the two or more data transformations.

2. 10. The processor of claim 1, wherein the combination of two or more data transformations results in a sequence of instructions that implements operations on the data to train one or more neural networks.

3. The processor of claim 2 , wherein the sequence of instructions implements operations to be performed by one or more parallel processing units.

4. The processor of claim 1 , wherein the two or more data transformations are combined based at least in part on the memory requirements of each of the two or more data transformations and memory availability of one or more parallel processing units.

5. The processor of claim 1 , wherein the two or more data transformations are combined based at least in part on the compute time requirements of each of the two or more data transformations.

6. The processor of claim 1 , wherein the two or more data transformations are combined based at least in part on available memory resources of a computing system.

7. 2. The processor of claim 1, wherein the two or more data transformations are a pre-transform and a post-transform to prepare three-dimensional image data for use in training a neural network.

8. 1. A system comprising: one or more processors that perform a first set of two or more data transformations and a second set of two or more data transformations, wherein the second set of two or more data transformations are combined from individual data transformations from the first set of two or more data transformations based at least in part on input and output data sizes of the individual data transformations.

9. 9. The system of claim 8, wherein the second set is performed by one or more parallel processing units, and the combining of individual data transformations from the first set is based at least in part on resource requirements for each of the two or more data transformations.

10. The system of claim 8 , wherein the second set performs a sequence of operations on three-dimensional (3D) image data.

11. The system of claim 10 , wherein the second set is accelerated by one or more parallel processing units.

12. 9. The system of claim 8, wherein the individual data transforms from the first set are combined based at least in part on memory requirements of each of the individual data transforms and memory availability of one or more parallel processing units.

13. The system of claim 8 , wherein the individual data transformations from the first set are combined such that a time requirement for applying the first set is reduced.

14. 10. The system of claim 8, wherein the individual data transformations are combined based on available memory resources of a computing system implementing one or more neural networks.

15. 15. The system of claim 14, wherein the one or more neural networks are trained using data transformed by the second set.

16. 9. The system of claim 8, wherein the first set of two or more data transformations and the second set of two or more data transformations include a pre-transform and a post-transform.

17. 10. The system of claim 8, wherein the first set of two or more data transformations and the second set of two or more data transformations prepare three-dimensional (3D) image data used to train one or more neural networks.

18. said second set of two or more data transformations is performed; a third set of data transformations is performed; 9. The system of claim 8, wherein the third set of data transformations consists of individual data transformations from the first set of two or more data transformations that were not selected in the second set of two or more data transformations.

19. When implemented by one or more processors, the one or more processors are configured to at least:

1. A machine-readable medium storing a set of instructions for performing a data transformation comprising a combination of two or more data transformations, wherein the two or more data transformations are combined based at least in part on input and output data sizes of the two or more data transformations; The machine-readable medium, when executed, further causes the one or more processors to combine two or more data transformations based at least in part on a resource requirement profile for each of the two or more data transformations.

20. 20. The machine-readable medium of claim 19, wherein the data transformations comprising a combination of two or more data transformations are performed by one or more parallel processing units.

21. 20. The machine-readable medium of claim 19, wherein the instructions, when executed, further cause the one or more processors to perform a sequence of data transformation operations on data used to train one or more neural networks, the sequence of data transformation operations specified by the combination of two or more data transformations.

22. 22. The machine-readable medium of claim 21, wherein the sequence of data transformation operations is accelerated by one or more graphics processing units.

23. 20. The machine-readable medium of claim 19, wherein the two or more data transformations are combined based at least in part on the memory requirements of each of the two or more data transformations and memory availability of one or more parallel processing units.

24. 20. The machine-readable medium of claim 19, wherein the two or more data transformations are combined such that the computing time required to perform each of the two or more data transformations is reduced.

25. 20. The machine-readable medium of claim 19, wherein the two or more data transformations are a pre-transform and a post-transform to prepare three-dimensional (3D) image data for use in training a neural network.

26. performing a first set of two or more data transformations using one or more parallel processing units, wherein the first set of two or more data transformations is based at least in part on a respective data transformation from a second set of two or more data transformations; selecting an individual data transformation from the second set of two or more data transformations for the first set of two or more data transformations based at least in part on input and output data sizes of the individual data transformation; The method, wherein the second set of two or more data transformations is performed by one or more parallel processing units.

27. 27. The method of claim 26, wherein combining individual data transforms from the second set is based at least in part on resource requirements for each of the two or more data transforms in the second set.

28. 27. The method of claim 26, wherein the second set of two or more data transformations performs a sequence of operations on three-dimensional (3D) image data.

29. 27. The method of claim 26, wherein the first set of two or more data transformations is performed and a third set of data transformations is performed, the third set of data transformations consisting of individual data transformations from the second set of two or more data transformations that were not selected in the first set of two or more data transformations.

30. 27. The method of claim 26, wherein the individual data transforms from the second set of two or more data transforms are selected based on memory requirements of each of the individual data transforms and memory availability of one or more parallel processing units.

31. 27. The method of claim 26, wherein the individual data transforms from the second set of two or more data transforms are selected based on a compute time requirement of each of the individual data transforms.

32. 27. The method of claim 26, wherein the individual data transforms from the second set of two or more data transforms are selected based on available memory resources of a computing system implementing one or more neural networks.

33. 33. The method of claim 32, wherein the one or more neural networks are trained using data transformed by the second set of two or more data transformations.

34. 33. The method of claim 32, wherein the one or more neural networks are used to perform inference on data transformed by the second set of two or more data transformations.

35. 27. The method of claim 26, further comprising using the first set of two or more data transformations and the second set of two or more data transformations to prepare three-dimensional (3D) image data used to train one or more neural networks.

36. 27. The method of claim 26, wherein the first set of two or more data transformations is performed on a batch of input data.

Images