System and method for synchronizing communications among multiple processors

Abstract

To synchronize multiple processes of one or more applications executed by multiple processors.SOLUTION: In addition to the processors, a system 10 includes multiple memories, each associated with a respective process and configured to maintain a local count representative of a message of the process with which the memory is associated and at least one remote count representative of a message of a corresponding process executed by another processor. The system also includes a reflector configured to reflect the local count of the process to a remote count of the corresponding process. For synchronization, a first process of a first application executed by a first processor is configured to enter a delay period if the local count and at least one remote count maintained by the memory associated with the first process fail to match.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure generally relates to systems, methods, and computer program products for synchronizing communications between multiple processors, such as improving synchronization of inbound and / or outbound message processing performed by parallel processes or applications executed by multiple processors. [Background technology]

[0002] Multiple processors can simultaneously execute multiple identical applications, each containing one or more processes, for various purposes. For example, multiple processors can execute the same application to improve fault tolerance. Alternatively, the results of concurrent execution of an application by multiple processors can be considered for purposes such as integrity monitoring. Furthermore, concurrent execution of the same application by multiple processors can also be used when availability of the application is required.

[0003] By synchronizing the execution of the same application, and therefore the same process, by multiple processors, multiple instances of the same process can access the same data, even when the processes are executed on different processors. In this case, it is necessary to synchronize inbound and outbound message processing associated with the execution of the process by multiple processors. One method for synchronizing inbound and outbound message processing associated with the execution of the same process by multiple processors uses a network switch loopback. However, this method not only incurs significant data latency but also requires external hardware in the form of a network switch. Another method for synchronizing inbound and outbound message processing during the execution of the same process by multiple processors relies on additional memory shared by the multiple processors. The additional memory also requires additional hardware, which increases the power requirements associated with the execution of the same process by multiple processors. Furthermore, this method typically requires additional software for multiple processors executing the same process to access the shared memory, increasing the system complexity. In this method, the size of the additional memory is generally set to a size corresponding to the worst-case skew between messages processed during the execution of the same process by multiple processors, resulting in a large additional memory. Summary of the Invention

[0004] A system, method, and computer program product according to an embodiment of the present disclosure are provided for improving synchronization between multiple processors executing applications including the same process, specifically, for example, for improving synchronization of inbound and / or outbound message processing performed by the multiple processors in association with the execution of the same process. As a result, the system, method, and computer program product according to an embodiment of the present disclosure can synchronize and provide the same data to the processes executed by the multiple processors, even if there is a time lag in the execution of the processes by the multiple processors. Furthermore, the system, method, and computer program product according to an embodiment of the present disclosure requires limited memory and external hardware to synchronize inbound and outbound message processing related to the processes executed by the multiple processors, and in some cases, no external hardware is required.

[0005] In one example of the present disclosure, a system configured to synchronize communications is provided. The system includes a plurality of processors, each configured to execute one or more applications, at least one of the applications including one or more processes. The system also includes a plurality of memories, each associated with a process of the application executed by the respective processor. Each memory is configured to maintain a local count indicative of messages communicated with respect to the process associated with the memory and at least one remote count indicative of messages communicated with respect to a corresponding process of an application executed by another processor of the plurality of processors. The system further includes a reflector configured to reflect the local count of the process to remote counts of corresponding processes in the other processors of the plurality of processors. To maintain synchronization, a first process of a first application executed by a first processor is configured to enter a delay period if the local count and the at least one remote count maintained by the memory associated with the first process do not match.

[0006] For example, the first process may be configured to enter the delay period if the local count exceeds at least one remote count, and to continue processing if the local count matches the remote count of the corresponding process. In one example, the memory location where the memory associated with the corresponding process of the application executed by the other processor maintains the remote count is identified by hardware addressing. In another example, the memory location where the memory associated with the corresponding process of the application executed by the other processor maintains the remote count is identified by a Peripheral Component Interconnect Express (PCIe) address. As used herein, "PCIe" refers to an interface standard for connecting high-speed components, such as that defined by the PCI-SIG Administration, Beaverton, Oregon 97003, USA.

[0007] The multiple processors may operate asynchronously due to differences in clocks or operation. The multiple processors may include multiple different processors that operate independently due to differences in architecture or clocks. In one example, the multiple processors are multiple multi-core processors, each core of the multi-core processor configured to execute one or more applications, at least one of the applications including one or more processes. When the first process of the first application executed by the first processor enters the delay period, one or more other processes of the first application executed by the first processor continue without delay.

[0008] In another example of the present disclosure, a method for synchronizing communications is provided. The method includes processing a plurality of messages in each of one or more processes of one or more applications executed by each of a plurality of processors. The method includes, for each process of an application executed by a respective processor, maintaining a local count and at least one remote count in a memory associated with the process. The local count indicates messages communicated with respect to the process with which the memory is associated. The at least one remote count indicates messages communicated with respect to a corresponding process of an application executed by another of the plurality of processors. The method also includes reflecting the local count of the process to a remote count of a corresponding process. The method further includes entering a delay period for a first process of a first application executed by a first processor if the local count and the at least one remote count maintained by a memory associated with the first process do not match.

[0009] In one example, the method includes, when placing the first process in the delay period, placing the first process in the delay period if the local count exceeds at least one remote count. In this example, the method further includes continuing processing the plurality of messages in the first process if the local count matches the remote count of the corresponding process. In one example, the method includes, when reflecting the local count, identifying a memory location where the memory associated with the corresponding process of the application executed by the other processor maintains the remote count by hardware addressing. In this example, the method includes, when identifying the memory location by hardware addressing, identifying the memory location where the memory associated with the corresponding process of the application executed by the other processor maintains the remote count by a PCIe address. In the method, when processing the plurality of messages, the method operates the plurality of processors asynchronously due to differences in clocks or operations. In one example, when reflecting the local count, the method includes, when reflecting the local count, asynchronously reflecting the local count.

[0010] In a further example of the present disclosure, a computer program product configured to synchronize communications is provided. The computer program product includes a non-transitory computer-readable medium having program code stored thereon, the program code including program code instructions that, when executed, are configured to process a plurality of messages in each of one or more processes of one or more applications executed by each of a plurality of processors. The program code also includes program code instructions configured to, for each process of an application executed by a respective processor, maintain a local count and at least one remote count in a memory associated with the process. The local count indicates messages communicated for the process with which the memory is associated, and the at least one remote count indicates messages communicated for a corresponding process of an application executed by another of the plurality of processors. The program code includes program code instructions configured to update the local count of the process with a remote count of a corresponding process, and program code instructions configured to enter a delay period for a first process of a first application executed by a first processor if the local count and the at least one remote count maintained by a memory associated with the first process do not match.

[0011] According to one example, the program code instructions configured to put the first process into the delay period include program code instructions configured to put the first process into the delay period if the local count exceeds at least one remote count. In this example, the program code further includes program code instructions configured to continue processing the plurality of messages in the first process if the local count matches the remote count of the corresponding process. In one example, the program code including the program code instructions configured to reflect the local count includes program code instructions configured to identify, by hardware addressing, a memory location where the memory associated with the corresponding process of the application executed by the other processor maintains the remote count. In this example, the program code instructions configured to identify the memory location by hardware addressing may include program code instructions configured to maintain, by a PCIe address, the memory location where the memory associated with the corresponding process of the application executed by the other processor maintains the remote count. The program code instructions configured to process the plurality of messages may include program code instructions configured to process the plurality of messages asynchronously with respect to processing of the plurality of messages by other processors of the plurality of processors due to clock or operational differences. The program code instructions configured to reflect the local count may include program code instructions configured to reflect the local count asynchronously. [Brief explanation of the drawings]

[0012] Having described embodiments of the present disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale.

[0013] [Figure 1]1 is a block diagram illustrating a system configured to synchronize communications between multiple processors according to an example of the present disclosure. [Figure 2] FIG. 2 is a more detailed block diagram illustrating a system configured to synchronize communications between multiple processors, according to an example of the present disclosure. [Figure 3] 3 is a flowchart illustrating operations performed by a system such as that shown in FIG. 1 or 2 according to an example of the present disclosure. [Figure 4] 1 is a chart showing local and remote counts maintained by two different processors, illustrating a period of delay incurred by one of the processors following a discrepancy between the local and remote counts, according to an example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Some embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. Note that the drawings illustrate some, but not all, embodiments of the present disclosure. Indeed, these embodiments may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are presented so that this disclosure will satisfy applicable legal requirements. Note that like elements will be designated by like numerals throughout the drawings. As used herein, the terms “data,” “content,” “information,” and the like may be used interchangeably and refer to data that may be transmitted, received, and / or stored in accordance with embodiments of the present disclosure. Therefore, these terms are not intended to limit the spirit or scope of the embodiments of the present disclosure.

[0015] Systems, methods, and computer program products according to examples of the present disclosure are provided for synchronizing communications, such as communications between multiple processors. In this specification, synchronization refers to time synchronization. The multiple processors may execute the same application to achieve fault tolerance, integrity, and / or to increase application availability. At least some of the applications executed by the multiple processors may include multiple processes, such as tasks or threads, that execute simultaneously and may operate at different speeds. Thus, the multiple processors may be executing one or more of the same processes simultaneously. For various reasons, such as mismatches in the clock sources of one or more of the multiple processors, the processes executed by the different processors may become unsynchronized. In this case, execution of the same process of the application by the multiple processors may not produce the same results for different data inputs. For example, time differences in the execution of the same process by the multiple processors may cause the process to be performed based on different instances of the same data element, resulting in different results. To mitigate this asynchronous execution of multiple processes, a system, method, and computer program product according to an embodiment of the present disclosure synchronizes communication between multiple processes, thereby facilitating synchronization of application processing by multiple processors. If the processes are not synchronized, the method, apparatus, and computer program product control the processors to resynchronize the execution of the processes by the processors.

[0016] Referring now to FIG. 1 , a system 10 configured to synchronize communications among multiple processors 12 is shown. The system 10 includes multiple processors 12 and multiple memories 14, with at least one memory associated with each of the processors. While the system 10 shown in FIG. 1 includes two processors 12, referred to as a first processor and a second processor, other embodiments of the system may include other numbers of processors, e.g., three or more processors. As also shown in FIG. 1 , the multiple processors 12 may include or embody respective memories 14, and one or more of the memories may be located external to the processors but remain in communication with the respective processors. As described below, in one example, the system 10 includes at least two memory locations, e.g., registers, associated with each of the multiple processors 12, with one memory location configured to maintain a local count 16 and another memory location configured to maintain a remote count 18. As shown in FIG. 1 , both the memory locations for maintaining the local count 16 and the remote count 18 of each processor 12 may be provided by a single memory device 14. However, in other examples, the processor 12 may include or be in communication with multiple separate memory devices 14, with one memory device configured to store a local count 16 and another memory device configured to store a remote count 18.

[0017] In one example, the multiple processors 12 are configured to operate synchronously, i.e., clocked by the same clock source. However, in other examples, the multiple processors 12 are configured to operate asynchronously, e.g., by being clocked by different clock sources. The multiple processors 12 may be multiple processors of the same type. Alternatively, the multiple processors 12 may be embodied as multiple processors of different types. That is, the multiple processors may be different processors (each having a different internal hardware architecture). In one example, the multiple processors 12 are multiple multi-core processors. Each of the processors 12 is configured to execute one or more applications, at least some of which are synchronized. At least some of the applications may include one or more processes, such as tasks or threads. In one example, two or more processes in an application may run in parallel, even if the processes run at different periodic rates or run aperiodically. In an example where the system 10 includes multiple multi-core processors, each application may run in a partition on a specific core of each processor. As a result, the same application, and therefore the same process, is executed by each core in two or more of the multi-core processors in this example.

[0018] As shown in FIG. 1 , the system 10 further includes a reflector 20. The reflector 20 may be embodied by a hardware component. In the illustrated example where the plurality of processors 12 includes a first and a second processor, the reflector is configured to reflect the local count 16 of the first processor to the remote count 18 of the second processor, and correspondingly, reflect the local count of the second processor to the remote count of the first processor. In an alternative example where the system 10 includes three or more processors 12, each processor is configured to maintain a remote count 18 of each of the other processors, and correspondingly, the reflector 20 is configured to reflect the local count 16 of the first processor as a remote count corresponding to the first processor and store it in the memory 14 associated with each of the other processors. Specifically, for example, the reflector 20 may be configured to reflect the local count of the first processor as the remote count of the first processor stored in the second processor, the remote count of the first processor stored in the third processor, the remote count of the first processor stored in the fourth processor, etc. The reflector 20 may be configured in various manners. In one example, reflector 20 is embodied as a network controller, such as a synchronous interface network controller (SINC), which in this example is embodied by an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0019] FIG. 2 details a system 10 for synchronizing communications between multiple processors 12, such as the first and second processors in this illustrative example, where the reflector 20 is embodied as a SINC 22. As noted above, each processor 12 includes or is associated with a memory 14 that maintains a local count 16 and a remote count 18 in a respective memory location. The illustrated sets of local counts 16 and remote counts 18 are associated with processes of an application executed by the processor 12. Because a processor 12 may execute multiple processes of one or more applications, the memory 14 associated with the processor may include multiple sets of local counts 16 and remote counts 18, one set associated with each process. The local count 16 of each process serves as a transaction counter, identifying the message number currently being communicated or most recently communicated for that process. For example, following the first message sent or received by each process, the processor 12 may set the value of the local count 16 to 1. Additionally, when the tenth message is sent or received by the respective process, processor 12 may respond by setting the value of local count 16 to 10. Similarly, remote count 18 maintained by processor 12 indicates messages executed by other processes, i.e., messages executed by corresponding processes of applications executed by other processors, such as the second processor in this example. Because multiple processors 12 are executing the same application and therefore the same processes, local count 16 and remote count 18 should be the same if the processors are synchronized. However, if the processors 12 are not synchronized, local count 16 and remote count 18 may have different values, resulting in system 10 in this example operating to re-synchronize the processors, and more specifically, the processes of the processors.

[0020] A reflector 20, such as the SINC 22 in the example shown in Figure 2, reflects the local count 16 of each operation of an application executed by a first processor 12 to the remote count 18 of the same operation of the same application executed by a second processor, and conversely, reflects the local count of each operation of an application executed by a second processor to the remote count of the same operation of the same application executed by a first processor. Thus, a set of local counts 16 and remote counts 18 represents the respective counts of messages sent and received for the same operation of the same application executed by multiple different processors. The reflector 20 in one example is configured to perform this reflection in real time or near real time, allowing valid comparisons to be made between the local counts 16 and remote counts 18 maintained by each processor 12 without significant delay or time lag in the remote count relative to the time required for the reflection process.

[0021] While reflector 20 can be embodied in various ways, the exemplary SINC 22 shown in FIG. 2 includes multiple register groups, one associated with each process of an application on multiple processors 12. Thus, each register group is associated with a set of local counts 16 and remote counts 18 corresponding to a respective process of an application executed by processor 12. For example, a first set of registers is associated with a process of an application executed by a first processor, and a second set of registers is associated with a corresponding process of an application executed by a second processor, i.e., the same process of the same application. While the SINC 22 of FIG. 2 includes only two register groups, a reflector may include any number of register groups, each associated with a different respective process of an application executed by processor 12. Each register group may include, for example, a status / configuration register 24, an outbound register 26, and an inbound register 28, where the outbound and inbound registers are used for transferring data to and from other external devices. The registers also include a reflector, as described below, in the form of at least one reflector register 20. In this regard, the registers associated with the processing of an application executed by one processor 12 may include one reflector register 20 configured to communicate with each of the other processors executing the same application and thus a corresponding process, e.g., the same process.

[0022] 2, a reflector register 20 associated with processing of an application executed by a first processor 12 is configured to communicate with a second processor executing the same application and thus a corresponding process, and a reflector register associated with corresponding processing of the same application executed by a second processor is configured to communicate with the first processor. In other examples including three or more processors 12, registers associated with processing of an application executed by one processor include multiple reflector registers 20, one reflector register configured to communicate with each of the other processors executing the same application and thus a corresponding process, e.g., the same process. In an example where system 10 includes three processors 12, registers associated with processing of an application executed by a first processor may include a first reflector register 20 configured to communicate with the second processor and a second reflector register configured to communicate with the third processor when both the second and third processors execute the same application and thus a corresponding process. Similarly, registers associated with corresponding operations of the same application executed by the second processor may include first reflector registers configured to communicate with the first processor and second reflector registers configured to communicate with the third processor, and registers associated with corresponding operations of the same application executed by the third processor may include first reflector registers configured to communicate with the first processor and second reflector registers configured to communicate with the second processor.

[0023] Each reflector register 20 is configured to receive a local count 16 maintained by the memory 14 of the processor 12 executing the application with which the reflector register is associated, and thus the process. As shown in FIG. 2 , each reflector register 20 can also communicate, e.g., via hardware, with a remote count 18 maintained by the memory 14 of another processor 12 with which the reflector register is configured to communicate. With respect to the example shown in FIG. 2 , the value of the reflector register 20 associated with an operation of an application executed by a first processor 12, i.e., the local count 16 stored in the memory 14 of the first processor, is provided to a memory location in the memory of a second processor that maintains the remote count 18. This provides, in one example, dynamically allocatable memory-mapped input / output. Conversely, the value of the reflector register 20 associated with a corresponding operation of the same application executed by a second processor 12, i.e., the local count 16 stored in the memory 14 of the second processor, is provided to a memory location in the memory of the first processor that maintains the remote count 18. In other words, the first processor 12 in this example writes the value of the local count 16 in the memory 14 associated with that first processor to the reflector register 20 associated with its respective process, which then provides that value to the memory associated with the corresponding process of the same application executed by the second processor for storage as the value of the remote count 18. In other examples including more than two processors 12, the local count of one processor is reflected via the respective reflector registers 20 to the corresponding remote counts of each of the other processors running the same application, and therefore the same process.

[0024] Regardless of the number of processors 12, the reflector 20 is configured to operate asynchronously so that the local count 16 provided by each processor 12 is provided to and reflected in the remote counts 18 of the other processors in real time with minimal delay. Therefore, clock control of the reflector, according to one example, is not required. In this regard, the memory locations where the memory 14 associated with a processor 12 maintains the remote counts 18 are identified, such as by the reflector 20, using hardware addressing. While various hardware addressing techniques can be used, the reflector 20, such as a network controller, uses PCIe addressing 30, as shown in FIG. 2, for the processors 12 and the reflector 20 to identify the memory locations where the other processors maintain the remote counts 18. This minimizes the delay incurred in reflecting the value of the local count 16 to the remote counts.

[0025] Reflection of the value of the local count 16 of one processor 12 to the remote count 18 of one or more other processors can be defined or controlled by one or more parameters. These parameters may be predefined as a result of static configuration or may be defined on the fly in conjunction with sending and receiving messages to and from the reflector 20. A combination of these may also be used, with some parameters predefined as a result of static configuration while others are defined in conjunction with sending and receiving messages to and from the reflector. The parameters may include the identity of the reflector register 20, the address of the other processor 12, and / or the number of words that one processor writes to the other processor. Another parameter may be an offset parameter, such as a PCIe address offset, defining an offset from a fixed address at which a memory location associated with the other processor and configured to store the remote count 18 is located. An additional parameter may be a timeout value that defines the period during which other processors are allowed to increment their counters, and an action may be taken if other processors fail to increment their counters within the period defined by the timeout value, thereby identifying the processor that has entered a delay period and taking appropriate corrective action. By allowing various parameters to be defined statically in advance or dynamically (on the fly) in relation to the exchange of messages, the system 10, method, and computer program product according to example embodiments may provide flexibility for multiple processors 12 and the communication therebetween.

[0026] Referring now to FIG. 3, steps performed by a system 10 such as that shown in FIG. 1 and, in some examples, FIG. 2 are described in method 38. As shown in block 40, the system 10, e.g., multiple processors 12, are configured to process multiple messages for the same process on each of the processors. In this regard, each of the multiple processors is configured to simultaneously execute the same application, and thus the same process of the same application. For the same process executed by each of the multiple processors 12, a local count 16 and at least one remote count 18 are maintained in memory 14 associated with each processor. In this regard, the local count 16 may be maintained, for example, to count the number of messages communicated in connection with the process by each processor 12 (or, more generally, the number of processed messages, e.g., measured in terms of the number of instructions executed or other criteria of the scope of the process pursuant to the processing of the application). Additionally, a remote count 18 is maintained representing corresponding processes of the same application executed by one or more of the other processors, which may be achieved, for example, by maintaining separate remote count values ​​for corresponding processes of the same application executed by each of the other processors. Similar to local count 16, remote count 18 may be configured to count, for example, the number of messages communicated with respect to a corresponding process on another processor 12 (or, more generally, the number of instructions executed or other criteria for the scope of processing according to the processing of the application, for example). For each process of an application, processor 12 may maintain a number of local counts 16 and remote counts 18 equal to the number of instances of the process of the application executed by the multiple processors. Thus, the number of remote counts 18 maintained by processor 12 will generally be one less than the total number of instances of each process of the application executed by the multiple processors.In association with each process in a system 10 including three processors 12 each executing the same application, and thus the same process, each processor maintains a local count 16 and two remote counts 18, each remote count value indicating a local count associated with a respective process of the application executed by each of the other processors. As described above and as shown in the block of Figure 3, the method 38 includes, for each process of the application executed by each processor, maintaining 42 a local count 16 and at least one remote count 18 in memory 14 associated with that process, the local count indicating messages communicated with respect to the process with which that memory is associated, and the at least one remote count indicating messages communicated with respect to a corresponding process of an application executed by another one of the multiple processors.

[0027] As shown in block 44 of Figure 3, the system 10, e.g., the reflector 20, is configured to reflect the local count 16 of the operations of an application executed by one processor 12 to the corresponding remote counts 18 of other processors executing the same application and therefore the corresponding, i.e., the same, process. If the system 10 includes three or more processors 12, the local count 16 of the operations of an application executed by one processor is reflected in the corresponding remote counts 18 maintained by each of the other processors executing the same application, including the corresponding operations. As shown in decision block 46 of Figure 3, the system 10, e.g., each processor 12, determines whether the local count 16 maintained by the processor is greater than the remote count 18 maintained by the same processor, or, in examples including three or more processors, whether the local count of the processor is greater than any one of the remote counts maintained by the same processor. If the local count 16 maintained by processor 12 is equal to or less than the remote count 18 maintained by the same processor, or if system 10 includes more than two processors and the local count maintained by a processor is equal to or less than each of multiple remote counts maintained by the same processor for the other processors, the processor continues to process the next message, for example, by communicating the message to or from that processor. At this time, the determination is "No" and flow of method 38 returns to block 40 of FIG. 3.

[0028] However, if the local count 16 maintained by a processor 12 exceeds the remote count maintained by the same processor, or if system 10 includes more than two processors and the local count maintained by a processor exceeds the remote count maintained by the same processor for any of the other processors, the determination is "yes," and the processing performed by each processor whose local count exceeds the remote count enters a delay period, as shown in block 48 of FIG. 3. The processor 12 that enters the delay period does not process the next message of the application's processing, e.g., by avoiding communication of the next message with that processor, but instead enters a wait state. During this time, one or more of the other processors continue executing the application, and specifically, continue executing that processing, e.g., by communicating the next message with one or more other processors and processing the next message of the application's processing, as shown in block 50 of FIG. 3. Even though a particular processing of a processor enters a delay period, other processing executing in parallel on that processor, such as other processing executing on other cores of a multi-core processor, continues to execute without delay. After processing the next message for processing by one or more of the other processors 12 and reflecting the local counts of the other processors in the corresponding remote counts maintained by each processor, the local counts maintained by each processor are repeatedly compared to the remote counts maintained by that processor, or, if the system includes three or more processors, the local counts maintained by each processor to the remote counts maintained by that processor for each of the other processors to determine whether the local count remains greater than the remote count, or, if the system includes three or more processors, whether the local count is greater than at least one remote count.If the local count 16 maintained by a respective processor 12 remains greater than at least one of the remote counts 18 maintained by that processor, that processor remains in a delay period, and one or more of the other processors (whose remote counts exceed the local counts maintained by that processor) continue executing the application, processing the next message, e.g., by communicating the next message with one or more of the other processors. However, if the other processors 12 catch up with the processor in the delay period, such that the remote counts maintained by the other processors equal the local counts 16 maintained by the other processors, that processor's delay period ends, and that processor and the other processors continue executing the application, processing the next message, e.g., by communicating the next message between themselves.

[0029] 3 are performed, according to one example, by each of the processors 12. That is, as described above in connection with a delay period established for one of the plurality of processors 12, the local count 16 and the remote count 18 maintained by the memory 14 associated with each processor are compared by the respective processor, and if the local count maintained by the respective processor exceeds the remote count maintained by that processor for the other processors, any one or more of the plurality of processors is configured to enter a delay period.

[0030] As an example of entering a delay period to resynchronize multiple processors 12 in processing messages related to the execution of the same operation of the same application, FIG. 4 illustrates operations performed by first and second processors executing the same application. More specifically, the figure illustrates the same operation of the same application over multiple consecutive time slices, along with the values ​​of the local count 16 and remote count 18 maintained by each of the first and second processors during each time slice. During time slice 1, the first and second processors each process a first message related to the execution of the same application, and thus the same operation. Because the local counts and remote counts maintained by each of the first and second processors are all zero during time slice 1, the initial values ​​of these local and remote counts match each other. Following the processing of the first message, during time slice 2, the local counts maintained by the first and second processors are updated to one, and the value of each processor's local count is reflected in the remote count of the other processor, so that the remote counts of the first and second processors also become one. At time slice 2 of the processing, the local count and remote count values ​​for each of the first and second processors are still equal, so each of the first and second processors processes the next message. At time slice 3, the local count and remote count are updated to 2. At time slice 3, the local count and remote count for each of the first and second processors are still equal, so the first and second processors process the next message associated with the execution of the same application, and therefore the same process.

[0031] As shown in time slice 4 of the process, the first processor is processing the third message, so its local count is updated to 3, which is reflected in the remote count of the second processor. However, the second processor has not yet processed the third message of the process, so its local count remains 2, which continues to be reflected in the remote count maintained by the first processor. Because the local count of the first processor exceeds the remote count maintained by the first processor in time slice 4 of the process, the first processor enters a delay period and does not process the next message in time slice 4. Although the first processor enters a delay period, other processes running in parallel on the first processor, such as other processes running on other cores of a multi-core processor, are not delayed and continue to execute. However, because the local count of the second processor does not exceed the remote count maintained by the second processor (but rather is less than the remote count maintained by the second processor), the second processor processes the next message in time slice 4 of the process. As a result of processing the next message in the transaction, the local count maintained by the second processor is incremented to 3 in time slice 5, and this value is reflected in the remote count maintained by the first processor. Because the local count and remote count maintained by each of the first and second processors are again equal to one another, the delay period for the first processor ends and both the first and second processors process the next message in time slice 5 of the transaction. This causes the local count and remote count for each of the first and second processors to be incremented to 4 in time slice 6 of the transaction, so that both the first and second processors can continue processing the next message, e.g., by communicating the next message between the processors.

[0032] As shown in the example of FIG. 4 , the system 10, method, and computer program product according to the exemplary embodiment enable multiple processors 12 to maintain synchronization of inbound and / or outbound message processing, such as sending and receiving messages, performed by the multiple processors while executing the same application, and thus the same process, even when the processors are operating asynchronously or not synchronized to a common clock. Ensuring synchronized communication among the multiple processors 12 allows multiple processors to achieve identical results when executing the same application, including the same process, thereby improving application fault tolerance, integrity, and availability. Furthermore, the system 10, method, and computer program product according to the exemplary embodiment require only a portion of memory and some external hardware, or only a portion of memory and no external hardware, to synchronize inbound and outbound message processing associated with the processes executed by the multiple processors, thereby reducing system complexity and power requirements. In this regard, the system 10 according to the exemplary embodiment can limit the amount of memory required by each processor 12 to store messages in progress to the amount required to store two messages, compared to conventional methods that require very large memory sizes to accommodate worst-case skew.

[0033] FIG. 3 illustrates a flowchart illustrating the operation of systems, methods, and computer program products according to the present disclosure. It should be noted that each block of the flowchart, and combinations of blocks in the flowchart, may be implemented in various ways and embodied as hardware, firmware, circuitry, and / or other devices associated with the execution of software including one or more software instructions. For example, one or more of the operations described above may be embodied by software instructions. In this regard, software instructions embodying the procedures described above may be stored in memory 14 and executed by a corresponding processor 12. It should be noted that such software instructions may be loaded into a computer or other programmable device (e.g., hardware) to produce a machine, with the resulting computer or other programmable device implementing the functions described in the flowchart blocks. These software instructions may be stored in a computer-readable memory capable of instructing a computer or other programmable device to function in a particular manner, and the software instructions stored in the computer-readable memory may form a product implementing the functions described in the flowchart blocks. The software instructions may also be loaded into a computer or other programmable device to create a computer-implementable process by causing the computer or other programmable device to perform a series of operations, such that the software instructions executing on the computer or other programmable device may provide steps for implementing the functions described in the flowchart blocks.

[0034] Furthermore, although the present disclosure includes the following appendices, please note that the scope of protection is defined by the claims, not by these appendices.

[0035] Clause 1. A system configured to synchronize communications, the system including: a plurality of processors; a plurality of memories; and a reflector, each of the plurality of processors configured to execute one or more applications, at least one of the applications including one or more processes; each of the plurality of memories associated with a process of the application executed by a respective processor; each memory configured to maintain a local count indicative of messages communicated with respect to the process with which the memory is associated and at least one remote count indicative of messages communicated with respect to a corresponding process of an application executed by another one of the plurality of processors; the reflector configured to reflect the local count of the process to a remote count of the corresponding process; and a first process of a first application executed by a first processor configured to enter a delay period if the local count and the at least one remote count maintained by the memory associated with the first process do not match.

[0036] Clause 2. The system of Clause 1, wherein the first process is configured to enter the delay period if the local count exceeds at least one remote count, and to continue processing if the local count matches a remote count of a corresponding process.

[0037] Appendix 3. The system of Appendix 1 or 2, wherein the memory location in which the memory associated with the corresponding processing of the application executed by the other processor maintains the remote count is identified by hardware addressing.

[0038] Appendix 4. The system of Appendix 3, wherein the memory location in which the memory associated with the corresponding processing of the application executed by the other processor maintains the remote count is identified by a PCIe address.

[0039] Appendix 5. The system according to any one of appendices 1 to 4, wherein the multiple processors operate asynchronously due to differences in clocks or operations.

[0040] Appendix 6. The system according to any one of appendices 1 to 5, wherein the plurality of processors includes a plurality of different processors that operate independently due to differences in architecture or clock.

[0041] Appendix 7. The system of any of Appendixes 1-6, wherein the plurality of processors are a plurality of multi-core processors, each core of the multi-core processor configured to execute one or more applications, at least one of the applications including one or more processes.

[0042] Appendix 8. A system described in any of Appendixes 1 to 7, wherein even when the first process of the first application executed by the first processor enters the delay period, one or more other processes of the first application executed by the first processor continue without delay.

[0043] Appendix 9. A method for synchronizing communications, comprising: processing a plurality of messages in each of one or more processes of one or more applications executed by each of a plurality of processors; maintaining, for each process of an application executed by each processor, a local count and at least one remote count in a memory associated with the process; the local count indicating messages communicated with respect to the process with which the memory is associated, and the at least one remote count indicating messages communicated with respect to a corresponding process of an application executed by another of the plurality of processors; reflecting the local count of the process in a remote count of a corresponding process; and entering the first process into a delay period if the local count and the at least one remote count maintained by a memory associated with a first process of a first application executed by a first processor do not match.

[0044] Appendix 10. The method of Appendix 9, further comprising: when entering the delay period for the first process, entering the delay period for the first process if the local count exceeds at least one remote count; and continuing processing of the plurality of messages in the first process if the local count matches the remote count of a corresponding process.

[0045] Appendix 11. The method of Appendix 9 or 10, wherein, in reflecting the local count, the memory associated with the corresponding processing of the application executed by the other processor identifies a memory location where the remote count is maintained by hardware addressing.

[0046] Appendix 12. The method of Appendix 11, wherein when identifying the memory location by hardware addressing, the memory location in which the memory associated with the corresponding processing of the application executed by the other processor maintains the remote count is identified by a PCIe address.

[0047] Appendix 13. The method according to any one of appendices 9 to 12, wherein when processing the plurality of messages, the plurality of processors are operated asynchronously due to differences in clocks or operations.

[0048] Supplementary Note 14: The method according to any one of Supplementary Notes 9 to 13, wherein the local count is reflected asynchronously when the local count is reflected.

[0049] Appendix 15. A computer program product configured to synchronize communications, the computer program product including a non-transitory computer-readable medium having program code stored thereon, the program code including program code instructions that, when executed, are configured to: process a plurality of messages in each of one or more processes of one or more applications executed by each of a plurality of processors; and for each process of an application executed by a respective processor, maintain a local count and at least one remote count in a memory associated with the process, the local count being indicative of messages communicated with respect to the process with which the memory is associated, and the at least one remote count being indicative of messages communicated with respect to a corresponding process of an application executed by another of the plurality of processors; the program code instructions are further configured to: update the local count of the process to a remote count of a corresponding process; and enter the first process into a delay period if the local count and the at least one remote count maintained by a memory associated with a first process of a first application executed by a first processor do not match.

[0050] Clause 16. The computer program product of Clause 15, wherein the program code instructions configured to cause the first process to enter the delay period include program code instructions configured to cause the first process to enter the delay period if the local count exceeds at least one remote count, and the program code further includes program code instructions configured to continue processing the plurality of messages in the first process if the local count matches a remote count of a corresponding process.

[0051] Appendix 17. The computer program product of Appendix 15 or 16, wherein the program code instructions configured to reflect the local count include program code instructions configured to identify, by hardware addressing, a memory location where the memory associated with a corresponding operation of the application executed by the other processor maintains the remote count.

[0052] Appendix 18. The computer program product of Appendix 17, wherein the program code instructions configured to identify the memory locations by hardware addressing include program code instructions configured to maintain, by PCIe address, the memory locations at which the memory associated with a corresponding operation of the application executed by the other processor maintains the remote count.

[0053] Appendix 19. The computer program product of any of Appendixes 15-18, wherein the program code instructions configured to process the plurality of messages include program code instructions configured to process the plurality of messages asynchronously with respect to processing of the plurality of messages by other ones of the plurality of processors due to clock or operational differences.

[0054] Appendix 20. The computer program product of any of Appendixes 15-19, wherein the program code instructions configured to reflect the local count include program code instructions configured to reflect the local count asynchronously.

[0055] The blocks of the flowcharts support a combination of means for performing a particular function and a combination of operations for performing a particular function. Note that one or more blocks of the flowcharts and combinations of blocks in the flowcharts may be implemented by a computer system based on special-purpose hardware that performs the particular function, or may be implemented by a combination of special-purpose hardware instructions and software instructions.

[0056] In some instances, some of the above steps may be modified or further expanded. Furthermore, in some instances, additional optional steps may be included. Modifications, expansions, or additions to the above steps may be performed in any order and in any combination.

[0057] Numerous modifications and other embodiments of the disclosure described herein will be apparent to one skilled in the art to which this disclosure pertains having the benefit of the disclosure in the foregoing description and the associated drawings. Accordingly, the disclosure should not be limited to the particular embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. Thus, while the foregoing description and associated drawings describe exemplary embodiments in connection with illustrative combinations of certain elements and / or features, alternative embodiments may employ different combinations of elements and / or features without departing from the scope of the appended claims. In this regard, for example, other combinations of elements and / or features are contemplated, some of which may be set forth in the appended claims. Although specific terms are employed herein, these terms are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. 1. A system configured to synchronize communications, comprising: a plurality of processors, a plurality of memories, and a reflector; each of the plurality of processors is configured to execute one or more applications, at least one of the applications including one or more processes; each of the plurality of memories is associated with a process of an application executed by a respective processor, and each memory is configured to maintain a local count indicative of messages communicated with respect to the process with which the memory is associated and at least one remote count indicative of messages communicated with respect to a corresponding process of an application executed by another of the plurality of processors; the reflector is configured to reflect the local count of the transaction to a remote count of a corresponding transaction; A system in which a first process of a first application executed by a first processor is configured to enter a delay period if a local count and at least one remote count maintained by a memory associated with the first process do not match.

2. 2. The system of claim 1, wherein the first process is configured to enter the delay period if the local count exceeds at least one remote count, and to continue processing if the local count matches the remote count of a corresponding process.

3. The system of claim 1 or 2, wherein the memory locations in which the memory associated with the corresponding processing of the application executed by the other processor maintains the remote count are identified by hardware addressing.

4. The system of claim 3 , wherein the memory location in which the memory associated with the corresponding processing of the application executed by the other processor maintains the remote count is identified by a PCIe address.

5. The system according to any one of claims 1 to 4, wherein the plurality of processors operate asynchronously due to differences in clocks or operations.

6. 6. The system according to claim 1, wherein the plurality of processors are different processors that operate independently due to differences in architecture or clocks.

7. 7. The system of claim 1, wherein the plurality of processors are a plurality of multi-core processors, each core of the multi-core processor configured to execute one or more applications, at least one of the applications including one or more processes.

8. A system as described in any one of claims 1 to 7, wherein even if the first processing of the first application executed by the first processor enters the delay period, one or more other processing of the first application executed by the first processor continues without delay.

9. 1. A method for synchronizing communications, comprising: processing a plurality of messages in each of one or more processes of one or more applications executed by each of the plurality of processors; For each process of the application executed by each processor maintaining a local count and at least one remote count in a memory associated with the process, the local count indicating messages communicated with respect to the process with which the memory is associated, and the at least one remote count indicating messages communicated with respect to a corresponding process of an application executed by another of the plurality of processors; reflecting the local count of the transaction to a remote count of a corresponding transaction; 1. A method comprising: placing a first process of a first application executed by a first processor into a delay period if a local count and at least one remote count maintained by a memory associated with the first process do not match.

10. 10. The method of claim 9, further comprising: in entering the delay period for the first process, entering the delay period if the local count exceeds at least one remote count; and continuing processing of the plurality of messages in the first process if the local count matches a remote count of a corresponding process.

11. 11. A method according to claim 9 or 10, wherein in reflecting the local count, the memory associated with the corresponding processing of the application executed by the other processor identifies a memory location in which the remote count is maintained by hardware addressing.

12. 12. The method of claim 11, wherein identifying the memory location by hardware addressing includes identifying the memory location in which the memory associated with a corresponding process of the application executed by the other processor maintains the remote count by a PCIe address.

13. The method according to any one of claims 9 to 12, wherein the processors are operated asynchronously due to differences in clocks or operations when processing the messages.

14. The method according to any one of claims 9 to 13, wherein, when reflecting the local count, the local count is reflected asynchronously.

15. A non-transitory computer-readable medium having recorded thereon program code for synchronizing communications, the program code executing instructions for: processing a plurality of messages in each of one or more processes of one or more applications executed by each of the plurality of processors; maintaining, for each process of an application executed by each processor, a local count and at least one remote count in a memory associated with that process, the local count indicating messages communicated with respect to the process with which the memory is associated, and the at least one remote count indicating messages communicated with respect to a corresponding process of an application executed by another of the plurality of processors; reflecting the local count of the transaction to a remote count of a corresponding transaction; A computer-readable medium configured to place a first process of a first application executed by a first processor into a delay period if a local count and at least one remote count maintained by a memory associated with the first process do not match.

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