Memory system and method

Abstract

To provide a memory system that enhances read performance and a method for controlling the memory system.SOLUTION: In a memory system, when receiving a read request designating a logical address range of a predetermined size or more from a host, a first processing circuit 12 of a memory controller issues a plurality of first sub-commands each of which is a sub-command for each first data unit, in logical address order. A second processing circuit 13 adds a serial number corresponding to the order of issuance to each of the plurality of first sub-commands. LUT engines 14e and 14o share the processing for specifying the position of the first data unit based on management information for each of the plurality of first sub-commands. An alignment circuit 16 aligns the plurality of first sub-commands in logical address order based on the serial number after processing by the plurality of LUT engines. A CPU 17 executes a read operation on a first memory based on the plurality of first sub-commands aligned in logical address order.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present embodiments relate to a memory system and method. [Background technology]

[0002] 2. Description of the Related Art Conventionally, memory systems including nonvolatile memories are known, such as NAND-type flash memories. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,789,161 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a memory system with high read performance and a method capable of improving the read performance. [Means for solving the problem]

[0005] According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory, a second memory, and a memory controller. The first memory is a non-volatile memory configured to store data received from the host. The second memory is configured to store management information that associates, for each first data unit, a logical address used by the host with a location in the first memory where the data is stored. The memory controller includes a first circuit, a second circuit, a plurality of third circuits, a fourth circuit, a fifth circuit, and a sixth circuit. The memory controller receives a read request from the host specifying a range of consecutive logical addresses each having a size equal to the size of the first data units. In response to receiving the read request, the first circuit is configured to issue a plurality of first subcommands in the order of the logical addresses, each of which requests the reading of all first data units included in the logical address range. Each of the plurality of first subcommands requests the reading of one first data unit. The second circuit is configured to assign a first serial number corresponding to the order of issuance to each of the plurality of first subcommands and distribute the plurality of first subcommands, each assigned with the first serial number, to the plurality of third circuits. Each of the plurality of third circuits is configured to identify a storage location of a first data unit associated with a first subcommand assigned to it among the plurality of first subcommands by referencing the management information and to add location information indicating the identified storage location to the first subcommand. The fourth circuit is configured to acquire the plurality of first subcommands, each assigned with the location information, from the plurality of third circuits. The fifth circuit is configured to sort the plurality of first subcommands acquired by the fourth circuit in order based on the first serial numbers. The sixth circuit is configured to execute a read operation on the first memory based on the sorted plurality of first subcommands. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a schematic diagram showing an example of a hardware configuration of a memory system according to an embodiment. [Figure 2] FIG. 1 is a schematic diagram showing an example of the configuration of a memory chip according to an embodiment. [Figure 3] 2 is a schematic diagram for explaining information stored in a memory included in the memory system according to the embodiment; [Figure 4] 3A and 3B are schematic diagrams for explaining details of an LUT according to the embodiment. [Figure 5] FIG. 2 is a schematic diagram showing an example of a plurality of circuits included in a memory controller according to an embodiment. [Figure 6] FIG. 10 is a schematic diagram showing an example of the structure of a lookup message transferred within a memory controller according to an embodiment. [Figure 7] FIG. 2 is a schematic diagram showing an example of the configuration of an alignment circuit according to the embodiment. [Figure 8] 10A and 10B are schematic diagrams illustrating an example of control of lookup messages in the case of sequential read by the memory controller according to the embodiment; [Figure 9] 10A and 10B are schematic diagrams illustrating another example of control of lookup messages in the case of sequential read by the memory controller according to the embodiment. [Figure 10] 10 is a flowchart showing an example of an operation of generating a lookup message based on a read request of a first processing circuit according to the embodiment. [Figure 11] 6 is a flowchart showing an example of an operation of a second processing circuit according to the embodiment. [Figure 12] 10 is a flowchart showing an example of the operation of an LUT engine according to the embodiment. [Figure 13] 10 is a flowchart showing an example of an operation of a third processing circuit according to the embodiment. [Figure 14] 10 is a flowchart showing an example of the operation of the alignment circuit according to the embodiment. [Figure 15] 10 is a flowchart showing an example of an operation of the CPU to process a lookup message transmitted from a third processing circuit according to the embodiment. [Figure 16] 10 is a flowchart showing an example of an operation of a CPU according to an embodiment, which sequentially retrieves and processes lookup messages from a message buffer group. [Figure 17] 10 is a flowchart showing an example of an operation of transmitting cluster data to be read by a first processing circuit to a host according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a memory system and method according to an embodiment will be described in detail with reference to the accompanying drawings, although the present invention is not limited to the embodiment.

[0008] (Embodiment) FIG. 1 is a schematic diagram illustrating an example of a hardware configuration of a memory system according to an embodiment.

[0009] The memory system 1 is configured to be connectable to a host 2. The standard for connection between the memory system 1 and the host 2 is not limited to a specific standard. The host 2 is, for example, a personal computer, a portable information terminal, or a server.

[0010] When accessing the memory system 1, the host 2 sends an access request to the memory system 1. The access request is a write request, a read request, or the like. The access request is accompanied by a logical address and size information. The logical address is information indicating a location within the logical address space that the memory system 1 provides to the host 2. In other words, when the host 2 accesses the memory system 1, it uses a logical address to specify the access destination. A logical address may also be referred to as an LBA (Logical Block Address). The size information included in the access request indicates a contiguous range in the logical address space starting from the position specified by the logical address. In other words, in each access request, the host 2 specifies the access range in the logical address space using the logical address and size information.

[0011] The host 2 transmits write target data corresponding to the write request, that is, data requested to be written, to the memory system 1. Such data transmitted from the host 2 to the memory system 1 is referred to as user data.

[0012] The memory system 1 includes a memory controller 10, a NAND flash memory (NAND memory) 20, and a DRAM (Dynamic Random Access Memory) 30.

[0013] The NAND memory 20 is a non-volatile memory that functions as a storage for storing user data. The NAND memory 20 is an example of a first memory configured to store user data. Any type of non-volatile memory can be used as the first memory.

[0014] The memory controller 10 controls the memory system 1. This control includes control related to data transfer between the host 2 and the NAND memory 20. The memory controller 10 uses the DRAM 30 as a buffer memory for data transfer and as a cache memory in which management information is cached.

[0015] An LUT (Look Up Table) 50 and an LUT segment 51, which will be described later, are examples of management information. The DRAM 30 is an example of a second memory configured to store management information.

[0016] The DRAM 30 is also an example of a third memory configured to store user data received from the host 2 until the data is stored in the NAND memory 20. The second memory and the third memory may be configured as separate memories, or may be configured as a single memory like the DRAM 30 of this embodiment.

[0017] The NAND memory 20 is composed of one or more memory chips 21. Each of the one or more memory chips 21 is connected to the memory controller 10 via one or more channels. In the example shown in FIG. 1, the NAND memory 20 includes memory chips 21-0, 21-1, 21-2, and 21-3. The memory chips 21-0 and 21-1 are connected to the memory controller 10 via channel ch.0, and the memory chips 21-2 and 21-3 are connected to the memory controller 10 via channel ch.1. Note that the number of memory chips 21 constituting the NAND memory 20 and the number of channels connecting the NAND memory 20 and the memory controller 10 are not limited to these.

[0018] 2 is a schematic diagram showing an example of the configuration of a memory chip 21 according to the embodiment. The memory chip 21 includes a memory cell array 211 and a page register 212. The page register 212 is an example of a first buffer.

[0019] The memory cell array 211 comprises multiple blocks. All data stored in one block is erased collectively. Each block comprises multiple storage areas called pages. Contiguous physical addresses are assigned to each page. Data is written to and read from the memory cell array 211 in units of pages. Data in units of pages is sometimes referred to as page data.

[0020] The page register 212 has a capacity of at least the size of a page. The page register 212 holds the page data to be written received from the memory controller 10 until programming of the memory cell array 211 is completed. The page register 212 also holds the page data read from the memory cell array 211 until transfer to the memory controller 10 is completed. Note that the operation of reading page data from the memory cell array 211 and storing the read page data in the page register 212, that is, the operation of transferring the page data from the memory cell array 211 to the page register 212, is referred to as a sense operation.

[0021] Data transfer from the page register 212 to the memory controller 10 is performed in cluster units. A cluster is an area of ​​the smallest size to which a logical address is assigned in the logical address space. The size of a cluster is smaller than the page size. Therefore, the page data read from the memory cell array 211 and stored in the page register 212 includes multiple cluster data 40. A cluster is an example of a first data unit. Each cluster data 40 is an example of data of a first data unit. By specifying a physical address within the page to the memory chip 21, the memory controller 10 can cause the page register 212 to output a desired cluster data 40 from the page data read from the memory cell array 211 and stored in the page register 212.

[0022] FIG. 3 is a schematic diagram for explaining information stored in a plurality of memories included in the memory system 1 according to the embodiment.

[0023] The NAND memory 20 stores user data DAT in a non-volatile manner.

[0024] Furthermore, the NAND memory 20 stores an LUT 50 in a non-volatile manner. The LUT 50 is a group of address conversion information that associates the logical address of each cluster with a physical address that indicates a location within the NAND memory 20. The LUT 201 has a data structure in which the physical addresses corresponding to the logical addresses of each cluster are arranged in the order of the logical addresses.

[0025] FIG. 4 is a schematic diagram for explaining details of the LUT 50 according to the embodiment.

[0026] In recent years, memory systems with very large user capacities have been developed. The larger the user capacity, the larger the maximum logical address and the larger the number of entries in the LUT. In other words, the larger the user capacity, the larger the LUT size.

[0027] In this embodiment, the LUT 50 is cached in the DRAM 30 to improve the speed at which the LUT 50 is used. However, if the notation capacity of the memory system 1 is large, attempting to cache the LUT 50 in the DRAM 30 requires a large-capacity DRAM 30, which is disadvantageous in terms of cost. Therefore, the memory system 1 is configured so that a portion of the LUT 50 is cached in the DRAM 30. Note that the memory system 1 may also be configured so that the entire LUT 50 is cached in the DRAM 30.

[0028] The LUT 50 is divided into a plurality of LUT segments 51, and cached in the DRAM 30 in units of LUT segments 51. That is, the LUT 50 is refilled in the DRAM 30 in units of LUT segments 51, or evicted to the NAND memory 20 in units of LUT segments 51. The size of the LUT segments 51 is, for example, common to all the LUT segments 51. The size of the LUT segments 51 can be determined based on, for example, the unit of access to the DRAM 30.

[0029] A segment index is assigned to each LUT segment 51. For example, the segment index is a serial number assigned in ascending order of logical addresses starting from the LUT segment 51 corresponding to the beginning of the logical address space. In the example shown in Fig. 4, the LUT 50 is divided into m+1 LUT segments 51, and each LUT segment 51 is assigned a number from 0 to m as a segment index. For example, a value obtained by deleting the least significant digits corresponding to the number of entries included in the LUT segment 51 from the logical address is used as the segment index.

[0030] The segment index is an example of a third serial number.

[0031] Returning to the explanation of Figure 3. An LUT cache 31, a write buffer 32, and a read buffer 33 are allocated to the DRAM 30. The LUT cache 31 is a cache area in which a plurality of LUT segments 51 can be cached. The write buffer 32 stores user data DAT received from the host 2 until it is stored in the NAND memory 20. The read buffer 33 stores user data DAT read from the NAND memory 20 until transmission to the host 2 is complete.

[0032] The memory controller 10 includes an internal SRAM 11. A work area 70 and a queue area 71 are allocated to the SRAM 11.

[0033] When the memory controller 10 (specifically, the plurality of LUT engines 14 described below) uses a certain LUT segment 51, it transfers the corresponding LUT segment 51 from the LUT cache 31 to the SRAM 11 and uses the LUT segment 51 transferred to the SRAM 11. Using the LUT segment 51 includes referencing the LUT segment 51 and updating the LUT segment 51. When the memory controller 10 updates the LUT segment 51 in the SRAM 11, it writes back the updated LUT segment 51 to the LUT cache 31 as appropriate.

[0034] A plurality of queues are allocated to the queue area 71. Each queue has a data structure for transmitting and receiving information between circuits included in the memory controller 10. Each circuit included in the memory controller 10 will be described later.

[0035] The SRAM 11 may be located in one place within the memory controller 10, or may be distributed across multiple places. A part or all of the SRAM 11 may be built into any circuit included in the memory controller 10.

[0036] FIG. 5 is a schematic diagram showing an example of a plurality of circuits included in the memory controller 10 according to the embodiment.

[0037] The memory controller 10 includes multiple circuits, including a first processing circuit 12, a second processing circuit 13, multiple LUT engines 14, a third processing circuit 15, a reordering circuit 16, and a central processing unit (CPU) 17. Each of the first processing circuit 12, the second processing circuit 13, the multiple LUT engines 14, and the third processing circuit 15 is implemented by a hardware circuit such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). However, some or all of the first processing circuit 12, the second processing circuit 13, the multiple LUT engines 14, and the third processing circuit 15 may be implemented by a processor operating based on a computer program, such as a CPU, or by a combination of a processor operating based on a computer program and a hardware circuit. The CPU 17 performs various processes based on a firmware program. However, some or all of the processes performed by the CPU 17 may be implemented by a hardware circuit.

[0038] The first processing circuit 12 is an example of a first circuit. The second processing circuit 13 is an example of a second circuit. Each of the multiple LUT engines 14 is an example of a third circuit. The third processing circuit 15 is an example of a fourth circuit. The alignment circuit 16 is an example of a fifth circuit. The CPU 17 is an example of a sixth circuit.

[0039] The first processing circuit 12 generates one or more messages requesting processing in units of clusters based on an access request received from the host 2.

[0040] For example, when the first processing circuit 12 receives an access request requesting access to a logical address range of a size of N clusters, it generates a message for each of the N clusters included in the logical range. The message generated when the received access request is a read request is referred to as a lookup message.

[0041] The lookup message is a subcommand requesting the reading of one cluster data 40. The lookup message is transferred sequentially to some of the circuits disposed downstream of the first processing circuit 12. Each circuit that receives the lookup message during the transfer of the lookup message executes part of a series of processes for storing one cluster data 40 of the user data DAT requested to be read in the DRAM 30.

[0042] 6 is a schematic diagram showing an example of the structure of a lookup message transferred within the memory controller 10 according to the embodiment. Hereinafter, the function of each circuit included in the memory controller 10 and the structure of the lookup message transferred by each circuit will be described with reference to FIGS.

[0043] 6, the lookup message Ma sent by the first processing circuit 12 includes a logical address. The logical address included in the lookup message Ma indicates the location in the logical address space of one of the one or more clusters included in the logical address range specified by the read request.

[0044] In the following description, lookup messages transferred within the memory controller 10, including the lookup message Ma, will be collectively referred to as the lookup message M.

[0045] The lookup message Ma may include a sequential read flag. Specifically, when the first processing circuit 12 receives a read request, it determines whether the access pattern related to the read request corresponds to a sequential read. If it is determined that the access pattern corresponds to a sequential read, the first processing circuit 12 adds a sequential read flag to the lookup message Ma. If it is determined that the access pattern does not correspond to a sequential read, the first processing circuit 12 does not add a sequential read flag to the lookup message Ma.

[0046] A sequential read is an access pattern in which cluster data 40 is read in logical address order from a contiguous logical address range of a size equal to or greater than a certain number (however plural) of clusters. In other words, when the first processing circuit 12 receives a read request from the host 2 specifying a contiguous logical address range of a size equal to the size of multiple cluster data 40, it generates multiple lookup messages Ma requesting the reading of all cluster data 40 located in this logical address range. Then, the first processing circuit 12 adds a sequential read flag to each of the multiple lookup messages Ma generated.

[0047] In addition to sequential read, the access patterns for the memory system 1 include sequential write, random read, and random write. Sequential write is an access pattern in which cluster data 40 is written in logical address order to a range of consecutive logical addresses having a size of a certain number (however plural) of clusters. Random read is an access pattern in which a small number of cluster data 40 (less than a certain number) is read from each of a plurality of locations where the logical addresses are not consecutive. Random write is an access pattern in which a small number of cluster data 40 (less than a certain number) is written to each of a plurality of locations where the logical addresses are not consecutive.

[0048] The plurality of cluster data 40 read by sequential read is often written from the host 2 using a sequential write access pattern. Furthermore, when user data DAT is received from the host 2 using a sequential write access pattern, the memory controller 10 basically writes the received user data DAT to a range of consecutive physical addresses in the NAND memory 20. Therefore, when a read request is made for the user data DAT written in the NAND memory 20 using a sequential read access pattern, the memory controller 10 is often able to obtain two or more cluster data 40 from one page out of the plurality of cluster data 40 that make up the user data DAT.

[0049] As described above, in a read operation on the memory chip 21, a plurality of cluster data 40 are transferred in page units from the memory cell array 211 to the page register 212 by a sense operation, and then the desired cluster data 40 is transferred from the page register 212 to the memory controller 10. In the case of sequential read, one page of data often contains a plurality of cluster data 40 to be read, so the number of cluster data 40 to be read that can be acquired per sense operation increases, improving read efficiency.

[0050] The first processing circuit 12 detects the sequential read access pattern so that efficient reading is possible when a read request is received with the sequential read access pattern. When the first processing circuit 12 detects the sequential read access pattern, it attaches a sequential read flag, which is a flag indicating a sequential read, to each generated lookup message Ma.

[0051] The first processing circuit 12 transmits each generated message to the second processing circuit 13 via the queue 101.

[0052] A sequential read is a read from multiple clusters with consecutive logical addresses. Therefore, in the case of a sequential read, the first processing circuit 12 generates multiple lookup messages Ma with sequential read flags added, and transmits the generated multiple lookup messages Ma to the second processing circuit 13 in logical address order.

[0053] The first processing circuit 12 further stores the user data DAT received from the host 2 in the write buffer 32, and prepares an area in the read buffer 33 where the user data DAT read from the NAND memory 20 can be stored.

[0054] Before describing the second processing circuit 13, the multiple LUT engines 14 will be described. Each LUT engine 14 refers to or updates an LUT segment 51 based on a message. When referring to or updating an LUT segment 51, the LUT engine 14 transfers the target LUT segment 51 from the LUT cache 31 to the SRAM 11 and performs the reference or update on the LUT segment 51 in the SRAM 11.

[0055] Referring to and updating the LUT segments 51 requires a relatively large computational cost. Therefore, in order to improve the read performance of the memory system 1, it is necessary to process the referring to and updating of the LUT segments 51 as quickly as possible. Therefore, in this embodiment, the memory controller 10 is provided with a plurality of LUT engines 14 that refer to and update the LUT segments 51. Each of the plurality of LUT engines 14 independently refers to or updates the LUT segments 51. As shown in FIGS. 5 and 6 , the memory controller 10 is provided with, as an example of a plurality of LUT engines 14, an LUT engine 14e that uses an LUT segment 51 assigned an even-numbered segment index and an LUT engine 14o that uses an LUT segment 51 assigned an odd-numbered segment index. Note that three or more LUT engines 14 may be provided in the memory controller 10.

[0056] When the LUT engine 14 receives a lookup message M (a lookup message Mb described later), it identifies the location in the memory system 1 of the target cluster data 40 corresponding to the lookup message M by referring to the corresponding LUT segment 51 stored in the LUT cache 31. The cluster data 40 corresponding to the lookup message M is the cluster data 40 at the location indicated by the logical address included in the lookup message M, and is one cluster data 40 included in the user data DAT for which reading is requested. The cluster data 40 corresponding to the lookup message M is referred to as the cluster data 40 to be read specified by the lookup message M, or simply as the cluster data 40 to be read.

[0057] If the cluster data 40 to be read is stored in the write buffer 32, the LUT engine 14 refers to the LUT segment 51 and acquires an address (referred to as a write buffer address) indicating the location where the cluster data 40 to be read is stored in the write buffer 32. If the cluster data 40 to be read is not stored in the write buffer 32, the LUT engine 14 refers to the LUT segment 51 and acquires an address indicating the location in the NAND memory 20, that is, a physical address.

[0058] That is, in addition to a physical address, a write buffer address can be associated with a logical address for each entry of each LUT segment 51 in the LUT cache 31. When cluster data 40 (referred to as first cluster data 40) received from the host 2 with a certain value (referred to as a first value) specified as a logical address is stored in the NAND memory 20, and another cluster data 40 (referred to as second cluster data 40) with the first value specified as a logical address is newly received from the host 2, the second cluster data 40 is first stored in the write buffer 32. At approximately the same time as the second cluster data 40 is stored in the write buffer 32, the LUT engine 14 associates the first value with a write buffer address indicating the location where the second cluster data 40 is stored in the corresponding LUT segment 51 in the LUT cache 31. When the second cluster data 40 stored in the write buffer 32 is written to the NAND memory 20, the LUT engine 14 associates the first value with the physical address of the storage destination of the second cluster data 40 in the NAND memory 20. Thereafter, when the second cluster data 40 in the write buffer 32 is invalidated, the LUT engine 14 cancels the association between the first value and the write buffer address indicating the location where the second cluster data 40 was stored.

[0059] Returning to the explanation of the processing for the lookup message M, the LUT engine 14 performs a search on the LUT segment 51 using the logical address included in the lookup message M as a search key. If the search by the LUT engine 14 obtains a write buffer address as the location of the cluster data 40 to be read, the LUT engine 14 adds the write buffer address to the lookup message M as the reference result. If the search by the LUT engine 14 obtains a physical address instead of a write buffer address as the location of the cluster data 40 to be read, the LUT engine 14 adds the physical address to the lookup message M as the reference result.

[0060] Note that when a write buffer address is obtained as the location of the cluster data 40 to be written by a search by the LUT engine 14, this may be expressed as a hit in the write buffer 32.

[0061] When the second processing circuit 13 receives a lookup message M (i.e., a lookup message Ma) via the queue 101, it searches for the referenced LUT segment 51, i.e., the LUT segment 51 including an entry related to the logical address included in the lookup message M, based on the logical address included in the received lookup message M. If the referenced LUT segment 51 is not cached in the LUT cache 31, the second processing circuit 13 performs a refill of the referenced LUT segment 51.

[0062] If the referenced LUT segment 51 is cached in the LUT cache 31 or if the referenced LUT segment 51 is refilled, the second processing circuit 13 distributes the lookup message M to the LUT engines 14e and 14o. More specifically, the second processing circuit 13 distributes the lookup message M based on the segment index of the referenced LUT segment 51. If the segment index of the referenced LUT segment 51 is even, the second processing circuit 13 sends the lookup message M to the LUT engine 14e. If the segment index of the referenced LUT segment 51 is odd, the second processing circuit 13 sends the lookup message M to the LUT engine 14o.

[0063] Furthermore, if a sequential read flag is attached to the received lookup message M, the second processing circuit 13 attaches a buffer index to the lookup message M. The buffer index attached to the lookup message M is used in the alignment circuit 16. As will be described in detail later, the alignment circuit 16 includes a message buffer group 161 consisting of multiple message buffers 163, each of which is assigned a buffer index as a serial number. Each message buffer 163 is a buffer capable of storing one lookup message M. After being processed by the second processing circuit 13 and the third processing circuit 15, the lookup message M attached with the sequential read flag is stored in one of the multiple message buffers 163 in the alignment circuit 16. The value of the buffer index attached to the lookup message M by the second processing circuit 13 indicates the message buffer 163 among the multiple message buffers 163 in which the lookup message M is to be stored. In other words, the second processing circuit 13 specifies the message buffer 163 in which the lookup message M is to be stored using the buffer index attached to the lookup message M.

[0064] When the second processing circuit 13 receives multiple lookup messages M with sequential read flags added, it determines the value of a buffer index to be added to each lookup message M so that the multiple lookup messages M are stored in order of logical addresses in the multiple message buffers 163. Since the first processing circuit 12 transmits the multiple lookup messages M with sequential read flags added to the second processing circuit 13 in order of logical addresses, the second processing circuit 13 adds, to the multiple lookup messages M, a value corresponding to the order in which they were received from the first processing circuit 12, as a buffer index.

[0065] The buffer index added to each of the plurality of lookup messages M to which the sequential read flag is added is an example of a first serial number.

[0066] The second processing circuit 13 stores the write pointer 131 and read pointer 132 used to determine the value of the buffer index in an internal register, etc. The write pointer 131 and read pointer 132 will be described in detail later.

[0067] The number of queues through which the second processing circuit 13 transmits the lookup message M to each LUT engine 14 is not limited to a specific number. Here, as an example, the second processing circuit 13 and the LUT engine 14e are connected via two queues 102 and 103, and the second processing circuit 13 and the LUT engine 14o are connected via two queues 104 and 105.

[0068] For example, when the second processing circuit 13 transmits a lookup message M in which the segment index of the target LUT segment 51 is an even number to the LUT engine 14e, the second processing circuit 13 selects one of the two queues 102 and 103 based on the segment index of the target LUT segment 51. If the value of the second least significant bit of the segment index of the target LUT segment 51 is an even number, the second processing circuit 13 selects the queue 102, and if the value of the second least significant bit of the segment index of the target LUT segment 51 is an odd number, the second processing circuit 13 selects the queue 103.

[0069] Furthermore, for example, when the second processing circuit 13 transmits a lookup message in which the segment index of the target LUT segment 51 is odd to the LUT engine 14o, it selects one of the two queues 104, 105 based on the segment index of the target LUT segment 51. If the value of the second least significant bit of the segment index of the target LUT segment 51 is even, the second processing circuit 13 selects the queue 104, and if the value of the second least significant bit of the segment index of the target LUT segment 51 is odd, the second processing circuit 13 selects the queue 105.

[0070] When the second processing circuit 13 executes a refill of the LUT segment 51 referenced by a certain lookup message M, it cannot transmit the lookup message M to the LUT engine 14 until the refill is completed. In the embodiment, since the transmission path (i.e., queue) to each LUT engine 14 is duplicated, the second processing circuit 13 can process the next lookup message M without waiting for the refill to be completed.

[0071] Note that refilling is not necessary if the memory system 1 is configured such that all LUTs 50 are cached in the DRAM 30. In such a case, there is no interruption in processing of lookup messages while waiting for the refill to complete. Therefore, the transmission paths (i.e., queues) to each LUT engine 14 do not necessarily need to be duplicated.

[0072] The lookup message M transferred from the second processing circuit 13 to each LUT engine 14 is referred to as a lookup message Mb. As shown in Fig. 6, in the case of sequential read, the lookup message Mb has a structure in which a buffer index is added to the lookup message Ma.

[0073] As described above, each LUT engine 14 adds the result of referencing the LUT segment 51 to a lookup message Mb. The lookup message M after being processed in this manner is referred to as a lookup message Mc. As shown in Fig. 6, the lookup message Mc includes a write buffer address if there is a hit in the write buffer 32, and includes a physical address if there is no hit in the write buffer 32.

[0074] The third processing circuit 15 receives the lookup message Mc from the LUT engine 14e via the queue 106. The third processing circuit 15 also receives the lookup message Mc from the LUT engine 14o via the queue 107.

[0075] The third processing circuit 15 performs different operations depending on whether the received lookup message Mc includes a write buffer address as a reference result of the LUT segment 51 and whether the received lookup message Mc includes a sequential read flag.

[0076] If the lookup message Mc includes a write buffer address but does not include a sequential read flag, the third processing circuit 15 transmits the lookup message Mc to the first processing circuit 12 via the queue 108. The lookup message M transferred from the third processing circuit 15 to the first processing circuit 12 is referred to as a lookup message Md. As shown in FIG. 6 , the lookup message Md includes a write buffer address. When the first processing circuit 12 receives the lookup message Md, it obtains cluster data 40 from the position in the write buffer 32 indicated by the write buffer address included in the lookup message Md, and transmits the obtained cluster data 40 to the host 2.

[0077] If the lookup message Mc does not include a write buffer address and does not include a sequential read flag, the third processing circuit 15 transmits the lookup message Mc to the CPU 17 via the queue 109. The lookup message Mc transferred from the third processing circuit 15 to the CPU 17 is referred to as a lookup message Me. As shown in FIG. 6, the lookup message Me includes only a logical address and a physical address. In other words, if a read is requested with a random read access pattern and the cluster data 40 to be read is not stored in the write buffer 32, the lookup message Me is transmitted from the third processing circuit 15 to the CPU 17.

[0078] If the lookup message Mc does not include a write buffer address and includes a sequential read flag, the third processing circuit 15 transmits the lookup message Mc to the alignment circuit 16 via the queue 110. The lookup message M transferred from the third processing circuit 15 to the first processing circuit 12 is referred to as a lookup message Mf.

[0079] If the lookup message Mc includes a write buffer address and a sequential read flag, the third processing circuit 15 copies the lookup message Mc and transmits one of the two lookup messages Mc obtained by the copying to the first processing circuit 12 via the queue 108 as a lookup message Md. The third processing circuit 15 also attaches a dummy flag to the other of the two lookup messages Mc and transmits it to the alignment circuit 16 via the queue 110 as a lookup message Mf.

[0080] Therefore, in the case of a sequential read, the lookup message Md includes a sequential read flag and a buffer index. In the case of a random read, the lookup message Md does not include either a sequential read flag or a buffer index. Note that the first processing circuit 12 does not use the sequential read flag or the buffer index. The third processing circuit 15 may transmit the lookup message M from which the sequential read flag and the buffer index have been deleted to the first processing circuit 12 as the lookup message Md.

[0081] The lookup message Mf includes a physical address if there is no hit in the write buffer 32. The lookup message Mf includes a write buffer address and a dummy flag if there is a hit in the write buffer 32. Note that the alignment circuit 16 and the CPU 17 do not use the write buffer address. Therefore, if there is a hit in the write buffer 32, the lookup message Mf that does not include a write buffer address may be transferred to the alignment circuit 16.

[0082] The alignment circuit 16 receives multiple lookup messages including sequential read flags via a queue 110. The alignment circuit 16 has a function of aligning the received multiple lookup messages in the order of logical addresses. After being aligned in the order of logical addresses by the alignment circuit 16, the multiple lookup messages Mf are acquired by the CPU 17 via a queue 111 in the aligned order.

[0083] 7 is a schematic diagram showing an example of the configuration of the alignment circuit 16 according to the embodiment. The alignment circuit 16 includes a message buffer group 161 and an SRAM 162.

[0084] The message buffer group 161 has a plurality of message buffers 163, each capable of storing one lookup message M (more precisely, lookup message Mf). A buffer index is assigned as a serial number to each message buffer 163. In the example shown in Fig. 7, the message buffer group 161 includes n+1 message buffers 163, and each message buffer 163 is assigned a buffer index of any number from 0 to n.

[0085] Each message buffer 163 is an example of a second buffer. The buffer index assigned to each message buffer 163 is an example of a second serial number.

[0086] A buffer management bitmap 60 is stored in the SRAM 162. The buffer management bitmap 60 has information bits, the number of which is equal to the number of message buffers 163, each of which is associated one-to-one with one message buffer 163. Each information bit indicates whether or not a lookup message Mf that has not yet been retrieved by the CPU 17 is stored in the corresponding message buffer 163. The state of an information bit indicating that a lookup message Mf that has not yet been retrieved is stored in the corresponding message buffer 163 is represented as "enable," and the state of an information bit indicating that a lookup message Mf that has not yet been retrieved is not stored in the corresponding message buffer 163 is represented as "disable."

[0087] The alignment circuit 16 stores each lookup message Mf received from the third processing circuit 15 in the message buffer 163 indicated by the buffer index added to each lookup message Mf. In response to the storage of each lookup message Mf, the alignment circuit 16 changes the information bit corresponding to the message buffer 163 in which the message Mf is stored from "disable" to "enable."

[0088] As described above, in the case of a sequential read, the first processing circuit 12 transmits multiple lookup messages M(Ma) with sequential read flags attached to them to the second processing circuit 13 in the order of their logical addresses. The second processing circuit 13 assigns, to the multiple lookup messages M(Ma), a buffer index corresponding to the order in which they were received from the first processing circuit 12. The alignment circuit 16 stores each lookup message Mf in the message buffer 163 indicated by the buffer index attached to the respective lookup message Mf. Thus, the message buffer group 161 stores multiple lookup messages Mf sorted in the order of their logical addresses. In other words, by retrieving lookup messages Mf from the message buffer group 161 in the order of their buffer indexes, the CPU 17 can obtain the lookup messages Mf in the order of their logical addresses. Note that retrieving lookup messages Mf from the message buffer group 161 (or the message buffer 163) may be referred to as obtaining lookup messages Mf from the alignment circuit 16.

[0089] Each lookup message Mf stored in the message buffer group 161 is extracted in the order of buffer index by the CPU 17. The alignment circuit 16 notifies the second processing circuit 13 of the buffer index of the message buffer 163 from which the last lookup message Mf was extracted.

[0090] More specifically, the buffer index of the message buffer 163 from which the lookup message Mf was last retrieved is stored in the second processing circuit 13 as the read pointer 132. The alignment circuit 16 increments the read pointer 132 each time the CPU 17 retrieves a lookup message Mf. By operating the read pointer 132 in this manner, the second processing circuit 13 is notified of the buffer index of the message buffer 163 from which the lookup message Mf was last retrieved.

[0091] The message buffer group 161 is treated as a ring buffer. For example, if the value of the read pointer 132 reaches the maximum value of the buffer index and is then further incremented, the value of the read pointer 132 returns to the minimum value of the buffer index.

[0092] The second processing circuit 13 manages the value of the buffer index to be added to the next lookup message M using the write pointer 131. Based on the write pointer 131 and the read pointer 132, the second processing circuit 13 adjusts the transmission timing of the lookup message Mb so that a new lookup message Mf is not stored in an overwritten format in the message buffer 163 in which a lookup message Mf that has not yet been extracted is stored.

[0093] The CPU 17 receives the lookup message Me via the queue 109. When the CPU 17 receives the lookup message Me, it generates a read command for reading one cluster data 40 from the location indicated by the physical address included in the lookup message Me.

[0094] Furthermore, the CPU 17 retrieves lookup messages Mf from message buffers 163 in the message buffer group 161 that correspond to information bits set to a value indicating "enable" in the buffer management bitmap 60. However, the CPU 17 retrieves the lookup messages Mf in the order of the buffer indexes. The CPU 17 generates a read command based on the sequentially retrieved lookup messages Mf. When two or more cluster data 40 out of multiple cluster data 40 included in one page are targeted for reading by different lookup messages Mf that are sequentially retrieved, the CPU 17 generates a read command so that the two or more cluster data 40 can be retrieved in one sensing operation.

[0095] After retrieving the lookup messages Mf that include a dummy flag from among the lookup messages Mf stored in the message buffer group 161, the CPU 17 discards the lookup messages Mf without using them. In other words, the CPU 17 generates a read command based on the lookup messages Mf that do not include a dummy flag from among the lookup messages Mf retrieved from the message buffer group 161.

[0096] The CPU 17 transmits the generated read command to the NAND memory 20 (more precisely, to the memory chip 21). Under the control of the CPU 17, the memory controller 10 stores the cluster data 40 received from the memory chip 21 in response to the read command in the read buffer 33. The CPU 17 notifies the first processing circuit 12 that the cluster data 40 has been stored in the read buffer 33. The first processing circuit 12 transmits the cluster data 40 stored in the read buffer 33 to the host 2. The operation of the CPU 17 acquiring one or more cluster data 40 from the NAND memory 20 by transmitting a read command to the NAND memory 20 may be referred to as a read operation.

[0097] 8 is a schematic diagram for explaining an example of control of the lookup message M in the case of sequential read by the memory controller 10 of the embodiment. This diagram shows control in the case where there is no hit in the write buffer 32.

[0098] In FIG. 8, the numeric information from 0 to 8 labeled on the lookup messages M represents the transmission order of the lookup messages M from the first processing circuit 12. In other words, the numeric information labeled on each lookup message M corresponds to the order of the logical addresses. A lookup message M labeled with the numeric information "x" may be written as a lookup message M#x. However, in the example shown in FIG. 8, "x" is an integer from 0 to 8.

[0099] The second processing circuit 13 distributes the lookup messages M#0 to M#8 received sequentially as lookup messages Ma to the LUT engine 14e and the LUT engine 14o via paths according to the segment indexes.

[0100] As an example, the second processing circuit 13 transmits lookup messages M#0 to M#2 to the LUT engine 14e via the queue 102. The second processing circuit 13 transmits lookup messages M#3 to M#5 to the LUT engine 14o via the queue 104. The second processing circuit 13 transmits lookup messages M#6 to M#8 to the LUT engine 14e via the queue 103.

[0101] The LUT engine 14e sequentially acquires the lookup messages Mb from the queues 102 and 103, performs the above-described processing on each acquired lookup message Mb, and transmits each processed lookup message Mb to the third processing circuit 15 as a lookup message Mc.

[0102] Here, as an example, the LUT engine 14e obtains lookup messages Mb in a round-robin manner from the queues 102 and 103. Therefore, the LUT engine 14e transmits lookup messages M#0, M#6, M#1, M#7, M#2, and M#8 as lookup messages Mc in this order.

[0103] The method by which the LUT engine 14e acquires the lookup message Mb is not limited to the round robin method.

[0104] The LUT engine 14o sequentially acquires lookup messages Mb from the queues 104 and 105 in the same manner as the LUT engine 14e, performs the processing already described for each acquired lookup message Mb, and then transmits each processed lookup message Mb to the third processing circuit 15 as a lookup message Mc.

[0105] As an example, the LUT engine 14o acquires lookup messages Mb from the queues 104 and 105 in a round-robin fashion. In this example, the LUT engine 14o acquires lookup messages M#3, M#4, and M#5 as lookup messages Mb in this order via the queue 104. Therefore, the LUT engine 14o transmits lookup messages M#3, M#4, and M#5 as lookup messages Mc in this order.

[0106] The third processing circuit 15 sequentially acquires the lookup messages Mc from the queues 106 and 107, performs the above-described processing on each acquired lookup message Mc, and transmits each processed lookup message Mc to the alignment circuit 16 as a lookup message Mf.

[0107] Here, as an example, the third processing circuit 15 obtains lookup messages Mc in a round-robin manner from the queues 106 and 107. Therefore, the third processing circuit 15 transmits lookup message M#0, lookup message M#3, lookup message M#6, lookup message M#4, lookup message M#1, lookup message M#5, lookup message M#7, lookup message M#2, and lookup message M#8 in this order as lookup messages Mf.

[0108] The method by which the third processing circuit 15 acquires the lookup message Mc is not limited to the round robin method.

[0109] The lookup messages M#0, M#3, M#6, M#4, M#1, M#5, M#7, M#2, and M#8 input to the alignment circuit 16 as lookup messages Mf are aligned in the order of logical addresses by the alignment circuit 16. These lookup messages Mf are then extracted by the CPU 17 in the order of logical addresses.

[0110] In the embodiment, the multiple LUT engines 14 share the task of referencing the LUT segments 51 corresponding to the multiple lookup messages M, and therefore the order of processing the multiple lookup messages M is shuffled by the multiple LUT engines 14. Then, circuits downstream of the multiple LUT engines 14, particularly the third processing circuit 15, acquire the multiple lookup messages Mc in an order different from the logical address order.

[0111] If the CPU 17 retrieves multiple lookup messages Mf in an order other than the logical address order, it will be difficult for the CPU 17 to generate a read command to retrieve multiple cluster data 40 from one page in a single sense operation, resulting in reduced read efficiency.

[0112] Therefore, in the embodiment, an alignment circuit 16 is provided between the third processing circuit 15 and the CPU 17. The plurality of lookup messages Mf that have been shuffled in an order different from the logical address order are aligned in the logical address order by the alignment circuit 16, and then acquired by the CPU 17 in the logical address order.

[0113] The above configuration enables the CPU 17 to generate a read command to acquire a plurality of cluster data 40 from one page in one sense operation, thereby suppressing a decrease in read efficiency.

[0114] That is, according to the embodiment, the positions of the cluster data 40 to be read that are related to the multiple lookup messages M can be identified at high speed by the multiple LUT engines 14, and in the case of sequential read, two or more cluster data 40 to be read can be acquired from the memory chip 21 per one sense operation on the memory chip 21. Therefore, the read performance of the memory system 1 is improved.

[0115] 9 is a schematic diagram for explaining another example of control of the lookup message M in the case of sequential read by the memory controller 10 of the embodiment. This diagram shows control when there is a hit in the write buffer 32. Regarding the example shown in FIG. 9, differences from the example shown in FIG. 8 will be explained, and explanations of the same matters as in the example shown in FIG. 8 will be omitted.

[0116] In the example shown in FIG. 9, it is assumed that the write buffer 32 stores cluster data 40 corresponding to each of lookup message M#0, lookup message M#5, and lookup message M#6.

[0117] The LUT engine 14e acquires a write buffer address as a reference result in processing each of the lookup messages M#0 and M#6. Therefore, the LUT engine 14e adds a write buffer address, rather than a physical address, as a reference result to each of the lookup messages M#0 and M#6.

[0118] In processing the lookup message M#5, the LUT engine 14o obtains a write buffer address as a reference result, and therefore adds the write buffer address, rather than a physical address, to the lookup message M#5 as a reference result.

[0119] In FIG. 9, the lookup messages M that hit the write buffer 32 are hatched with dots.

[0120] The third processing circuit 15 transmits the lookup message M#0, lookup message M#5, and lookup message M#6 that hit the write buffer 32 to the first processing circuit 12 in the order in which they were acquired, that is, in the order of lookup message M#0, lookup message M#6, and lookup message M#5.

[0121] 8, the third processing circuit 15 transmits the lookup messages M#0 to M#8 as lookup messages Mf to the alignment circuit 16. However, the third processing circuit 15 transmits the lookup messages M#0, M#5, and M#6 that hit the write buffer 32 to the alignment circuit 16 with dummy flags added.

[0122] When the CPU 17 retrieves a lookup message Mf that includes a dummy flag, it discards the retrieved lookup message Mf without using it. That is, the CPU 17 retrieves lookup message M#0, lookup message M#1, lookup message M#2, lookup message M#3, lookup message M#4, lookup message M#5, lookup message M#6, lookup message M#7, and lookup message M#8 from the message buffer group 161 in this order, and uses lookup message M#1, lookup message M#2, lookup message M#3, lookup message M#4, lookup message M#7, and lookup message M#8.

[0123] Consider a case where the third processing circuit 15 sends the lookup message M that hits the write buffer 32 only to the first processing circuit 12, and does not send it to the alignment circuit 16. The technology where the third processing circuit 15 sends the lookup message M that hits the write buffer 32 only to the first processing circuit 12, and does not send it to the alignment circuit 16, is referred to as the technology according to the comparative example.

[0124] According to the technology of the comparative example, in the alignment circuit 16, only the lookup message Mf that does not hit the write buffer 32 is stored in the message buffer group 161, and the lookup message Mf that hits the write buffer 32 is not stored in the message buffer group 161. Therefore, the message buffer 163 corresponding to the lookup message M that hits the write buffer 32 is maintained as “disabled” in the buffer management bitmap 60.

[0125] In the technology according to the comparative example, the CPU 17 can retrieve lookup messages Mf only from message buffers 163 corresponding to information bits set to a value indicating “enable” in the buffer management bitmap 60, and the CPU 17 can retrieve lookup messages Mf in the order of buffer indexes. If a lookup message M that has hit the write buffer 32 exists, even if a subsequent lookup message Mf in terms of logical address is stored in the message buffer 163, the CPU 17 suspends processing until the message buffer 163 corresponding to the lookup message M that has hit the write buffer 32 is set to “enable.” However, the lookup message M that has hit the write buffer 32 is not stored in the message buffer 163. Therefore, according to the technology according to the comparative example, if a hit occurs in the write buffer 32, the CPU 17 cannot proceed with processing, and the memory controller 10 cannot continue operating. For example, even if a time limit is set for suspending processing, it takes time to resume processing.

[0126] In contrast, in the embodiment, the lookup message M that hits the write buffer 32 is duplicated, and one of the two lookup messages M obtained by duplication is sent to the first processing circuit 12, and the other is sent to the alignment circuit 16 with a dummy flag added. Then, the information bit in the buffer management bitmap 60 that corresponds to the message buffer 163 in which the lookup message Mf with the dummy flag added is stored is set to "enable." Therefore, the CPU 17 can extract the lookup message Mf with the dummy flag added from the message buffer 163 in which the lookup message Mf is stored, and continue processing.

[0127] Next, the operation of the memory system 1 according to the embodiment will be described. Here, only the operation in response to a read request will be described.

[0128] FIG. 10 is a flowchart showing an example of an operation of the first processing circuit 12 according to the embodiment to generate a lookup message Ma based on a read request.

[0129] The first processing circuit 12 determines whether or not the first processing circuit 12 has received a read request (S101). If a read request has not been received (S101: No), the first processing circuit 12 executes the processing of S101 again.

[0130] When the first processing circuit 12 receives a read request (S101: Yes), it divides the logical address range for which reading is requested into cluster units and generates a lookup message Ma for each cluster (S102).

[0131] Furthermore, the memory controller 10 determines whether the access pattern according to the read request corresponds to a sequential read (S103).

[0132] The method for determining whether an access pattern corresponding to a read request corresponds to a sequential read can be designed arbitrarily. In one example, whether an access pattern corresponding to a read request corresponds to a sequential read is determined based on a comparison between size information included in the read request and a predetermined threshold. If the size information exceeds the threshold, the first processing circuit 12 determines that the access pattern corresponding to the read request corresponds to a sequential read. If the size information does not meet the threshold, the first processing circuit 12 determines that the access pattern corresponding to the read request does not correspond to a sequential read.

[0133] In another example, when the memory controller 10 receives one or more read requests within a specified period, it may determine whether the access pattern corresponding to the read requests corresponds to a sequential read based on a comparison between the sum of the size information included in the one or more read requests and a threshold value.

[0134] If the access pattern according to the read request corresponds to a sequential read (S103: Yes), the first processing circuit 12 adds a sequential read flag to each lookup message Ma (S104) and transmits each lookup message Ma to the second processing circuit 13 (S105).

[0135] If the access pattern according to the read request does not correspond to a sequential read (S103: No), the first processing circuit 12 skips the process of S104 and executes the process of S105.

[0136] After the process of S105, the first processing circuit 12 executes the process of S101 again.

[0137] FIG. 11 is a flowchart showing an example of the operation of the second processing circuit 13 according to the embodiment.

[0138] The second processing circuit 13 determines whether or not the second processing circuit 13 has received the lookup message Ma from the first processing circuit 12 (S201). If the second processing circuit 13 has not received the lookup message Ma (S201: No), the second processing circuit 13 executes the process of S201 again.

[0139] When the second processing circuit 13 receives the lookup message Ma (S201: Yes), the second processing circuit 13 determines whether the target LUT segment 51 is stored in the LUT cache 31 (S202). The target LUT segment 51 is the LUT segment 51 that includes an entry associated with the logical address included in the received lookup message Ma.

[0140] If the target LUT segment 51 is not stored in the LUT cache 31 (S202: No), the second processing circuit 13 executes refill of the target LUT segment 51 (S203). That is, the second processing circuit 13 reads the target LUT segment 51 from the NAND memory 20 and stores it in the LUT cache 31.

[0141] If the target LUT segment 51 is stored in the LUT cache 31 (S202: Yes), the second processing circuit 13 skips the processing of S203.

[0142] Next, the second processing circuit 13 identifies the segment index of the target LUT segment (S204), and then determines whether or not the lookup message Ma includes a sequential read flag (S205).

[0143] If the lookup message Ma includes a sequential read flag (S205: Yes), the second processing circuit 13 determines whether the value of the write pointer 131 is equal to the value of the read pointer 132 advanced by 1 (S206).

[0144] If the value of the write pointer 131 is equal to the value of the read pointer 132 advanced by 1 (S206: Yes), the second processing circuit 13 executes the process of S206 again. That is, the second processing circuit 13 waits (postpones) for the execution of the subsequent processes (S207 to S209), specifically, the transmission of the lookup message Mb for which the next message buffer 163 is set as the storage destination.

[0145] As described above, the message buffer group 161 is treated as a ring buffer. By waiting to send the lookup message Mb until the determination condition of S206 is satisfied, the position indicated by the write pointer 131 is prevented from overtaking the position indicated by the read pointer 132. In other words, a lookup message Mf that has not yet been retrieved by the CPU 17 is prevented from being overwritten by another lookup message Mf.

[0146] If the value of the write pointer 131 is not equal to the value of the read pointer 132 advanced by 1 (S206: No), the second processing circuit 13 adds the value of the write pointer 131 to the lookup message Ma as a buffer index representing the message buffer where the message is stored (S207), and then increments the write pointer 131 (S208).

[0147] The second processing circuit 13 transmits the lookup message Ma that has undergone the above processing as a lookup message Mb to one of the LUT engines 14 via a route according to the segment index (S209). Then, the second processing circuit 13 executes the processing of S201 again.

[0148] If the lookup message Ma does not include a sequential read flag (S205: No), the second processing circuit 13 skips the processes from S206 to S208 and executes the process of S209.

[0149] FIG. 12 is a flowchart showing an example of the operation of the LUT engine 14 according to the embodiment.

[0150] The LUT engine 14 determines whether or not it has received a lookup message Mb from the second processing circuit 13 (S301). If the LUT engine 14 has not received a lookup message Mb (S301: No), the LUT engine 14 executes the process of S301 again.

[0151] When the LUT engine 14 receives the lookup message Mb (S301: Yes), the LUT engine 14 refers to the target LUT segment 51 (S302). That is, the LUT engine 14 acquires a physical address or a write buffer address associated with the logical address included in the lookup message Mb based on the target LUT segment 51.

[0152] The LUT engine 14 adds the lookup result, i.e., the physical address or the write buffer address, to the lookup message Mb (S303).Then, the LUT engine 14 transmits the lookup message M that has undergone the above processing as a lookup message Mc to the third processing circuit 15 (S304).Then, the LUT engine 14 executes the processing of S301 again.

[0153] FIG. 13 is a flowchart showing an example of the operation of the third processing circuit 15 according to the embodiment.

[0154] The third processing circuit 15 determines whether or not the third processing circuit 15 has received a lookup message Mc from any of the LUT engines 14 (S401). If the third processing circuit 15 has not received a lookup message Mc (S401: No), the third processing circuit 15 executes the process of S401 again.

[0155] When the third processing circuit 15 receives the lookup message Mc (S401: Yes), the third processing circuit 15 determines whether or not the lookup message Mc includes a sequential read flag (S402).

[0156] If the lookup message Mc includes a sequential read flag (S402: Yes), the third processing circuit 15 further determines whether the lookup message Mc includes a write buffer address (S403).

[0157] If the lookup message Mc includes a write buffer address (S403: Yes), the third processing circuit 15 copies the lookup message Mc twice (S404), and then transmits one of the two lookup messages Mc to the first processing circuit 12 as a lookup message Md (S405).

[0158] The third processing circuit 15 adds a dummy flag to the other of the two lookup messages Mc (S406), and then transmits the lookup message Mc with the dummy flag added to the alignment circuit 16 as a lookup message Mf (S407).

[0159] If the lookup message Mc does not include a write buffer address (S403: No), the lookup message Mc is sent to the alignment circuit 16 as a lookup message Mf (S408).

[0160] If the lookup message Mc does not include a sequential read flag (S402: No), the third processing circuit 15 further determines whether the lookup message Mc includes a write buffer address (S409).

[0161] If the lookup message Mc includes a write buffer address (S409: Yes), the third processing circuit 15 transmits the lookup message Mc to the first processing circuit 12 as a lookup message Md (S410).

[0162] If the lookup message Mc does not include a write buffer address (S409: No), the third processing circuit 15 transmits the lookup message Mc to the CPU 11 as a lookup message Me (S411).

[0163] After the process of S407, S408, S410, or S411, the third processing circuit 15 executes the process of S401 again.

[0164] FIG. 14 is a flowchart showing an example of the operation of the alignment circuit 16 according to the embodiment.

[0165] The alignment circuit 16 determines whether or not the alignment circuit 16 has received a lookup message Mf from the third processing circuit 15 (S501).

[0166] When the alignment circuit 16 receives a lookup message Mf (S501: Yes), the alignment circuit 16 stores the lookup message Mf in the message buffer 163 indicated by the buffer index included in the lookup message Mf (S502). Then, the alignment circuit 16 sets the information bit corresponding to the message buffer 163 in which the lookup message Mf is stored to "enable" in the buffer management bitmap 60 (S503). Then, the alignment circuit 16 executes the process of S501 again.

[0167] If the alignment circuit 16 has not received a lookup message Mf (S501: No), the alignment circuit 16 determines whether or not one lookup message Mf has been retrieved by the CPU 17 from the message buffer group 161 (S504). The CPU 17 can retrieve a lookup message Mf from the message buffer 163 having a buffer index subsequent to the buffer index of the message buffer 163 from which the last lookup message Mf was retrieved.

[0168] If one lookup message Mf has been retrieved from the message buffer group 161 (S504: Yes), the alignment circuit 16 sets the information bit in the buffer management bitmap 60 corresponding to the message buffer 163 from which the lookup message Mf was retrieved to "disable" (S505). The alignment circuit 16 also increments the read pointer 132 (S506). Then, the alignment circuit 16 executes the process of S501 again.

[0169] If one lookup message Mf has not been retrieved from the message buffer group 161 (S504: No), the alignment circuit 16 skips the processes of S505 and S506 and executes the process of S501 again.

[0170] FIG. 15 is a flowchart showing an example of an operation of the CPU 17 according to the embodiment to process the lookup message Me transmitted from the third processing circuit 15.

[0171] The CPU 17 determines whether or not the CPU 17 has received a lookup message Me from the third processing circuit 15 (S601). If the CPU 17 has not received a lookup message Me (S601: No), the CPU 17 executes the process of S601 again.

[0172] When the CPU 17 receives the lookup message Me (S601: Yes), the CPU 17 generates a read command based on the lookup message Me (S602). That is, the CPU 17 generates a read command for acquiring the cluster data 40 to be read that is specified by the lookup message Me. According to this read command, page data including the cluster data 40 to be read that is specified by the lookup message Me is transferred from the memory cell array 211 to the page register 212 by a sense operation, and then the cluster data 40 is output from the page register 212 to the memory controller 10.

[0173] The CPU 17 transmits the generated read command to the memory chip 21 in which the cluster data 40 to be read is stored (S603). Then, the CPU 17 stores the cluster data 40 to be read, which is output from the memory chip 21 in response to the read command, in the read buffer 33 (S604).

[0174] The CPU 17 notifies the first processing circuit 12 that the cluster data 40 to be read has been stored in the read buffer 33 (S605). Then, the CPU 17 executes the processing of S601 again.

[0175] FIG. 16 is a flowchart showing an example of the operation of the CPU 17 according to the embodiment to sequentially retrieve and process lookup messages Mf from the message buffer group 161.

[0176] The CPU 17 determines whether or not a lookup message Mf that has not yet been retrieved is stored in a message buffer 163 subsequent to the message buffer 163 from which the last lookup message Mf was retrieved (S701). The message buffer 163 subsequent to the message buffer 163 from which the last lookup message Mf was retrieved, as mentioned in the description of the processing of S701, is referred to as the first message buffer 163. Furthermore, if a lookup message Mf that has not yet been retrieved is stored in the first message buffer 163, this lookup message Mf is referred to as the first lookup message Mf.

[0177] If the first message buffer 163 does not store a lookup message Mf that has not yet been extracted (S701: No), the CPU 17 executes the process of S701 again.

[0178] If the first message buffer 163 stores a lookup message Mf that has not yet been retrieved, i.e., the first lookup message Mf (S701: Yes), the CPU 17 retrieves the first lookup message Mf from the first message buffer 163 (S702). Then, the CPU 17 determines whether a subsequent message buffer 163 stores a lookup message Mf that has not yet been retrieved (S703).

[0179] When the processing of S703 is executed following the processing of S702, the subsequent message buffer 163 mentioned in the description of the processing of S703 refers to the message buffer 163 with the buffer index subsequent to the buffer index of the first message buffer 163. When the processing of S703 is executed following the processing of S705 or S707, the subsequent message buffer 163 mentioned in the description of the processing of S703 refers to the message buffer 163 with the buffer index subsequent to the buffer index of the message buffer 163 from which the lookup message Mf was extracted by the processing of S705 or S707. The subsequent message buffer 163 mentioned in the description of the processing of S703 is referred to as the second message buffer 163. Note that the second message buffer 163 refers to the message buffer 163 mentioned in the latest (current) processing of S703, and does not refer to the message buffer 163 mentioned in processing of S703 that was executed in the past.

[0180] If a lookup message Mf that has not yet been extracted is stored in the second message buffer 163 (S703: Yes), the CPU 17 determines whether the lookup message Mf stored in the second message buffer 163 includes a dummy flag (S704).

[0181] If the lookup message Mf stored in the second message buffer 163 includes a dummy flag (S704: Yes), the CPU 17 removes and discards this lookup message Mf from the second message buffer 163 (S705). Then, the CPU 17 executes the process of S703 again.

[0182] If the lookup message Mf stored in the second message buffer 163 does not contain a dummy flag (S704: No), the CPU 17 determines whether the cluster data 40 to be read specified by the lookup message Mf stored in the second message buffer 163 is stored in the same page as the cluster data 40 to be read specified by the first lookup message Mf (S706).

[0183] If the cluster data 40 to be read specified by the lookup message Mf stored in the second message buffer 163 is stored in the same page as the cluster data 40 to be read specified by the first lookup message Mf (S706: Yes), the CPU 17 retrieves the lookup message Mf from the second message buffer 163 (S707), and then executes the processing of S703 again.

[0184] If the second message buffer 163 does not store a lookup message Mf that has not yet been retrieved (S703: No), or if the cluster data 40 to be read specified by the lookup message Mf stored in the second message buffer 163 is not stored in the same page as the cluster data 40 to be read specified by the first lookup message Mf (S706: No), the CPU 17 generates a read command based on all the lookup messages Mf retrieved after the latest processing of S701 (S708). That is, the CPU 17 transfers one page of data including the cluster data 40 to be read specified by the first lookup message Me from the memory cell array 211 to the page register 212 by one sensing operation, and generates a read command to output the cluster data 40 to be read specified by each lookup message Mf retrieved after the latest processing of S701 from the one page of data stored in the page register 212.

[0185] The CPU 17 transmits the generated read command to the memory chip 21 (S709). Then, the CPU 17 stores the respective cluster data 40 to be read, which are output from the memory chip 21 in response to the read command, in the read buffer 33 (S710).

[0186] The CPU 17 notifies the first processing circuit 12 that each of the cluster data 40 to be read has been stored in the read buffer 33 (S711). Then, the CPU 17 executes the processing of S701 again.

[0187] FIG. 17 is a flowchart showing an example of the operation of transmitting the cluster data 40 to be read by the first processing circuit 12 to the host 2 according to the embodiment.

[0188] 17, the first processing circuit 12 transfers the cluster data 40 stored in the location indicated by the write buffer address included in the lookup message Mc in the write buffer 32 or the read buffer 33 to the host 2 (S801). The first processing circuit 12 repeatedly executes the process of S801.

[0189] As described above, according to the embodiment, when the first processing circuit 12 receives from the host 2 at least one read request specifying a contiguous logical address range of a size of multiple clusters, it issues multiple lookup messages M requesting the reading of all cluster data 40 located in the logical address range in the order of logical addresses. The second processing circuit 13 assigns a buffer index indicating the message buffer 163 where the messages are stored to each of the multiple lookup messages M as a first serial number corresponding to the order of issuance, and distributes the multiple lookup messages M with the assigned buffer index to multiple LUT engines 14. Each of the multiple LUT engines 14 identifies the location of the cluster data 40 to be read that corresponds to the lookup message M assigned to it by referencing one of the LUT segments 51 in the LUT cache 31, and adds location information indicating the identified location to the lookup message M assigned to it. The third processing circuit 15 acquires the multiple lookup messages M with the assigned buffer index from the multiple LUT engines 14. The alignment circuit 16 aligns the multiple lookup messages M acquired by the third processing circuit 15 based on the buffer indexes added to the respective lookup messages M. The CPU 17 executes a read operation on the NAND memory 20 based on the aligned multiple lookup messages M.

[0190] Therefore, by using multiple LUT engines 14, the memory controller 10 can efficiently execute processes required for referencing and updating the LUT 50, which have a high computational cost. Furthermore, even if the processing order of multiple lookup messages M issued in logical address order is shuffled by passing through multiple LUT engines 14, the processing order of the multiple lookup messages M is returned to logical address order by the alignment circuit 16, so the memory controller 10 can efficiently acquire each cluster data 40 to be read from the NAND memory 20. As a result, the read performance of the memory system 1 can be improved.

[0191] Moreover, according to the embodiment, each memory chip 21 constituting the NAND memory 20 includes a page register 212 and a memory cell array 211 configured to store user data DAT. In a read operation, the memory chip 21 is configured to execute a sense operation and output at least one cluster data 40 of the page data stored in the page register 212 by the sense operation to the memory controller 10. The sense operation is an operation of transferring page data of the user data DAT stored in the memory cell array 211 that is larger than the cluster data 40 from the memory cell array 211 to the page register 212. The CPU 17 executes a read operation to cause the memory chip 21 to output two or more cluster data 40 from the page register 212 per sense operation.

[0192] Therefore, the memory controller 10 can efficiently acquire each cluster data 40 to be read from the NAND memory 20.

[0193] According to the embodiment, the memory system 1 further includes a write buffer 32 configured to store user data DAT received from the host 2 until the user data DAT is stored in the NAND memory 20. Each LUT segment 51 stored in the LUT cache 31 associates a logical address with a location in the NAND memory 20 or the write buffer 32 where the user data DAT is stored, in units of cluster data 40. The third processing circuit 15 transmits, to the alignment circuit 16, a lookup message M to which a physical address has been added, among a plurality of lookup messages M each to which a sequential read flag has been added, acquired from the plurality of LUT engines 14, without transmitting the lookup message M to the first processing circuit 12. The third processing circuit 15 also transmits, to the first processing circuit 12 and the alignment circuit 16, a lookup message M to which a write buffer address has been added, among a plurality of lookup messages M each to which a sequential read flag has been added, acquired from the plurality of LUT engines 14, The CPU 17 executes a read operation based only on a lookup message to which a physical address, not a write buffer address, is added, among the multiple lookup messages M sorted in logical address order by the sorting circuit 16. The first processing circuit 12 transmits to the host 2 the data read from the NAND memory 20 by the read operation and the data stored at the location indicated by the write buffer address added to the lookup message M received from the third processing circuit 15.

[0194] Therefore, in the case of a sequential read, the CPU 17 can obtain all lookup messages M related to the sequential read from the alignment circuit 16 in the order of logical addresses, regardless of whether or not there is a hit in the write buffer 32.

[0195] Furthermore, according to the embodiment, the third processing circuit 15 does not add a dummy flag to a lookup message M to which a physical address has been added among the multiple lookup messages M acquired from the multiple LUT engines 14, but adds a dummy flag to a lookup message M to which a write buffer address has been added among the multiple lookup messages M acquired from the multiple LUT engines 14. The CPU 17 identifies whether or not a lookup message M to which a physical address has been added among the multiple lookup messages M acquired from the alignment circuit 16 is a lookup message M to which a physical address has been added, based on the presence or absence of a dummy flag.

[0196] Therefore, the CPU 17 can easily identify lookup messages M to be discarded, that is, lookup messages M not to be used in the read operation, from among all lookup messages M acquired from the alignment circuit 16 in logical address order.

[0197] Moreover, according to the embodiment, the alignment circuit 16 includes a plurality of message buffers 163, each of which is assigned a buffer index. The alignment circuit 16 stores a plurality of lookup messages M in a message buffer 163 indicated by a buffer index assigned to each of the plurality of lookup messages M among the plurality of message buffers 163. The CPU 17 retrieves the plurality of lookup messages M from the plurality of message buffers 163 in the order of the buffer indexes assigned to each message buffer 163.

[0198] Therefore, the CPU 17 can obtain a plurality of lookup messages M from the alignment circuit 16 in the order of logical addresses.

[0199] Furthermore, each of the multiple LUT engines 14 is connected to the second processing circuit via multiple queues. The LUT 50 is divided into multiple LUT segments 51, each of which is assigned a segment index. The LUT cache 31 is configured to cache the LUT 50 in units of LUT segments 51. The second processing circuit 13 receives multiple lookup messages M in the order in which they were issued. If the LUT segment 51 required to identify the position of the cluster data 40 to be read corresponding to the received lookup message M is cached in the LUT cache 31, the second processing circuit 13 transmits the lookup message M to one of the multiple LUT engines 14 via a queue corresponding to the segment index assigned to the LUT segment 51. If the LUT segment 51 required to identify the position of the cluster data 40 to be read corresponding to the received lookup message M is not cached in the LUT cache 31, the second processing circuit 13 refills the LUT cache 31 and then transmits the lookup message M to one of the multiple LUT engines 14 via a queue corresponding to the segment index assigned to the LUT segment 51.

[0200] Therefore, even if the second processing circuit 13 has performed a refill for one lookup message M, it is possible to process any lookup message M that is subsequently received without waiting for the refill to be completed.

[0201] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0202] 1 Memory system, 2 Host, 10 Memory controller, 11 SRAM, 12 First processing circuit, 13 Second processing circuit, 14, 14e, 14o LUT engine, 15 Third processing circuit, 16 Alignment circuit, 17 CPU, 20 NAND memory, 21, 21-0, 21-1, 21-2, 21-3 Memory chip, 31 LUT cache, 32 Write buffer, 33 Read buffer, 40 Cluster data, 50 LUT, 51 LUT segment, 60 Buffer management bitmap, 70 Work area, 71 Queue area, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111 Queue, 131 Write pointer, 132 Read pointer, 161 Message buffer group, 163 Message buffer, 211 Memory cell array, 212 Page register, DAT User data, M, Ma, Mb, Mc, Md, Me, Mf lookup messages.

Claims

1. 1. A memory system connectable to a host, comprising: a first non-volatile memory configured to store data received from the host; a second memory configured to store management information that associates a logical address used by the host with a location in the first memory where the data is stored for each first data unit; a memory controller including a first circuit, a second circuit, a plurality of third circuits, a fourth circuit, a fifth circuit, and a sixth circuit; Equipped with the memory controller receives a read request from the host specifying a range of consecutive logical addresses each having a size equal to a plurality of the first data units; the first circuit is configured to issue, in response to receiving the read request, a plurality of first sub-commands requesting reading of data of all first data units included in the logical address range, each of the first sub-commands requesting reading of data of one first data unit, in order of the logical addresses; the second circuit is configured to assign a first serial number corresponding to an issuing order to each of the plurality of first sub-commands, and to distribute the plurality of first sub-commands each assigned with the first serial number to the plurality of third circuits; each of the plurality of third circuits is configured to identify a storage location of a first data unit related to a first sub-command allocated to itself among the plurality of first sub-commands by referring to the management information, and to add location information indicating the identified storage location to the first sub-command; the fourth circuit is configured to acquire the plurality of first sub-commands, each having the position information added thereto, from the plurality of third circuits; the fifth circuit is configured to arrange the plurality of first sub-commands acquired by the fourth circuit in an order based on the first serial numbers; the sixth circuit is configured to execute a read operation on the first memory based on the aligned first sub-commands. Memory system.

2. the first memory comprises a first buffer and a memory cell array configured to store the data, and is configured to perform a sense operation in the read operation to transfer a second data unit, which is larger than the first data unit, of the data stored in the memory cell array from the memory cell array to the first buffer, and to output at least one first data unit of data of the second data unit stored in the first buffer by the sense operation to the memory controller; the sixth circuit is configured to execute the read operation to cause the first memory to output two or more of the first data units from the first buffer per one sense operation.

10. The memory system of claim 1.

3. a third memory configured to store the data received from the host until the data is stored in the first memory; the management information associates a logical address with a location in the first memory or the third memory where the data is stored for each first data unit; The fourth circuit is a second sub-command among the plurality of first sub-commands acquired from the third circuit is transmitted to the fifth circuit without being transmitted to the first circuit, the second sub-command being a first sub-command to which first position information indicating a position in the first memory is added; a third sub-command among the plurality of first sub-commands acquired from the third circuit is transmitted to the first circuit and the fifth circuit, the third sub-command being a first sub-command to which second position information indicating a position within the third memory is added; the sixth circuit executes the read operation based only on the second sub-commands among the aligned first sub-commands; the first circuit is configured to transmit to the host the first data read from the first memory by the read operation and the second data stored in the third memory at a location indicated by the second location information added to the third subcommand.

3. The memory system according to claim 1.

4. the fourth circuit is configured not to add a first flag to a first sub-command corresponding to the second sub-command among the plurality of first sub-commands acquired from the plurality of third circuits, and to add the first flag to a first sub-command corresponding to the third sub-command among the plurality of first sub-commands acquired from the plurality of third circuits; the sixth circuit identifies a first sub-command corresponding to the second sub-command from among the aligned first sub-commands based on the presence or absence of the first flag; 4. The memory system of claim 3.

5. the fifth circuit includes a plurality of second buffers each assigned with a second serial number, and stores the plurality of first sub-commands acquired by the fourth circuit in a second buffer assigned with the second serial number having the same value as the first serial number assigned to each of the plurality of first sub-commands among the plurality of second buffers; the sixth circuit extracts the first sub-commands from the second buffers in the order of the second serial numbers; 5. The memory system according to claim 3.

6. each of the plurality of third circuits is connected to the second circuit via a plurality of queues; the management information is divided into a plurality of management information segments, each of which is assigned a third serial number; the second memory is a cache memory configured to cache the management information in units of management information segments, The second circuit is receiving the plurality of first sub-commands in the order of issuance; If a first management information segment, which is a management information segment required to identify the location of data of a first data unit related to one of the received plurality of first subcommands, is cached in the cache memory, transmitting the one first subcommand to one of the plurality of third circuits via a queue corresponding to the third serial number assigned to the first management information segment among the plurality of queues, If the first management information segment is not cached in the cache memory, refilling the first management information segment, and then transmitting the one first sub-command to the one of the plurality of third circuits via a queue corresponding to the third serial number assigned to the first management information segment among the plurality of queues.

6. The memory system according to claim 1.

7. A method for controlling a memory system including: a non-volatile first memory configured to store data received from a host; and a second memory configured to store management information that associates a logical address used by the host with a location in the first memory where the data is stored for each first data unit, the method comprising: receiving a read request from the host specifying a range of consecutive logical addresses each having a size of a plurality of first data units; In response to receiving the read request, issuing a plurality of first sub-commands requesting reading of data of all first data units included in the logical address range, each of the first sub-commands requesting reading of data of one first data unit, in order of the logical addresses; assigning a first serial number corresponding to the order of issuance to each of the plurality of first sub-commands; specifying storage locations of first data units associated with each of the plurality of first sub-commands by referencing the management information, and adding location information indicating the specified storage locations to the first sub-commands, by a plurality of engines sharing the task; arranging the plurality of first sub-commands, each having the position information added thereto, in order based on the first serial numbers; performing a read operation on the first memory based on the aligned first sub-commands; A method comprising:

Images