Driving circuit and display device

Abstract

[Problem] To provide a drive circuit and a display device in which writing deficiency to a signal line does not occur. [Solution] A drive circuit is provided with a grayscale voltage generating unit that generates a plurality of grayscale voltages that can be supplied to a signal line, and a voltage selector that selects whether to supply, out of the plurality of grayscale voltages, a grayscale voltage of a same voltage level as an assumed grayscale voltage to the signal line, or to supply a grayscale voltage that approaches the assumed grayscale voltage to the signal line.

Description

[Technical Field]

[0001] The present disclosure relates to a drive circuit and a display device. [Background technology]

[0002] Projection display devices using LCOS (Liquid Crystal On Silicon, registered trademark) technology have been proposed (see Patent Document 1). Display devices using LCOS technology include three-panel display devices using three LCOS devices, as well as single-panel display devices using one LCOS device. Single-panel display devices have the advantage of being simpler in configuration than three-panel display devices. Single-panel display devices sometimes employ a driving method called color sequential driving, which displays multiple color images sequentially in a time-division manner.

[0003] In color sequential driving, one frame is divided into multiple subframes for each color. When driving high-resolution display devices such as 4K or 8K, a high-resolution display can be achieved by dividing one color into multiple low-resolution subframes and displaying them in sequence. Therefore, to achieve high-resolution display on a single-panel display device using LCOS, it is necessary to increase the number of subframes and drive each subframe at high speed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-53239 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when attempting to drive a single-panel display device at high speed, insufficient writing occurs in the signal lines within each subframe, resulting in a deterioration in image quality.

[0006] Therefore, the present disclosure provides a drive circuit and a display device that prevent insufficient writing to signal lines. [Means for solving the problem]

[0007] In order to solve the above problem, according to the present disclosure, a grayscale voltage generating unit that generates a plurality of grayscale voltages that can be supplied to a signal line; and a voltage selector that selects, from the plurality of gradation voltages, whether to supply a gradation voltage having the same voltage level as an expected gradation voltage to the signal line, or a gradation voltage close to the expected gradation voltage to the signal line.

[0008] A plurality of the signal lines are arranged at intervals in a first direction, The voltage selector may supply the gradation voltage equal to the expected gradation voltage to one of two signal lines arranged in a first direction, and may supply the gradation voltage different from the expected gradation voltage to the other signal line.

[0009] The voltage selector may supply a gradation voltage having the same voltage level as the expected gradation voltage to a signal line during one of two consecutive frame periods, and a gradation voltage close to the expected gradation voltage during the other frame period.

[0010] The voltage selector may select, from the plurality of gradation voltages, whether to supply a gradation voltage having the same voltage level as an expected gradation voltage to the signal line, or to switch between two or more gradation voltages close to the expected gradation voltage and supply them to the signal line.

[0011] The two or more gray scale voltages close to the assumed gray scale voltage may include a gray scale voltage having a voltage level higher than the assumed gray scale voltage and a gray scale voltage having a voltage level lower than the assumed gray scale voltage.

[0012] The voltage selector may select whether to continuously supply the same level of gray scale voltage to the signal line within one horizontal line period, or to switch between the two or more gray scale voltages and supply them to the signal line within the one horizontal line period.

[0013] The display device may further include a voltage combiner that generates a voltage by combining the two or more grayscale voltages that are switched and supplied within one horizontal line period, and supplies the voltage to the corresponding signal line.

[0014] The voltage combiner an amplifier connected to the signal line and amplifying the voltage of the signal line; a first capacitor connected in parallel between an input node of the amplifier and an output node of the voltage selector, and a first switch that switches between short-circuiting both ends of the first capacitor and not short-circuiting; The voltage selector may select a first gradation voltage with both ends of the first capacitor shorted by the first switch within one horizontal line period, and then select a second gradation voltage with both ends of the first capacitor released from the short circuit by the first switch.

[0015] The amplifier may further include a second capacitor connected between the input node of the amplifier and a reference voltage node.

[0016] a plurality of the voltage selectors are provided for each of the signal lines; The liquid crystal display device may further include a voltage switcher that switches between the plurality of grayscale voltages selected by the plurality of voltage selectors and supplies the selected grayscale voltages to the signal lines.

[0017] The voltage switch may supply different grayscale voltages selected by the voltage selector to the corresponding signal lines in one and the other of two consecutive frame periods.

[0018] the gradation voltage generation unit includes a ladder resistor having a plurality of output nodes for outputting the plurality of gradation voltages obtained by resistively dividing two or more reference voltages; The voltage selector may include a plurality of second switches that switch between connecting and disconnecting the plurality of output nodes of the ladder resistor and the signal line based on a grayscale signal.

[0019] In another aspect of the present disclosure, a pixel having a luminance modulation element whose luminance is modulated according to a voltage of a signal line; a signal line for supplying a gradation voltage to the pixel; a drive circuit for generating the gradation voltage; The drive circuit a grayscale voltage generating unit that generates a plurality of grayscale voltages that can be supplied to the signal lines; and a voltage selector that selects, from the plurality of gradation voltages, whether to supply a gradation voltage having the same voltage level as an expected gradation voltage to the signal line, or a gradation voltage close to the expected gradation voltage to the signal line.

[0020] a pixel array unit having a plurality of the pixels arranged in a first direction and a second direction; A plurality of the signal lines are arranged at intervals in the first direction, The voltage selector may supply different grayscale voltages to two of the signal lines adjacent to each other in the first direction.

[0021] The voltage selector may supply the gray scale voltage equal to the expected gray scale voltage to one of two signal lines adjacent in a first direction, and supply the gray scale voltage different from the expected gray scale voltage to the other signal line.

[0022] The voltage selector may switch between two or more of the gray scale voltages different from the assumed gray scale voltage and supply them to the other of the two signal lines within one horizontal line period.

[0023] The pixel array section may include a voltage combiner that generates a voltage by combining the two or more grayscale voltages that are switched and supplied within one horizontal line period, and supplies the voltage to the corresponding signal line.

[0024] The voltage combiner may be provided within the pixel.

[0025] The voltage combiner a third switch and a fourth switch connected in series between the signal line and the luminance modulation element; a third capacitor connected between the signal line and a connection node between the third switch and the fourth switch; The fourth capacitor may have one end connected between the fourth switch and the luminance modulation element and the other end connected to a reference voltage node.

[0026] The voltage combiner a fifth switch and a sixth switch connected in series between the signal line and the luminance modulation element; a seventh switch connected between the signal line and a connection node between the fifth switch and the sixth switch; a fifth capacitor connected between the connection node and a reference voltage node; and a sixth capacitor connected between the connection node and the reference voltage node. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a diagram illustrating the principle of a single-panel display device. [Figure 2] FIG. 2 is a diagram schematically showing a plurality of subframes within one frame. [Figure 3] FIG. 2 is a waveform diagram showing frame and subframe timing. [Figure 4] FIG. 1 is a block diagram of a display system including a display device and a driver IC according to an embodiment. [Figure 5] FIG. 10 is a block diagram of a display system including a driving IC, a source driver IC, and a display device according to a modified example. [Figure 6A] FIG. 2 is a block diagram showing the internal configuration of a source driver according to the first embodiment. [Figure 6B] FIG. 10 is a circuit diagram showing a modified example of a ladder resistor. [Figure 7A] 6B is a diagram for explaining a procedure for writing grayscale voltages to signal lines in even-numbered columns in FIG. 6A during one horizontal line period. [Figure 7B] Continuation of Figure 7A. [Figure 7C] Figure continues from Figure 7B. [Figure 8]FIG. 6B is a timing diagram of the source driver of FIG. 6A. [Figure 9] FIG. 10 is a diagram showing an example in which the driving method of the grayscale voltages of two adjacent signal lines is reversed for each subframe. [Figure 10] FIG. 6B is a block diagram of a modified example of the source driver of FIG. 6A. [Figure 11] 11 is a diagram showing voltage changes at input and output nodes of the source amplifier of FIG. 10; [Figure 12] FIG. 10 is a circuit diagram showing the main parts of a source driver and a pixel array unit according to a second embodiment. [Figure 13] FIG. 13 is a timing diagram of the display device of FIG. [Figure 14] FIG. 13 is a block diagram of a modified example of the pixel array unit in FIG. [Figure 15] FIG. 15 is a timing diagram for the display device of FIG. [Figure 16] FIG. 10 is a circuit diagram showing the internal configuration of a source driver in a display device according to a third embodiment. [Figure 17] FIG. 17 is a timing diagram of the source driver of FIG. [Figure 18] 10A and 10B are diagrams for explaining combination candidates of signal lines for switching the type of gray scale voltage; DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments of a driving circuit and a display device will be described with reference to the drawings. The following description will focus on the main components of the driving circuit and the display device, but the driving circuit and the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] 1 is a diagram illustrating the principle of a single-panel display device 1. The display device 1 in FIG.

[0030] The light source 2 emits light of each of the RGB color components in sequence in a time-division manner. The light emitted from the light source 2 passes through an optical system 3 and enters the light modulation element 4. The light modulation element 4 has, for example, an LCOS chip. The light modulation element 4 drives a liquid crystal element in synchronization with the color of the light emitted from the light source 2. As a result, the display device 1 of FIG. 1 projects image light of each of the RGB color components in a time-division manner. The projected image light is combined on the screen to generate a color image. The light modulation element 4 controls the rotation amount of the liquid crystal in accordance with the voltage of the signal line, thereby controlling the amount of reflection and transmission of the incident light. Alternatively, the light modulation element 4 performs brightness modulation in accordance with the voltage of the signal line. In this specification, the light modulation element 4 may also be referred to as a brightness modulation element.

[0031] FIG. 2 is a diagram schematically showing multiple sub-frames Sub_FR within one frame FR. The image light of each sub-frame Sub_FR in FIG. 2 is projected in turn from the display device 1 and combined on the screen 5 to obtain one frame image (color image). Although each sub-frame Sub_FR is projected onto the screen 5 at a different timing, the human eye perceives a color image that is a combination of multiple sub-frames Sub_FR due to the persistence of images. FIG. 2 shows an example in which RGB sub-frames are displayed in turn, but sub-frames of colors other than RGB (such as white) may also be provided.

[0032] Figure 3 is a waveform diagram showing the timing of frames FR and subframes Sub_FR. Each frame FR is made up of m subframes Sub_FR (m is an integer of 2 or greater). Within one subframe Sub_FR period, n lines (n is an integer of 2 or greater) are driven, and p signal lines (p is an integer of 2 or greater) are driven on each line. Furthermore, m subframes Sub_FR are driven within one frame period.

[0033] FIG. 4 is a block diagram of a display system 10 including a display device 1 and a driving IC 6 according to one embodiment. The display device 1 is formed on an insulating substrate such as a glass substrate. The driving IC 6 may be mounted on the same insulating substrate as the display device 1, or may be mounted on a substrate separate from the display device 1 and may exchange various signals with the display device 1 using an FPC (Flexible Printed Circuit board) or the like. The driving IC 6 has a video signal generator 6a and a frame memory 6b. The video signal generator 6a generates a digital video signal. The frame memory 6b has a frame memory 6b that stores, for example, one frame FR worth of video signal. The driving IC 6 supplies the video signal and a control signal to the display device 1. The control signal includes a clock signal, and the display device 1 controls the display timing based on this clock signal.

[0034] The display device 1 includes an IF unit 11, a signal processing unit 12, a gamma voltage generating circuit 13, a pixel array unit 14, a source driver 15, a gate driver 16, and a timing controller 17.

[0035] The video signal output from the driving IC 6 is input to the signal processing unit 12 via the IF unit 11. The signal processing unit 12 determines a gradation voltage based on the video signal. More specifically, the signal processing unit 12 generates a gradation signal consisting of multiple bits according to the gradation voltage.

[0036] The gamma voltage generation circuit 13 has an amplifier 18 and a ladder resistor 19, as shown in FIG. 6A (described later). The amplifier 18 generates a reference voltage to be supplied to the ladder resistor 19. The ladder resistor 19 has a plurality of resistors R connected in series between two reference voltage nodes. The ladder resistor 19 outputs a plurality of gamma voltages from between the plurality of resistors R. The plurality of gamma voltages are voltages written to each signal line. The plurality of gamma voltages are input to the source driver 15.

[0037] The pixel array section 14 has a plurality of pixels 20 arranged in a matrix in the horizontal and vertical directions, a plurality of signal lines Sig each extending vertically and spaced apart in the horizontal direction, and a plurality of gate lines Gate each extending horizontally and spaced apart in the vertical direction.

[0038] The source driver 15 drives a plurality of signal lines Sig. The source driver 15 selects one of a plurality of gamma voltages generated by the gamma voltage generation circuit 13 based on a grayscale signal representing a grayscale voltage output from the signal processing unit 12. The source driver 15 has a decoder for each signal line. Each decoder turns on one of a plurality of switches based on a grayscale signal consisting of multiple bits from the signal processing unit 12. The plurality of switches are provided corresponding to a plurality of gamma voltages, and when one switch is turned on, the gamma voltage connected to the turned-on switch is supplied to the corresponding signal line. In this specification, the decoder may be referred to as a voltage selector, as will be described later.

[0039] The gate driver 16 drives the gate lines Gate in turn based on the control signals output from the driving IC 6. In this way, display driving is performed for each horizontal line.

[0040] Based on the clock signal from the driver IC 6, the timing controller 17 generates a clock signal for synchronously operating the source driver 15 and the gate driver 16.

[0041] At least part of the internal configuration of the display device 1 in Fig. 4 can be modified. Fig. 5 is a block diagram of a display system 10a according to one modification, which includes a drive IC 6, a source driver IC 30, and a display device 1a. In the display device 1a in Fig. 5, the source driver 15 is integrated into an IC and provided outside the display device 1.

[0042] The display system 10a in Fig. 5 includes a display device 1a, a driving IC 6, and a source driver IC 30. The internal configuration of the driving IC 6 is the same as that in Fig. 4. Note that multiple source driver ICs 30 may drive signal lines in the pixel array section 14.

[0043] The display device 1a in Fig. 5 includes a pixel array unit 14, a gate driver 16, and a timing controller 17a. The source driver IC 30 includes an IF unit 11, a signal processing unit 12, a gamma voltage generation circuit 13, a source driver 15, and a timing controller 17. A clock signal output from the driving IC 6 is input to the timing controller 17 in the source driver IC 30 via the IF unit 11. The timing controller 17 supplies the clock signal to the timing controller 17a in the display device 1. As a result, the driving IC 6, the source driver IC 30, and the display device 1 operate in synchronization with a common clock signal.

[0044] The display device 1 according to this embodiment is characterized by the internal configuration of the source driver 15. The source driver 15 according to this embodiment has a function of driving the signal lines at high speed without causing insufficient writing to the signal lines.

[0045] (First embodiment) 6A is a block diagram showing the internal configuration of a source driver 15 according to the first embodiment. The source driver 15 in FIG.

[0046] The grayscale voltage generator 21 generates a plurality of grayscale voltages that can be supplied to the signal lines. The grayscale voltage generator 21 corresponds to the gamma voltage generator circuit 13 in Fig. 4 and is configured using a plurality of amplifiers 18 that each output a different reference voltage, and ladder resistors 19 connected between the output nodes of two amplifiers 18 that are adjacent in the vertical direction.

[0047] In the example of FIG. 6A , the ladder resistor 19 is configured by connecting six resistors R in series between reference voltage nodes output from two amplifiers 18. The ladder resistor 19 has two output nodes that output two reference voltages, as well as five output nodes connected between the stages of the six series-connected resistors R. The gradation voltage generation unit 21 in FIG. 6A outputs a gradation voltage V1 from an output node between the third resistor R and the fourth resistor R from the top of the ladder resistor 19, a gradation voltage V2A from an output node between the second resistor R and the third resistor R from the top, and a gradation voltage V2B from an output node between the fourth resistor R and the fifth resistor R from the top. The gradation voltage generation unit 21 in FIG. 6A also outputs a gradation voltage V3A from an output node between the first resistor R and the second resistor R from the top of the ladder resistor 19, and a gradation voltage V3B from an output node between the fifth resistor R and the sixth resistor R from the top.

[0048] It should be noted that there is no particular limitation on the number of resistors R connected in series to form the ladder resistor 19. In this specification, the wiring connecting the output nodes between the resistors R of the ladder resistor 19 is referred to as a gradation voltage line.

[0049] Although FIG. 6A illustrates only one ladder resistor 19 in which multiple resistors R are connected in series, it is also possible to add more amplifiers 18 and connect the ladder resistors 19 between them. The number and resistance values ​​of the ladder resistors between the amplifiers may vary for each amplifier. For example, FIG. 6B is a circuit diagram showing a modified version of the ladder resistor 19. FIG. 6B illustrates an example in which three amplifiers 18 are connected to the ladder resistor 19, different reference voltages are output from the output nodes of each amplifier 18, and the number of resistors R connected in series between the output nodes of each amplifier 18 varies for each combination of two amplifiers 18. In this way, multiple ladder resistors 19 may be connected in series. Each time one ladder resistor 19 is added, one amplifier 18 must be added.

[0050] The voltage selector 22 selects, from among a plurality of gray scale voltages, whether to supply a gray scale voltage having the same voltage level as the expected gray scale voltage to the signal line, or a gray scale voltage close to the expected gray scale voltage to the signal line. For example, the voltage selector supplies a gray scale voltage equal to the expected gray scale voltage to one of two signal lines adjacent in the first direction, and a gray scale voltage different from the expected gray scale voltage to the other signal line.

[0051] More specifically, the voltage selector 22 may select from a plurality of gray scale voltages whether to supply a gray scale voltage having the same voltage level as the expected gray scale voltage to the signal line, or whether to switch between two or more gray scale voltages close to the expected gray scale voltage and supply them to the signal line. The two or more gray scale voltages close to the expected gray scale voltage include a gray scale voltage having a voltage level higher than the expected gray scale voltage and a gray scale voltage having a voltage level lower than the expected gray scale voltage. The voltage selector 22 may also select whether to continuously supply a gray scale voltage of the same level to the signal line within one horizontal line period, or whether to switch between two or more gray scale voltages and supply them to the signal line within one horizontal line period. The voltage selector 22 is composed of a decoder 24.

[0052] The decoder 24 in Fig. 6A has seven switches (second switches) SW1 to SW7 connected to each signal line. The decoder 24 in Fig. 6A turns on one of the switches SW1 to SW7 based on the grayscale signal from the driver IC 6. Of the seven switches SW1 to SW7, three switches SW4, SW3, and SW5 select one of the grayscale voltages V1, V2A, and V2B output from the ladder resistor 19. When the resistance R values ​​of the multiple resistors R connected in series in the ladder resistor 19 are equal, V1 = (V2A + V2B) / 2.

[0053] When supplying the same gradation voltage to two adjacent signal lines, the decoder 24 of this embodiment supplies one of the two with gradation voltage V1, which has the same voltage level as the expected gradation voltage, and supplies the remaining line with gradation voltages V2A and V2B, which are close to the expected gradation voltage, by switching between them within one horizontal line period. This makes it possible to reduce the number of signal lines driven by one gradation voltage line, and to alleviate insufficient writing to the signal lines.

[0054] A corresponding source amplifier 23 is connected to each signal line. One end nodes of switches SW1 to SW7 in the decoder 24 are all connected to the non-inverting input node of the source amplifier 23. A capacitor (first capacitor) C_mix and a switch (first switch) SW11 are connected in parallel between these one end nodes and the non-inverting input node of the source amplifier 23. The capacitor C_mix is ​​also called a storage capacitor. The inverting input node of the source amplifier 23 is short-circuited to the output node of the source amplifier 23. The output node of the source amplifier 23 is the output node of the source driver 15, and is connected to the signal line of the pixel array section 14.

[0055] The decoder 24 in the source driver 15 in FIG. 6A switches between two or more gradation voltages during one horizontal line period and supplies them to at least some of the signal lines. The decoder 24 may also switch between the types of gradation voltages supplied to the same signal line between one and the other of two consecutive sub-frame Sub_FR periods. More specifically, the decoder 24 supplies a gradation voltage equal to an expected gradation voltage to one of two signal lines adjacent in the first direction, and a gradation voltage different from the expected gradation voltage to the other of the two signal lines. The decoder 24 may switch between two or more gradation voltages different from the expected gradation voltage during one horizontal line period and supply them to the other of the two signal lines.

[0056] 6A, the switch SW4 is turned on to supply the gradation voltage V1 to the signal lines of the odd-numbered columns, and the switch SW3 is turned on to supply the gradation voltage V2A to the signal lines of the even-numbered columns within one horizontal line period, and then the switch SW5 is turned on to supply the gradation voltage V2B to the signal lines of the even-numbered columns.

[0057] More specifically, when driving the signal lines of odd-numbered columns, the decoder 24 turns on the switch SW4 while keeping the switch SW11 on. This causes the gradation voltage V1 to be supplied to one end of the capacitor (storage capacitance) C_mix. Next, by turning off the switch SW11 while keeping the switch SW4 on, the gradation voltage V1 can be continuously written to the corresponding signal line for one horizontal line period.

[0058] 7A to 7C are diagrams illustrating the procedure for writing gradation voltages V2A and V2B to the signal lines of the even-numbered columns in FIG. 6A during one horizontal line period. First, as shown in FIG. 7A, with switch SW11 turned on, decoder 24 turns on switch SW3 to supply gradation voltage V2A to one end of capacitor (storage capacitance) C_mix. Since switch SW11 is on, this voltage is also supplied to the non-inverting input node of source amplifier 23. As a result, the nodes on both ends of capacitor (storage capacitance) C_mix become gradation voltage V2A, which is the same voltage level. At this time, the voltages on one end of capacitor (storage capacitance) C_mix and parasitic capacitance C_amp of source amplifier 23 become gradation voltage V2A.

[0059] Next, as shown in FIG. 7B, with switch SW11 turned off, decoder 24 turns on switch SW4 to supply grayscale voltage V2B to one end of capacitor (storage capacitance) C_mix. This causes the voltage at the other end of capacitor (storage capacitance) C_mix to increase by Δ, where Δ=V2B-V2A.

[0060] At this time, if the capacitor (storage capacitance) C_mix and the parasitic capacitance C_amp of the source amplifier 23 have the same capacitance, the gray scale voltage input to the source amplifier 23 is expressed by the following equation (1). V2A+Δ / 2=(V2A+V2B) / 2 …(1)

[0061] The voltage shown in equation (1) is a voltage of approximately the same voltage level as the gradation voltage V1, and the odd-numbered signal lines and the even-numbered signal lines can be set to approximately the same voltage level while using separate gradation voltage lines.

[0062] In this way, the source driver 15 in Fig. 6A writes a specific grayscale voltage to the odd-numbered signal lines continuously for one horizontal line period, and writes a composite voltage to the even-numbered signal lines by switching between two types of grayscale voltages within one horizontal line period. The source amplifier 23, capacitor (storage capacitance) C_mix, and switch SW11 in Fig. 6A form a voltage combiner. The voltage combiner generates a voltage by combining two or more grayscale voltages that have been switched and supplied within one horizontal line period, and supplies the voltage to the corresponding signal line.

[0063] It is also possible to provide a mode in which the gradation voltage selected by the decoder 24 is continuously supplied to all signal lines for one horizontal line period. In this case, the switch SW11 may be kept on for one horizontal line period.

[0064] Figure 8 is a timing diagram of the source driver 15 in Figure 6A. Figure 8 shows the drive timing of two horizontally adjacent signal lines Sig_1 and Sig_2. In Figure 8, the gradation signal corresponding to signal line Sig_1 is Data_1, and the gradation signal corresponding to signal line Sig_2 is Data_2. Figure 8 also shows the logic of switch SW11 and the data held by capacitor (storage capacitance) C_mix_1 of signal line Sig_1 and capacitor (storage capacitance) C_mix_2 of signal line Sig_2.

[0065] Times t1 to t3 in FIG. 8 correspond to one horizontal line period of the first line. The decoder 24 corresponding to the signal line Sig_1 continuously selects a grayscale voltage corresponding to the grayscale signal D(1)1 during one horizontal line period (times t1 to t3). A charge corresponding to this voltage is held in the capacitor (storage capacitance) C_mix_1. The decoder 24 corresponding to the signal line Sig_2 selects a grayscale voltage V2A corresponding to the grayscale signal D(1)2A during the first half of one horizontal line period (times t1 to t2), and selects a grayscale voltage V2B corresponding to the grayscale signal D(1)2B during the second half of the horizontal line period (times t2 to t3). The capacitor (storage capacitance) C_mix holds a charge corresponding to the grayscale signal D(1)2A during the first half of the horizontal line period (times t1 to t2), and holds a charge corresponding to the grayscale signal D(1)2B during the second half of the horizontal line period (times t2 to t3).

[0066] As a result, when the grayscale signals of the signal lines Sig_1 and Sig_2 are the same, both signal lines are maintained at the same voltage level, V1. However, the grayscale voltage line that supplies the grayscale voltage V1 is connected to the signal line Sig_1, and the grayscale voltage line that supplies the grayscale voltage V2A and the grayscale voltage line that supplies the grayscale voltage V2B are alternately connected to the signal line Sig_2. This reduces the load capacitance of each grayscale voltage line, and prevents insufficient writing to the signal lines Sig_1 and Sig_2.

[0067] The above operation is repeated for each horizontal line. Times t3 to t5 indicate the drive timing for the second horizontal line, times t5 to t6 for the third horizontal line, times tn-1 to tn for the (n-1)th horizontal line, and times tn to tn+1 for the nth horizontal line. The timing diagram in Fig. 8 shows an example in which all signal lines are simultaneously driven for each horizontal line within one sub-frame Sub_FR. After the display of one sub-frame Sub_FR is completed, the source driver 15 in Fig. 6A simultaneously drives all signal lines for each horizontal line for the next sub-frame Sub_FR with the same timing as in Fig. 8.

[0068] 6A, for the signal lines of odd-numbered columns, the source driver 15 continuously supplies the same gray scale voltage to the signal lines for one horizontal line period without switching the gray scale voltage, whereas for the signal lines of even-numbered columns, the gray scale voltage is switched during one horizontal line period, and a composite voltage of the two gray scale voltages is supplied to the signal lines. Ideally, the gray scale voltage V1 and the gray scale voltage (V2A+V2B) / 2 should be at the same voltage level, but variations in the resistance R of each resistor R in the ladder resistor 19 and variations in the parasitic capacitance of each gray scale voltage line may cause a discrepancy between the gray scale voltage V1 and the gray scale voltage (V2A+V2B) / 2.

[0069] Even if the gradation voltages are the same, if there is a discrepancy in the signal line voltages, color unevenness occurs and image quality deteriorates. Therefore, the driving method of the gradation voltages of two adjacent signal lines Sig_1 and Sig_2 may be reversed for each frame FR or sub-frame Sub_FR.

[0070] Figure 9 shows an example in which the driving method of the gradation voltages of two adjacent signal lines is reversed for each sub-frame Sub_FR. The left side of Figure 9 is the same as Figure 6A, in which the gradation voltage V1, which is the expected gradation voltage, is continuously supplied to the signal line Sig_1 for one horizontal line period, and the signal line Sig_2 is supplied with two gradation voltages V2A and V2B, which are approximate to the expected gradation voltage, by switching between them during one horizontal line period.

[0071] After one subframe Sub_FR is displayed using the method on the left side of Fig. 9, the next subframe Sub_FR is displayed using the method on the right side of Fig. 9. On the right side of Fig. 9, contrary to the left side of Fig. 9, two gradation voltages V2A and V2B that approximate the expected gradation voltage are alternately supplied to the signal line Sig_1 during one horizontal line period, and the gradation voltage V1, which is the expected gradation voltage, is continuously supplied to the signal line Sig_2 during one horizontal line period.

[0072] In this way, in Figure 9, for each subframe Sub_FR, switching is performed between supplying a fixed gradation voltage to each signal line or supplying a composite voltage of two gradation voltages, so that variations in gradation voltage between two adjacent signal lines become less noticeable.

[0073] In the source driver 15 of FIG. 6A, the parasitic capacitance C_amp of the source amplifier 23 and the capacitor (storage capacitance) C_mix store electric charges according to the gray scale voltage, but an additional capacitor C_mix_ex may be provided.

[0074] Fig. 10 is a block diagram of a modified example of the source driver 15 of Fig. 6A. The source driver 15 of Fig. 10 has a capacitor (second capacitor) C_mix_ex connected between the non-inverting input node of the source amplifier 23 and the ground node. By providing this capacitor C_mix_ex, the voltage of the signal line can be adjusted. It is desirable that the combined capacitance of the capacitor C_mix_ex and the parasitic capacitance C_amp of the source amplifier 23 be equal to the capacitor (combined capacitance) C_mix.

[0075] Figure 11 is a diagram showing voltage changes at the input / output nodes of the source amplifier 23 of Figure 10. First, when the decoder 24 selects the gradation voltage V2A with the switch SW11 turned off, the voltage on one end of the capacitor (hold capacitance) C_mix and the non-inverting input node of the source amplifier 23 both become V2A. Thereafter, when the decoder 24 selects the gradation voltage V2B with the switch SW11 turned off, the voltage on one end of the capacitor (hold capacitance) C_mix becomes V2A+V2B. Therefore, if Δ=V2B-V2A, the output of the source amplifier 23 becomes V2A+Δ / 2=(V2A+V2B) / 2, as in equation (1).

[0076] 6A shows an example in which the decoder 24 selects one of the specific gradation voltages V1, V2A, and V2B from the ladder resistor 19, which is configured by connecting six resistors R in series. However, the decoder 24 may select other gradation voltages. For example, for the signal lines of even columns, as shown in FIG. 6A, a composite voltage may be generated using a gradation voltage V3A that is one level higher than the gradation voltage V2A and a gradation voltage V3B that is one level lower than the gradation voltage V3B. In this case, the composite voltage may be generated by switching among a total of four voltages, namely, the gradation voltages V3A, V2A, V2B, and V3B, within one horizontal line period. Alternatively, the composite voltage may be generated by switching among the gradation voltages V3A and V3B within one horizontal line period.

[0077] 6A, the method of driving the gradation voltage differs between the odd-numbered signal lines and the even-numbered signal lines, but the method of driving the gradation voltage of each of the n signal lines may be different for a unit of n signal lines (n is an integer greater than or equal to 3). For example, for a unit of three signal lines, an assumed gradation voltage may be continuously supplied to one of the signal lines for one horizontal line period, gradation voltages V2A and V2B may be switched between and supplied to the remaining one within one horizontal line period, and gradation voltages V3A and V3B may be switched between and supplied to the final signal line within one horizontal line period.

[0078] As described above, in the first embodiment, one of two adjacent signal lines is continuously supplied with a grayscale voltage having the same voltage level as the expected grayscale voltage for one horizontal line period, and the remaining signal line is supplied with multiple grayscale voltages close to the expected grayscale voltage, switching between them during one horizontal line period. This prevents multiple signal lines from being driven by only some of the grayscale voltage lines output from the ladder resistor 19, and allows each signal line to be driven in a distributed manner by each grayscale voltage line. This reduces the load capacitance of each grayscale voltage line, preventing insufficient writing to a signal line. This enables high-speed writing to each signal line, improving the image quality of the high-resolution display device 1.

[0079] (Second embodiment) The source driver 15 according to the first embodiment switches between multiple gradation voltages within one horizontal line period and supplies them to a signal line, and generates a composite voltage by combining the multiple gradation voltages using a capacitor (storage capacitance) C_mix connected to the source amplifier 23 and parasitic capacitance, and supplies the composite voltage to the signal line. However, the generation of the composite voltage may be performed by the pixel array unit 14 instead of the source driver 15.

[0080] The display device 1 according to the second embodiment has a block configuration similar to that of Fig. 4 or 5. The display device 1 according to the second embodiment differs from the first embodiment in part of the internal configuration of the source driver 15 and the pixel array unit 14 therein.

[0081] FIG. 12 is a circuit diagram showing essential parts of a source driver 15 and a pixel array unit 14 according to a second embodiment. The non-inverting input node of the amplifier 18 in the source driver 15 in FIG. 12 is not connected to the capacitor (storage capacitance) C_mix and switch SW11 shown in FIG. 6A. Furthermore, a signal line connected to the output node of the source driver 15 is connected to a corresponding pixel 20 in the pixel array unit 14. The pixel 20 includes switches SW21, SW22, and SW23, a capacitor C_mix, a capacitor C_st, a transfer gate 25, and a liquid crystal element 26. The switch SW23 switches whether or not the pixel 20 is connected to the signal line Sig. One end of the switch SW23 is connected to the signal line Sig, and the other end is connected to one end of the switch SW21 and one end of the capacitor C_mix. The other end of the switch SW21 and the other end of the capacitor C_mix are connected to one end of the switch SW22. The other end of the switch SW22 is connected to the input node of the transfer gate 25 and one end of the capacitor C_st. The other end of the capacitor C_st is grounded. The other end of the transfer gate 25 is connected to a liquid crystal element 26.

[0082] When the decoder 24 outputs the grayscale data of the row to be written to the signal line Sig, the switch SW23 corresponding to that row is turned on. This allows the grayscale data on the signal line Sig to be written to the pixels 20 of the corresponding row on a row-by-row basis. In this way, only the switch SW23 connected to the pixel 20 of the row to be written is turned on. The behavior of the switches SW21 to SW23 changes for each row.

[0083] Furthermore, for example, for the signal lines of odd-numbered columns, the decoder 24 continuously selects a grayscale voltage at the same voltage level as the expected grayscale voltage during one horizontal line period. This grayscale voltage is supplied to the corresponding signal line via the corresponding amplifier 18. By turning on both switches SW21 and SW23 in the pixel 20, a charge corresponding to the grayscale voltage supplied to the signal line is accumulated in the capacitor C_mix. Thereafter, by turning off the switch SW23 and turning on the switches SW21 and SW22, the accumulated charge in the capacitor C_mix is ​​transferred to the capacitor C_st, and the liquid crystal element 26 is driven by the charge accumulated in the capacitor C_st.

[0084] For the signal lines of even-numbered columns, the decoder 24 switches between two grayscale voltages V2A and V2B that approximate the expected grayscale voltage during one horizontal line period. While the grayscale voltage V2A is selected, for example, by turning on both switches SW21 and SW22, a charge corresponding to the grayscale voltage V2A is accumulated in the capacitor C_st. Next, when the switch selector selects the grayscale voltage V2B, by turning off the switch SW21 and turning on the switch SW22, a charge corresponding to the combined voltage of the grayscale voltages V2A and V2B is accumulated in the capacitor C_st.

[0085] FIG. 13 is a timing diagram of the display device 1 of FIG. 12. In FIG. 13, the capacitors C_st in the pixels 20 connected to the signal lines of the odd and even columns are denoted as C_st1 and C_st2, respectively. Times t1 to t3 represent one horizontal line period. During one horizontal line period from times t1 to t3, grayscale data D(1)1 of the yth row is supplied to the display device 1, and a grayscale voltage V1 corresponding to the grayscale data D(1)1 is written to the signal line Sig_1. Furthermore, during the first half of this one horizontal line period (times t1 to t2), a grayscale voltage V2A corresponding to the grayscale data D(1)2A is written to the signal line Sig_2 adjacent to the signal line Sig_1. Subsequently, during the second half of the one horizontal line period (times t2 to t3), a grayscale voltage V2B corresponding to the grayscale data D(1)2B is written to the signal line Sig_2. As a result, a composite voltage obtained by combining the gradation voltages V2A and V2B is applied to the liquid crystal element .

[0086] On the other hand, from time t3 to time t4, the gradation data D(2)2 of the y+1th row is supplied to the display device 1. In this case, the switch SW23 of the yth row is turned off, and gradation data is not written to the pixels 20 of the yth row. In this way, the switch SW23 is turned on only when gradation data is to be written to the pixels 20 of the corresponding row.

[0087] The same applies after time t3, where the odd-numbered signal lines are driven with a fixed gradation voltage for each horizontal line period, and the even-numbered signal lines are driven with a switched gradation voltage for each horizontal line period.

[0088] The internal configuration of the pixel 20 in the pixel array unit 14 in FIG. 12 is merely an example, and various modifications are possible. FIG. 14 is a block diagram of a modification of the pixel array unit 14 in FIG. 12. Each pixel 20 in the pixel array unit 14 in FIG. 14 includes switches SW31 to SW33, capacitors C_mix_a and C_mix_b, a transfer gate 25, and a liquid crystal element 26. The switches SW31 and SW33 are connected in series between a signal line Sig and the input node of the transfer gate 25. The switch SW32 is connected between the signal line Sig and the input node of the transfer gate 25. The capacitor C_mix_a is connected between the connection node of the switches SW31 and SW33 and the ground node. The capacitor C_mix_b is connected between the connection node of the switch SW32 and the input node of the transfer gate 25 and the ground node.

[0089] When the decoder 24 outputs the grayscale data of the row to be written to the signal line Sig, the switches SW31 to SW33 corresponding to that row are sequentially turned on. This allows the grayscale data on the signal line Sig to be written to the pixels 20 of the corresponding row on a row-by-row basis. In this way, only the switches SW31 to SW33 connected to the pixels 20 of the row to be written are turned on. The behavior of the switches SW31 to SW33 changes for each row.

[0090] Figure 15 is a timing diagram of the display device 1 of Figure 14. In Figure 15, the data applied to the liquid crystal elements 26 in the pixels 20 connected to the signal lines of the odd and even columns are denoted as LC_Data_1 and LC_Data_2. Times t1 to t4 in Figure 15 correspond to one horizontal line period. Between times t1 and t2, when the decoder 24 outputs the grayscale data of the row to be written to the signal line Sig, the switch SW31 of the corresponding row is turned on and the switches SW32 and SW33 are turned off.

[0091] The decoder 24 corresponding to the signal line Sig_1 of the odd-numbered column continuously selects, for example, the gradation voltage V1 during one horizontal line period. This gradation voltage V1 is supplied to the signal line Sig_1 via the source amplifier 23. The switches SW31 and SW32 in the corresponding pixel 20 of the pixel array unit 14 are turned on at different times (from time t1 to t2 and from time t2 to t3), and the switch SW33 is turned off. As a result, the capacitors C_mix_a and C_mix_b accumulate charges corresponding to the gradation voltage V1. Thereafter, from time t3 to t4, the switches SW31 and SW32 are turned off and the switch SW33 is turned on, and voltages LC_Data_1 and LC_Data_2 corresponding to the accumulated charges in the capacitors C_mix_a and C_mix_b are applied to the liquid crystal element 26 via the transfer gate 25, thereby performing display.

[0092] Furthermore, the decoder 24 corresponding to the signal line Sig_2 of the even-numbered column switches between, for example, gradation voltages V2A and V2B within one horizontal line period (times t1 to t2 and t2 to t3). While the decoder 24 selects the gradation voltage V2A (times t1 to t2), it turns on the switch SW31 and turns off the switches SW32 and SW33, and accumulates a charge corresponding to the gradation voltage V2A in the capacitor C_mix_a. Thereafter, while the decoder 24 selects the gradation voltage V2B (times t2 to t3), it turns on the switch SW32 and turns off the switches SW31 and SW33, and accumulates a charge corresponding to the gradation voltage V2B in the capacitor C_mix_b. Thereafter, it turns off the switches SW31 and SW32 and turns on the switch SW33 (times t3 to t4), thereby driving the liquid crystal element 26 with a voltage corresponding to the charge accumulated in the capacitors C_mix_a and C_mix_b.

[0093] 12 and 14, the driving method for the signal lines in the odd-numbered columns may be switched with the driving method for the signal lines in the even-numbered columns for each frame FR or sub-frame Sub_FR, thereby suppressing color unevenness and improving image quality.

[0094] As described above, in the second embodiment, instead of providing a capacitor C_mix and a switch SW11 inside the source driver 15 to synthesize the gradation voltages, capacitors C_mix_a and C_mix_b and switches SW31 and SW32 are provided in each pixel 20 in the pixel array section 14 to synthesize the gradation voltages, thereby simplifying the internal configuration of the source driver 15 and enabling the source driver 15 to be made smaller.

[0095] (Third embodiment) In the first and second embodiments described above, one decoder 24 is provided for each signal line, but a plurality of decoders 24 may be provided for each signal line.

[0096] FIG. 16 is a circuit diagram showing the internal configuration of a source driver 15 in a display device 1 according to the third embodiment, and FIG. 17 is a timing diagram of the source driver 15 of FIG. 16. The source driver 15 of FIG. 16 has multiple decoders 24 for each signal line. The source driver 15 of FIG. 16 also has voltage switches SW41 and SW42 that switch between multiple grayscale voltages selected by the multiple decoders 24 and supply them to the signal lines, for each signal line. The voltage switches SW41 and SW42 can switch between and select one of the output nodes of the multiple decoders 24 for each signal line. This allows the grayscale voltage selected by one of the multiple decoders 24 to be supplied to the signal line for each signal line.

[0097] Similar to the source driver 15 in FIG. 6A, one end of the voltage switches SW41 and SW42 is connected to one end of the switch SW11 and one end of the capacitor (storage capacitance) C_mix.

[0098] One of the decoders 24 provided for each signal line selects, for example, a gray scale voltage (e.g., V1) having the same voltage level as the expected gray scale voltage, and the remaining one of the decoders 24 selects, for example, a gray scale voltage (e.g., V2A and V2B) having a voltage level close to the expected gray scale voltage by switching between them within one horizontal line period.

[0099] For example, voltage switches SW41 and SW42 select the output of decoder 24 that outputs gradation voltage V1 for signal lines in odd-numbered columns, and select the output of decoder 24 that switches between and outputs gradation voltages V2A and V2B for signal lines in even-numbered columns.

[0100] As shown in the timing diagram of FIG. 17, while the voltage switch SW41 is on for the odd-numbered signal lines, the voltage switch SW42 is on for the even-numbered signal lines. In this case, the gray scale voltage V1 having the same voltage level as the expected gray scale voltage is continuously supplied to the odd-numbered signal lines for one horizontal line period. Furthermore, the gray scale voltages V2A and V2B having voltage levels close to the expected gray scale voltage are switched and supplied to the even-numbered signal lines for one horizontal line period. Meanwhile, in the next subframe, while the voltage switch SW42 is on for the odd-numbered signal lines, the voltage switch SW41 is on for the even-numbered signal lines. In this case, the gray scale voltage V2A and V2B having voltage levels close to the expected gray scale voltage are switched and supplied to the odd-numbered signal lines for one horizontal line period. Furthermore, the gray scale voltage V1 having the same voltage level as the expected gray scale voltage is continuously supplied to the even-numbered signal lines for one horizontal line period.

[0101] In the first and second embodiments, there was only one decoder 24 for each signal line, so it was necessary to finely switch and control the gradation voltage selected by the decoder 24. However, in this embodiment, there are multiple decoders 24 for each signal line, so the selection operation of each decoder 24 can be simplified.

[0102] Between two adjacent frames FR or sub-frames Sub_FR, the voltage switches SW41 and SW42 may select different grayscale voltages output from the plurality of decoders 24 to be supplied to the signal lines. For example, in a certain sub-frame Sub_FR, the decoder 24 that supplies the grayscale voltage V1 to the signal line Sig_1 may be selected, and the decoder 24 that switches between supplying the grayscale voltages V2A and V2B to the adjacent signal line Sig_2 may be selected, whereas in the next sub-frame Sub_FR, the decoder 24 that switches between supplying the grayscale voltages V2A and V2B to the signal line Sig_1 may be selected, and the decoder 24 that supplies the grayscale voltage V1 to the signal line Sig_2 may be selected.

[0103] In this way, in the third embodiment, multiple decoders 24 and voltage switches SW41 and SW42 are provided for each signal line, so the selection operation of the decoder 24 can be simplified and the selection of the gradation voltage can be made in detail for each signal line or for each sub-frame Sub_FR.

[0104] (Fourth embodiment) In the first to third embodiments described above, different gradation voltages are supplied to the signal lines in the even-numbered columns and the odd-numbered columns. However, it is not necessary to switch the type of gradation voltage between two adjacent signal lines; the type of gradation voltage may be switched between two non-adjacent signal lines. For example, FIG. 18 is a circuit diagram showing an example of a source driver 15. FIG. 18 shows four signal lines Sig1 to Sig4 arranged in the column direction. For example, signal lines Sig1 and Sig3 form a pair, one of which is supplied with gradation voltage V1, and the other of which is supplied with gradation voltages V2A and V2B in a switchable manner. Furthermore, signal lines Sig2 and Sig4 form a pair, one of which is supplied with gradation voltage V1, and the other of which is supplied with gradation voltages V2A and V2B in a switchable manner. 18 is also an example, and for example, gradation voltage V1 may be supplied to one of any two combinations of signal lines Sig1 to Sig4, and gradation voltages V2A and V2B may be switched and supplied to the other signal line. Alternatively, different gradation voltages may be supplied to any three or more signal lines.

[0105] The present technology can be configured as follows: (1) a grayscale voltage generating unit that generates a plurality of grayscale voltages that can be supplied to a signal line; a voltage selector that selects, from the plurality of gradation voltages, whether to supply a gradation voltage having the same voltage level as an expected gradation voltage to the signal line, or a gradation voltage close to the expected gradation voltage to the signal line. (2) a plurality of the signal lines are arranged at intervals in a first direction; The driving circuit described in (1), wherein the voltage selector supplies the gradation voltage equal to the expected gradation voltage to one of two signal lines arranged in a first direction, and supplies the gradation voltage different from the expected gradation voltage to the other signal line. (3) A driving circuit according to (1) or (2), wherein the voltage selector supplies a gradation voltage of the same voltage level as the expected gradation voltage to a signal line during one of two consecutive frame periods, and supplies a gradation voltage close to the expected gradation voltage during the other frame period. (4) A driving circuit described in any one of (1) to (3), wherein the voltage selector selects from the plurality of gradation voltages whether to supply a gradation voltage having the same voltage level as an expected gradation voltage to the signal line, or to switch between two or more gradation voltages close to the expected gradation voltage and supply them to the signal line. (5) The drive circuit according to (4), wherein the two or more gradation voltages close to the expected gradation voltage include a gradation voltage having a voltage level higher than the expected gradation voltage and a gradation voltage having a voltage level lower than the expected gradation voltage. (6) A driving circuit according to (4) or (5), wherein the voltage selector selects whether to continuously supply the same level of gradation voltage to the signal line within one horizontal line period, or to switch between the two or more gradation voltages and supply them to the signal line within the one horizontal line period. (7) The driving circuit according to (6), further comprising a voltage combiner that generates a voltage by combining the two or more grayscale voltages that are switched and supplied within one horizontal line period, and supplies the resulting voltage to the corresponding signal line. (8) The voltage combiner an amplifier connected to the signal line and amplifying the voltage of the signal line; a first capacitor connected in parallel between an input node of the amplifier and an output node of the voltage selector, and a first switch that switches between short-circuiting both ends of the first capacitor and not short-circuiting; The driving circuit described in (7), wherein the voltage selector selects a first gradation voltage with both ends of the first capacitor shorted by the first switch within one horizontal line period, and then selects a second gradation voltage with both ends of the first capacitor released by the first switch. (9) The drive circuit according to (8), further comprising a second capacitor connected between the output node of the amplifier and a reference voltage node. (10) A plurality of the voltage selectors are provided for each of the signal lines; The drive circuit according to any one of (4) to (9), further comprising a voltage switcher that switches the grayscale voltages selected by the voltage selectors and supplies the selected grayscale voltages to the signal line. (11) The driving circuit according to (10), wherein the voltage switch supplies the corresponding signal line with a gradation voltage selected by the voltage selector that is different from each other during one of two consecutive frame periods and the other. (12) The gradation voltage generating unit includes a ladder resistor having a plurality of output nodes for outputting the plurality of gradation voltages obtained by resistively dividing two or more reference voltages, The driving circuit according to any one of (1) to (11), wherein the voltage selector has a plurality of second switches that switch between connecting or disconnecting the plurality of output nodes of the ladder resistor and the signal line based on a gradation signal. (13) A pixel having a luminance modulation element whose luminance is modulated according to the voltage of the signal line; a signal line for supplying a gradation voltage to the pixel; a drive circuit for generating the gradation voltage; The drive circuit a grayscale voltage generating unit that generates a plurality of grayscale voltages that can be supplied to the signal lines; a voltage selector that selects, from the plurality of gradation voltages, whether to supply a gradation voltage having the same voltage level as an expected gradation voltage to the signal line, or a gradation voltage close to the expected gradation voltage to the signal line. (14) A pixel array unit having a plurality of the pixels arranged in a first direction and a second direction, A plurality of the signal lines are arranged at intervals in the first direction, The display device according to (13), wherein the voltage selector supplies different grayscale voltages to two of the signal lines adjacent to each other in the first direction. (15) The display device described in (14), wherein the voltage selector supplies the gradation voltage equal to the expected gradation voltage to one of two signal lines adjacent in a first direction, and supplies the gradation voltage different from the expected gradation voltage to the other signal line. (16) The display device described in (15), wherein the voltage selector switches between two or more of the gradation voltages different from the expected gradation voltage within one horizontal line period and supplies the other of the two signal lines. (17) The display device described in (16), wherein the pixel array section has a voltage synthesizer that generates a voltage by synthesizing the two or more gradation voltages that are switched and supplied within one horizontal line period and supplies the voltage to the corresponding signal line. (18) The display device according to (17), wherein the voltage combiner is provided within the pixel. (19) The voltage combiner a third switch and a fourth switch connected in series between the signal line and the luminance modulation element; a third capacitor connected between the signal line and a connection node between the third switch and the fourth switch; The display device according to (18), further comprising: a fourth capacitor having one end connected between the fourth switch and the luminance modulation element and the other end connected to a reference voltage node. (20) The voltage combiner a fifth switch and a sixth switch connected in series between the signal line and the luminance modulation element; a seventh switch connected between the signal line and a connection node between the fifth switch and the sixth switch; a fifth capacitor connected between the connection node and a reference voltage node; The display device according to (18), further comprising: a sixth capacitor connected between the connection node and the reference voltage node.

[0106] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0107] 1, 1a display device, 2 light source, 3 optical system, 4 light modulation element, 5 screen, 6a video signal generation unit, 6b frame memory, 10, 10a display system, 11 IF unit, 12 signal processing unit, 13 gamma voltage generation circuit, 14 pixel array unit, 15 source driver, 16 gate driver, 17 timing controller, 17a timing controller, 18 amplifier, 19 ladder resistor, 20 pixel, 21 grayscale voltage generation unit, 22 voltage selector, 23 source amplifier, 24 decoder, 25 transfer gate, 26 liquid crystal element

Claims

1. a grayscale voltage generating unit that generates a plurality of grayscale voltages that can be supplied to the signal lines; a voltage selector that selects whether to supply a gray scale voltage having the same voltage level as an expected gray scale voltage to a signal line continuously within one horizontal line period from among the plurality of gray scale voltages, or to switch between two or more gray scale voltages close to the expected gray scale voltage and supply them to the signal line within the one horizontal line period.

2. A plurality of the signal lines are arranged spaced apart in a first direction, 2. The drive circuit according to claim 1, wherein the voltage selector supplies the gradation voltage equal to the expected gradation voltage to one of two signal lines arranged in a first direction, and supplies the gradation voltage different from the expected gradation voltage to the other signal line.

3. 3. The drive circuit according to claim 1, wherein the voltage selector supplies a gradation voltage having the same voltage level as the expected gradation voltage to a signal line during one of two consecutive frame periods, and supplies a gradation voltage close to the expected gradation voltage during the other frame period.

4. 4. The drive circuit according to claim 1, wherein the two or more grayscale voltages close to the assumed grayscale voltage include a grayscale voltage having a voltage level higher than the assumed grayscale voltage and a grayscale voltage having a voltage level lower than the assumed grayscale voltage.

5. 5. The drive circuit according to claim 1, further comprising a voltage combiner that generates a voltage by combining the two or more grayscale voltages that are switched and supplied within one horizontal line period, and supplies the resulting voltage to the corresponding signal line.

6. The voltage combiner an amplifier connected to the signal line and amplifying the voltage of the signal line; a first capacitor connected in parallel between an input node of the amplifier and an output node of the voltage selector; and a first switch that switches between short-circuiting and non-short-circuiting both ends of the first capacitor, 6. The drive circuit of claim 5, wherein the voltage selector selects a first gradation voltage with both ends of the first capacitor shorted by the first switch within one horizontal line period, and subsequently selects a second gradation voltage with both ends of the first capacitor released by the first switch.

7. 7. The drive circuit of claim 6, further comprising a second capacitor connected between the output node of the amplifier and a reference voltage node.

8. a plurality of the voltage selectors are provided for each of the signal lines; The drive circuit according to claim 1 , further comprising a voltage switcher that switches between the plurality of grayscale voltages selected by the plurality of voltage selectors and supplies the selected grayscale voltages to the signal line.

9. 9. The drive circuit according to claim 8, wherein the voltage switch supplies, to the corresponding signal line, gray scale voltages selected by the voltage selector that are different from each other during one of two consecutive frame periods.

10. the gradation voltage generation unit includes a ladder resistor having a plurality of output nodes for outputting the plurality of gradation voltages obtained by resistively dividing two or more reference voltages; 10. The drive circuit according to claim 1, wherein the voltage selector has a plurality of second switches that switch between connecting or disconnecting the plurality of output nodes of the ladder resistor and the signal line based on a gradation signal.

11. a pixel having a luminance modulation element whose luminance is modulated in accordance with the voltage of a signal line; a signal line for supplying a gradation voltage to the pixel; a drive circuit for generating the gradation voltage; The drive circuit a grayscale voltage generating unit that generates a plurality of grayscale voltages that can be supplied to the signal lines; a voltage selector that selects whether to supply a gray scale voltage having the same voltage level as an expected gray scale voltage to the signal line from among the plurality of gray scale voltages continuously within one horizontal line period, or to switch between two or more gray scale voltages close to the expected gray scale voltage and supply them to the signal line within the one horizontal line period.

12. a pixel array unit having a plurality of the pixels arranged in a first direction and a second direction; A plurality of the signal lines are arranged to be spaced apart in the first direction, The display device of claim 11 , wherein the voltage selector supplies different grayscale voltages to two of the signal lines adjacent to each other in the first direction.

13. 13. The display device according to claim 12, wherein the pixel array section includes a voltage combiner that generates a voltage by combining the two or more grayscale voltages that are switched and supplied within one horizontal line period, and supplies the voltage to the corresponding signal line.

14. The display device according to claim 13 , wherein the voltage combiner is provided within the pixel.

15. The voltage combiner a third switch and a fourth switch connected in series between the signal line and the luminance modulation element; a third capacitor connected between the signal line and a connection node between the third switch and the fourth switch; 15. The display device according to claim 14, further comprising: a fourth capacitor having one end connected between the fourth switch and the luminance modulation element and the other end connected to a reference voltage node.

16. The voltage combiner a fifth switch and a sixth switch connected in series between the signal line and the luminance modulation element; a seventh switch connected between the signal line and a connection node between the fifth switch and the sixth switch; a fifth capacitor connected between the connection node and a reference voltage node; 15. The display device according to claim 14, further comprising: a sixth capacitor connected between the connection node and the reference voltage node.

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