Neural network device and synaptic weight updating method

Abstract

To allow a neural network device to learn accurately with small-scale circuitry.SOLUTION: A neural network device includes a plurality of neuron circuits, a plurality of synapse circuits, and a plurality of random number circuits. Each of the random number circuits outputs a random signal. Each of the synapse circuits receives the random signal from one of the random number circuits and updates synaptic weight with a probability generated on the basis of the received random signal. The synapse circuits are divided into synapse groups. Each of two or more synapse circuits belonging to a first synapse group receives the random signal output from a first random number circuit. Each of two or more synapse circuits outputting output signals to a first neuron circuit belongs to a synapse group different from a synapse group to which other synapse circuits outputting the output signal to the first neuron circuit belong.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to a neural network device and a synaptic weight updating method. [Background technology]

[0002] In recent years, advances in computer hardware, such as GPUs (Graphical Processing Units), have led to rapid advances in artificial intelligence technology. For example, image recognition and classification technologies, such as CNNs (Convolutional Neural Networks), are already being used in a variety of real-world applications. Currently widely used artificial intelligence technologies are based on mathematical models that simplify the behavior of biological neural networks. For this reason, such technologies are executed using computers such as GPUs. However, executing such technologies on GPUs requires a large amount of power. In particular, the learning process, which involves extracting and storing features from large amounts of data, requires a massive amount of computation. For this reason, such learning processes require a significant amount of power, making them difficult to execute on edge devices, for example.

[0003] On the other hand, the human brain constantly learns huge amounts of data online, despite consuming only about 20 W of energy. Therefore, research is being conducted around the world into technologies that can process information by relatively faithfully reproducing brain activity using electrical circuits.

[0004] In the brain's neural network, information is transmitted from neuron (nerve cell) to neuron as signals in the form of voltage spikes. Neurons are connected by junctions called synapses. When a neuron fires and generates a voltage spike, the voltage spike is input to the subsequent neuron via the synapse. At this time, the strength of the voltage spike input to the subsequent neuron is adjusted by the connection strength (also called synaptic weight) of the synapse. If the synaptic weight is large, the voltage spike is transmitted to the subsequent neuron with high strength. However, if the synaptic weight is small, the voltage spike is transmitted to the subsequent neuron with low strength. Therefore, in the brain's neural network, the greater the synaptic weight connecting two neurons, the stronger the informational relationship between those two neurons.

[0005] It is known that synaptic weights change depending on the timing of input voltage spikes and the internal state of neurons. The most well-known synaptic update rule is STDP (Spike Timing Dependent Plasticity).

[0006] The synaptic update rule based on STDP operates as follows: Suppose a voltage spike is input from a certain neuron (preceding neuron) to the next neuron (following neuron) via a synapse. If the internal potential of the following neuron reaches a threshold in response to the input of the voltage spike from the preceding neuron, causing the following neuron to fire, then there is a causal relationship between the information held by the preceding neuron and the information held by the following neuron. In such a case, the synaptic weight of the synapse connecting the preceding neuron and the following neuron becomes large. Conversely, if a voltage spike is input from the preceding neuron to the following neuron after the following neuron fires, there is no causal relationship between the information held by the preceding neuron and the information held by the following neuron. In such a case, the synaptic weight of the synapse connecting the preceding neuron and the following neuron becomes small.

[0007] Information processing that mimics the information transmission principle of the brain's neural circuit network is called a spiking neural network. Spiking neural networks express the flow of information in the brain's neural circuit network as spike trains. Spiking neural networks process information by accumulating, generating, and transmitting voltage spikes, without performing numerical calculations. Conventional artificial intelligence required a huge amount of calculation for learning operations. However, spiking neural networks learn synaptic weights using update rules such as STDP, allowing for efficient learning operations.

[0008] Synaptic weights are generally expressed as continuous values. Furthermore, synaptic weights change by an amount determined by a synaptic update rule. Therefore, a spiking neural network implemented in hardware must have a memory for storing synaptic weights expressed as continuous values. Currently, widely used memories store information digitally. Digital memory must have a sufficiently large number of bits to treat the stored values ​​as continuous. Therefore, a spiking neural network implemented in hardware has the problem of requiring large memory capacity when storing synaptic weights expressed as continuous values ​​in a digital memory.

[0009] Analog memories that store analog values, such as resistance change memories and phase change memories, are also known. However, analog memories require precise signal control to accurately store the desired value. Therefore, when a spiking neural network is configured using hardware, the circuits and systems required to control the analog memory become complex and large.

[0010] To avoid these problems, spiking neural networks implemented in hardware may use synaptic weights represented by discrete values. For example, spiking neural networks implemented in hardware may use synaptic weights represented by binary values, i.e., synaptic weights represented by 0 or 1. However, in spiking neural networks using binary synaptic weights, the amount of change in synaptic weight is 1, making it difficult to properly represent changes in synaptic weights that depend on the input timing of voltage spikes and the internal state of neurons. Therefore, when spiking neural networks implemented in hardware use synaptic weights represented by discrete values, such as binary, it has been difficult to properly train them on a small circuit scale. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] U.S. Patent No. 9,129,220 [Non-patent literature]

[0012] [Non-Patent Document 1] MorphIC chip, IEEE Trans. Bio CAS, vol. 13, 999(2019), Catholic University of Leuven (Belgium) [Non-patent document 2] Elisabetta Chicca, et al., “Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems”, Proceedings of the IEEE (Volume: 102 , Issue: 9 , Sept. 2014), P1367-1388, May 1, 2014 [Non-patent document 3] Joseph M. Brader et al., “Learning real-world stimuli in a neural network with spike-driven synaptic dynamics ”, Neural computation, Volume 19, Massachusetts Institute of Technology, P2881-2912, November 2007 Summary of the Invention [Problem to be solved by the invention]

[0013] The problem to be solved by the present invention is to provide a neural network device and a synapse weight updating method that can perform learning with high accuracy using a small circuit scale. [Means for solving the problem]

[0014] A neural network device according to an embodiment includes a plurality of neuron circuits, a plurality of synapse circuits, and a plurality of random number circuits. Each of the plurality of neuron circuits receives an output signal output from one or more synapse circuits among the plurality of neuron circuits and outputs an ignition signal in response to the received output signal. Each of the plurality of random number circuits outputs a random signal representing a periodically changing random number. Each of the plurality of synapse circuits includes a memory circuit, a transmission circuit, a probability control circuit, and an update circuit. The memory circuit stores synapse weights. The transmission circuit receives an input signal, which is the ignition signal output from a preceding neuron circuit that is one of the plurality of neuron circuits, and outputs the output signal, which is obtained by adding the influence of the synapse weight to the received input signal, to a succeeding neuron circuit that is one of the plurality of neuron circuits. The probability control circuit receives the random signal from one of the plurality of random number circuits and permits updating of the synapse weights with a probability generated based on the received random signal, and prohibits updating of the synapse weights except when updating of the synapse weights is permitted. When the update circuit receives the input signal from the previous-stage neuron circuit, it updates the synapse weights in response to a feedback signal representing the operation or state of the next-stage neuron circuit, provided that updating of the synapse weights is permitted. The plurality of synapse circuits are divided into a plurality of synapse groups. Two or more synapse circuits belonging to a first synapse group among the plurality of synapse groups each receive the random signal output from a first random number circuit among the plurality of random number circuits. Two or more synapse circuits that output the output signal to a first neuron circuit among the plurality of neuron circuits each belong to a different synapse group from other synapse circuits that output the output signal to the first neuron circuit. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a configuration diagram of a neural network device according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating the configuration of a reservoir computing device. [Figure 3] FIG. 2 is a diagram showing a connection relationship based on STDP in the first embodiment. [Figure 4] FIG. 10 is a diagram showing an example of update probability based on STDP. [Figure 5] FIG. 10 is a diagram showing another example of update probability based on STDP. [Figure 6] FIG. 3 is a diagram showing a connection relationship based on Fusi's law in the first embodiment. [Figure 7] FIG. 10 is a diagram showing an example of update probability based on Fusi's rule. [Figure 8] FIG. 1 is a configuration diagram of a synapse circuit according to a first embodiment. [Figure 9] FIG. 1 is a diagram illustrating the configuration of a synapse circuit based on STDP according to a first embodiment. [Figure 10] FIG. 1 is a configuration diagram of a synapse circuit based on Fusi's rule according to a first embodiment. [Figure 11] A diagram showing a spiking neural network. [Figure 12] FIG. 10 is a graph showing the recognition rate when receiving independent random signals. [Figure 13] FIG. 10 is a diagram showing the recognition rate when a common random signal is received. [Figure 14] FIG. 2 is a diagram showing a first connection example in the first embodiment. [Figure 15] FIG. 10 is a diagram showing a second connection example in the first embodiment. [Figure 16] FIG. 10 is a diagram showing a third connection example in the first embodiment. [Figure 17] FIG. 10 is a diagram showing a fourth connection example in the first embodiment. [Figure 18] FIG. 4 is a diagram showing a recognition rate in the first embodiment. [Figure 19] FIG. 10 is a diagram showing the number of transistors relative to the number of neurons. [Figure 20] FIG. 10 is a configuration diagram of a neural network device according to a second embodiment. [Figure 21] FIG. 10 is a diagram showing a connection relationship based on STDP in the second embodiment. [Figure 22]FIG. 10 is a configuration diagram of a synapse circuit according to a second embodiment. [Figure 23] FIG. 10 is a configuration diagram of a probability control circuit according to the second embodiment. [Figure 24] FIG. 10 is a diagram showing a first connection example in the second embodiment. [Figure 25] FIG. 10 is a diagram showing a second connection example in the second embodiment. [Figure 26] FIG. 10 is a diagram showing a third connection example in the second embodiment. [Figure 27] FIG. 10 is a diagram showing a recognition rate in the second embodiment. [Figure 28] FIG. 10 is a diagram showing the recognition rate when the first probability and the second probability are changed. DETAILED DESCRIPTION OF THE INVENTION

[0016] A neural network device 10 according to an embodiment will be described below with reference to the drawings.

[0017] The neural network device 10 according to the embodiment is a spiking neural network configured with hardware, and updates synaptic weights according to a probabilistic update rule. The neural network device 10 according to the embodiment is capable of performing learning with high accuracy using a small circuit scale. As a result, the neural network device 10 according to the embodiment can perform inference with high accuracy using a small circuit scale.

[0018] (First embodiment) 1 is a diagram showing an example of the configuration of a neural network device 10 according to the first embodiment. The neural network device 10 according to the first embodiment includes, as an example, N-stage (N is an integer equal to or greater than 2) layers 12, (N-1) synapse units 14, and a random number generation unit 16.

[0019] Each of the N layers 12 includes a plurality of neuron circuits 22. Each of the plurality of neuron circuits 22 receives a plurality of signals output from the previous layer 12 via the previous synapse unit 14 and performs a process corresponding to a sum-of-products operation on the received signals. The first layer 12 of the N layers 12 receives a plurality of signals from an external device or an input layer. Each of the plurality of neuron circuits 22 outputs a signal obtained by performing a process corresponding to an activation function on a signal representing the operation result. Each of the plurality of neuron circuits 22 may perform a process corresponding to a sum-of-products operation using an analog circuit. Each of the plurality of neuron circuits 22 may perform a process corresponding to an activation function using an analog circuit. By using an analog circuit, each of the plurality of neuron circuits 22 can perform a process corresponding to a sum-of-products operation and a process corresponding to an activation function with low power consumption.

[0020] Each of the (N-1) synapse units 14 includes a plurality of synapse circuits 20. A synapse weight is set for each of the plurality of synapse circuits 20.

[0021] The nth synapse unit 14 (n is an integer greater than or equal to 1 and less than or equal to (N-1)) of the (N-1) synapse units 14 is arranged between the nth layer 12 and the (n+1)th layer 12.

[0022] Each of the plurality of synapse circuits 20 included in the nth synapse unit 14 receives, as a binary input signal, a signal output from one of the plurality of neuron circuits 22 included in the nth layer 12. Each of the plurality of synapse circuits 20 included in the nth synapse unit 14 generates an output signal by adding the influence of a set synapse weight to the received input signal. In this embodiment, the output signal is a binary voltage signal. Alternatively, the output signal may be a binary current signal. Each of the plurality of synapse circuits 20 included in the nth synapse unit 14 provides an output signal to one of the plurality of neuron circuits 22 included in the (n+1)th layer 12.

[0023] The random number generating unit 16 includes a plurality of random number circuits 24. Each of the plurality of random number circuits 24 outputs a random signal representing a periodically changing random number. Each of the plurality of random number circuits 24 is independent from the other random number circuits 24 in terms of circuitry, and generates a random signal representing a random number different from that of the other random number circuits 24. Each of the plurality of random number circuits 24 is, for example, a pseudo-random number generating circuit. The pseudo-random number generating circuit is, for example, a linear feedback shift register (LFSR) circuit generated by a CMOS semiconductor circuit.

[0024] The random number represented by the random signal is a value within a predetermined range, for example, a value within a 10-bit range (0 to 1023).

[0025] In such a neural network device 10, the first layer 12 receives one or more signals from an external device or an input layer. Then, the neural network device 10 outputs one or more signals representing the results of performing a neural network operation on the received one or more signals from the Nth layer 12.

[0026] Here, a synapse weight expressed by a discrete value is set for each of the plurality of synapse circuits 20. In this embodiment, a synapse weight expressed by a binary value is set for each of the plurality of synapse circuits 20.

[0027] Furthermore, each of the plurality of synapse circuits 20 receives a random signal output from any one of the plurality of random number circuits 24. Then, each of the plurality of synapse circuits 20 stochastically updates the set synapse weight in accordance with a predetermined synapse update rule using a stochastic signal generated based on the received random signal. The stochastic signal is a signal that takes a first value (e.g., 1) with a predetermined probability and takes a second value (e.g., 9) in other cases.

[0028] For example, each of the plurality of synapse circuits 20 updates the set synapse weight according to a probabilistic update rule based on spike-timing dependent synaptic plasticity (STDP). For example, each of the plurality of synapse circuits 20 updates the synapse weight according to the update rule based on STDP when the probability signal is a first value (e.g., 1), and does not update the synapse weight when the probability signal is a second value (e.g., 0).

[0029] Furthermore, each of the plurality of synapse circuits 20 may update the set synapse weights, for example, according to a probabilistic update rule based on the Fusi rule shown in Non-Patent Document 3. For example, when the probability signal is a first value (for example, 1), each of the plurality of synapse circuits 20 updates the synapse weights according to the update rule based on the Fusi rule, and when the probability signal is a second value (for example, 0), the synapse weights are not updated.

[0030] When the synaptic weights of each of the plurality of synaptic circuits 20 are expressed as binary values ​​of 0 or 1, the synaptic weights can be changed from 0 to 1 or from 1 to 0 by the stochastic STDP update rule or the stochastic Fusi update rule. This allows the neural network device 10 to appropriately learn the synaptic weights even if the synaptic weights are expressed as discrete values ​​such as binary.

[0031] FIG. 2 is a diagram showing the configuration of the reservoir computing device 26 according to the embodiment.

[0032] The neural network device 10 is not limited to a structure that transfers signals in a forward direction as shown in Fig. 1, but may be a recurrent neural network that internally feeds back signals. When the neural network device 10 is a recurrent neural network, it can be applied to, for example, a reservoir computing device 26 as shown in Fig. 2.

[0033] The reservoir computing device 26 includes an input layer 28 , a neural network device 10 that is a recurrent neural network, and an output layer 30 .

[0034] The input layer 28 receives one or more signals from an external device. The input layer 28 provides the received one or more signals to the neural network device 10. The output layer 30 receives one or more signals from the neural network device 10. Then, the output layer 30 outputs one or more signals to the external device.

[0035] Some of the neuron circuits 22 included in the neural network device 10 receive signals from the input layer 28. Furthermore, synapse circuits 20 that do not receive signals from the input layer 28 receive, as input signals, signals output from any one of the neuron circuits 22. Some of the neuron circuits 22 among the plurality of synapse circuits 20 provide output signals to other neuron circuits 22. Other of the plurality of neuron circuits 22 provide output signals to the output layer 30.

[0036] At least one of the multiple synapse circuits 20 feeds back its output signal and provides it as an input signal to itself or to another neuron circuit 22. That is, at least one of the multiple synapse circuits 20 provides an output signal to itself, the neuron circuit 22 that provided the input signal to itself, or a neuron circuit 22 that is located in a stage preceding the neuron circuit 22 that provided the input signal to itself.

[0037] 2 also includes a random number generator 16, similar to that of FIG 1. Each of the plurality of synapse circuits 20 receives a random signal and updates the synapse weights according to a probabilistic update rule.

[0038] Reservoir computing device 26 configured in this manner can function as a hardware device that performs reservoir computing.

[0039] FIG. 3 is a diagram showing the connection relationship between the synapse circuit 20 according to the first embodiment and other circuits when synapse weights are updated according to a probabilistic update rule based on STDP.

[0040] Each of the plurality of synapse circuits 20 receives as an input signal a firing signal output from a preceding neuron circuit 32, which is one of the plurality of neuron circuits 22. Each of the plurality of synapse circuits 20 outputs an output signal that is the received input signal and is influenced by a stored synapse weight. The synapse circuit 20 then supplies the output signal to a succeeding neuron circuit 34, which is one of the plurality of neuron circuits 22.

[0041] Each of the plurality of synapse circuits 20 receives a feedback signal from the subsequent neuron circuit 34. The feedback signal represents the operation or state of the subsequent neuron circuit 34.

[0042] When synaptic weights are updated by a stochastic update rule based on STDP, the feedback signal is a firing signal output from the subsequent neuron circuit 34. The firing signal is, for example, a binary signal representing a first value (e.g., 1) or a second value (e.g., 0), and changes from the second value (e.g., 0) to the first value (e.g., 1) at the firing timing of the subsequent neuron circuit 34, and returns to the second value (e.g., 0) after a certain period. In other words, when synaptic weights are updated by a stochastic update rule based on STDP, the feedback signal is a signal that becomes the first value (e.g., 1) for a certain period after the subsequent neuron circuit 34 fires, and becomes the second value (e.g., 0) for the other period.

[0043] Furthermore, each of the plurality of synapse circuits 20 receives a random signal from any one of the plurality of random number circuits 24 .

[0044] FIG. 4 is a diagram showing an example of update probability in a stochastic update rule based on STDP.

[0045] When synaptic weights are updated according to a probabilistic update rule based on STDP, each of the plurality of synapse circuits 20 changes the update probability according to the time difference (Δt) from the input signal to the feedback signal. That is, each of the plurality of synapse circuits 20 changes the update probability according to the time difference (Δt) from the timing at which the input signal changes from a second value (e.g., 0) to a first value (e.g., 1) to the timing at which the feedback signal changes from the second value (e.g., 0) to the first value (e.g., 1).

[0046] For example, when the time difference (Δt) is positive, i.e., when a feedback signal occurs after an input signal occurs, each of the plurality of synapse circuits 20 increases its synapse weight. In this case, each of the plurality of synapse circuits 20 increases the update probability as the absolute value of the time difference (Δt) decreases, and decreases the update probability as the absolute value of the time difference (Δt) increases.

[0047] For example, when the time difference (Δt) is negative, i.e., when a feedback signal occurs before an input signal occurs, each of the plurality of synapse circuits 20 decreases its synapse weight. In this case, each of the plurality of synapse circuits 20 increases the update probability as the absolute value of the time difference (Δt) decreases, and decreases the update probability as the absolute value of the time difference (Δt) increases.

[0048] By updating in this way, each of the plurality of synapse circuits 20 can update the synapse weight according to the magnitude of the information relationship between the preceding neuron circuit 32 and the succeeding neuron circuit 34. In addition, each of the plurality of synapse circuits 20 can learn the synapse weight with high accuracy even if the synapse weight is a discrete value such as binary.

[0049] 5 is a diagram showing another example of update probabilities in the probabilistic update rule based on STDP. Each of the plurality of synapse circuits 20 may update its synaptic weight as shown in FIG. 5, instead of updating as shown in FIG.

[0050] That is, when the time difference (Δt) is negative, each of the plurality of synapse circuits 20 does not update its synapse weight. When the time difference (Δt) is positive and smaller than a predetermined value (T), each of the plurality of synapse circuits 20 probabilistically increases its synapse weight with a predetermined increase probability (p). When the time difference (Δt) is positive and equal to or greater than the predetermined value (T), each of the plurality of synapse circuits 20 probabilistically decreases its synapse weight with a predetermined decrease probability (q).

[0051] When updating the synapse weights in this way, each of the plurality of synapse circuits 20 can update its synapse weight by measuring the time from when it receives an input signal to when it receives a feedback signal using a timer. Therefore, each of the plurality of synapse circuits 20 can update its synapse weight with a simple circuit.

[0052] FIG. 6 is a diagram showing the connection relationship between the synapse circuit 20 according to the first embodiment and other circuits when synapse weights are updated according to a probabilistic update rule based on Fusi's rule.

[0053] Each of the neuron circuits 22 holds an internal potential. Each of the neuron circuits 22 changes its internal potential according to the level or duration of the output signal received from the synapse circuit 20 connected in the preceding stage. Each of the neuron circuits 22 outputs a firing signal when the internal potential exceeds a preset firing threshold.

[0054] When synaptic weights are updated by a probabilistic update rule based on Fusi's rule, the feedback signal is an internal potential signal that represents the internal potential of the subsequent neuron circuit 34. For example, the internal potential signal has a first value (e.g., 1) when the internal potential is equal to or greater than a predetermined value, and has a second value (e.g., 0) when the internal potential is smaller than the predetermined value.

[0055] FIG. 7 is a diagram showing an example of update probability in a probabilistic update rule based on Fusi's rule.

[0056] When synapse weights are updated according to a probabilistic update rule based on Fusi's rule, each of the plurality of synapse circuits 20 changes the update probability according to the combination of the value of the input signal and the value of the feedback signal.

[0057] For example, when the input signal is a first value (e.g., 1) and the internal potential signal is also a first value (e.g., 1), each of the plurality of synapse circuits 20 increases the synapse weight with a predetermined increase probability (p). Also, when the input signal is a second value (e.g., 0) and the internal potential signal is also a first value (e.g., 1), each of the plurality of synapse circuits 20 decreases the synapse weight with a predetermined decrease probability (q).

[0058] Furthermore, each of the plurality of synapse circuits 20 does not change the synapse weight when the input signal is a first value (e.g., 1) and the internal potential signal is a second value (e.g., 0). Furthermore, each of the plurality of synapse circuits 20 does not change the synapse weight when the input signal is a second value (e.g., 0) and the internal potential signal is a first value (e.g., 1).

[0059] By updating in this way, each of the plurality of synapse circuits 20 can update the synapse weight according to the magnitude of the information relationship between the preceding neuron circuit 32 and the succeeding neuron circuit 34. In addition, each of the plurality of synapse circuits 20 can learn the synapse weight with high accuracy even if the synapse weight is a discrete value such as binary.

[0060] 8 is a diagram showing the configuration of a synapse circuit 20 according to the first embodiment. Each of the plurality of synapse circuits 20 includes a memory circuit 42, a transmission circuit 44, a probability control circuit 46, and an update circuit 48.

[0061] The memory circuit 42 stores synaptic weights. In this embodiment, the memory circuit 42 stores binary synaptic weights representing a first value (e.g., 1) or a second value (e.g., 0). The memory circuit 42 may store synaptic weights of three or more discrete values, may store synaptic weights of continuous values ​​represented by a large number of bits, or may store synaptic weights represented by analog values.

[0062] The transmission circuit 44 receives the firing signal output from the previous neuron circuit 32 as an input signal, and supplies an output signal to the next neuron circuit 34, which is the input signal to which the synaptic weight stored in the memory circuit 42 has been added.

[0063] For example, when the transfer circuit 44 receives an input signal from the preceding neuron circuit 32 and the synaptic weight stored in the memory circuit 42 is a first value (e.g., 1), it supplies an output signal of a first current amount to the succeeding neuron circuit 34. For example, when the transfer circuit 44 receives an input signal from the preceding neuron circuit 32 and the synaptic weight stored in the memory circuit 42 is a second value (e.g., 0), it supplies an output signal of a second current amount lower than the first current amount to the succeeding neuron circuit 34.

[0064] Alternatively, for example, when the transfer circuit 44 receives an input signal from the preceding neuron circuit 32 and the synaptic weight stored in the memory circuit 42 is a second value (e.g., 0), the transfer circuit 44 may not provide an output signal to the succeeding neuron circuit 34. Also, for example, when the transfer circuit 44 receives an input signal from the preceding neuron circuit 32 and the synaptic weight stored in the memory circuit 42 is a second value (e.g., 0), the transfer circuit 44 may provide an output signal with a lower voltage level than when the synaptic weight is a first value (e.g., 1), or may provide an output signal with a delay compared to when the synaptic weight is the first value (e.g., 1). For example, the transfer circuit 44 may include a DPI (Differential Pair-Integrator) circuit shown in Non-Patent Document 2. In this case, the transfer circuit 44 outputs an output signal corresponding to the signal output from the DPI circuit. Such a transfer circuit 44 can supply an output signal to the succeeding neuron circuit 34, in which the received input signal is affected by the synaptic weight stored in the memory circuit 42.

[0065] The probability control circuit 46 receives a random signal from any one of the plurality of random number circuits 24. The probability control circuit 46 permits updating of synaptic weights with a probability generated based on the received random signal, and prohibits updating of synaptic weights except when updating of synaptic weights is permitted.

[0066] For example, the random signal represents a random number within a range from a predetermined lower limit to a predetermined upper limit. In this case, the probability control circuit 46 allows the update of the synaptic weight when the random signal is within the range corresponding to a predetermined first probability, and prohibits the update of the synaptic weight when the random signal is not within the range corresponding to the first probability.

[0067] For example, suppose the random signal represents a random number within a numerical range from 0 to (N-1), and the first probability is p. Here, p is a real number greater than 0 and less than 1. In this case, for example, if the random signal is a value smaller than (p×N) within the numerical range from 0 to (N-1) or a value larger than (Np×N), the probability control circuit 46 may permit the update of the synaptic weights, assuming that the random signal is a value within the range corresponding to the first probability. Furthermore, if the random signal is one of P preselected values ​​within the numerical range from 0 to (N-1), the probability control circuit 46 may permit the update of the synaptic weights, assuming that the random signal is a value within the range corresponding to the first probability. Here, P is an integer obtained by rounding down or rounding up the decimal point of (p×N). This allows the probability control circuit 46 to permit the update of the synaptic weights with a probability generated based on the random signal.

[0068] For example, the probability control circuit 46 receives an update instruction signal from the update circuit 48 that instructs the memory circuit 42 to update the synaptic weights. When the probability control circuit 46 permits the update of the synaptic weights, it provides the synaptic weight update instruction signal received from the update circuit 48 to the memory circuit 42 as is. When the probability control circuit 46 prohibits the update of the synaptic weights, it masks the synaptic weight update instruction signal received from the update circuit 48 and does not provide it to the memory circuit 42. In this way, the probability control circuit 46 can control whether to permit or prohibit the update of the synaptic weights by the update circuit 48.

[0069] The update circuit 48 receives an input signal from the previous neuron circuit 32. The update circuit 48 also receives a feedback signal from the next neuron circuit 34 that represents the operation or state of the next neuron circuit 34.

[0070] When the update circuit 48 receives an input signal from the previous neuron circuit 32, it updates the synaptic weights stored in the memory circuit 42 in accordance with the feedback signal, provided that the update of the synaptic weights is permitted by the probability control circuit 46.

[0071] For example, when updating synaptic weights using an update rule based on STDP, the update circuit 48 operates as follows: The update circuit 48 receives a firing signal as a feedback signal from the downstream neuron circuit 34. If the time difference (Δt) between the input signal and the feedback signal is greater than 0 and less than a predetermined value (T), the update circuit 48 outputs an update instruction signal to increase the synaptic weight. If the time difference (Δt) between the input signal and the feedback signal is less than 0 or greater than the predetermined value (T), the update circuit 48 outputs an update instruction signal to decrease the synaptic weight.

[0072] For example, when updating synaptic weights using an update rule based on the Fusi rule, the update circuit 48 operates as follows: That is, the update circuit 48 receives an internal potential signal from the subsequent neuron circuit 34 as a feedback signal. Then, when the input signal is a first value (e.g., 1) indicating firing and the feedback signal is a first value (e.g., 1) indicating that the internal potential is equal to or greater than a predetermined value, the update circuit 48 outputs an update instruction signal to increase the synaptic weight. On the other hand, when the input signal is a second value (e.g., 0) and the feedback signal is the first value (e.g., 1), the update circuit 48 outputs an update instruction signal to decrease the synaptic weight.

[0073] The update circuit 48 provides an update instruction signal to the memory circuit 42 via the probability control circuit 46. Therefore, the update circuit 48 can update the synapse weights stored in the memory circuit 42, provided that the probability control circuit 46 permits updating of the synapse weights.

[0074] When the memory circuit 42 receives an update instruction signal from the update circuit 48 via the probability control circuit 46, it changes the stored synaptic weights. For example, when the memory circuit 42 receives an update instruction signal to increase the synaptic weights, it increases the stored synaptic weights. When the memory circuit 42 receives an update instruction signal to decrease the synaptic weights, it decreases the stored synaptic weights.

[0075] However, the synaptic weights are represented by discrete values ​​within a predetermined numerical range. Therefore, even when the memory circuit 42 receives an update instruction signal to increase the synaptic weight, it does not change the synaptic weight above the upper limit of the numerical range. Also, even when the memory circuit 42 receives an update instruction signal to decrease the synaptic weight, it does not change the synaptic weight below the lower limit of the numerical range.

[0076] For example, a synaptic weight is represented by a binary value of a first value (e.g., 1) or a second value (e.g., 0). In this case, when the memory circuit 42 receives an update instruction signal to change the synaptic weight in an increasing direction while the stored synaptic weight is the first value (e.g., 1), the memory circuit 42 does not change the synaptic weight. Also, when the memory circuit 42 receives an update instruction signal to change the synaptic weight in a decreasing direction while the stored synaptic weight is the second value (e.g., 0), the memory circuit 42 does not change the synaptic weight.

[0077] FIG. 9 is a diagram showing an example of the configuration of the memory circuit 42, the update circuit 48, and the probability control circuit 46 when synaptic weights are updated according to a stochastic update rule based on STDP.

[0078] The storage circuit 42 includes an SR latch circuit 52. The SR latch circuit 52 receives an increase instruction signal at a set terminal and a decrease instruction signal at a reset terminal. The increase instruction signal is an update instruction signal that instructs changing a synapse weight in an increasing direction, and takes a first value (e.g., 1) when instructing to change a synapse weight in an increasing direction. The decrease instruction signal is an update instruction signal that instructs to change a synapse weight in a decreasing direction, and takes a first value (e.g., 1) when instructing to change a synapse weight in a decreasing direction.

[0079] The SR latch circuit 52 stores a synapse weight that represents a first value (for example, 1) or a second value (for example, 0). The SR latch circuit 52 outputs the stored synapse weight from a Q terminal to the transmission circuit 44.

[0080] When synaptic weights are updated according to a stochastic update rule based on STDP, the update circuit 48 includes a timer circuit 54, a first inversion circuit 56, a first AND circuit 58, and a second AND circuit 60.

[0081] The timer circuit 54 receives an input signal from the previous neuron circuit 32. The timer circuit 54 outputs a timer signal that represents 1 or 0. The timer circuit 54 sets the value of the timer signal to 1 during the period from when the input signal changes from 0 to 1 until a predetermined time T has elapsed, and sets the value of the timer signal to 0 during the other period.

[0082] The first inversion circuit 56 receives the timer signal and outputs an inverted timer signal obtained by inverting the value of the timer signal.

[0083] The first AND circuit 58 receives the feedback signal, which is the firing signal output from the subsequent neuron circuit 34, and the inverted timer signal. The first AND circuit 58 calculates the logical product of the feedback signal and the inverted timer signal. The first AND circuit 58 outputs the result of the logical product of the feedback signal and the inverted timer signal as an increase instruction signal.

[0084] The second AND circuit 60 receives the feedback signal, which is the firing signal output from the subsequent neuron circuit 34, and the timer signal. The second AND circuit 60 calculates the logical product of the feedback signal and the timer signal. The second AND circuit 60 outputs the result of the logical product of the feedback signal and the timer signal as a decrease instruction signal.

[0085] The update circuit 48 configured as described above can output an increase instruction signal when the time difference (Δt) from the time the input signal changes from 0 to 1 to the time the feedback signal changes from 0 to 1 is smaller than a predetermined time T. Furthermore, the update circuit 48 can output a decrease instruction signal when the time difference (Δt) from the time the feedback signal changes from 0 to 1 is equal to or greater than the predetermined time T.

[0086] The probability control circuit 46 includes a first increasing probability circuit 62 , a first decreasing probability circuit 64 , a third AND circuit 66 , and a fourth AND circuit 68 .

[0087] The first increasing probability circuit 62 and the first decreasing probability circuit 64 receive a random signal from any one of the plurality of random number circuits 24. For example, the random signal represents a random number within a numerical range from 0 to (N-1), and the value changes periodically.

[0088] Based on the received random signal, the first increase probability circuit 62 generates a first increase probability signal that becomes 1 with a probability of p1, which is a preset first increase probability, and becomes 0 with a probability of (1-p1). p1 is a value greater than 0 and less than 1.

[0089] The first increase probability circuit 62 generates a first increase probability signal that is 1 when the value represented by the random signal is smaller than (p1×N) or larger than (N-p1×N), and is 0 in other cases. Alternatively, the first increase probability circuit 62 may generate a first increase probability signal that is 1 when the value represented by the random signal is one of P1 pre-selected values, and is 0 in other cases. P1 is an integer obtained by rounding down or rounding up the decimal point of (p1×N).

[0090] Based on the received random signal, the first decrease probability circuit 64 generates a first decrease probability signal that becomes 1 with a probability of q1, which is a preset first decrease probability, and becomes 0 with a probability of (1-q1). q1 is a value greater than 0 and less than 1.

[0091] In this case, the first decrease probability circuit 64 generates a first decrease probability signal that is 1 when the value represented by the random signal is smaller than (q1×N) or larger than (N-q1×N), and is 0 in other cases. Alternatively, the first decrease probability circuit 64 may generate a first decrease probability signal that is 1 when the value represented by the random signal is one of Q1 pre-selected values, and is 0 in other cases. Q1 is an integer obtained by rounding down or rounding up the decimal point of (q1×N).

[0092] The third AND circuit 66 receives the increase instruction signal and the first increase probability signal output from the update circuit 48. The third AND circuit 66 calculates the logical product of the increase instruction signal and the first increase probability signal. The third AND circuit 66 outputs the result of the logical product of the increase instruction signal and the first increase probability signal to the set terminal of the memory circuit 42 as the increase instruction signal.

[0093] The fourth AND circuit 68 receives the decrease instruction signal and the first decrease probability signal output from the update circuit 48. The fourth AND circuit 68 calculates the logical product of the decrease instruction signal and the first decrease probability signal. The fourth AND circuit 68 outputs the result of the logical product of the decrease instruction signal and the first decrease probability signal to the reset terminal of the memory circuit 42 as the decrease instruction signal.

[0094] The probability control circuit 46 can provide the increase instruction signal output from the update circuit 48 to the memory circuit 42 with a probability of p1 and mask the increase instruction signal with a probability of 1-p1. This allows the probability control circuit 46 to permit the update circuit 48 to change the synaptic weight in an increasing direction with a first increase probability p1 generated based on a random signal. The probability control circuit 46 can prohibit the update circuit 48 from changing the synaptic weight in an increasing direction except when it permits the change in the synaptic weight in an increasing direction.

[0095] Furthermore, the probability control circuit 46 can provide the decrease instruction signal output from the update circuit 48 to the memory circuit 42 with a probability of q1 and mask the decrease instruction signal with a probability of 1-q1. This allows the probability control circuit 46 to permit the update circuit 48 to change the synaptic weight in a decreasing direction with a second decrease probability q2 generated based on a random signal. The probability control circuit 46 can prohibit the change of the synaptic weight in a decreasing direction except when permitting the change of the synaptic weight in a decreasing direction.

[0096] FIG. 10 is a diagram showing an example of the configuration of the storage circuit 42, the update circuit 48, and the probability control circuit 46 when synaptic weights are updated according to a probabilistic update rule based on Fusi's rule.

[0097] When synaptic weights are updated according to a probabilistic update rule based on Fusi's rule, the memory circuit 42 and the probability control circuit 46 have the same configuration as shown in FIG.

[0098] When synaptic weights are updated according to a probabilistic update rule based on Fusi's rule, the update circuit 48 includes a second inversion circuit 70, a fifth AND circuit 72, and a sixth AND circuit 74.

[0099] The second inversion circuit 70 receives a feedback signal, which is an internal potential signal output from the subsequent neuron circuit 34. The second inversion circuit 70 outputs an inverted feedback signal obtained by inverting the value of the feedback signal.

[0100] The fifth AND circuit 72 receives the input signal output from the previous neuron circuit 32 and the feedback signal. The fifth AND circuit 72 calculates the logical product of the input signal and the feedback signal. The fifth AND circuit 72 outputs the result of the logical product of the input signal and the feedback signal as an increase instruction signal.

[0101] The sixth AND circuit 74 receives the input signal output from the previous neuron circuit 32 and the inverted feedback signal. The sixth AND circuit 74 calculates the logical product of the input signal and the inverted feedback signal. The sixth AND circuit 74 outputs the result of the logical product of the input signal and the inverted feedback signal as a decrease instruction signal.

[0102] The update circuit 48 configured as above can output an update instruction signal to increase the synapse weight when the input signal is 1 and the feedback signal is 1. Furthermore, the update circuit 48 can output an update instruction signal to decrease the synapse weight when the input signal is 0 and the feedback signal is 1.

[0103] FIG. 11 shows an MNIST handwritten character and a spiking neural network.

[0104] Here, we consider training a spiking neural network on MNIST handwritten characters of 784 (=28 × 28) pixels. The spiking neural network under consideration includes an input layer and a processing layer following the input layer. The input layer includes 784 neurons. The processing layer includes 400 neurons. The 784 neurons in the input layer and the 400 neurons in the processing layer are connected via multiple synapses.

[0105] The 784 neurons in the input layer capture the contrast of 784 pixels in the MNIST handwritten characters, generate spike trains with spike densities corresponding to the contrast of the 784 pixels, and send voltage spikes via synapses to each of the 400 neurons in the processing layer.

[0106] The update rule for synaptic weights in the spiking neural network under consideration is a probabilistic update rule that follows the STDP shown in Figure 5. The probability p of increasing a synaptic weight from 0 to 1 is, for example, about 0.01. The probability q of decreasing a synaptic weight from 1 to 0 is, for example, about 0.001. Furthermore, the spiking neural network under consideration is designed to prevent multiple neurons from firing simultaneously.

[0107] Furthermore, each of the multiple synapses in the spiking neural network under consideration controls its probability based on a random signal generated by a probability generator.

[0108] FIG. 12 shows the results of a simulation of the recognition rate when the spiking neural network shown in FIG. 11 is configured such that all of the multiple synapses receive random signals from independent probability generators.

[0109] The spiking neural network shown in Figure 11 was configured so that all of the multiple synapses received random signals from independent probability generators. When this type of spiking neural network was trained on MNIST handwritten characters and used for pattern recognition, the recognition rate relative to the number of training attempts exceeded 80%, as shown in Figure 12.

[0110] FIG. 13 shows the results of a simulation of the recognition rate when the spiking neural network shown in FIG. 11 is configured such that all of the multiple synapses receive random signals from a single common probability generator.

[0111] The spiking neural network shown in Figure 11 is configured so that all of the multiple synapses receive random signals from a single, common probability generator. When this type of spiking neural network is trained on MNIST handwritten characters and used for pattern recognition, the recognition rate relative to the number of training rounds never exceeds 70%, as shown in Figure 13. Furthermore, in this case, the recognition rate relative to the number of training rounds is unstable. Therefore, in this case, the spiking neural network cannot train correctly.

[0112] The random signal varies over time. Each of the multiple synapses updates its weight at a different timing. Therefore, even in the case shown in FIG. 13, the probability signal indicating whether to permit or prohibit updating of the synapse weight at the update timing differs for each of the multiple synapses.

[0113] From the above, when comparing Figures 12 and 13, in a spiking neural network that employs an update rule for probabilistically updating synaptic weights, it is preferable that all of the multiple synapses be probability-controlled based on random signals generated by mutually independent probability generators.

[0114] A probability generator generates a random signal that changes randomly over time. A pseudorandom number generator is known as such a probability generator. A linear feedback shift register (LFSR) circuit, a typical pseudorandom number generator, can be created using common silicon CMOS digital circuit technology. An LFSR circuit uses many shift registers. Therefore, an LFSR circuit contains a large number of transistors and has a large footprint.

[0115] Therefore, a spiking neural network implemented in hardware, which has independent LFSR circuits for each of the multiple synapses, would require a large circuit scale. For example, if the probability of synaptic weight update is approximately 0.001, the LFSR circuit must have a period of 1023 or more. An LFSR circuit with a period of 1023 or more requires approximately 160 transistors when implemented in hardware. The number of transistors in this LFSR circuit is significantly larger than the number of transistors in the circuit for synaptic signal transmission. Therefore, when implementing a spiking neural network in hardware that employs an update rule that probabilistically updates synaptic weights, it is desirable to reduce the number of probability generators and the circuit scale.

[0116] FIG. 14 is a diagram showing a first connection example in the neural network device 10 according to the first embodiment.

[0117] The plurality of synapse circuits 20 are divided into a plurality of synapse groups 80. Each of the plurality of synapse groups 80 includes two or more synapse circuits 20. Each of the plurality of synapse groups 80 corresponds to one of the plurality of random number circuits 24.

[0118] Each of the two or more synapse circuits 20 belonging to any one of the multiple synapse groups 80 receives a random signal output from one of the multiple random number circuits 24. That is, each of the two or more synapse circuits 20 belonging to the same synapse group 80 receives a random signal output from the same random number circuit 24. For example, each of the two or more synapse circuits 20 belonging to a first synapse group 80-1 of the multiple synapse groups 80 receives a random signal output from a first random number circuit 24-1 of the multiple random number circuits 24.

[0119] Furthermore, each of the multiple neuron circuits 22 receives two or more synapse signals from two or more synapse circuits 20 that belong to mutually different synapse groups 80. That is, each of the two or more synapse circuits 20 that output an output signal to any one of the multiple neuron circuits 22 belongs to a mutually different synapse group 80. For example, each of the two or more synapse circuits 20 that output an output signal to a first neuron circuit 22-1 of the multiple neuron circuits 22 belongs to a synapse group 80 that is different from the other synapse circuits 20 that output an output signal to the first neuron circuit 22-1.

[0120] In the neural network device 10 according to the first embodiment, attention is focused on one arbitrary neuron circuit 22. The neuron circuit 22 in question learns the informational relationships with the multiple preceding neuron circuits 32 connected thereto by adjusting the synaptic weights. In this case, each of the multiple preceding neuron circuits 32 has information independent of each other. Therefore, the neuron circuit 22 in question must not learn the informational relationships with each of the multiple preceding neuron circuits 32 in synchronization with each other, but must learn them independently of each other.

[0121] In the neural network device 10 according to the first embodiment, each of the two or more synapse circuits 20 that output an output signal to the first neuron circuit 22-1 belongs to a synapse group 80 that is different from the other synapse circuits 20 that output an output signal to the first neuron circuit 22-1. Therefore, each of the two or more synapse circuits 20 that output an output signal to the first neuron circuit 22-1 probabilistically updates its synapse weight based on a random signal output from a random number circuit 24 that is different from the other synapse circuits 20 that output an output signal to the first neuron circuit 22-1. Therefore, the neural network device 10 according to the first embodiment can independently learn the informational associations between the first neuron circuit 22-1 and each of the plurality of preceding neuron circuits 32. This allows the neural network device 10 according to the first embodiment to appropriately learn the synapse weights to be set for each of the plurality of synapse circuits 20.

[0122] Furthermore, the neural network device 10 according to the first embodiment includes a random number circuit 24 for each of the plurality of synapse groups 80. Therefore, the neural network device 10 according to the first embodiment can reduce the number of the plurality of synapse circuits 20, and can be realized with a small circuit scale.

[0123] FIG. 15 is a diagram showing a second connection example in the neural network device 10 according to the first embodiment.

[0124] The neural network device 10 according to the first embodiment may, for example, have a plurality of synapse circuits 20 arranged three-dimensionally in a plurality of layers. Furthermore, the neural network device 10 has two or more neuron circuits 22 arranged in each of the plurality of layers.

[0125] In this case, each of the multiple synapse circuits 20 supplies an output signal to the neuron circuit 22 arranged in the same layer. Also, each of the multiple synapse circuits 20 may receive, as an input signal, a firing signal output from the same neuron circuit 22 by two or more synapse circuits 20 arranged in the same layer.

[0126] In this case, each of the plurality of synapse groups 80 includes two or more synapse circuits 20 arranged in different layers.

[0127] The neural network device 10 according to the second connection example of the first embodiment can have a plurality of random number circuits 24 arranged in a layer different from the layer in which the synapse circuits 20 are arranged. Each of the plurality of random number circuits 24 can supply a random signal to two or more synapse circuits 20 by passing it through a plurality of layers.

[0128] In the neural network device 10 according to the second connection example of the first embodiment, the plurality of synapse circuits 20, the plurality of neuron circuits 22, and the plurality of random number circuits 24 can be arranged efficiently.

[0129] FIG. 16 is a diagram showing a third connection example in the neural network device 10 according to the first embodiment.

[0130] The third connection example of the first embodiment has substantially the same configuration as the first connection example shown in Fig. 14. Therefore, for the third connection example of the first embodiment, differences from the first connection example shown in Fig. 14 will be described.

[0131] In the third connection example, each of two or more synapse circuits 20 belonging to any one of the plurality of synapse groups 80 receives, as an input signal, a firing signal output from one of the plurality of neuron circuits 22. That is, each of two or more synapse circuits 20 belonging to the same synapse group 80 receives, as an input signal, a firing signal output from the same neuron circuit 22.

[0132] For example, each of the two or more synapse circuits 20 belonging to a first synapse group 80-1 among the N synapse groups 80 receives, as an input signal, a firing signal output from a second neuron circuit 22-2 among the plurality of neuron circuits 22.

[0133] The neural network device 10 according to the third connection example of the first embodiment can efficiently connect the wiring that transmits the input signals.

[0134] FIG. 17 is a diagram showing a fourth connection example in the neural network device 10 according to the first embodiment.

[0135] The fourth connection example of the first embodiment has substantially the same configuration as the second connection example shown in Fig. 15. Therefore, for the fourth connection example of the first embodiment, differences from the second connection example shown in Fig. 15 will be described.

[0136] In the fourth connection example, each of two or more synapse circuits 20 belonging to any one of the plurality of synapse groups 80 receives, as an input signal, a firing signal output from one of the plurality of neuron circuits 22. That is, each of two or more synapse circuits 20 belonging to the same synapse group 80 receives, as an input signal, a firing signal output from the same neuron circuit 22.

[0137] The neural network device 10 according to the fourth connection example of the first embodiment can efficiently arrange a plurality of synapse circuits 20, a plurality of neuron circuits 22, and a plurality of random number circuits 24, and can efficiently connect the wiring that transmits input signals.

[0138] Furthermore, in the fourth connection example, each of the plurality of synapse groups 80 includes two or more synapse circuits 20 that are included in the same layer and output signals to different neuron circuits 22. This allows the neural network device 10 in the fourth connection example according to the first embodiment to further reduce the number of the plurality of random number circuits 24.

[0139] Fig. 18 shows the results of a simulation of the recognition rate of the neural network device 10 in the first embodiment. Line A in Fig. 18 represents the recognition rate when the spiking neural network shown in Fig. 11 is configured according to the third connection example of the first embodiment. Line B in Fig. 18 represents the recognition rate when the spiking neural network shown in Fig. 11 is configured so that all of the multiple synapses receive random signals from independent probability generators.

[0140] When a spiking neural network configured according to the third connection example of the first embodiment is trained on MNIST handwritten characters and pattern recognized, the recognition rate relative to the number of training attempts approaches 80%, as shown in FIG. 18A. The recognition rate in FIG. 18A is lower than the recognition rate shown in FIG. 18B, where all of the multiple synapses receive random signals from independent probability generators, but the values ​​are very close. The recognition rate in FIG. 18A is stable even with respect to the number of training attempts. Therefore, the spiking neural network of FIG. 11 configured according to the third connection example of the first embodiment can train with high accuracy.

[0141] Fig. 19 shows the number of transistors relative to the number of neurons. A in Fig. 19 shows the number of transistors in a spiking neural network configured according to the third connection example of the first embodiment. B in Fig. 19 shows the number of transistors in a spiking neural network configured such that all of the multiple synapses receive random signals from independent probability generators. C in Fig. 19 is (B-A) / A, which indicates the reduction ratio of the number of transistors.

[0142] For example, the synapse circuit 20 shown in Figure 9 or 10 can be configured with approximately 40 transistors. When the synapse circuit 20 shown in Figure 10 is employed, each of the neuron circuits 22 includes a comparator circuit for comparing the magnitude of the internal potential with a threshold potential. The comparator circuit can be configured with approximately 16 transistors.

[0143] Furthermore, each of the multiple random number circuits 24 according to the first embodiment is an LFSR circuit with a period of 1023. Furthermore, in the spiking neural network shown in Fig. 11, in which multiple synapses all receive random signals from independent probability generators, the probability generators are also LFSR circuits with a period of 1023. An LFSR circuit with a period of 1023 can be configured using approximately 160 transistors.

[0144] The number of neurons in the input layer of the spiking neural network shown in FIG. 11 is set to n (n is an integer equal to or greater than 2).

[0145] In this case, the number of transistors required to configure the spiking neural network shown in Fig. 11 is smaller in the configuration according to the third connection example of the first embodiment (Fig. 19A) than in the configuration in which all of the multiple synapses receive random signals from independent probability generators (Fig. 19B). The reduction rate is about 20%, as shown in Fig. 19C.

[0146] As described above, the neural network device 10 according to the first embodiment is a spiking neural network configured with hardware, and is capable of updating synaptic weights using a probabilistic update rule. Furthermore, the neural network device 10 according to the first embodiment appropriately arranges the random number circuits 24 while reducing the number thereof, thereby enabling accurate learning with a small circuit scale. As a result, the neural network device 10 according to the first embodiment is capable of performing accurate inference with a small circuit scale.

[0147] (Second embodiment) Next, a neural network device 10 according to the second embodiment will be described. Since the neural network device 10 according to the second embodiment has substantially the same functions and configuration as the first embodiment, elements having substantially the same functions and configurations are denoted by the same reference numerals, and detailed descriptions thereof will be omitted except for the differences.

[0148] 20 is a diagram showing an example of the configuration of a neural network device 10 according to the second embodiment. As an example, the neural network device 10 according to the second embodiment includes N-stage (N is an integer equal to or greater than 2) layers 12, (N-1) synapse units 14, a random number generation unit 16, and an additional random number generation unit 86. That is, compared to the configuration of the first embodiment shown in FIG. 1, the neural network device 10 according to the second embodiment further includes an additional random number generation unit 86.

[0149] The additional random number generation unit 86 includes a plurality of additional random number circuits 88. Each of the plurality of additional random number circuits 88 outputs an additional random signal representing a random number that changes periodically. Each of the plurality of additional random number circuits 88 is independent in terms of circuitry from the other additional random number circuits 88 and the plurality of random number circuits 24, and generates an additional random signal representing a random number different from those of the plurality of random number circuits 24 and the other additional random number circuits 88. Each of the plurality of additional random number circuits 88 is, for example, a pseudo-random number generation circuit.

[0150] The random number represented by the additional random signal is a value within a predetermined range, for example, a value within a 10-bit range (0 to 1023).

[0151] The multiple additional random number circuits 88 correspond to any one of the multiple neuron circuits 22. For example, there is a one-to-one correspondence between the multiple additional random number circuits 88 and the multiple neuron circuits 22. Note that each of the multiple additional random number circuits 88 may correspond to two or more neuron circuits 22. However, each of the multiple neuron circuits 22 corresponds to any one of the multiple additional random number circuits 88.

[0152] Although FIG. 20 shows a layered neural network device 10, the neural network device 10 according to the second embodiment may be a recurrent neural network as shown in FIG.

[0153] FIG. 21 is a diagram showing the connection relationship between the synapse circuit 20 according to the second embodiment and other circuits.

[0154] Each of the plurality of synapse circuits 20 further receives an additional random signal output from any one of the plurality of additional random number circuits 88. For example, each of the plurality of synapse circuits 20 receives an additional random signal from an additional random number circuit 88, among the plurality of additional random number circuits 88, that corresponds to the neuron circuit 22 from which it outputs an output signal. In other words, each of the plurality of additional random number circuits 88 outputs an additional random signal to two or more synapse circuits 20 from which the corresponding neuron circuit 22 receives an output signal, among the plurality of synapse circuits 20.

[0155] Each of the plurality of synapse circuits 20 probabilistically updates the set synapse weight in accordance with a predetermined synapse update rule, using a probability obtained by multiplying a predetermined first probability generated based on the received random signal by a predetermined second probability generated based on the additional random signal. The first probability is greater than the second probability.

[0156] Note that while Figure 21 shows the connection relationship between the synapse circuit 20 and other circuits when synaptic weights are updated using a probabilistic update rule based on STDP, the connection relationship between the additional random number circuit 88 and the synapse circuit 20 is similar in the case of the Fusi rule.

[0157] 22 is a diagram showing the configuration of a synapse circuit 20 according to the second embodiment. In the second embodiment, the probability control circuit 46 receives an additional random signal from any one of the multiple additional random number circuits 88.

[0158] The probability control circuit 46 permits updating of synaptic weights with a probability obtained by multiplying a first probability generated based on the received random signal by a second probability generated based on the received additional random signal, and prohibits updating of synaptic weights except when updating of synaptic weights is permitted.

[0159] For example, the random signal represents a random number within a range of values ​​from a first predetermined lower limit value to a first predetermined upper limit value, and the additional random signal represents a random number within a range of values ​​from a second predetermined lower limit value to a second predetermined upper limit value.

[0160] In this case, the probability control circuit 46 allows the update of the synaptic weights when the random signal has a value within a range corresponding to a predetermined first probability and the additional random signal has a value within a range corresponding to a predetermined second probability, and prohibits the update of the synaptic weights when the random signal does not have a value within a range corresponding to the predetermined first probability or when the additional random signal does not have a value within a range corresponding to the predetermined second probability.

[0161] FIG. 23 is a diagram showing an example of the configuration of the probability control circuit 46 according to the second embodiment.

[0162] The probability control circuit 46 according to the second embodiment includes a first increase probability circuit 62, a first decrease probability circuit 64, a third AND circuit 66, a fourth AND circuit 68, a second increase probability circuit 90, a second decrease probability circuit 92, a seventh AND circuit 94, and an eighth AND circuit 96. That is, compared to the configuration of the first embodiment shown in FIG. 9 , the probability control circuit 46 according to the second embodiment further includes a second increase probability circuit 90, a second decrease probability circuit 92, a seventh AND circuit 94, and an eighth AND circuit 96.

[0163] The second increasing probability circuit 90 and the second decreasing probability circuit 92 receive an additional random signal from any one of the multiple additional random number circuits 88. For example, the additional random signal represents a random number within a numerical range from 0 to (N-1), and the value changes periodically.

[0164] The second increase probability circuit 90 generates a second increase probability signal that becomes 1 at a preset second increase probability p2 and becomes 0 with a probability of (1-p2), based on the received additional random signal. p2 is a value greater than 0 and less than 1.

[0165] The second increase probability circuit 90 generates a second increase probability signal that is 1 when the value represented by the additional random signal is smaller than (p2 × N) or larger than (N - p2 × N), and is 0 in other cases. Alternatively, the second increase probability circuit 90 may generate a second increase probability signal that is 1 when the value represented by the additional random signal is one of P2 preselected values, and is 0 in other cases. P2 is an integer obtained by rounding down or rounding up the decimal point of (p2 × N).

[0166] The second decrease probability circuit 92 generates a second decrease probability signal that becomes 1 at a preset second decrease probability q2 and becomes 0 with a probability of (1-q2), based on the received additional random signal. q2 is a value greater than 0 and less than 1.

[0167] In this case, the second reduction probability circuit 92 generates a second reduction probability signal that is 1 when the value represented by the additional random signal is smaller than (q2 × N) or larger than (N - q2 × N), and is 0 in other cases. Alternatively, the second reduction probability circuit 92 may generate a second reduction probability signal that is 1 when the value represented by the additional random signal is one of Q2 pre-selected values, and is 0 in other cases. Note that Q2 is an integer obtained by rounding down or rounding up the decimal point of (q2 × N).

[0168] The seventh AND circuit 94 receives the signal output from the third AND circuit 66 and the second increase probability signal. The seventh AND circuit 94 calculates the logical product of the signal output from the third AND circuit 66 and the second increase probability signal. The seventh AND circuit 94 outputs the result of the logical product of the signal output from the third AND circuit 66 and the second increase probability signal to the set terminal of the memory circuit 42 as an increase instruction signal.

[0169] The eighth AND circuit 96 receives the signal output from the fourth AND circuit 68 and the second decrease probability signal. The eighth AND circuit 96 calculates the logical product of the signal output from the fourth AND circuit 68 and the second decrease probability signal. The eighth AND circuit 96 outputs the result of the logical product of the signal output from the fourth AND circuit 68 and the second decrease probability signal to the reset terminal of the memory circuit 42 as a decrease instruction signal.

[0170] The probability control circuit 46 according to the second embodiment provides the increase instruction signal output from the update circuit 48 to the memory circuit 42 with a probability of (p1×p2) and can mask the increase instruction signal with a probability of 1-(p1×p2). This allows the probability control circuit 46 to permit the update circuit 48 to change the synaptic weight in an increasing direction with a probability obtained by multiplying the first increase probability p1 generated based on the random signal by the second increase probability p2 generated based on the additional random signal. The probability control circuit 46 can prohibit the update circuit 48 from changing the synaptic weight in an increasing direction except when it permits the change in the synaptic weight in an increasing direction.

[0171] Furthermore, the probability control circuit 46 can provide the decrease instruction signal output from the update circuit 48 to the memory circuit 42 with a probability of (q1×q2) and mask the decrease instruction signal with a probability of 1-(q1×q2). This allows the probability control circuit 46 to permit the update circuit 48 to change the synaptic weight in a decreasing direction with a probability obtained by multiplying a first decrease probability q1 generated based on a random signal by a second decrease probability q2 generated based on an additional random signal. The probability control circuit 46 can prohibit the change of the synaptic weight in a decreasing direction except when permitting the change of the synaptic weight in a decreasing direction.

[0172] FIG. 24 is a diagram showing a first connection example in the neural network device 10 according to the second embodiment.

[0173] Each of the plurality of neuron circuits 22 corresponds to any one of the plurality of additional random number circuits 88. For example, the plurality of neuron circuits 22 correspond to the plurality of additional random number circuits 88 in a one-to-one relationship.

[0174] Each of the multiple additional random number circuits 88 supplies an additional random signal to two or more synapse circuits 20 that supply an output signal to a corresponding neuron circuit 22 among the multiple neuron circuits 22. That is, each of the two or more synapse circuits 20 that belong to any one of the multiple synapse groups 80 receives an additional random signal from a different additional random number circuit 88.

[0175] This allows each of the plurality of synapse circuits 20 to update its synapse weight independently of other synapse circuits 20 belonging to the same synapse group 80 in terms of probability.

[0176] FIG. 25 is a diagram showing a second connection example in the neural network device 10 according to the second embodiment.

[0177] The neural network device 10 according to the second embodiment may, for example, have a plurality of synapse circuits 20 arranged three-dimensionally in a plurality of layers.

[0178] In the neural network device 10 according to the second connection example of the second embodiment, the multiple synapse circuits 20, the multiple neuron circuits 22, and the multiple random number circuits 24 are arranged in the same manner as in the second connection example of the first embodiment of FIG. 15.

[0179] In the second connection example of the second embodiment, a plurality of additional random number circuits 88 are arranged in each of a plurality of layers in correspondence with a plurality of neuron circuits 22.

[0180] In this case, each of the multiple synapse circuits 20 supplies an output signal to the neuron circuit 22 arranged in the same layer. Also, each of two or more synapse circuits 20 arranged in the same layer may receive an ignition signal output from the same neuron circuit 22 as an input signal.

[0181] In this case, each of the plurality of synapse groups 80 includes two or more synapse circuits 20 arranged in different layers.

[0182] The neural network device 10 according to the second connection example of the second embodiment can have a plurality of random number circuits 24 arranged in a layer different from the layer in which the synapse circuits 20 are arranged. Each of the plurality of random number circuits 24 supplies a random signal to two or more corresponding synapse circuits 20, passing through a plurality of layers.

[0183] The neural network device 10 according to the second connection example of the second embodiment can efficiently arrange a plurality of synapse circuits 20, a plurality of neuron circuits 22, a plurality of random number circuits 24, and a plurality of additional random number circuits 88.

[0184] FIG. 26 is a diagram showing a third connection example in the neural network device 10 according to the second embodiment.

[0185] The third connection example of the second embodiment has substantially the same configuration as the fourth connection example of the first embodiment shown in Fig. 17. Therefore, the third connection example of the second embodiment will be described focusing on the differences from the fourth connection example of the first embodiment shown in Fig. 17.

[0186] In the third connection example of the second embodiment, a plurality of additional random number circuits 88 are arranged in each of a plurality of layers in correspondence with a plurality of neuron circuits 22.

[0187] In this case, each of the multiple synapse circuits 20 supplies an output signal to a neuron circuit 22 arranged in the same layer. Furthermore, each of two or more synapse circuits 20 arranged in the same layer receives an ignition signal output from the same neuron circuit 22 as an input signal.

[0188] The neural network device 10 according to the third connection example of the second embodiment can have a plurality of random number circuits 24 arranged in a layer different from the layer in which the synapse circuits 20 are arranged. Each of the plurality of random number circuits 24 supplies a random signal to two or more corresponding synapse circuits 20, passing through a plurality of layers.

[0189] The neural network device 10 according to the third connection example of the second embodiment can efficiently arrange the multiple synapse circuits 20, the multiple neuron circuits 22, the multiple random number circuits 24, and the multiple additional random number circuits 88. Furthermore, the neural network device 10 according to the third connection example of the second embodiment can efficiently connect the wiring that transmits the input signals.

[0190] Moreover, in the third connection example of the second embodiment, each of the plurality of synapse groups 80 includes two or more synapse circuits 20 arranged in different layers. Furthermore, each of the plurality of synapse groups 80 includes two or more synapse circuits 20 that output signals to different neuron circuits 22 included in the same layer. This allows the neural network device 10 according to the third connection example of the second embodiment to further reduce the number of the plurality of random number circuits 24.

[0191] Fig. 27 shows the results of a simulation of the recognition rate of the neural network device 10 in the second embodiment. Line A in Fig. 27 represents the recognition rate when the spiking neural network shown in Fig. 11 is configured according to the third connection example of the second embodiment. Line B in Fig. 27 represents the recognition rate when the spiking neural network shown in Fig. 11 is configured so that all of the multiple synapses receive random signals from independent probability generators.

[0192] When a spiking neural network configured according to the third connection example of the second embodiment is trained on MNIST handwritten characters and pattern recognition is performed, the recognition rate for the number of training rounds is approximately 80%, as shown in A of Fig. 27. The recognition rate in A of Fig. 27 is approximately equivalent to the recognition rate when all of the multiple synapses receive random signals from independent probability generators, as shown in B of Fig. 27. Therefore, the spiking neural network of Fig. 11 configured according to the third connection example of the second embodiment can train with high accuracy.

[0193] The synapse circuit 20 according to the first embodiment stochastically updates synapse weights based on a random signal obtained from the random number circuit 24. In contrast, the synapse circuit 20 according to the second embodiment stochastically updates synapse weights based on two signals: a random signal obtained from the random number circuit 24 and an additional random signal obtained from the additional random number circuit 88. This increases the independence of the stochastic updating of synapse weights in each of the multiple synapse circuits 20 according to the second embodiment, improving learning accuracy.

[0194] However, the neural network device 10 according to the second embodiment has a larger circuit size than the first embodiment due to the addition of multiple additional random number circuits 88. However, in the spiking neural network shown in FIG. 11 , when an independent probability generator is provided for each synapse of the multiple synapse circuits 20, the number of probability generators is n × m. Here, n is the number of neurons included in the input layer, and m is the number of neurons included in the processing layer. In contrast, when the neural network device 10 according to the second embodiment is applied, the spiking neural network shown in FIG. 11 has n + m random number circuits 24 and multiple additional random number circuits 88. That is, while a squared probability generator was required for the network size in the conventional system, the neural network device 10 according to the second embodiment requires a linear number of random number generators for the network size. Therefore, the neural network device 10 according to the second embodiment significantly reduces the circuit size in a large-scale network.

[0195] FIG. 28 is a diagram showing the simulation results of the recognition rate of the neural network device 10 in the second embodiment when the first probability and the second probability are changed.

[0196] Line A in Fig. 28 represents the recognition rate when the spiking neural network shown in Fig. 11 is configured according to the third connection example of the second embodiment and the first probability is set larger than the second probability. Line B in Fig. 28 represents the recognition rate when the spiking neural network shown in Fig. 11 is configured according to the third connection example of the second embodiment and the second probability is set larger than the first probability.

[0197] Each of the multiple synapse circuits 20 probabilistically updates the set synapse weight in accordance with a predetermined synapse update rule using a probability obtained by multiplying a predetermined first probability generated based on the received random signal by a predetermined second probability generated based on an additional random signal.

[0198] In this embodiment, the first probability is set to be greater than the second probability. That is, each of the multiple synapse circuits 20 performs probability control by predominantly using the random signal output from the random number circuit 24 rather than the additional random signal output from the additional random number circuit 88. The additional random number circuit 88 is provided corresponding to the neuron circuit 22. Therefore, if each of the multiple synapse circuits 20 performs probability control by predominantly using the additional random signal, independence may be weakened, and learning accuracy may deteriorate. As shown in FIG. 28, the recognition rate is higher and more stable with respect to the number of learning iterations when the first probability is greater than the second probability (A in FIG. 28) than when the second probability is greater than the first probability (B in FIG. 28).

[0199] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0200] (Addendum) The above-described embodiments can be summarized as the following technical proposals.

[0201] [Technical proposal 1] Multiple neuronal circuits, Multiple synaptic circuits and A plurality of random number circuits; Equipped with each of the plurality of neuron circuits receives an output signal output from one or more synapse circuits of the plurality of neuron circuits, and outputs a firing signal in response to the received output signal; each of the plurality of random number circuits outputs a random signal representing a periodically changing random number; Each of the plurality of synapse circuits a memory circuit for storing synaptic weights; a transmission circuit that receives an input signal, which is the firing signal output from a preceding neuron circuit that is one of the plurality of neuron circuits, and outputs the output signal obtained by adding the influence of the synaptic weight to the received input signal to a succeeding neuron circuit that is one of the plurality of neuron circuits; a probability control circuit that receives the random signal from any one of the plurality of random number circuits, permits updating of the synaptic weights with a probability generated based on the received random signal, and prohibits updating of the synaptic weights except when the update of the synaptic weights is permitted; an update circuit that updates the synaptic weights in response to a feedback signal representing the operation or state of the subsequent neuron circuit, when receiving the input signal from the previous neuron circuit, on the condition that updating of the synaptic weights is permitted; Including, the plurality of synapse circuits are divided into a plurality of synapse groups; each of two or more synapse circuits belonging to a first synapse group among the plurality of synapse groups receives the random signal output from a first random number circuit among the plurality of random number circuits; Each of the two or more synapse circuits that outputs the output signal to a first neuron circuit among the plurality of neuron circuits belongs to a synapse group different from other synapse circuits that output the output signal to the first neuron circuit. Neural network device.

[0202] [Technical proposal 2] the random signal represents a random number within a numerical range from a predetermined lower limit value to a predetermined upper limit value; The probability control circuit permits updating of the synaptic weights when the random signal is a value within a range corresponding to a predetermined first probability, and prohibits updating of the synaptic weights when the random signal is not a value within the range corresponding to the first probability. A neural network device according to Technical Proposal 1.

[0203] [Technical proposal 3] Each of the two or more synapse circuits belonging to the first synapse group receives the input signal output from a second neuron circuit among the plurality of neuron circuits. A neural network device according to Technical Scheme 1 or 2.

[0204] [Technical proposal 4] Multiple additional random number circuits Furthermore, each of the plurality of additional random number circuits outputs an additional random signal representing a periodically changing random number; The probability control circuit further receiving the additional random signal from any one of the plurality of additional random number circuits; The synaptic weight is permitted to be updated at a probability obtained by multiplying a first probability generated based on the random signal by a predetermined second probability generated based on the additional random signal. A neural network device according to any one of technical proposals 1 to 3.

[0205] [Technical proposal 5] the additional random signal represents a random number within a numerical range from a predetermined lower limit value to a predetermined upper limit value; The probability control circuit permitting the update of the synaptic weight when the random signal is within a range of values ​​corresponding to the first probability and the additional random signal is within a range of values ​​corresponding to the second probability; If the random signal is not within a range of values ​​corresponding to the first probability, or if the additional random signal is not within a range of values ​​corresponding to the second probability, the update of the synaptic weight is prohibited. A neural network device according to Technical Proposal 4.

[0206] [Technical proposal 6] the plurality of additional random number circuits are provided in one-to-one correspondence with the plurality of neuron circuits, Each of the plurality of synapse circuits receives the additional random signal from an additional random number circuit, among the plurality of additional random number circuits, that corresponds to a neuron circuit that outputs the output signal. A neural network device according to Technical Scheme 4 or 5.

[0207] [Technical proposal 7] The first probability is greater than the second probability A neural network device according to any one of technical proposals 4 to 6.

[0208] [Technical proposal 8] the feedback signal is represented by a first value or a second value; The update circuit When the input signal is received in a state in which the feedback signal is at the first value, the synaptic weight is increased on condition that updating of the synaptic weight is permitted; When the input signal is received in a state in which the feedback signal is at the second value, the synaptic weight is decreased on condition that updating of the synaptic weight is permitted; The probability control circuit When the synaptic weight is changed in an increasing direction, updating of the synaptic weight is permitted with a predetermined first increase probability generated based on the random signal; When the synaptic weight is changed in a decreasing direction, updating of the synaptic weight is permitted with a predetermined first probability of decrease generated based on the random signal. A neural network device according to any one of technical proposals 1 to 3.

[0209] [Technical proposal 9] the feedback signal is represented by a first value or a second value; When the input signal is received in a state in which the feedback signal is at the first value, the update circuit increases the synaptic weights on condition that updating of the synaptic weights is permitted; When the input signal is received in a state in which the feedback signal is at the second value, the update circuit decreases the synaptic weight on condition that the synaptic weight is enabled; The update circuit When changing the synaptic weight in an increasing direction, allowing the synaptic weight to be updated with a probability obtained by multiplying a predetermined first increase probability generated based on the random signal by a predetermined second increase probability generated based on the additional random signal; When the synapse weight is changed in a decreasing direction, updating of the synapse weight is permitted at a probability obtained by multiplying a predetermined second decrease probability generated based on the random signal by a predetermined second decrease probability generated based on the additional random signal. A neural network device according to any one of technical proposals 4 to 7.

[0210] [Technical proposal 10] The synaptic weights are varied within a predetermined range of values; The memory circuit Do not change the synaptic weight to above the upper limit of the numerical range, The synaptic weight is not changed to a value below the lower limit of the numerical range. A neural network device according to Technical Solution 8 or 9.

[0211] [Technical proposal 11] The feedback signal has the first value for a certain period after the subsequent neuron circuit fires, and has the second value for another period. A neural network device according to any one of technical proposals 8 to 10.

[0212] [Technical proposal 12] Each of the plurality of neuron circuits holds an internal potential that changes depending on the level or time width of the received output signal, and outputs the firing signal when the internal potential is greater than a preset firing threshold value; The feedback signal has the first value when the internal potential held in the subsequent neuron circuit is equal to or greater than a predetermined value, and has the second value when the internal potential is smaller than the predetermined value. A neural network device according to any one of technical proposals 8 to 10.

[0213] [Technical proposal 13] The synaptic weights are represented by discrete values. A neural network device according to any one of technical proposals 1 to 12.

[0214] [Technical proposal 14] The synaptic weights are represented by binary A neural network device according to Technical Proposal 13.

[0215] [Technical proposal 15] At least one of the plurality of synapse circuits supplies the output signal to the preceding neuron circuit or to a neuron circuit that is arranged in a stage preceding the synapse circuit that supplies the output signal to the preceding neuron circuit. A neural network device according to any one of technical proposals 1 to 14.

[0216] [Technical proposal 16] A synaptic weight update method executed in a neural network device, comprising: The neural network device comprises: Multiple neuronal circuits, Multiple synaptic circuits and A plurality of random number circuits; Equipped with each of the plurality of neuron circuits receives an output signal output from one or more synapse circuits of the plurality of neuron circuits, and outputs a firing signal in response to the received output signal; each of the plurality of random number circuits outputs a random signal representing a periodically changing random number; Each of the plurality of synapse circuits a memory circuit for storing synaptic weights; a transmission circuit that receives an input signal, which is the firing signal output from a preceding neuron circuit that is one of the plurality of neuron circuits, and outputs the output signal obtained by adding the influence of the synaptic weight to the received input signal to a succeeding neuron circuit that is one of the plurality of neuron circuits; Including, the plurality of synapse circuits are divided into a plurality of synapse groups; each of two or more synapse circuits belonging to a first synapse group among the plurality of synapse groups receives the random signal output from a first random number circuit among the plurality of random number circuits; each of the two or more synapse circuits that outputs the output signal to a first neuron circuit among the plurality of neuron circuits belongs to a synapse group different from other synapse circuits that output the output signal to the first neuron circuit; Each of the plurality of synapse circuits receiving the random signal from any one of the plurality of random number circuits, permitting updating of the synaptic weights with a probability generated based on the received random signal, and prohibiting updating of the synaptic weights except when the update of the synaptic weights is permitted; When the input signal is received from the preceding neuron circuit, the synaptic weight is updated in response to a feedback signal representing the operation or state of the succeeding neuron circuit, provided that updating of the synaptic weight is permitted. Synaptic weight update method. [Explanation of symbols]

[0217] 10 Neural network device 12 layers 14 Synapse 16 Random number generator 20 Synaptic Circuits 22 Neuron Circuits 24 Random Number Circuit 26 Reservoir Computing Device 32 Front-stage neuron circuit 34 Post-neuron circuit 42 Memory circuit 44 Transmission Circuit 46 Probability Control Circuit 48 Update circuit 52 SR latch 54 Timer Circuit 56 First Inverter 58 1st AND circuit 60 2nd AND circuit 62 First increasing probability circuit 64 First Reduced Probability Circuit 66 3rd AND circuit 68 4th AND circuit 70 Second inverting circuit 72 5th AND circuit 74 6th AND circuit 80 Synapse Group 86 Additional random number generator 88 Additional random number circuit

Claims

1. Multiple neuronal circuits, Multiple synaptic circuits and A plurality of random number circuits; Equipped with each of the plurality of neuron circuits receives an output signal output from one or more synapse circuits among the plurality of neuron circuits, and outputs a firing signal in response to the received output signal; each of the plurality of random number circuits outputs a random signal representing a periodically changing random number; Each of the plurality of synapse circuits a memory circuit for storing synaptic weights; a transmission circuit that receives an input signal, which is the firing signal output from a preceding neuron circuit that is any one of the plurality of neuron circuits, and outputs the output signal obtained by adding the influence of the synaptic weight to the received input signal to a succeeding neuron circuit that is any one of the plurality of neuron circuits; a probability control circuit that receives the random signal from any one of the plurality of random number circuits, permits updating of the synaptic weights with a probability generated based on the received random signal, and prohibits updating of the synaptic weights except when the update of the synaptic weights is permitted; an update circuit that updates the synaptic weights in response to a feedback signal representing the operation or state of the subsequent neuron circuit, when receiving the input signal from the previous neuron circuit, on the condition that updating of the synaptic weights is permitted; Including, the plurality of synapse circuits are divided into a plurality of synapse groups; each of two or more synapse circuits belonging to a first synapse group among the plurality of synapse groups receives the random signal output from a first random number circuit among the plurality of random number circuits; Each of the two or more synapse circuits that outputs the output signal to a first neuron circuit among the plurality of neuron circuits belongs to a synapse group different from other synapse circuits that output the output signal to the first neuron circuit. Neural network device.

2. the random signal represents a random number within a numerical range from a predetermined lower limit value to a predetermined upper limit value; The probability control circuit permits updating of the synaptic weights when the random signal is a value within a range corresponding to a predetermined first probability, and prohibits updating of the synaptic weights when the random signal is not a value within the range corresponding to the first probability.

2. The neural network device according to claim 1.

3. Each of the two or more synapse circuits belonging to the first synapse group receives the input signal output from a second neuron circuit among the plurality of neuron circuits.

2. The neural network device according to claim 1.

4. Multiple additional random number circuits Furthermore, each of the plurality of additional random number circuits outputs an additional random signal representing a periodically changing random number; The probability control circuit further receiving the additional random signal from any one of the plurality of additional random number circuits; The synaptic weight is permitted to be updated at a probability obtained by multiplying a first probability generated based on the random signal by a predetermined second probability generated based on the additional random signal.

2. The neural network device according to claim 1.

5. the additional random signal represents a random number within a numerical range from a predetermined lower limit value to a predetermined upper limit value; The probability control circuit permitting the synaptic weight to be updated when the random signal is within a range of values ​​corresponding to the first probability and the additional random signal is within a range of values ​​corresponding to the second probability; If the random signal is not within a range of values ​​corresponding to the first probability, or if the additional random signal is not within a range of values ​​corresponding to the second probability, updating of the synaptic weight is prohibited.

5. The neural network device according to claim 4.

6. the plurality of additional random number circuits are provided in one-to-one correspondence with the plurality of neuron circuits, Each of the plurality of synapse circuits receives the additional random signal from an additional random number circuit, among the plurality of additional random number circuits, that corresponds to a neuron circuit that outputs the output signal.

5. The neural network device according to claim 4.

7. The first probability is greater than the second probability.

5. The neural network device according to claim 4.

8. the feedback signal is represented by a first value or a second value; The update circuit When the input signal is received in a state in which the feedback signal is at the first value, the synaptic weight is increased on condition that updating of the synaptic weight is permitted; When the input signal is received in a state in which the feedback signal is at the second value, the synaptic weight is decreased on condition that updating of the synaptic weight is permitted; The probability control circuit When the synaptic weight is changed in an increasing direction, updating of the synaptic weight is permitted with a predetermined first increase probability generated based on the random signal; When the synapse weight is changed in a decreasing direction, updating of the synapse weight is permitted with a predetermined first probability of decrease generated based on the random signal.

2. The neural network device according to claim 1.

9. the feedback signal is represented by a first value or a second value; When the input signal is received in a state in which the feedback signal is at the first value, the update circuit increases the synaptic weights on condition that updating of the synaptic weights is permitted; When the input signal is received in a state in which the feedback signal is at the second value, the update circuit decreases the synaptic weight on condition that the synaptic weight is enabled; The update circuit When changing the synapse weight in an increasing direction, updating of the synapse weight is permitted with a probability obtained by multiplying a predetermined first increase probability generated based on the random signal by a predetermined second increase probability generated based on the additional random signal; When the synapse weight is changed in a decreasing direction, updating of the synapse weight is permitted with a probability obtained by multiplying a predetermined second decrease probability generated based on the random signal by a predetermined second decrease probability generated based on the additional random signal.

5. The neural network device according to claim 4.

10. The synaptic weights are varied within a predetermined range of values; The memory circuit Do not change the synaptic weight to above the upper limit of the numerical range, The synaptic weight is not changed to a value below the lower limit of the numerical range.

9. The neural network device according to claim 8.

11. The feedback signal has the first value for a certain period after the subsequent neuron circuit fires, and has the second value for another period.

9. The neural network device according to claim 8.

12. Each of the plurality of neuron circuits holds an internal potential that changes depending on the level or duration of the received output signal, and outputs the firing signal when the internal potential is greater than a preset firing threshold value; The feedback signal has the first value when the internal potential held in the subsequent neuron circuit is equal to or greater than a predetermined value, and has the second value when the internal potential is smaller than the predetermined value.

9. The neural network device according to claim 8.

13. The synaptic weights are represented by discrete values.

2. The neural network device according to claim 1.

14. The synaptic weights are represented by binary 14. The neural network device of claim 13.

15. At least one of the plurality of synapse circuits supplies the output signal to the preceding neuron circuit or to a neuron circuit that is arranged in a stage preceding the synapse circuit that supplies the output signal to the preceding neuron circuit.

2. The neural network device according to claim 1.

16. A synaptic weight update method executed in a neural network device, comprising: The neural network device comprises: Multiple neuron circuits, Multiple synaptic circuits and A plurality of random number circuits; Equipped with each of the plurality of neuron circuits receives an output signal output from one or more synapse circuits among the plurality of neuron circuits, and outputs a firing signal in response to the received output signal; each of the plurality of random number circuits outputs a random signal representing a periodically changing random number; Each of the plurality of synapse circuits a memory circuit for storing synaptic weights; a transmission circuit that receives an input signal, which is the firing signal output from a preceding neuron circuit that is any one of the plurality of neuron circuits, and outputs the output signal obtained by adding the influence of the synaptic weight to the received input signal to a succeeding neuron circuit that is any one of the plurality of neuron circuits; Including, the plurality of synapse circuits are divided into a plurality of synapse groups; each of two or more synapse circuits belonging to a first synapse group among the plurality of synapse groups receives the random signal output from a first random number circuit among the plurality of random number circuits; each of two or more synapse circuits that outputs the output signal to a first neuron circuit among the plurality of neuron circuits belongs to a synapse group different from other synapse circuits that output the output signal to the first neuron circuit; Each of the plurality of synapse circuits receiving the random signal from any one of the plurality of random number circuits, permitting updating of the synaptic weights with a probability generated based on the received random signal, and prohibiting updating of the synaptic weights except when the update of the synaptic weights is permitted; When the input signal is received from the preceding neuron circuit, the synaptic weight is updated in response to a feedback signal representing the operation or state of the succeeding neuron circuit, provided that updating of the synaptic weight is permitted. Synaptic weight update method.

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