MEMORY STORAGE DEVICE HAVING CONFIGURABLE DATA TRANSFER TRIGGER - Patent application

Abstract

To provide a storage device that includes a configurable automatic data transfer trigger.SOLUTION: A storage device includes: a host interface to receive a host command from a host device via a storage interface; one or more memory conversion layers that execute one or more operations relevant to the host command, and retrieve one or more chunks of data relevant to the host command; a bitmap circuit that includes a bitmap tracking a constrained order of the one or more chunks of data to be transferred to the host device; and a transfer trigger that triggers a data transfer to the host device with respect to the one or more chunks of data in the constrained order according to a state of one or more bits of the bitmap.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One or more embodiments of the present invention relate to storage devices, and more particularly to storage devices having configurable data transfer triggers and methods including the same. [Background technology]

[0002] A storage system generally includes a host device and a storage device. The host device can access data stored in the storage device by sending commands to the storage device. For example, the host device can send a read command to the storage device to access data stored in one or more logical blocks of the storage device. In this case, the read command may include several phases, such as a command issuance phase, a data transfer phase, and a response phase. During the command issuance phase, the host device can issue a read command to the storage device so that the storage device can retrieve data associated with the read command stored in the logical blocks of the storage device. The storage device can send data corresponding to the read command to the host device in the data transfer phase. Once all data has been sent to the host device, during the response phase, the storage device can send a response to the host device indicating that all data has been successfully sent.

[0003] The above information disclosed in this Background section is intended to enhance understanding of the background of the present invention and, therefore, may include information that does not constitute prior art. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 7,792,027 [Patent Document 2] U.S. Patent No. 8,553,469 [Patent Document 3] U.S. Patent No. 8,738,841 [Patent Document 4] U.S. Patent No. 9,152,580 [Patent Document 5] US Patent Application Publication No. 2007 / 0195777 [Patent Document 6] US Patent Application Publication No. 2014 / 0281147 [Patent Document 7] US Patent Application Publication No. 2015 / 0186068 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-described conventional technology, and it is an object of one or more embodiments of the present invention to provide a storage device that includes a configurable automatic data transfer trigger. The storage device can track out-of-order completions and automatically trigger in-order data transfers. In some embodiments, the data transfer trigger of the storage device is dynamically configured to reduce or minimize idle time on the data transfer bus. [Means for solving the problem]

[0006] According to one or more embodiments of the present invention, a storage device includes a host interface that receives host commands from a host device via a storage interface; one or more memory translation layers that perform one or more operations associated with the host commands to retrieve one or more data chunks associated with the host commands; a bitmap circuit that includes a bitmap that tracks a constrained order of the one or more data chunks sent to the host device; and a transfer trigger that triggers a data transfer to the host device for the one or more data chunks in the constrained order depending on the state of one or more bits in the bitmap.

[0007] In an embodiment, one or more data chunks are retrieved from the storage memory in an order different from the constrained order.

[0008] In an embodiment, consecutive bits from among one or more bits of the bitmap correspond to a constrained order.

[0009] In an embodiment, a first bit from the series of bits corresponds to a first data chunk from the one or more data chunks in the constrained order.

[0010] In an embodiment, the next adjacent bit from the series of bits corresponds to a second data chunk from the one or more data chunks in the constrained order.

[0011] In an embodiment, the transfer trigger is configured to trigger the data transfer in response to a specified number of bits, starting from a first bit, of one or more bits in the bitmap having a changed state from an initial state.

[0012] In an embodiment, the one or more memory translation layers are configured to set a corresponding bit in the bitmap to have the changed state in response to performing a corresponding operation from among the one or more operations associated with the host command.

[0013] In an embodiment, the one or more memory translation layers are configured to set the specified number of bits to have the modification states in an order different from the constrained order.

[0014] In an embodiment, the bitmap circuitry is configured to dynamically change the specified number of bits depending on a threshold value.

[0015] In an embodiment, the threshold value can be set to the specified number of bits and the position of the first bit from among the specified number of bits.

[0016] According to one or more embodiments of the present invention, a method for triggering a data transfer from a storage device to a host device includes receiving, by the storage device, a host command from the host device to retrieve data from a storage memory; allocating, by the storage device, a bitmap for the host command; performing, by the storage device, one or more operations associated with the host command to retrieve one or more data chunks from the storage memory; changing, by the storage device, a state of a corresponding bit from one or more designated bits in the bitmap in response to completion of execution of a corresponding operation from the one or more operations; monitoring, by the storage device, the designated bit in the bitmap; and triggering, by the storage device, a data transfer of the one or more data chunks in a constrained order in response to the designated bit in the bitmap having a changed state from an initial state.

[0017] In an embodiment, the one or more operations associated with the host command are performed to retrieve the one or more data chunks in an order different from the constrained order.

[0018] In an embodiment, the one or more designated bits correspond to one or more consecutive bits of the bitmap, and the one or more consecutive bits correspond to the constrained order.

[0019] In an embodiment, a first bit from the series of bits corresponds to a first data chunk from the one or more data chunks in the constrained order.

[0020] In an embodiment, the next adjacent bit from the series of bits corresponds to a second data chunk from the one or more data chunks in the constrained order.

[0021] In an embodiment, the data transfer is triggered in response to a specified number of bits, starting from a first bit, having the changed state.

[0022] In an embodiment, the method may further comprise the step of changing, by the storage device, the number of designated bits in accordance with a threshold value.

[0023] In an embodiment, the threshold value sets the number of the designated bits and the position of the first bit from among the designated bits.

[0024] According to one or more embodiments of the present invention, a storage device includes a storage controller that performs one or more operations associated with a host command received from a host device via a storage interface, the one or more operations being retrieving one or more data chunks associated with the host command from a storage memory; and a bitmap circuit that tracks a constrained order of the one or more data chunks sent to the host device, the bitmap circuit including: an allocated bitmap including one or more designated bits corresponding to the constrained order; a comparison bitmap circuit that generates a comparison bitmap according to a count value and a start position indicating the one or more designated bits in the allocated bitmap; and a trigger bitmap circuit that compares the allocated bitmap with the comparison bitmap to determine a state of the designated bits in the allocated bitmap and triggers a data transfer of the one or more data chunks to the host device in the constrained order according to the state of the designated bits, the trigger bitmap circuit triggering the data transfer in response to the designated bits having a changed state from an initial state.

[0025] In an embodiment, the storage controller is configured to change a state of a corresponding bit from the designated bits to the changed state in response to a corresponding operation from the one or more operations being completed, wherein the one or more operations are completed in an order different from the constrained order. [Effects of the Invention]

[0026] According to the present invention, a storage device can reduce or minimize idle time on a data transfer bus by tracking out-of-order completions and automatically triggering in-order data transfers. [Brief explanation of the drawings]

[0027] The above and other aspects of the present invention will become more apparent to those skilled in the art from the detailed description of the embodiments given, taken in conjunction with the accompanying drawings.

[0028] [Figure 1] 1 is a system diagram of a storage system in accordance with one or more embodiments of the present invention. [Figure 2] 1 is a block diagram of a storage device in accordance with one or more embodiments of the present invention. [Figure 3] FIG. 2 is a detailed block diagram of a storage device in accordance with one or more embodiments of the present invention. [Figure 4] FIG. 2 is a block diagram of a transfer trigger circuit in accordance with one or more embodiments of the present invention. [Figure 5] FIG. 1 is a schematic circuit diagram illustrating a mask bitmap circuit in accordance with one or more embodiments of the present invention. [Figure 6] FIG. 1 is a schematic circuit diagram illustrating a comparison bitmap circuit in accordance with one or more embodiments of the present invention. [Figure 7] FIG. 1 is a schematic circuit diagram illustrating a trigger bitmap circuit in accordance with one or more embodiments of the present invention. [Figure 8] 1 is a flowchart of a method for triggering data transfer in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] The embodiments will now be described more particularly with reference to the accompanying drawings, in which like reference numerals may indicate similar components throughout. However, the present invention may be embodied in many different forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Accordingly, descriptions of processes, elements, and techniques not necessary for those skilled in the art to fully understand the aspects and features of the present invention may be omitted. Unless otherwise indicated, like reference numerals indicate similar elements throughout the accompanying drawings and disclosed description, and therefore, descriptions thereof may not be repeated.

[0030] A storage device may execute a single read command issued by a host device by performing one or more read operations to retrieve data corresponding to the read command stored in one or more logical blocks of the storage device. For example, depending on the size of the data corresponding to the single read command, the storage device may perform multiple read operations to retrieve portions or chunks of data from the logical block. In this case, depending on the workload of the storage device, the read operation may be completed out of order, resulting in some or chunks of data being retrieved from the logical block being received out of order. However, the storage device may send data associated with a single read command to the host device in an appropriate order (e.g., a predetermined order or a specific order), for example, in ascending order of logical block addresses (LBAs).

[0031] For example, a storage device may execute a read command using a host-to-device command frame, one or more device-to-host data frames, and a device-to-host response frame. The command frame of the read command specifies a starting logical block address (LBA) and a logical block address count, and one data frame may send, for example, up to 1,024 bytes of data. In this case, if the read command requires one or more data frames to be sent to the host device, the data frames are transferred in a predetermined order, for example, from the lowest logical block address to the highest logical block address. Additionally, a storage device may execute multiple read operations to execute a single read command, with each read operation retrieving a portion or chunk of data (e.g., page data) associated with the single read command from the corresponding logical block. However, because read operations may be completed out of order depending on the workload of the storage device, portions or chunks of data may not be received in the predetermined order in which the data was sent to the host device. In this case, the storage device may convert out-of-order operation completions into in-order DATA frame transmissions to transmit the DATA frames to the host device in the predetermined order.

[0032] The storage device may also transfer in-order data frames to the host device via a connection established between the storage device and the host device, and may open and close the connection as needed. In this case, the connection may be switched circuit-wise, so that while the connection is open, the connection may not be shared with other host devices and / or other storage devices. Because connection resources may be limited, efficient use of the connection is required to improve or maximize performance. Furthermore, when either the host device or the storage device determines that there are no more data frames to send, the connection may be degraded from a full-duplex state (e.g., a two-way data transfer state) to a half-duplex state (e.g., a one-way data transfer state). In the half-duplex state, the connection may be idle, wasting bandwidth. Therefore, it may be preferable to keep the connection as short as possible to reduce or minimize half-duplex states, but it should not be kept so short that the connection establishment overhead becomes noticeable.

[0033] According to one or more embodiments of the present invention, a storage device may include a hardware module (e.g., a bitmap circuit) that tracks out-of-order operation completions that are to be converted to in-order data frame transfers. For example, in some embodiments, the hardware module includes an array of bitmaps, each of which corresponds to a single host command (e.g., a single read command). In this case, each bit in the bitmap corresponds to one operation (e.g., a read operation) from among one or more operations (e.g., multiple read operations) performed to execute the single host command (e.g., a single read command). In other words, each bit corresponds to a portion or chunk of data (e.g., page data) received as a result of completion of a corresponding operation (e.g., a corresponding read operation) from among multiple operations (e.g., multiple read operations) associated with the single host command (e.g., a single read command). As each data portion or chunk (e.g., each page of data) is received as a result of completion of the corresponding operation, the state of the corresponding bit in the bitmap is changed from an initial state to a changed state (e.g., from 0 to 1). In this case, bits in the bitmap may be set to the changed state out of order because data portions or chunks may not have been read in order. Data transfer to the host device may be automatically triggered in response to a sufficient number of corresponding bits in the bitmap (e.g., consecutive bits) having the changed state, starting with the first bit (e.g., the least significant bit), indicating that data is ready to be sent to the host device in the proper order.

[0034] According to one or more embodiments of the present invention, a hardware module (e.g., a bitmap circuit) may have a dynamically configurable data transfer trigger to improve or maximize bus utilization and / or efficiency. For example, in some embodiments, the sufficient number of consecutive bits used to automatically trigger a data transfer may be dynamically configured according to a suitable or desired threshold value so that the burst size of the data transfer may be varied. For example, in this case, the threshold value may be set to minimize or reduce connection establishment overhead by ensuring that an appropriate amount of data is ready to be transferred before the connection is opened, and / or to minimize or reduce bus idle time by ensuring that data is ready to be transferred before the connection is opened, while avoiding transferring an excessively large amount of data over a single connection. For example, the threshold value may be dynamically adjusted at startup, at runtime, and / or on a command basis as needed, depending on the performance, application, implementation, and / or the like of the storage device and / or storage system. Thus, data transfer bus idle time may be reduced, half-duplex connections may be reduced, and performance may be improved.

[0035] In some embodiments, a storage device includes a hardware module (e.g., a bitmap circuit) that automatically triggers data transfers rather than using firmware or software. Using firmware or software to manage data transfers can be complex, difficult to tune, and / or difficult to maintain. In contrast, hardware modules according to some embodiments of the present invention automatically trigger data transfers depending on the state of corresponding bitmap bits, and data transfer triggers can be dynamically configured as needed. Additionally, hardware modules increase parallelism, while using firmware or software can more closely resemble a serial process. Thus, hardware modules (e.g., a bitmap circuit) can improve performance and increase the flexibility of the storage device.

[0036] FIG. 1 is a system diagram of a storage system in accordance with one or more embodiments of the present invention.

[0037] Generally viewed, a storage system 100 according to one or more embodiments of the present invention may include a host device 102 (e.g., a host computer) and a storage device 104. The host device 102 issues commands to the storage device 104, which may cause the storage device 104 to retrieve data associated with the commands stored on the storage device 104. For example, the host device 102 may be communicatively coupled to the storage device 104 (e.g., via a storage interface 110). The host device 102 may issue a read command to the storage device 104 such that data corresponding to the read command is retrieved from the storage device 104 and sent to the host device 102. Once all data has been successfully sent to the host device 102, the storage device 104 may send an appropriate response to the host device 102 indicating that all data associated with the read command has been successfully transferred.

[0038] In one or more embodiments, the storage device 104 may include a hardware module (e.g., bitmap circuit 118) that tracks out-of-order operation completions and automatically triggers in-order data frame transfers. For example, in some embodiments, the hardware module may include an array of bitmaps and supporting logic. Each bitmap may include n bits (where n is a natural number) that represent data sent in association with a single read command. For example, each bit represents one portion or chunk of data (e.g., page data) being read from the storage device 104 (e.g., storage memory 116). That is, each bitmap corresponds to a mapping of bits to a single read command, with each bit representing the read status of one portion or chunk of data corresponding to the single read command. The hardware module can identify a bit number that corresponds to the first bit (e.g., the least significant bit) in a single burst of data to be sent and set the size of the burst in bits. When a suitable or desired number of consecutive bits (e.g., starting from the first bit or least significant bit) of the corresponding bitmap have a state that has been changed from its initial state, this may indicate that data is ready to be sent to the host device in the proper order, and the hardware module may automatically trigger a data transfer to the host device 102.

[0039] More specifically, with reference to FIG. 1 , host device 102 may include host processor 106 and host memory 108. For example, host processor 106 may be a general-purpose processor, such as a central processing unit (CPU) core of host device 102. Host memory 108 may be considered a high-performance main memory (e.g., main memory) of host device 102. For example, in some embodiments, host memory 108 may include (or be) a volatile memory, such as dynamic random access memory (DRAM). However, the present invention is not limited in this respect, and host memory 108 may be replaced with a high-performance main memory (e.g., main memory) suitable for host device 102, as known to those skilled in the art. For example, in other embodiments, the host memory 108 may be a relatively high-performance non-volatile memory such as NAND flash memory, phase change memory (PCM), resistive RAM, spin transfer torque RAM (STTRAM), suitable memory based on PCM or memristor technology, and / or resistive random access memory (ReRAM), which may include, for example, chalcogenides.

[0040] Storage device 104 may be considered a secondary memory capable of persistently storing data accessible by host device 102. In this context, storage device 104 may include (or may be) a relatively slow memory compared to the high-performance memory of host memory 108. For example, in some embodiments, storage device 104 may be a secondary memory of host device 102, such as a solid-state drive (SSD). However, the present invention is not limited thereto, and in other embodiments, storage device 104 may include (or may be) any suitable storage device, such as, for example, a magnetic storage device (e.g., a hard disk drive (HDD)), an optical storage device (e.g., a blue light disc drive, a CD drive, a DVD drive), and / or other types of flash memory devices (e.g., a USB flash drive), etc. In various embodiments, storage device 104 may conform to a large form factor standard (e.g., a 3.5-inch hard drive form factor), a small form factor standard (e.g., a 2.5-inch hard drive form factor), an M.2 form factor, an E1.S form factor, etc. In other embodiments, storage device 104 may conform to an adaptation or desired derivative of such form factors. For convenience, storage device 104 is described below in the context of an SSD, although the invention is not limited thereto.

[0041] The storage device 104 is communicatively coupled to the host device 102 via a storage interface 110. The storage interface 110 enables communication (e.g., using a connector and protocol) between the host device 102 and the storage device 104. In some embodiments, the storage interface 110 enables the exchange of storage requests and responses between the host device 102 and the storage device 104. In some embodiments, via the storage interface 110, the storage device 104 can transfer data to and from the host memory 108 of the host device 102. For example, in embodiments, the storage interface 110 (e.g., its connector and protocol) may be a standard interface such as a Small Computer System Interface (SCSI), a Serial ATA (Serial Attached SCSI), or a standard interface such as a Serial ATA (Serial Attached SCSI). However, the present invention is not limited thereto, and in other embodiments, the storage interface 110 (e.g., its connector and protocol) may include (or may be) PCIe (Peripheral Component Interconnect Express), RDMA (Remote Direct Memory Access) over Ethernet, SATA (Serial ATA), etc. The storage interface 110 may conform to other suitable storage interfaces, such as SAS (Single Serial Adapter Attachment), Fiber Channel, Non-Volatile Memory Express (NVMe), and / or NVMe-oF (NVMe over Fabric), etc. In other embodiments, the storage interface 110 (e.g., its connectors and protocols) may include (or be) various general-purpose interfaces, such as Ethernet and / or Universal Serial Bus (USB), etc. For convenience, the storage interface 110 is described below in the context of a SAS interface, although the invention is not limited thereto.

[0042] In some embodiments, the storage device 104 may include a host interface 112, a storage controller 114, and a storage memory 116. The host interface 112 is connected to the storage interface 110 and may respond to input / output (I / O) requests received from the host device 102 via the storage interface 110. For example, the host interface 112 may receive a command (e.g., a read command) from the host device 102 via the storage interface 110 and send the command to the storage controller 114 to retrieve data associated with the command from the storage memory 116. The storage controller 114 may control the storage memory 116 and provide an interface for accessing the storage memory 116. For example, the storage controller 114 may include at least one processing circuit built in for interfacing with the storage memory 116. The processing circuitry may include, for example, digital circuitry (e.g., a microcontroller, microprocessor, digital signal processor, or logic device (e.g., a field programmable gate array (FPGA) and / or an application-specific integrated circuit (ASIC))) capable of executing data access instructions (e.g., via firmware and / or software) to provide access to data stored in the storage memory 116 in response to the data access instructions. For example, the data access instructions may include commands for appropriate data storage and retrieval algorithms (e.g., READ / WRITE). The storage memory 116 may persistently store data received from the host device 102 in multiple logical blocks. For example, in an embodiment, the storage memory 116 may include non-volatile memory such as NAND flash memory. However, the present invention is not limited in this respect, and the storage memory 116 may include appropriate memory depending on the type of storage device 104 (e.g., magnetic disk, tape, optical disk, and / or the like).

[0043] Although the host interface 112 and the storage controller 114 are shown as separate components of the storage device 104, the invention is not so limited. For example, the host interface 112 and the storage controller 114 are shown as separate components to distinguish between a front end of the storage device 104 that receives commands from the host device 102 and a back end of the storage device 104 that retrieves (e.g., READs) data associated with the commands from the storage memory 116. Thus, in various embodiments, the host interface 112 can be integrated with the storage controller 114 (e.g., as an integrated circuit (IC)) or embodied separately from the storage controller 114 and attached to the storage device 104, for example, as a system on a chip (SOC).

[0044] In one or more embodiments, the storage device 104 may further include a bitmap circuit 118 and a transfer circuit 120. The bitmap circuit 118 may track out-of-order operation completions and automatically trigger in-order (e.g., constrained-order) data frame transfers. The transfer circuit 120 may receive a trigger (e.g., a trigger bit) from the bitmap circuit 118 and send data associated with the command to the host device 102 in a predetermined order. For example, in an embodiment, the bitmap circuit 118 may include an array of bitmaps, each of which may correspond to a single host command. Each bit in the bitmap corresponding to a single host command may correspond to a portion or chunk of data (e.g., a page of data) to be read from the storage memory 116. For example, a data portion or chunk may be the smallest unit of data, such as a page of data, read from the storage memory 116 by a single read operation. As a non-limiting example, if a single read command requires five pages of data to be read from storage memory 116 (e.g., a logical block of storage memory 116), then five corresponding bits (e.g., five consecutive bits) of the bitmap may correspond to the five pages of data read from storage memory 116. For example, as the five pages of data are read from storage memory 116 in any order, the corresponding bits of the bitmap may be modified, e.g., by completing each corresponding read operation in any order. As each of the five bits is modified, the bitmap circuit 118 may trigger a transfer of the data corresponding to the single read command to the transfer circuit 120.

[0045] In some embodiments, the bitmap circuit 118 may be embodied as a hardware module (e.g., an electronic circuit) that is communicatively coupled to the host interface 112 and the storage controller 114. For example, in embodiments, the bitmap circuit 118 is embodied as an IC that is attached to (or mounted on) the storage device 104 (e.g., is integrated on the same board or circuit board as) the storage device 104. For example, the bitmap circuit 118 may be embodied on (e.g., attached to or mounted on) the storage device 104. However, the invention is not limited in this respect. For example, in other embodiments, the bitmap circuit 118 may be implemented on a circuit board (e.g., a printed circuit board (PCB)) separate from the storage device 104 and communicatively coupled to the storage device 104.

[0046] Although transfer circuitry 120 is shown as a separate component of storage device 104, the invention is not so limited. For example, transfer circuitry 120 is shown as a separate component that distinguishes between triggering a transfer and transferring data. Thus, in various embodiments, transfer circuitry 120 is embodied as part of host interface 112 and / or as part of bitmap circuitry 118, for example.

[0047] FIG. 2 is a block diagram of a storage device in accordance with one or more embodiments of the present invention.

[0048] Generally speaking, the host device 102 can send a command to the storage device 104 via the storage interface 110. The command can include a logical block address (LBA) such that the storage device 104 executes the command on data stored in the storage memory 116 (e.g., one or more logical blocks thereof) according to the LBA. For example, the logical block address (LBA) can include a start LBA and an LBA count. The storage device 104 executes the command by performing multiple operations, which can be completed in any order depending on the workload of the storage device 104. Once the appropriate number of operations are completed, the storage device 104 can send the data corresponding to the command to the host device 102 in an appropriate order (e.g., a predetermined order or a specific order), for example, from lowest LBA to highest LBA.

[0049] 2, the host interface 112 may receive a command from the host device 102 via the storage interface 110. For example, the command may be a read command, although the invention is not limited thereto. The host interface 112 may send the command to the storage controller 114 to perform one or more operations associated with the command and allocate a bitmap in the bitmap circuit 118 for the command. The storage controller 114 may perform the one or more operations associated with the command in any order, depending on the workload, and may change the state of each of the bits in the allocated bitmap as each operation completes.

[0050] For example, the storage controller 114 may include one or more memory translation layers (202_1, 202_2) (e.g., flash memory translation layers), generally referred to as "memory translation layers 202," each connected to one or more NAND dies (204_1, 204_2) of the storage memory 116. In this case, data associated with a command is stored in one or more of the NAND dies (204_1, 204_2), such that one or more of the memory translation layers 202 can perform operations associated with a read command to retrieve data portions or chunks (e.g., pages of data) from the respective NAND dies. Each of the memory translation layers 202 may include a queue of any number of operations for the respective one or more NAND dies, such that the one or more operations associated with a command are completed in order according to the queue in the memory translation layer 202. Thus, one or more operations related to a read command may be completed in any order, and correspondingly, data portions or chunks associated with the command may be read from the NAND dies (204_1, 204_2) in any order.

[0051] The bitmap circuit 118 tracks the state of bits in the allocated bitmap and can automatically trigger a data transfer in response to a sufficient number of bits (e.g., a sufficient number of consecutive bits) having a change state, starting with the first bit (e.g., the least significant bit). For example, the allocated bitmap can have one or more consecutive bits, each corresponding to an operation from among multiple operations associated with a command. In this case, because operations may not be completed in order, the bits in the allocated bitmap can be changed out of order to correspond to out-of-order operation completion. Thus, the consecutive bits correspond to a predetermined order of data portions or chunks to be transferred to the host device 102, and accordingly, a sufficient number of consecutive bits having a change state, starting with the first bit, can indicate that data is ready to be sent to the host device 102 in the proper order (e.g., the predetermined sequence).

[0052] As a non-limiting example, when a read command requests that three pages of data be read from the NAND dies (204_1, 204_2) be sent to the host device 102 in a predetermined order, starting with the first page, followed by the second page, and then the third page, three consecutive bits are designated in the allocated bitmap to correspond to the three pages of data. In this case, the first bit (e.g., the least significant bit) of the three consecutive bits corresponds to the first page, the next bit of the three consecutive bits corresponds to the second page, and the last bit of the three consecutive bits corresponds to the third page, thereby maintaining the predetermined order of the three pages of data based on the bit order. Because the three pages of data are read from the NAND dies (204_1, 204_2) in any order, the storage controller 114 may change the state of the three bits in the allocated bitmap in any order. However, because data is sent to the host device 102 in a predetermined order, the transfer of data may not be triggered until at least the first bit (or some configurable number of consecutive bits starting from the first bit) has a changed state, indicating that the corresponding page of data has been received.

[0053] In some embodiments, the bitmap circuit 118 may have a configurable data transfer trigger that controls the burst size of data sent to the host device 102. For example, the bitmap circuit 118 may have a configurable threshold that sets an appropriate number of bits, starting with the first bit, that can have a change state before triggering a data transfer. The threshold may be dynamically adjusted to improve performance of the storage device 104. For example, the threshold may be dynamically adjusted to reduce connection establishment overhead, reduce idle time on the data transfer bus, and / or reduce half-duplex connections. Thus, dynamically adjusting the threshold as needed can improve performance. The bitmap circuit 118 may track the state of each bit present in the bitmap allocated for a single command, and when an appropriate number of bits, starting with the first bit in the allocated bitmap, have a change state, the bitmap circuit 118 may trigger the transfer circuit 120 to send data to the host device 102 in a predetermined order during a single burst.

[0054] FIG. 3 is a block diagram of a storage device in accordance with one or more embodiments of the present invention.

[0055] 3 , in some embodiments, the host interface 112 may include a scheduling circuit 302. The host interface 112 receives host commands from the host device 102, and the scheduling circuit 302 may issue a request to the storage controller 114 to perform one or more operations associated with the host command. For example, if the host command is a read command, the scheduling circuit 302 may issue a read request to the storage controller 114 so that one or more read operations associated with the read command are performed. Each of the read operations may thereby retrieve a portion or chunk of data (e.g., a page of data) associated with the read command from the storage memory 116.

[0056] In some embodiments, the scheduling circuit 302 can identify multiple pages of data to be read to execute a single read command and issue a read request to the storage controller 114 to retrieve the multiple pages of data from the storage memory 116 (e.g., NAND dies (204_1, 204_2)) in chunks of a threshold size corresponding to a single transfer burst. For example, in some embodiments, the scheduling circuit 302 can create a data structure (DD) (e.g., a DMA (Direct Memory Access)) for each page to be read. The scheduling circuit 302 may generate a data structure (DD) for each of the eight pages and send corresponding DD indexes to the storage controller 114 to read the corresponding pages of data from the storage memory 116 (e.g., NAND dies (204_1, 204_2)). In some embodiments, the scheduling circuit 302 may send multiple read requests (e.g., multiple DD indexes) to the storage controller 114 in chunks of a threshold size that satisfies the size of a single transfer burst, thereby allowing the corresponding threshold number of pages to be read from the storage memory 116 at a time. For example, if the threshold is set to "8" so that eight consecutive pages of data are sent to the host device 102 at a time, the scheduling circuit 302 may generate a data structure (DD) for each of the eight pages and send corresponding DD indexes for the eight pages to the storage controller 114 to read the eight pages of data from the storage memory 116.

[0057] In some embodiments, the scheduling circuit 302 may issue a series of read requests to the storage controller 114 to read page data prior to the completion of a previous data transfer. For example, when a threshold-sized chunk of data associated with a read request is ready to be sent to the host device 102, the scheduling circuit 302 may issue a next series of read requests to the storage controller 114 to read the next threshold-sized chunk of data from the storage memory 116. In this case, the next series of read requests may be for the same read command or a different command. As a non-limiting example, a single read command may require 15 read operations to retrieve 15 pages of data from the storage memory 116, and the threshold may be set to "8" so that when eight consecutive bits in the allocated bitmap, starting with the first bit corresponding to the first eight pages, have a changed state, the first eight pages are sent to the host device 102 at a time (e.g., during one open connection). In this case, when the first eight pages are sent to the host device 102, the scheduling circuit 302 can issue the next seven read requests in parallel to the storage controller 114 to retrieve the next seven pages to be sent to the host device 102 during the next transfer burst, thereby improving parallel processing capability and increasing performance.

[0058] In some embodiments, the scheduling circuit 302 can extend a single transfer burst to include more pages of data, for example, when more consecutive pages of data associated with a single host command are ready to be sent at the end of the single transfer burst. Returning to the 15-page example, in some embodiments, if the first page of data (e.g., page 9 data) for a second transfer burst is ready to be sent when the last page of data (e.g., page 8 data) in the first transfer burst is sent to the host device 102, the scheduling circuit 302 can extend the first transfer burst to include the first page of data (e.g., page 9 data) of the second transfer burst. Thus, connection establishment overhead can be reduced.

[0059] In some embodiments, the scheduling circuit 302 assigns a bitmap in the bitmap circuit 118 for each host command, and the bitmap circuit 118 can track out-of-order read operation completions for each host command accordingly. For example, in some embodiments, the scheduling circuit 302 can assign a bitmap to a single host command and set a relative start position (e.g., indicating the position of the first bit) of a data transfer within the bitmap for the single host command and a count value of the number of bits in the bitmap that can have a change state to trigger an in-order (e.g., constrained order) data transfer. For example, the count value corresponds to the number of read requests issued to the storage controller 114 for a single transfer burst, and the count value can thereby determine the transfer burst size in bits (e.g., a threshold size for the data transfer). Thus, in some embodiments, the count value and the relative start position are dynamically set to control the threshold size corresponding to the appropriate number of bits that can have a change state to trigger a data transfer. In an embodiment, the corresponding bit of the corresponding bitmap is initially set to an initial state, for example, initialized at power-on.

[0060] Although the scheduling circuit 302 is shown as part of the host interface 112, the invention is not limited in this respect. For example, in various embodiments, the scheduling circuit 302 is embodied as a separate circuit (e.g., an electronic circuit) coupled to the host interface 112 and the storage controller 114, or as part of the host interface 112 and part of the storage controller 114, etc. In another embodiment, the scheduling circuit 302 is embodied in firmware or software, for example, as part of the host interface 112 and / or as part of the storage controller 114.

[0061] In some embodiments, completion of a read request by the storage controller 114 (e.g., the memory mapping layer 202) can cause the storage controller 114 (or the memory mapping layer 202) to change a corresponding bit in the bitmap to have a modified state indicating that the data for the corresponding page has been read. For example, in some embodiments, the storage controller 114 (or the memory mapping layer 202) can provide a ready index to the bitmap circuit 118 indicating that the data for the page corresponding to a particular data structure (DD) (e.g., a particular bit in the bitmap) is now available. In some embodiments, a portion or chunk of data (e.g., page data) read from the storage memory 116 is stored in a buffer so that the transfer circuit 120 can send the data from the buffer to the host device 102. In this case, the storage controller 114 (or the corresponding memory mapping layer 202) can send a buffer index to the bitmap circuit 118 indicating the location of the page data for data transfer.

[0062] The bitmap circuit 118 may monitor designated bits (e.g., a threshold number of bits starting from the first bit) of a bitmap currently in use (e.g., a bitmap currently assigned to a host command) and detect a bitmap in which the designated bits have a changed state. When the bitmap circuit 118 detects a bitmap in which the designated bits have a changed state, the bitmap circuit 118 may trigger the transfer circuit 120 to send the corresponding data in a predetermined order and initialize the bits of the bitmap to an initial state to be used for a subsequent transfer or a subsequent command. In an embodiment, if the scheduling circuit 302 issues a series of read requests to the storage controller 114 to read page data before completing a previous data transfer, the storage controller 114 changes the bit state before the subsequent data transfer is specified, and accordingly, when the next data transfer is specified, the data is already available, so the next data transfer is triggered immediately upon completion of the previous data transfer.

[0063] For example, in some embodiments, the bitmap circuit 118 may include a count status register 304, a ready bitmap register 306, a buffer index register 308, and a transfer trigger circuit 310. In embodiments, the count status register 304 is set by the scheduling circuit 302 to assign bitmaps to host commands. In embodiments, the count status register 304 is a two-dimensional array in which each row represents an index of a data transfer (TR index) corresponding to a single host command. For example, each row may include a count value corresponding to a threshold number of bits that may be set before triggering a data transfer associated with a single host command, and a relative start index of bits that indicates the relative start position of the first bit within the assigned bitmap.

[0064] In an embodiment, the ready bitmap register 306 is set in response to a ready index provided by the storage controller 114 (or a corresponding memory translation layer 202) to change a corresponding bitmap bit when a read operation is completed. For example, in an embodiment, the ready bitmap register 306 may be a two-dimensional array in which each row corresponds to a particular TR index (e.g., a particular host command). Each row may include a bitmap (e.g., a 64-bit bitmap) including multiple bits corresponding to the maximum number of read requests generated by the scheduling circuit 302 for a single transfer burst. Each time the storage controller 114 provides a ready index (e.g., by writing a ready index to a special function register (SFR)), the bitmap circuit 118 may change the state of the corresponding bit in the corresponding bitmap (e.g., based on the TR index) to indicate that the corresponding data portion or chunk (e.g., page data) associated with that bit is ready for transfer.

[0065] In some embodiments, the buffer index register 308 is set by the storage controller 114 (or corresponding memory translation layer 202) to indicate the location of data that is ready to be transferred. For example, when the storage controller 114 reads a particular portion or chunk of data (e.g., a page of data) from the storage memory 116, the read data may be stored in a buffer to be retrieved during the corresponding data transfer. Thus, in some embodiments, the buffer index register 308 may contain a buffer index that indicates the location of the data to be transferred during the corresponding data transfer.

[0066] In some embodiments, the transfer trigger circuit 310 can determine whether an appropriate number of bits (e.g., consecutive bits) of a corresponding bitmap in the ready bitmap register 306 have a change state, indicating that the data corresponding to those bits are ready to be transferred. For example, in some embodiments, the transfer trigger circuit 310 can monitor designated bits (e.g., identified based on a relative start position and a count value) of a currently used bitmap (e.g., a bitmap currently assigned to a host command) and detect a bitmap in which the designated bits (e.g., a threshold number of bits) have a change state. In response to detecting a bitmap with designated bits having a change state, the transfer trigger circuit 310 can automatically trigger a data transfer corresponding to that bitmap. For example, in some embodiments, the transfer trigger circuit 310 can set a trigger bit corresponding to the assigned bitmap (e.g., based on a TR index) to the transfer circuit 120 to trigger the corresponding data transfer. The transfer trigger circuit 310 is described in further detail below with reference to FIGS. 4-7.

[0067] The transfer circuit 120 can send data associated with a host command to the host device 102 in response to a trigger (e.g., a trigger bit) from the bitmap circuit 118. For example, the transfer circuit 120 can include a transfer register 312, a context generator 314, and a buffer reset trigger 316. The transfer register 312 can be a special function register (SFR) that contains a trigger bitmap used to start the transfer of data when a corresponding bit (e.g., a trigger bit) of the trigger bitmap is set based on a corresponding TR index received from the transfer trigger circuit 310. The context generator 314 can arrange the data corresponding to the bitmap in a predetermined order so that the data transfer to the host device 102 begins in the predetermined order. Once the data is successfully sent, the buffer reset trigger 316 releases (e.g., resets) the buffer associated with the transferred data so that the buffer is used for a subsequent transfer.

[0068] Figure 4 is a block diagram of a transfer trigger circuit in accordance with one or more embodiments of the present invention. Figure 5 is a schematic circuit diagram of a mask bitmap circuit in accordance with one or more embodiments of the present invention. Figure 6 is a schematic circuit diagram of a comparison bitmap circuit in accordance with one or more embodiments of the present invention. Figure 7 is a schematic circuit diagram of a trigger bitmap circuit in accordance with one or more embodiments of the present invention.

[0069] 4, the transfer trigger circuit 310 may include a mask bitmap circuit 402, a comparison bitmap circuit 404, and a trigger bitmap circuit 406. Briefly, the mask bitmap circuit 402 may convert the count value and relative start position of the count status register 304 for a particular host command (e.g., a particular TR index) to generate a mask bitmap that indicates the count value relative to the relative start position in bits. The comparison bitmap circuit 404 generates a comparison bitmap based on the mask bitmap, which is used to compare the count value with designated bits of a corresponding bitmap of the readiness bitmap register 306 that has a change status. The trigger bitmap circuit 406 may compare the comparison bitmap with a corresponding bitmap (e.g., a corresponding DD readiness bitmap) to generate a trigger bit that automatically triggers a data transfer.

[0070] 5, in some embodiments, the mask bitmap circuit 402 can generate a mask bitmap 502 based on the count value and the relative start position (e.g., relative start index) stored in a particular row of the count status register 304. In some embodiments, the mask bitmap 502 can be used to handle wrap-up conditions. For example, in an embodiment, if the bitmap in the readiness bitmap register 306 is a 64-bit bitmap and the corresponding count value is 64 with the corresponding relative start index being 63, the mask bitmap 502 can be a 128-bit bitmap. In this case, when a comparison bitmap is generated according to the mask bitmap, the comparison bitmap is generated as a 64-bit bitmap, which allows the comparison bitmap to be compared with the corresponding 64-bit bitmap in the readiness bitmap register 306 (e.g., the corresponding DD readiness bitmap). For example, in some embodiments, the comparison bitmap is generated by inverting (logically negating) the result of a bitwise OR of the upper and lower 64 bits of the mask bitmap. For example, the 63rd bit of the mask bitmap 502 is set to the first bit (e.g., the 0th or least significant bit) of the corresponding comparison bitmap, and an appropriate number of consecutive bits starting from this first bitmap correspond to other bits of the specified bits (e.g., a threshold number of bits).

[0071] In some embodiments, the mask bitmap circuit 402 can automatically select one of the rows of the count status register 304 based on a TR index received from either the scheduling circuit 302 or the storage controller 114. For example, because the scheduling circuit 302 and the storage controller 114 perform separate processes, the TR index can be received from either the scheduling circuit 302 or the storage controller 114 in any order. For example, as described above, the scheduling circuit 302 can provide a TR index when assigning a bitmap to a host command. For example, the scheduling circuit 302 can provide a TR index to assign a bitmap to a new host command, to set a threshold (e.g., a count value and / or a relative starting position) for the next transfer of data associated with an existing host command, to assign a bitmap to one or more read-ahead requests, to expand the burst size for data transfers corresponding to a particular host command, and / or the like. The storage controller 114 may, for example, provide a TR index when a ready index is provided so that a corresponding bitmap in the ready bitmap register 306 can be compared to determine whether an appropriate number of bits in the bitmap have a change state.

[0072] For example, in some embodiments, the mask bitmap circuit 402 may include a first multiplexer (MUX) 504, a finite state machine (FSM) 506, a second MUX 508, a count left shift circuit 510, a subtractor circuit 512, and a start left shift circuit 514. The first MUX 504 may select either the first TR index (e.g., provided by the scheduling circuit 302) or the second TR index (e.g., provided by the storage controller 114) as a selection signal provided to the second MUX 508. In some embodiments, the first MUX 504 may select either the first TR index or the second TR index in response to an arbitration signal provided by the FSM 506. For example, because the first TR index and the second TR index may be received in any order, as described above, an arbitration signal may be provided to handle situations, such as when the first TR index and the second TR index are received simultaneously or substantially simultaneously. In this case, the arbitration signal is controlled according to the state of the FSM 506. For example, in an embodiment, the storage controller 114 is given a higher priority than the scheduling circuit 302 because the storage controller 114 operates on writes to special function registers (SFRs).

[0073] Continuing to refer to FIG. 5 , in some embodiments, the second MUX 508 can automatically select one of the rows of the count status register 304 based on the first TR index or the second TR index. As described above, each row of the count status register 304 can include a count value and a relative starting position for a bit in the corresponding bitmap to be searched based on the TR index. The count left shift circuit 510 can convert multiple count values ​​into a bitmap. For example, the count left shift circuit 510 can generate an array of bits having a value of “1” followed by the number of “0”s in the count value (e.g., 1<<count value). As a non-limiting example, assuming the count value is “5,” the count left shift circuit 510 can generate a bit array having a value of “100000” (e.g., 1<<5=“100000”).

[0074] The subtractor circuit 512 can convert the output of the count left shift circuit 510 to generate a number of bits corresponding to the count value, where the bit has a value of 1. For example, the subtractor circuit 512 can subtract a value of 1 from the output of the count left shift circuit 510 (e.g., 1<<count value−1). Returning to the non-limiting example where the count value is 5, the subtractor circuit 512 subtracts 1 from the “100000” output from the count left shift circuit 510, causing the subtractor circuit 512 to generate a bitmap having a number of consecutive bits corresponding to the count value, where the bit has a value of 1 (e.g., 100000−1=“11111”).

[0075] The start shift left circuit 514 can transform the output of the subtractor circuit based on the relative start position to generate the mask bitmap 502. For example, the start shift left circuit 514 can shift the output of the subtractor circuit 512 to the left by the number of relative start positions. Returning to the non-limiting example where the count value is 5, if the relative start position is 0, the start shift left circuit 514 can shift the output of the subtractor circuit 512 (e.g., "11111") to the left by the relative start position of 0 (e.g., 11111<<0=11111).

[0076] 6, in some embodiments, the comparison bitmap circuit 404 may generate a comparison bitmap 602 based on the mask bitmap 502, which is compared to the assigned bitmap in the prepared bitmap register 306. For example, in some embodiments, the comparison bitmap circuit 404 may include a plurality of logic gates 604 and a plurality of inverters 606. For example, in some embodiments, each of the plurality of logic gates 604 may be an OR gate that performs a two-bit OR operation on the most significant bit and the least significant bit of the mask bitmap 502. For example, the first OR gate 604_1 performs an OR operation on the first bit M[0] and the 65th bit M

[64] of the mask bitmap 502, the second OR gate 604_2 performs an OR operation on the second bit M[1] and the 66th bit M

[65] of the mask bitmap 502, and the 64th OR gate 604_64 performs an OR operation on the 64th bit M

[63] and the 128th bit M

[0127] of the mask bitmap 502. Thus, the OR gates 604 can eliminate the wrap-up condition as described above. Each output of the OR gates 604 is inverted by a corresponding one of the inverters 606. Thus, the comparison bitmap 602 is generated such that all bits have a value of 1, except for designated bits corresponding to the data portion or chunk (e.g., page of data) being read by the storage controller 114 (or corresponding memory translation layer 202), which may be generated to have a bit value of 0.

[0077] 7 , in some embodiments, the trigger bitmap circuit 406 can compare the comparison bitmap 602 with the assigned bitmap of the readiness bitmap register 306 to generate a trigger bit that triggers a data transfer. For example, as described above, each time the storage controller 114 (or the memory mapping layer 202) sends a readiness index corresponding to a page of data read from the storage memory 116 (e.g., by writing the readiness index to the SFR), the state of the corresponding bit in the assigned bitmap of the readiness bitmap register 306 is set to have a changed state. To determine whether a designated bit in the assigned bitmap of the readiness bitmap register 306 that corresponds to a portion or chunk of data (e.g., a page of data) being read by the storage controller 114 (or the memory mapping layer 202) has a changed state, the trigger bitmap circuit 406 can compare the bit in the corresponding bitmap of the readiness bitmap register 306 with the bit in the comparison bitmap 602.

[0078] For example, in some embodiments, the trigger bitmap circuit 406 may include a bitwise OR circuit 704, a reduction AND gate 706, and a demultiplexer (DMUX) 708. The bitwise OR circuit 704 may perform a bitwise OR operation on the bits of the comparison bitmap 602 and the bits of the assigned bitmap of the readiness bitmap register 306. The reduction AND gate 706 may perform an AND operation on the output of the bitwise OR circuit 704. The reduction AND gate 706 may output a 1 when each of the outputs of the bitwise OR circuit 704 has a value of 1, indicating that all readiness indexes have been received, and may output a 0 when any one of the outputs of the bitwise OR circuit 704 has a value of 0. For example, if all bits in the comparison bitmap 602 have a value of 1 except for the designated bit (which may have a value of 0) corresponding to the data portion or chunk (e.g., page data) to be read by the storage controller 114 (or memory translation layer 202), and therefore all designated bits in the allocated bitmap of the readiness bitmap register 306 have a changed state (e.g., a value of 1), indicating that all readiness indexes have been received, the bitwise OR circuit 704 may output a value of 1. On the other hand, if any one of the designated bits in the allocated bitmap still has an initial state (e.g., a bit value of 0), the bitwise OR circuit 704 may output a value of 0 for these bit comparisons. Thus, the reduction AND gate 706 may output a value of 1 if all of the readiness indexes have been received (setting the corresponding bit in the readiness bitmap register 306 to have a value of 1), or may output a value of 0 if at least one of the designated bits still has an initial state (e.g., indicating that a readiness index for the corresponding bit has not yet been received).

[0079] The DMUX 708 can assign the output of the reduction AND gate 706 to a corresponding bit in the trigger bitmap 702. The corresponding bit in the trigger bitmap 702 is selected according to a TR index (e.g., the first TR index or the second TR index selected by the arbitration signal). When the corresponding bit is set to 1 (e.g., based on the 1 output by the AND gate 706), the corresponding bit in the trigger bitmap 702 is set to 1. This automatically triggers the transfer trigger circuit 310 to start an in-order (e.g., constrained order) data transfer for the corresponding host command. Thus, the data transfer is automatically triggered according to the state of the designated bit in the assigned bitmap of the readiness bitmap register 306.

[0080] 8 is a flowchart of a method for triggering data transfer in accordance with one or more embodiments of the present invention. However, the present invention is not limited to the order or number of operations of method 800 illustrated in FIG. 8 , and those skilled in the art will recognize that the order or number of operations may be changed to any desired order. For example, in some embodiments, the order may be changed, or the method may include fewer or additional operations. It should be noted that the operations illustrated in method 800 may be performed by any one of the components of one or more embodiments described above, or by an appropriate combination of several components of one or more embodiments.

[0081] 8, method 800 starts, and at operation 805, a host command to retrieve data from storage memory may be received from a host device. For example, in some embodiments, the host command may be a read command, although the invention is not limited thereto. The host command may be received by the storage device from the host device via a storage interface. For example, in some embodiments, host interface 112 may receive the host command from host device 102 via storage interface 110.

[0082] In some embodiments, a bitmap is assigned to the host command in operation 810. For example, in some embodiments, the host interface 112 or the scheduling circuit 302 may send one or more requests to the storage controller 114 to retrieve one or more data portions or chunks (e.g., one or more pages of data) associated with the host command from the storage memory 116 (e.g., one or more logical blocks of the storage memory 116) and perform one or more operations. In this case, the host interface 112 or the scheduling circuit 302 may assign a bitmap (e.g., a bitmap in the ready bitmap register 306) to the host command (e.g., based on the TR index), send one or more data structures (e.g., DMA descriptors) (DD) to the storage controller 114, and perform one or more operations according to the one or more data structures (DD). In some embodiments, the host interface 112 or the scheduling circuit 302 provides a count value (e.g., corresponding to the number of requests issued to the storage controller 114) and a relative start index (corresponding to the first bit) so that a specified bit in the allocated bitmap can be identified according to the number of requests (or number of data structures (DDs)) issued to the storage controller.

[0083] In some embodiments, in operation 815, one of one or more operations may be performed to retrieve a portion or chunk of data from storage memory. For example, the storage controller 114 (or a corresponding one in the memory mapping layer 202) may perform one of the one or more operations with one of the one or more requests (or data structure (DD)). In some embodiments, in operation 820, the state of a corresponding bit (e.g., one of the specified bits) may be changed in the allocated bitmap. For example, in some embodiments, when one of the one or more operations is completed, the storage controller (or a corresponding one in the memory mapping layer 202) may change the state of the corresponding bit in the allocated bitmap (e.g., by issuing a corresponding ready index).

[0084] At operation 825, designated bits in the allocated bitmap may be monitored to determine whether the designated bits have a change state. For example, in some embodiments, the trigger bitmap circuit 406 may compare a corresponding comparison bitmap with a corresponding prepared bitmap (e.g., an allocated bitmap) to determine whether all designated bits have a change state. For example, if any of the designated bits do not have a change state, e.g., if any of the designated bits remain in their initial state at operation 825 (e.g., no at operation 825), method 800 may return to operation 815 and monitor the states of the designated bits as one or more operations are completed. On the other hand, if all designated bits have a change state (e.g., yes at operation 825), an in-order data transfer is triggered at operation 830, and the data is sent to the host device at operation 835. For example, in some embodiments, data associated with a host command may be transferred in a predetermined order (e.g., a constrained order) regardless of the order in which the operations are completed. Once the data is transferred to the host device, the storage device may send a response indicating that the data was successfully transferred, and method 800 may end.

[0085] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated or simplified for clarity. Although terms such as "first," "second," and "third" are used herein to describe various elements, components, regions, layers, and / or sections, it will be understood that these elements, components, regions, layers, and / or sections are not limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section previously described may be referred to as a second element, component, region, layer, or section without departing from the spirit of the present invention.

[0086] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be understood that the element or layer is directly on, connected to, or coupled to the other element or layer, or that there can be one or more intervening elements or layers. Moreover, when an element or layer is referred to as being between two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0087] The terms used herein are merely for the purpose of describing particular embodiments and are not intended to limit the present invention. As used herein, the singular forms are intended to include the plural forms unless the context clearly dictates otherwise. The terms "comprises," "comprising," "have," and "having," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the addition or presence of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations associated with one or more listed items. An expression such as "at least one", when it appears before a list of elements, modifies the list of elements as a whole, not individual elements of the list.

[0088] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, rather than degree, and are intended to account for inherent variations in measurements or calculations, as will be appreciated by those of ordinary skill in the art. Furthermore, when describing embodiments of the present invention, the use of "can" means "one or more embodiments of the present invention." As used herein, the term "use" is considered synonymous with the term "utilize."

[0089] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention pertains. In general, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0090] Although several embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the embodiments without departing from the spirit and scope of the present invention. It will be understood that, unless otherwise stated, the description of a feature or aspect of each embodiment should generally be considered applicable to other similar features or aspects of other embodiments. Therefore, the above description is an example of various embodiments and should not be construed as being limited to the specific embodiments disclosed herein. It should be understood that various modifications to the disclosed embodiments and other embodiments are intended to be included within the spirit and scope of the present invention, as defined by the appended claims and their equivalents. [Explanation of symbols]

[0091] 102: Host device 106: Host processor 108: Host memory 104: Storage device 112: Host interface 114: Storage controller 116: Storage memory 118: Bitmap circuit 120: Transfer circuit

Claims

1. A storage device, a host interface for receiving host commands from a host device via a storage interface; one or more memory translation layers that perform one or more operations associated with the host command to retrieve one or more data chunks associated with the host command from storage memory; a bitmap circuit including a bitmap that tracks a constrained order of the one or more data chunks sent to the host device; a transfer trigger that triggers a data transfer to the host device for the one or more data chunks in the constrained order according to the state of one or more bits in the bitmap; the transfer trigger is configured to trigger the data transfer in response to a specified number of bits, starting from a first bit, of the one or more bits in the bitmap having a changed state from an initial state; the bitmap circuit is configured to dynamically change the specified number of bits in response to a threshold value; Storage device.

2. the one or more data chunks are retrieved from the storage memory in an order different from the constrained order; The storage device according to claim 1 .

3. consecutive bits from among the one or more bits of the bitmap correspond to the constrained order; The storage device according to claim 1 .

4. a first bit from the sequence of bits corresponds to a first data chunk from the one or more data chunks in the constrained order; The storage device according to claim 3 .

5. a next adjacent bit from the consecutive bits corresponds to a second data chunk from the one or more data chunks in the constrained order; The storage device according to claim 4.

6. the one or more memory translation layers are configured to set a corresponding bit in the bitmap to have the changed state in response to performing a corresponding operation from among the one or more operations associated with the host command. The storage device according to claim 1 .

7. the one or more memory translation layers are configured to set the specified number of bits to have the modification states in an order different from the constrained order. The storage device according to claim 6.

8. the threshold value sets the specified number and the position of the first bit from among the specified number of bits; The storage device according to claim 1 .

9. 1. A method for triggering a data transfer from a storage device to a host device, comprising: receiving, by the storage device, a host command from the host device to retrieve data from storage memory; allocating a bitmap for the host command by the storage device; performing, by the storage device, one or more operations associated with the host command to retrieve one or more data chunks from the storage memory; changing, by the storage device, a state of a corresponding bit from one or more designated bits in the bitmap in response to completion of execution of a corresponding operation from the one or more operations; monitoring, by the storage device, the designated bit of the bitmap; triggering, by the storage device, a data transfer of the one or more data chunks in a constrained order in response to the designated bit in the bitmap having a changed state from an initial state; The method further includes changing, by the storage device, the number of designated bits in response to a threshold value. method.

10. the one or more operations associated with the host command are performed to retrieve the one or more data chunks in an order different from the constrained order.

10. The method of claim 9.

11. the one or more designated bits correspond to one or more consecutive bits of the bitmap, the one or more consecutive bits corresponding to the constrained order; 10. The method of claim 9.

12. a first bit from the sequence of bits corresponds to a first data chunk from the one or more data chunks in the constrained order; The method of claim 11.

13. a next adjacent bit from the consecutive bits corresponds to a second data chunk from the one or more data chunks in the constrained order; The method of claim 12.

14. the data transfer is triggered in response to a specified number of bits, beginning with a first bit, having the changed state; 10. The method of claim 9.

15. The threshold value sets the number of the specified bits and the position of the first bit among the specified bits.

10. The method of claim 9.

16. A storage device, a storage controller that performs one or more operations associated with a host command received from a host device via a storage interface, the one or more operations retrieving one or more data chunks associated with the host command from a storage memory; a bitmap circuit for tracking a constrained order of the one or more data chunks sent to the host device; The bitmap circuit an allocated bitmap including one or more designated bits corresponding to the constrained order; a comparison bitmap circuit for generating a comparison bitmap according to a count value and a start position indicating the one or more designated bits in the allocated bitmap; a trigger bitmap circuit that compares the allocated bitmap with the comparison bitmap to determine a state of the designated bit in the allocated bitmap, and triggers a data transfer of the one or more data chunks to the host device in the constrained order according to the state of the designated bit; the trigger bitmap circuit triggers the data transfer in response to the designated bit having a changed state from an initial state; the bitmap circuitry is further configured to dynamically change the number of designated bits in response to a threshold value. Storage device.

17. the storage controller is configured to change a state of a corresponding bit from the designated bits to the changed state in response to a corresponding operation from the one or more operations being completed; the one or more operations are completed in an order different from the constrained order; The storage device according to claim 16.

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