SYSTEM-ON-CHIP BASED TASK SCHEDULING METHOD, SYSTEM-ON-CHIP, AND ELECTRONIC DEVICE - Patent application

Abstract

To provide a task scheduling method based on a system-on-chip (SoC), a system-on-chip, and an electronic apparatus.TECHNICAL MEANS: The task scheduling method includes the steps of: determining a task set that needs to be executed by an SoC and dependencies between tasks in the task set; determining first scheduling information for a first task that can be executed by a first accelerator in the SoC based on the task set and the dependencies; transmitting, by a first task scheduler in the SoC, the first scheduling information to a second task scheduler of the SoC for scheduling the first accelerator; and scheduling the first accelerator by the second task scheduler based on the first scheduling information, and executing the first task by the first accelerator.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This application claims priority to a Chinese patent application bearing application number 202310594269.6, filed on May 24, 2023, and a Chinese patent application bearing application number 202310780260.4, filed on June 28, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the technical field of computers, and in particular to a task scheduling method based on a system on a chip, a system on a chip, a computer-readable storage medium, and an electronic device. [Background technology]

[0003] In intelligent drives, as applications become more and more complex, the granularity of data and task scheduling becomes smaller and smaller, and the demand for high-efficiency and low-latency task scheduling becomes stronger. In related art, a central processing unit (CPU) schedules and executes tasks through software, but this cannot meet the requirements for high-efficiency and low-latency task scheduling. Summary of the Invention [Problem to be solved by the invention]

[0004] In order to solve the above technical problems, the present disclosure provides a task scheduling method based on a system on a chip (SoC), an SoC, a computer-readable storage medium, and an electronic device, in which a processor can schedule an accelerator to execute a task by hardware scheduling, and since the speed of hardware scheduling is faster than the speed of software scheduling, the use of hardware scheduling can improve the efficiency of task scheduling, reduce the delay in task scheduling, ensure the real-time nature of task scheduling, and ensure that tasks are executed with high efficiency and low delay. [Means for solving the problem]

[0005] A first aspect of the present disclosure provides a task scheduling method based on a system-on-chip, the task scheduling method including the steps of: determining a task set that needs to be executed by the system-on-chip and dependencies between tasks in the task set; determining first scheduling information for a first task that can be executed by a first accelerator in the system-on-chip based on the task set and the dependencies; transmitting the first scheduling information by a first task scheduler in the system-on-chip to a second task scheduler in the system-on-chip for scheduling the first accelerator; and scheduling the first accelerator by the second task scheduler based on the first scheduling information, and executing the first task by the first accelerator.

[0006] A second aspect of the present disclosure provides a system-on-chip comprising: a processor; a first accelerator; a first task scheduler; and a second task scheduler, wherein the processor is coupled to the second task scheduler via the first task scheduler; the second task scheduler is coupled to the first accelerator; the processor is used to determine a task set that needs to be executed by the system-on-chip and dependencies between tasks in the task set, and to determine initial scheduling information for a first task that can be executed by the first accelerator based on the task set and the dependencies; the first task scheduler is used to determine first scheduling information for the first task based on the initial scheduling information and to send the first scheduling information to a second task scheduler for scheduling the first accelerator; the second task scheduler is used to schedule the first accelerator based on the first scheduling information; and the first accelerator is used to execute the first task.

[0007] A third aspect of the present disclosure provides a computer-readable storage medium having stored thereon a computer program for executing a task scheduling method based on any one of the above system-on-chips.

[0008] A fourth aspect of the present disclosure provides an electronic device comprising a processor and a memory in which instructions executable by the processor are stored, the processor being used to realize a task scheduling method based on any one of the above-described system-on-chips by reading and executing the instructions from the memory.

[0009] A fifth aspect of the present disclosure provides a computer program product, the instructions of which, when executed by a processor, cause a task scheduling method based on any one of the above-described system-on-chips of the present disclosure to be performed. [Effects of the Invention]

[0010] The present disclosure provides a system-on-chip with a first task scheduler that schedules a second task scheduler in the system-on-chip, a first accelerator that schedules a first task, and task scheduling performed by the first task scheduler and the second task scheduler, thereby enabling a processor to schedule the first task scheduler to execute tasks using hardware. This improves task scheduling efficiency, reduces task scheduling delays, and ensures real-time task scheduling, thereby ensuring that tasks are executed efficiently and with low latency. Furthermore, in the process of executing each task in a task set, the accelerator is directly scheduled by the hardware scheduler to execute the task, eliminating the need for the processor to suspend the main program. This reduces the frequency of interrupts to the processor and improves system processing power. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a structural schematic diagram of a system-on-chip according to one exemplary embodiment of the present disclosure. [Figure 2] FIG. 1 is a structural schematic diagram of a system-on-chip according to another exemplary embodiment of the present disclosure. [Figure 3] 1 is a schematic flowchart of a task scheduling method according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 2 is a schematic diagram of the dependencies between tasks in one exemplary task set of the present disclosure. [Figure 5] 10 is a schematic flowchart of a task scheduling method according to another exemplary embodiment of the present disclosure; [Figure 6] 10 is a schematic flowchart of a task scheduling method according to another exemplary embodiment of the present disclosure; [Figure 7] FIG. 2 is a schematic diagram illustrating the configuration structure of a data packet according to one exemplary embodiment of the present disclosure. [Figure 8] 10 is a schematic flowchart of a task scheduling method according to another exemplary embodiment of the present disclosure; [Figure 9] 10 is a schematic flowchart of a task scheduling method according to another exemplary embodiment of the present disclosure; [Figure 10] 10 is a schematic flowchart of a task scheduling method according to another exemplary embodiment of the present disclosure; [Figure 11] 1 is a structural schematic diagram of a system-on-chip according to one exemplary embodiment of the present disclosure. [Figure 12] FIG. 10 is a structural schematic diagram of a system-on-chip according to another exemplary embodiment of the present disclosure. [Figure 13] FIG. 2 is a structural schematic diagram of a first task scheduler according to one exemplary embodiment of the present disclosure; [Figure 14] FIG. 10 is a structural schematic diagram of a second task scheduler according to an exemplary embodiment of the present disclosure; [Figure 15] FIG. 10 is a structural schematic diagram of a third task scheduler according to an exemplary embodiment of the present disclosure; [Figure 16] FIG. 10 is a structural schematic diagram of a first task scheduler according to another exemplary embodiment of the present disclosure; [Figure 17] 1 is a structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] In order to explain the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings. The described embodiments are not all of the embodiments of the present disclosure, but are merely a part of the embodiments of the present disclosure, and the present disclosure is not limited to the exemplary embodiments.

[0013] The relative arrangement of parts and steps, formulas, and numerical values ​​described in these examples do not limit the scope of the present disclosure unless specifically stated otherwise.

[0014] (Application Summary) To ensure the safety of intelligent drives, intelligent drive assistance system chips must meet the requirements of low-latency task scheduling and fast interrupt processing. Specific tasks are performed using hardware accelerators capable of implementing various specific functions. Different hardware accelerators can process data in parallel, resulting in superior processing power and lower latency than a CPU. In related technology, hardware accelerators in a system-on-chip (SoC) are typically managed and scheduled by a CPU using software. When a hardware accelerator needs to be scheduled to perform a specific task, the main program being processed by the CPU is interrupted, the CPU saves its current state, and then enters interrupt service, scheduling the hardware accelerator to execute the task using software scheduling. After the task execution is completed, the CPU resumes the previous processing and continues processing the interrupted main program. To ensure real-time task scheduling and avoid long wait times when there are many tasks, the number of CPU cores is usually increased to improve parallelism. Multi-core parallel scheduling ensures real-time task scheduling, improves task scheduling efficiency, and reduces task scheduling delays.

[0015] However, as chips realize more and more functions, the granularity of task scheduling becomes smaller and smaller, and the number of tasks that need to be executed increases. In the related art, a scheduling method in which a CPU schedules an accelerator to execute tasks through software tends to stabilize as the number of CPU cores increases, making it impossible to achieve lower latency. This is because, each time scheduling is performed, the CPU needs to save the current state and resume the previous process, which can take a certain amount of time. Even if there is no need to queue a task during scheduling, it takes hundreds of microseconds to execute the task. Therefore, in the related art, a scheduling method in which a CPU schedules an accelerator to execute tasks through software cannot reduce latency to below a hundred microseconds, even if the number of CPU cores increases, which has a certain impact on special scenarios with high real-time requirements, such as intelligent drives. Furthermore, in the related art, a scheduling method in which a CPU schedules an accelerator to execute tasks through software causes interrupts every time the CPU schedules the accelerator, as the number of tasks increases, resulting in frequent interrupts that affect the system's processing power.

[0016] To address the issues of low efficiency and high latency in task scheduling, an embodiment of the present disclosure provides an SoC-based task scheduling method, which provides multiple hardware task schedulers between a CPU and a hardware accelerator, and schedules the hardware accelerator to execute tasks using hardware scheduling, thereby reducing scheduling latency to the nanosecond level, achieving highly efficient and low-latency task scheduling, and ensuring real-time task scheduling. Furthermore, in the process of using a task scheduler to schedule a hardware accelerator to execute each task, direct scheduling is performed among multiple task schedulers, eliminating the need for the CPU to suspend the main program, thereby reducing the frequency of CPU interrupts and indirectly improving system performance.

[0017] (Example System) 1 is a structural schematic diagram of a system-on-chip according to an exemplary embodiment of the present disclosure. As shown in FIG. 1, a system-on-chip (SoC) 10 includes a processor 101, a first task scheduler 102, a second task scheduler 103, a first accelerator 104, a scheduling bus 105, and a memory 106. Here, the memory 106, the processor 101, the first task scheduler 102, the second task scheduler 103, and the first accelerator 104 are sequentially coupled. As shown in FIG. 1, the first task scheduler 102 and the second task scheduler 103 may be coupled via a dedicated scheduling bus 105.

[0018] The processor 101 may be a CPU and is used to determine a task set that needs to be executed by the SoC 10 and the dependencies between each task in the task set, and to determine initial scheduling information for a first task based on the task set and the dependencies, where the first task is a task that can be executed by the first accelerator 104. In some examples, the first task is any task in the task set, and the task set and the dependencies between each task in the task set can be pre-compiled by a compiler and stored in memory. When the task set needs to be executed, the processor 101 reads it from memory.

[0019] Illustratively, the SoC 10 may include one or more second task schedulers 103. If the SoC 10 includes multiple second task schedulers 103, each of the multiple second task schedulers 103 schedules one first accelerator 104. In the embodiment of the present disclosure, the number of second task schedulers 103 and first accelerators 104 included in the SoC 10 is not limited. 1 and 2 illustrate, as an example, the SoC 10 including one second task scheduler 103 and one first accelerator 104.

[0020] The first task scheduler 102 has a scheduling function and can schedule other task schedulers. In an embodiment of the present disclosure, the first task scheduler 102 determines first scheduling information for a first task based on the initial scheduling information, and schedules the second task scheduler 103 based on the first scheduling information.

[0021] The second task scheduler 103 has a scheduling function and can schedule the hardware accelerator to execute a specific task. In an embodiment of the present disclosure, the second task scheduler 103 receives first scheduling information from the first task scheduler 102 and schedules the first accelerator 104 based on the first scheduling information.

[0022] The first accelerator 104 may be an artificial intelligence (AI) accelerator, a neural network processor (Intelligent Processing Unit (IPU)), or the like, and may include a hardware acceleration unit capable of implementing various specific computing functions, such as a tensor processing unit (TPU). In an embodiment of the present disclosure, the first accelerator 104 is used to execute a first task according to scheduling by the second task scheduler 103.

[0023] 2 is a structural schematic diagram of an SoC according to another exemplary embodiment of the present disclosure. As shown in FIG. 2, in addition to the SoC 10 shown in FIG. 1, the SoC 10 further includes a third task scheduler 205 and a second accelerator 206. Here, the third task scheduler 205 is coupled to the first task scheduler 102, the second task scheduler 103, and the second accelerator 206, respectively. In some embodiments, the first task scheduler 102, the second task scheduler 205, and the third task scheduler 205 can be coupled via a dedicated scheduling bus 105.

[0024] The processor 101 is also used to determine initial scheduling information for a second task based on the task set and dependencies, the second task being a task that the second accelerator 206 can execute.

[0025] The first task scheduler 102 is used to determine second scheduling information of the second task based on the initial scheduling information of the second task, and send the second scheduling information to the third task scheduler 205. Illustratively, the second task is a task that has a dependency relationship with the first task in the task set, for example, the second task is a successor task of the first task, that is, the execution of the second task needs to depend on the execution result of the first task.

[0026] The second task scheduler 103 is also used to determine the execution result of the first task, generate third scheduling information based on the execution result of the first task and the first scheduling information, and send the third scheduling information to the third task scheduler 205.

[0027] The third task scheduler 205 receives second scheduling information from the first task scheduler 102 and third scheduling information from the second task scheduler 103, and is also used to schedule the second accelerator 206 based on the second scheduling information and the third scheduling information.

[0028] The second accelerator 206 is used to execute the second task according to the scheduling of the third task scheduler 205 .

[0029] Illustratively, SoC 10 may include one or more third task schedulers 205. If SoC 10 includes multiple third task schedulers 205, each of the multiple third task schedulers 205 schedules one second accelerator 206. In the embodiment of the present disclosure, the number of third task schedulers 205 and second accelerators 206 included in SoC 10 is not limited. FIG. 2 illustrates, as an example, that SoC 10 includes one third task scheduler 205 and one second accelerator 206.

[0030] Furthermore, the embodiments of the present disclosure do not limit the specific structure of the SoC 10, and the SoC 10 may include more or fewer components than those shown in Figures 1 and 2. For example, the SoC 10 may further include components such as a configuration bus and an input / output interface.

[0031] (Exemplary Method) 3 is a schematic flowchart of a task scheduling method according to an exemplary embodiment of the present disclosure. The task scheduling method according to the embodiment of the present disclosure can be applied to the SoC 10 shown in FIG. 3, and as shown in FIG. 3, the method includes steps 301 to 305.

[0032] In step 301, a set of tasks that need to be executed by the SoC and the dependencies between each task in the set of tasks are determined.

[0033] In an embodiment of the present disclosure, each task in a task set may include, but is not limited to, an image processing task, an audio processing task, or a data calculation task. The dependency relationship represents the execution sequence of each task in the task set. The task set and the dependency relationships between each task in the task set may be pre-compiled by a compiler and stored in memory in the SoC. Illustratively, the dependency relationships between each task may be stored in memory in a manner such as a sequence or a link. When each task in the task set needs to be executed, the processor in the SoC reads each task and the dependency relationships between each task from memory.

[0034] Illustratively, FIG. 4 is a schematic diagram of the dependencies between each task in one exemplary task set of the present disclosure. As shown in FIG. 4, there are dependencies between Task 1 and Task 2 and Task 3; there are dependencies between Task 2 and Task 1, Task 4 and Task 5; there are dependencies between Task 3 and Task 1 and Task 4; there are dependencies between Task 4 and Task 2, Task 3 and Task 6; there are dependencies between Task 5 and Task 2 and Task 6; and there is a dependency between Task 6 and Task 4 and Task 5. In the task scheduling process, after the processing of Task 1 is completed, Task 2 and Task 3 are triggered; after the processing of Task 2 is completed, Task 4 and Task 5 are triggered; after the processing of Task 3 is completed, Task 4 is triggered; after the processing of Task 4 is completed, Task 6 is triggered; and after the processing of Task 5 is completed, Task 6 is triggered. Here, task 4 starts to be executed only when the two trigger conditions of task 2 and task 3 are met simultaneously, and task 6 starts to be executed only when the two trigger conditions of task 4 and task 5 are met simultaneously.

[0035] In step 302, first scheduling information for a first task executable by a first accelerator in the SoC is determined based on the task set and dependencies.

[0036] An accelerator in an SoC is a hardware module capable of executing a specific task. In an embodiment of the present disclosure, the first task is a task in the task set that needs to be executed by the accelerator. After obtaining the task set, the processor first determines the first task to be executed by the accelerator from the task set, and the accelerator used to execute the first task is the first accelerator. Then, the processor determines initial scheduling information for the first task based on dependencies, and schedules the first task scheduler based on the initial scheduling information. The first task scheduler determines the first scheduling information for the first task based on the initial scheduling information.

[0037] The first task is a task that the first accelerator can execute, including, but not limited to, an image processing task, an audio processing task, or a data calculation task. The first accelerator corresponding to the first task can include, but is not limited to, an image processing accelerator, an audio processing accelerator, or a data calculation accelerator. If the first task is an image processing task, the first accelerator is an accelerator that can execute the image processing task, and if the first task is a data calculation task, the first accelerator is an accelerator that can execute the data calculation task.

[0038] 4, for example, a task set includes {task 1, task 2, task 3, task 4, task 5, task 6}, where task 1, task 2, task 4, task 5, and task 6 are tasks that can be executed by each accelerator in the SoC, and task 3 is a special task that cannot be executed by the accelerator and needs to be executed by the processor. For example, if all accelerators in the SoC cannot process images in a certain special format, task 3 needs to be executed by the CPU to process the images in the special format.

[0039] In this case, the first scheduling information of the first task that needs to be executed currently may be determined, and when other first tasks in the task set are executed, the first scheduling information of the other first tasks may be determined in real time, or the first scheduling information of all first tasks in the task set may be determined collectively, and when a certain first task is executed, the first scheduling information of the corresponding first task that was previously determined may be used as is without having to be determined multiple times. For example, when determining the first scheduling information of first tasks that can be executed by the first accelerator, only the first scheduling information of the first task currently waiting to be executed (e.g., task 1) may be determined, or the first scheduling information of all first tasks waiting to be executed (including task 1, task 2, task 4, task 5, and task 6) may be determined.

[0040] In an embodiment of the present disclosure, first scheduling information for a first task can be determined based on dependencies for the first task. The dependencies include dependencies and dependencies. A task that needs to be dependent on for the first task to be executed is called the predecessor task of the first task, and a task that needs to be dependent on for the execution of the first task is called the successor task of the first task. The first scheduling information for the first task includes at least the predecessor task and the successor task of the first task. If the execution of the first task does not depend on other tasks in the task set, the predecessor task of the first task is empty and is marked as null. In this case, the first task is scheduled and started by the main program executed by the processor. If other tasks in the task set do not depend on the first task, the successor task of the first task is empty and is marked as null. In this case, after the execution of the first task is completed, the processor returns to the main program.

[0041] 4, the first scheduling information of task 1 may include {null} and {task 2, task 3}, the first scheduling information of task 2 may include {task 1} and {task 4, task 5}, and the first scheduling information of task 6 may include {task 4, task 5} and {null}. In the above first scheduling information, the first set includes all predecessor tasks of the first task (if the predecessor tasks are empty, it is written as null), and the second set includes all successor tasks of the first task (if the successor tasks are empty, it is written as null).

[0042] In step 303, the first scheduling information is sent by a first task scheduler in the SoC to a second task scheduler in the SoC for scheduling the first accelerator.

[0043] After determining first scheduling information for the first task, the first task scheduler may transmit the first scheduling information to a second task scheduler via a scheduling bus in the SoC. The first task scheduler is a hardware scheduler in the SoC for scheduling a second task scheduler, and the second task scheduler is a hardware scheduler in the SoC for scheduling a first accelerator, where the first accelerator is an accelerator capable of executing the first task. In an embodiment of the present disclosure, hardware scheduling may be performed directly between the first task scheduler and the second task scheduler, which are coupled via the scheduling bus.

[0044] In step 304, the first accelerator is scheduled by the second task scheduler based on the first scheduling information.

[0045] After receiving the first scheduling information, the second task scheduler schedules the first accelerator according to the first scheduling information. During scheduling, if the predecessor task of the first task is empty, the second task scheduler directly schedules the first accelerator according to the first scheduling information; if the predecessor task of the first task is not empty, the second task scheduler needs to obtain the execution result of the predecessor task of the first task and schedule the first accelerator according to the first scheduling information and the execution result of the predecessor task of the first task.

[0046] Taking the example where task 1 is executed by accelerator 1 and task 2 is executed by accelerator 2, if the first task is task 1, the second task scheduler schedules accelerator 1 based on the first scheduling information of task 1; if the first task is task 2, the second task scheduler determines the execution result of task 1 based on the first scheduling information of task 1, and schedules accelerator 2 based on the execution result of task 1 and the first scheduling information of task 2.

[0047] In an embodiment of the present disclosure, the first task scheduler and the second task scheduler are hardware modules provided in an SoC and capable of implementing a scheduling function. When executing task scheduling, the processor first schedules the first task scheduler, then the first task scheduler schedules the second task scheduler, and finally the second task scheduler schedules the first accelerator, thereby enabling the processor to schedule the first accelerator in hardware.

[0048] In step 305, a first task is executed by a first accelerator.

[0049] The first accelerator reads the calculation data required for executing the first task from the memory and performs calculations on the data based on the configuration information determined by the second task scheduler to obtain the execution result of the first task. In some examples, after completing the execution of the first task, the first accelerator can send the execution result of the first task to the second task scheduler so that the second task scheduler can schedule and execute the next waiting first task based on the execution result of the first task.

[0050] According to a task scheduling method according to an embodiment of the present disclosure, a processor schedules a first accelerator to execute a first task using a first task scheduler and a second task scheduler. The first task scheduler and the second task scheduler are hardware modules provided in an SoC and capable of implementing a scheduling function, and the processor performs task scheduling using hardware. This improves task scheduling efficiency, reduces task scheduling delays, and ensures real-time task scheduling, thereby ensuring that tasks are executed efficiently and with low latency. Furthermore, direct scheduling between the first task scheduler and the second task scheduler eliminates the need to suspend the main program being processed by the processor during scheduling, thereby reducing the frequency of processor interrupts and indirectly improving system processing performance.

[0051] In some examples, step 302 in the embodiment shown in FIG. 3 above, "determining first scheduling information for a first task executable by a first accelerator in an SoC based on a task set and dependencies," can be realized by steps 3021 to 3023 shown in FIG. 5.

[0052] In step 3021, a first task from the task set that can be executed by the first accelerator is determined.

[0053] The processor first selects tasks that can be executed by accelerators in the SoC from the task set, sets these tasks as first tasks, and executes each first task using the first accelerator.

[0054] For example, in the task set shown in FIG. 4, if task 1, task 2, task 4, task 5, and task 6 are tasks that can be executed by an accelerator in an SoC, then task 1, task 2, task 4, task 5, and task 6 are all first tasks.

[0055] In step 3022, based on the dependencies, related tasks from the task set that have dependencies with the first task are determined.

[0056] The processor selects, from each task included in the task set based on the dependency relationships, tasks that have a dependency relationship with the first task as related tasks of the first task. The related tasks of the first task include the predecessor task of the first task and the successor task of the first task.

[0057] As shown in the task set in Figure 4, the predecessor tasks of Task 1 are empty and the successor tasks of Task 1 include Task 2 and Task 3, so the related tasks in the task set that have a dependency relationship with Task 1 include Task 2 and Task 3.As another example, the predecessor tasks of Task 4 include Task 2 and Task 3 and the successor task of Task 4 includes Task 6, so the related tasks in the task set that have a dependency relationship with Task 4 include Task 2, Task 3, and Task 6.

[0058] In step 3023, first scheduling information for the first task is determined based on the first task and the related tasks.

[0059] The first scheduling information of the first task includes at least the predecessor task of the first task and the successor task of the first task, and can be used to determine whether the first task satisfies a task execution condition (also called a trigger condition), and can also be used to determine the successor tasks of the first task and, based on the successor tasks, determine that the execution result of the first task needs to be sent to a corresponding task scheduler.

[0060] For example, if the first task is task 1, tasks that have a dependency relationship with task 1 include task 2 and task 3, and the first scheduling information of task 1 may include {null} and {task 2, task 3}. Based on the first scheduling information of task 1, it is determined that the predecessor task of task 1 is empty, and it is directly determined that task 1 satisfies the task execution condition. After the execution of task 1 is completed, it is determined based on the first scheduling information of task 1 that the execution result of task 1 needs to be sent to the task scheduler corresponding to task 2 and the task scheduler corresponding to task 3.

[0061] Also, for example, if the first task is task 4, tasks that have a dependency relationship with task 4 include task 2, task 3, and task 6, and the first scheduling information for task 4 may include {task 2, task 3} and {task 6}. Based on the first scheduling information for task 4, it is determined that task 2 and task 3 are predecessor tasks of task 4, and it is determined whether the execution results of task 2 and task 3 have been received. If the execution results of task 2 and task 3 have been received, it is determined that task 4 satisfies the task execution condition. After the execution of task 4 is completed, it is determined based on the first scheduling information for task 4 that the execution results of task 4 need to be sent to the task scheduler corresponding to task 6.

[0062] In an embodiment of the present disclosure, the task scheduler determines whether the first task satisfies a trigger condition based on the first scheduling information, and determines that the execution result of the first task needs to be sent to the corresponding next task scheduler. By realizing direct scheduling between task schedulers using the first scheduling information, the frequency of processor interruptions can be reduced, and the processing capacity of the system can be indirectly improved.

[0063] In some embodiments, as shown in FIG. 6, step 304 of “scheduling the first accelerator by the second task scheduler based on the first scheduling information” in the embodiment shown in FIG. 3 above may include steps 3041 to 3043.

[0064] In step 3041, it is determined that the first task satisfies the task execution condition based on the first scheduling information.

[0065] When the second task scheduler receives the first scheduling information from the first task scheduler, it determines whether the first task can be triggered to execute based on the first scheduling information, and if it determines based on the first scheduling information that all of the predecessor tasks of the first task have been executed or if it determines based on the first scheduling information that the predecessor tasks of the first task are empty, it determines that the first task satisfies the task execution condition and proceeds to step 3042 to trigger the execution of the first task. Otherwise, it determines that the first task does not satisfy the task execution condition.

[0066] In step 3042, the first scheduling information is analyzed by the second task scheduler to determine first configuration information required for executing the first task.

[0067] The first scheduling information of the first task includes the predecessor task of the first task and the successor task of the first task, as well as information required for executing the first task. After receiving the first scheduling information, the second task scheduler analyzes it to obtain parameters and a task type required for executing the first task, and configures the parameters required for executing the first task based on the task type to obtain first configuration information.

[0068] In some examples, the first task scheduler may transmit the first scheduling information in the form of a data packet. Figure 7 is a schematic diagram of a data packet structure according to one exemplary embodiment of the present disclosure. As shown in Figure 7, the data packet corresponding to the first scheduling information includes a header section and a data section. The header section includes a length, a source, a target, a task type, and an associated task, and the data section includes a task number, static parameters, dynamic parameters, and data flow parameters. The second task scheduler determines the first configuration information based on the task type, static parameters, and dynamic parameters.

[0069] In the header section of the data packet corresponding to the first scheduling information, the length is the data length of the entire data packet, the source is the address of the first task scheduler, and the target is the address of the second task scheduler, where the source and target respectively indicate the sender and receiver of the first scheduling information, the task type indicates the type of task that needs to be executed and is used to initialize the first configuration information, and the associated tasks include predecessor tasks and successor tasks. In the data section of the data packet corresponding to the first scheduling information, the task number is the number of the task in the task set, the static parameters are memory addresses of static calculation data required to execute the task, the dynamic parameters are memory addresses of dynamic calculation data required to execute the task, and the data flow parameters are associated data flow information corresponding to the task, such as a timestamp. For example, when processing a multi-frame image, the timestamp can be used to determine which frame of the image is currently being processed.

[0070] In step 3043, the first accelerator is scheduled by the second task scheduler based on the first configuration information.

[0071] The first accelerator receives first configuration information from the second task scheduler, executes an operation based on the first configuration information, and outputs an operation result obtained by the first accelerator executing the first task. Illustratively, the first configuration information may include a memory address in a memory of operation data required for executing the first task, and the first accelerator reads the operation data from the memory based on the memory address included in the first configuration information, executes the operation, and obtains the operation data result.

[0072] In some examples, the number of second task schedulers in the SoC may be one, and this single second task scheduler schedules the first accelerators corresponding to each first task to execute the first tasks. The number of second task schedulers may be multiple, and direct scheduling may be performed among multiple second task schedulers, with different task schedulers used to schedule the accelerators corresponding to each task. The following description will be given using two second task schedulers as an example. For ease of distinction, the second task scheduler will be referred to as the third task scheduler, the accelerator scheduled by the third task scheduler will be referred to as the second accelerator, and the task executed by the second accelerator will be referred to as the second task. FIG. 8 is a schematic flowchart of a task scheduling method according to another exemplary embodiment of the present disclosure. The task scheduling method according to the embodiment of the present disclosure can be applied to the SoC 10 shown in FIG. 2. As shown in FIG. 8, the method includes the following steps 801 to 810.

[0073] In step 801, a set of tasks that need to be executed by the SoC and the dependencies between each task in the set of tasks are determined.

[0074] When a main program processed by a processor in an SoC needs to execute each task in a task set, the processor reads each task and the dependencies between each task from a memory in the SoC. The task set stored in memory and the dependencies between each task in the task set can be pre-compiled by a compiler and stored in memory.

[0075] In step 802, first scheduling information for a first task executable by a first accelerator in the SoC and second scheduling information for a second task executable by a second accelerator in the SoC are determined based on the task set and the dependencies.

[0076] In some examples, the method for implementing the step of determining first scheduling information for a first task executable by a first accelerator in an SoC based on a task set and dependencies in step 802 can refer to the aforementioned step 302, and the description thereof will be omitted here.

[0077]

[0023] Exemplarily, the second task may be a subsequent task of the first task. The method for determining the second scheduling information of the second task based on the task set and the dependency relationships is similar to the method for determining the first scheduling information. For example, the step of determining the second scheduling information of the second task based on the task set and the dependency relationships includes: determining, based on the dependency relationships, related tasks that have a dependency relationship with the second task from the task set; determining initial scheduling information of the second task based on the second task and related tasks of the second task; and determining the second scheduling information of the second task by the first task scheduler based on the initial scheduling information of the second task.

[0078] As shown in FIG. 4 , the processor determines that the first task is task 2 from the task set {task 1, task 2, task 3, task 4, task 5, task 6}, and determines that the related tasks of task 2 include task 1, task 4, and task 5 based on the dependencies, and determines initial scheduling information for task 2. In a data packet corresponding to the initial scheduling information for task 2, the source is the processor, the target is the first task scheduler, the related tasks include {task 1} and {task 4, task 5}, the task number is task 2, and the static parameter is the memory address in the memory of static calculation data required for executing task 2. The processor transmits the initial scheduling information to the configuration bus, and the first task scheduler determines that the target in the initial scheduling information for task 2 matches itself, receives the initial scheduling information for task 2, and generates first scheduling information for task 2 based on the initial scheduling information for task 2. In the data packet corresponding to the first scheduling information of the task 2, the source is the first task scheduler, the target is the second task scheduler, the related tasks include {task 1} and {task 4, task 5}, the task number is task 2, and the static parameter is the memory address in the memory of the static calculation data required to execute task 2.

[0079] Based on the related tasks of task 2, it is determined that the next tasks of task 2 include task 4 and task 5. Based on the dependencies, it is determined that the related tasks of task 4 include {task 2, task 3} and {task 6}, and that the related tasks of task 5 include {task 2} and {task 6}. Based on task 4 and its related tasks, initial scheduling information for task 4 is determined. In a data packet corresponding to the initial scheduling information of task 4, the source is the processor, the target is the first task scheduler, the related tasks include {task 2, task 3} and {task 6}, the task number is task 4, and the static parameter is the memory address in the memory of static calculation data required for executing task 4. The processor transmits the initial scheduling information to the configuration bus, and the first task scheduler determines that the target in the initial scheduling information of task 4 matches itself, receives the initial scheduling information of task 4, and generates second scheduling information for task 4 based on the initial scheduling information of task 4. In the data packet corresponding to the second scheduling information of task 4, the source is the first task scheduler, the target is the third task scheduler, the related tasks include {task 2, task 3} and {task 6}, the task number is task 4, and the static parameter is the memory address in the memory of the static calculation data required to execute task 4.

[0080] In some embodiments, if the second task includes other subsequent tasks in the task set, step 802 may also determine scheduling information for the other tasks based on the task set and dependencies.

[0081] In step 803, a first task scheduler in the SoC sends first scheduling information to a second task scheduler in the SoC for scheduling the first accelerator, and sends second scheduling information to a third task scheduler in the SoC for scheduling the second accelerator.

[0082] In one implementation, a first task scheduler can transmit first and second scheduling information to a dedicated scheduling bus. Each task scheduler coupled to the scheduling bus determines whether each scheduling information is to be transmitted to itself based on the target in each scheduling information. If the target in the scheduling information matches itself, the task scheduler receives the corresponding scheduling information. The second task scheduler receives the first scheduling information, and the third task scheduler receives the second scheduling information.

[0083] In step 804, the first accelerator is scheduled by the second task scheduler based on the first scheduling information.

[0084] In step 805, a first task is executed by a first accelerator.

[0085] In an embodiment of the present disclosure, the first task scheduler and the second task scheduler are hardware modules provided in an SoC that are capable of realizing a scheduling function, and the processor schedules the first accelerator using the first task scheduler and the second task scheduler, thereby realizing the processor scheduling the accelerator using hardware.

[0086] In step 806, a third task scheduler in the SoC determines second scheduling information for a second task executable by a second accelerator in the SoC.

[0087] In an embodiment of the present disclosure, a third task scheduler is used to schedule the second accelerator, and the third task scheduler receives second scheduling information transmitted by the first task scheduler via the scheduling bus.

[0088] In step 807, the second task scheduler determines the execution result of the first task.

[0089] After completing the execution of the first task, the first accelerator transmits the execution result of the first task to the second task scheduler.

[0090] In step 808, the second task scheduler sends third scheduling information to the third task scheduler based on the execution result of the first task and the first scheduling information.

[0091] The second task scheduler determines, based on the subsequent task in the first scheduling information, that the execution result of the first task needs to be sent to a third task scheduler corresponding to the second task. Based on the execution result of the first task and the first scheduling information, the second task scheduler generates third scheduling information to be sent to the third task scheduler. In the data packet corresponding to the third scheduling information, the source is the second task scheduler, the target is the third task scheduler, the task number is task 4, the dynamic parameter is a memory address in the memory of dynamic calculation data required for executing task 4, and the dynamic parameter is the execution result of the first task.

[0092] In step 809, the second accelerator is scheduled by the third task scheduler based on the second scheduling information and the third scheduling information.

[0093] The third task scheduler determines, based on the second scheduling information, static parameters and a task type required for executing task 4, and determines, based on the third scheduling information, dynamic parameters required for executing task 4. The third task scheduler configures the static parameters and dynamic parameters based on the task type to obtain configuration information for the second task, and schedules the second accelerator to execute the second task based on the configuration information for the second task.

[0094] In step 810, a second task is executed by a second accelerator.

[0095] In an embodiment of the present disclosure, after the execution of the second task is completed, if the task set includes other tasks that follow the second task and are tasks that can be executed by an accelerator in an SoC, the other tasks can be scheduled and executed by referring to the above steps until the execution of all tasks in the task set is completed, thereby realizing the scheduling and execution of each task in the task set.

[0096] According to a task scheduling method according to an embodiment of the present disclosure, a first task scheduler, a second task scheduler, and a third task scheduler are hardware modules provided in an SoC and capable of implementing a scheduling function. The first task scheduler can schedule the second task scheduler and the third task scheduler. The second task scheduler can schedule the first accelerator and the third task scheduler. The third task scheduler can schedule the second accelerator. A processor uses the multiple task schedulers to implement scheduling for multiple accelerators. This improves task scheduling efficiency, reduces task scheduling delays, and ensures real-time task scheduling, thereby ensuring that tasks are executed efficiently and with low latency. Furthermore, in the process of executing each task in a task set, scheduling can be performed directly between each task scheduler, and by having the hardware scheduler directly schedule the accelerator to execute the task, there is no need to interrupt the main program that the processor is processing, which reduces the frequency with which the processor is interrupted by interrupts and indirectly improves the processing power of the system.

[0097] In some embodiments, as shown in FIG. 9, step 809 of "scheduling the second accelerator by the third task scheduler based on the second scheduling information and the third scheduling information" in the embodiment shown in FIG. 8 above may include the following steps 8091 to 8093.

[0098] In step 8091, a third task scheduler determines a preceding task that has a dependency relationship with the second task based on the second scheduling information.

[0099] For example, if the second task is task 4 in the task set shown in Figure 4, the predecessor task that has a dependency relationship with the second task is the predecessor task of task 4. Based on the second scheduling information of task 4, the third task scheduler determines that the predecessor tasks of task 4 include task 2 and task 3.

[0100] In step 8092, the execution result of the preceding task is determined based on the third scheduling information.

[0101] The third task scheduler receives and analyzes data packets corresponding to third scheduling information whose target is the third task scheduler from the scheduling bus to obtain the execution results of the predecessor tasks of the second task. The number of received third scheduling information is the same as the number of predecessor tasks of the second task. For example, task 4 has two predecessor tasks, so it needs to receive third scheduling information from the task schedulers corresponding to the two predecessor tasks. The third task scheduler receives the third scheduling information transmitted by the second task scheduler from the scheduling bus, and the third scheduling information includes the execution results of task 2. The third task scheduler receives the third scheduling information transmitted by the first task scheduler from the scheduling bus, and the third scheduling information includes the execution results of task 3.

[0102] If the predecessor tasks of the second task include only tasks that can be executed by the accelerator, the third scheduling information is sent to the scheduling bus by the second task scheduler for scheduling the accelerator, and in this case, the third task scheduler is scheduled by the second task scheduler. If the predecessor tasks of the second task include only special tasks that cannot be executed by the accelerator, the third scheduling information is sent to the scheduling bus by the first task scheduler for scheduling the processor, and in this case, the third task scheduler is scheduled by the first task scheduler. If the predecessor tasks of the second task include a task that can be executed by an accelerator and a special task that cannot be executed by an accelerator, the third scheduling information includes information sent to the scheduling bus by the second task scheduler for scheduling the accelerator and information sent to the scheduling bus by the first task scheduler for scheduling the processor, and in this case, the third task scheduler is scheduled by the first task scheduler and the second task scheduler.

[0103] In step 8093, the second accelerator is scheduled by the third task scheduler based on the execution result of the preceding task and the second scheduling information.

[0104] When the execution results of all the preceding tasks of the second task and the second scheduling information are acquired, it is determined that the second task satisfies the task execution conditions, and the third task scheduler analyzes the second scheduling information to determine second configuration information required for executing the second task, and schedules the second accelerator based on the execution results of the preceding tasks and the second configuration information.

[0105] The second scheduling information for the second task includes information necessary for executing the second task, as well as the predecessor task and the successor task of the second task. After receiving the second scheduling information from the first task scheduler, the third task scheduler analyzes the second scheduling information to obtain second configuration information necessary for executing the second task. The second configuration information may include a memory address in a memory of static calculation data necessary for executing the second task, and reads the static calculation data of the second task based on the memory address of the static calculation data. The execution result of the predecessor task of the second task is the dynamic parameters of the second task. The third task scheduler determines the configuration information necessary for executing the second task based on the task type, static parameters, and dynamic parameters of the second scheduling information, and sends the configuration information to the second accelerator to schedule the second accelerator to execute the second task.

[0106] After receiving the configuration information required to execute the second task, the second accelerator executes a calculation based on the configuration information and outputs a calculation result that is the execution result obtained by the second accelerator executing the second task.

[0107] According to the task scheduling method of the embodiment of the present disclosure, the third task scheduler schedules the second accelerator to execute the second task (i.e., the task following the first task) based on the second scheduling information and the third scheduling information, and after the execution is completed, the second task becomes the new first task and repeats the above steps to schedule and execute each task in the task set. In the process of executing each task in the task set, scheduling among multiple task schedulers schedules each accelerator to execute each task, eliminating the need for the processor to suspend the main program, thereby reducing the frequency of CPU interrupts and improving system processing performance.

[0108] After the second task scheduler obtains the execution result of the first task from the first accelerator, if the second task scheduler determines, based on the first scheduling information, that the successor task of the first task is a special task that needs to be executed by the processor, the second task scheduler needs to schedule the first task scheduler, and the first scheduling schedules the processor to execute the special task. Based on the above embodiment, an embodiment of the present disclosure further provides another task scheduling method. FIG. 10 is a schematic flowchart of a task scheduling method according to another exemplary embodiment of the present disclosure. As shown in FIG. 10, the method includes the following steps 1001 to 1010.

[0109] In step 1001, a task set that needs to be executed by the SoC and the dependencies between each task in the task set are determined.

[0110] In step 1002, based on the task set and the dependencies, first scheduling information for a first task that can be executed by a first accelerator in the SoC and fourth scheduling information for a third task that needs to be executed by a processor in the SoC are determined.

[0111] For example, if the first task is task 1 in the task set shown in FIG. 4, in the data packet corresponding to the first scheduling information, the source is the first task scheduler, the target is the second task scheduler, the related tasks include {null} and {task 2, task 3}, the task number is task 1, and the static parameters include the memory address in the memory of the static calculation data required to execute task 1.

[0112] For example, if the third task is task 3 in the task set shown in FIG. 4, in the data packet corresponding to the fourth scheduling information, the source is the processor, the target is the first task scheduler, the related tasks include {task 1} and {task 4}, the task number is task 3, and the static parameters include the memory address in the memory of the static calculation data required to execute task 3.

[0113] In step 1003, the first task scheduler determines fourth scheduling information of a third task that needs to be executed by a processor in the SoC.

[0114] The first task scheduler receives the first scheduling information and the fourth scheduling information transmitted by the processor via the scheduling bus.

[0115] In step 1004, the first scheduling information is sent by a first task scheduler in the SoC to a second task scheduler in the SoC for scheduling the first accelerator.

[0116] In step 1005, the first accelerator is scheduled by the second task scheduler based on the first scheduling information.

[0117] In step 1006, the first task is executed by the first accelerator.

[0118] In step 1007, the second task scheduler determines the execution result of the first task.

[0119] In step 1008, the second task scheduler sends fifth scheduling information to the first task scheduler based on the execution result of the first task and the first scheduling information.

[0120] The second task scheduler determines, based on the first scheduling information, that the successor task of the first task is a special task that needs to be executed by the processor. After receiving the execution result of the first task from the first accelerator, the second task scheduler generates fifth scheduling information for scheduling the first task scheduler based on the execution result of the first task and the first scheduling information. Taking task 3 in the task set shown in FIG. 4 as an example, task 3 in the successor tasks of task 1 is a special task. In the data packet corresponding to the fifth scheduling information generated by the second task scheduler, the source is the second task scheduler, the target is the first task scheduler, the task number is task 3, and the dynamic parameter includes the memory address in memory of the execution result of task 1.

[0121] In step 1009, the first task scheduler schedules the processor based on the fourth scheduling information and the fifth scheduling information.

[0122] The first task scheduler analyzes the received fourth scheduling information to determine the task type and static parameters of task 3, the first task scheduler analyzes the received fifth scheduling information to determine the static parameters of task 3, generates configuration information for task 3 based on the task type, static parameters and dynamic parameters of task 3, and schedules the processor to execute task 3 based on the configuration information of task 3.

[0123] In step 1010, a third task is executed by the processor.

[0124] The processor executes the third task, obtains the execution result of the third task, and then transmits the execution result of the third task to the first task scheduler.

[0125] The first task scheduler determines, based on the fourth scheduling information, that the succeeding task of the third task is the fourth task that needs to be executed by the third accelerator. After obtaining the execution result of the third task from the processor, the first task scheduler generates sixth scheduling information for scheduling the fourth task scheduler based on the execution result of the third task and the fourth scheduling information. The subsequent steps are similar to steps 1004 to 1010, and therefore will not be described here.

[0126] According to the task scheduling method of the embodiment of the present disclosure, the first task scheduler not only schedules other task schedulers, but also schedules the processor to execute a special task that the accelerator cannot execute, thereby realizing the scheduling and execution of the special task. When the first task scheduler schedules other task schedulers, it schedules and executes a task that the accelerator can execute, and when the first task scheduler schedules the processor, it schedules and executes a task that the accelerator cannot execute, thereby realizing the scheduling of different types of tasks by hardware and improving the flexibility of task scheduling.

[0127] (Exemplary Device) 11 is a structural schematic diagram of an SoC according to one exemplary embodiment of the present disclosure. As shown in FIG. 11, an SoC 1100 includes a processor 1101, a first accelerator 1104, a first task scheduler 1102, and a second task scheduler 1103. The processor 1101 is coupled to the second task scheduler 1103 via the first task scheduler 1102, and the second task scheduler 1103 is coupled to the first accelerator 1104.

[0128] Here, the processor 1101 determines a task set that needs to be executed by the SoC 1100 and the dependencies between each task in the task set, and is used to determine initial scheduling information for a first task that can be executed by the first accelerator 1104 based on the task set and the dependencies.

[0129] The first task scheduler 1102 is used to determine first scheduling information of the first task based on the initial scheduling information, and send the first scheduling information to the second task scheduler 1103 for scheduling the first accelerator 1104.

[0130] The second task scheduler 1103 is used to schedule the first accelerator 1104 based on the first scheduling information.

[0131] The first accelerator 1104 is used to execute the first task.

[0132] In some examples, the processor 1101 is also used to determine a first task from the task set that can be executed by the first accelerator 1104, determine related tasks from the task set that have dependencies on the first task based on the dependencies, and determine initial scheduling information for the first task based on the first task and the related tasks.

[0133] The first task scheduler 1102 is also used to determine first scheduling information of the first task based on the initial scheduling information of the first task.

[0134] In some examples, the second task scheduler 1103 is also used to determine, based on the first scheduling information, that the first task satisfies a task execution condition, analyze the first scheduling information to determine first configuration information required for executing the first task, and schedule the first accelerator based on the first configuration information.

[0135] FIG. 12 is a structural schematic diagram of an SoC according to another exemplary embodiment of the present disclosure. As shown in FIG. 12, in addition to the SoC 1100 shown in FIG. 11, the SoC 1100 further includes a second accelerator 1106 and a third task scheduler 1105 for scheduling the second accelerator 1106, and the first task scheduler 1102 is coupled to the second accelerator 1106 via the third task scheduler 1105.

[0136] The third task scheduler 1105 is used to determine second scheduling information for a second task that can be executed by the second accelerator 1106 .

[0137] The second task scheduler 1103 is also used to determine the execution result of the first task and send third scheduling information to the third task scheduler 1105 based on the execution result of the first task and the first scheduling information.

[0138] The third task scheduler 1105 is also used to schedule the second accelerator 1106 based on the second scheduling information and the third scheduling information.

[0139] The second accelerator 1106 is used to execute a second task, which is the next task after the first task.

[0140] In some examples, the third task scheduler 1105 is also used to determine a predecessor task that has a dependency relationship with the second task based on the second scheduling information, determine an execution result of the predecessor task based on the third scheduling information, and schedule the second accelerator 1106 based on the execution result of the predecessor task and the second scheduling information.

[0141] In some embodiments, the third task scheduler 1105 is also used to analyze the second scheduling information to determine second configuration information required for executing the second task, and schedule the second accelerator 1106 based on the execution result of the preceding task and the second configuration information.

[0142] In some embodiments, the first task scheduler 1102 is also used to determine fourth scheduling information for a third task that needs to be executed by a processor in the SoC.

[0143] The second task scheduler 1103 is also used to determine the execution result of the first task and send fifth scheduling information to the first task scheduler 1102 based on the execution result of the first task and the first scheduling information.

[0144] The first task scheduler 1102 is also used to schedule the processor 1101 based on the fourth scheduling information and the fifth scheduling information.

[0145] The processor 1101 is also used to perform a third task.

[0146] FIG. 13 is a structural schematic diagram of a first task scheduler according to an exemplary embodiment of the present disclosure. As shown in FIG. 13, the first task scheduler 1102 includes a task sending module 11021.

[0147] The task transmission module 11021 is coupled to the processor 1101 and the scheduling bus. In the SoC 1100 shown in FIG. 11, the task transmission module 11021 is used to receive initial scheduling information of a first task from the processor 1101, determine first scheduling information based on the initial scheduling information of the first task, and transmit the first scheduling information to the second task scheduler 1103 via the scheduling bus. In the SoC 1200 shown in FIG. 12, the task transmission module 11021 is used to receive initial scheduling information of a first task and initial scheduling information of a second task from the processor 1101, determine first scheduling information based on the initial scheduling information of the first task, determine second scheduling information based on the initial scheduling information of the second task, transmit the first scheduling information to the second task scheduler 1103 via the scheduling bus, and transmit the second scheduling information to the third task scheduler 1105.

[0148] 14 is a structural schematic diagram of a second task scheduler according to an exemplary embodiment of the present disclosure. As shown in FIG. 14, the second task scheduler 1103 includes a task receiving module 11031, a precondition determination module 11032, and a task trigger module 11033, which are coupled in sequence, and an interrupt response module 11034, an output module 11035, and a task transmission module 11036, which are coupled in sequence. The task receiving module 11031 and the task transmission module 11036 are both coupled to a scheduling bus, and are coupled to other task schedulers (the third task scheduler 1105 is shown as an example in FIG. 14) via the scheduling bus. The task trigger module 11033 and the interrupt response module 11034 are both coupled to the first accelerator 1104.

[0149] The task receiving module 11031 is used to receive first scheduling information from the scheduling bus, where the first scheduling information is the scheduling information from the task sending module 11021 in the first task scheduler 1102 shown in FIG.

[0150] The precondition determination module 11032 is used to determine whether the first task satisfies the task execution condition based on the first scheduling information, and if the first task satisfies the task execution condition, the first task can be triggered. In one implementation, if the first task is the first task waiting to be executed in the task set, the precondition determination module 11032 determines that the first task does not have a predecessor task with a dependency relationship and satisfies the task execution condition; if the first task is not the first task waiting to be executed in the task set, the precondition determination module 11032 determines that the first task has a predecessor task with a dependency relationship and satisfies the task execution condition when all the predecessor tasks on which the first task depends are executed.

[0151] The task trigger module 11033 is used to convert the first task that satisfies the task execution condition into configuration information corresponding to the first accelerator 1104. The first accelerator 1104 executes the first task based on the configuration information. In one implementation, the task trigger module 11033 can analyze the first scheduling information to determine first configuration information required to execute the first task, where the first configuration information is configuration information corresponding to the first accelerator 1104.

[0152] The interrupt response module 11034 is used to perform local processing on the interrupt of the first accelerator 1104, convert the interrupt into a processing result, and set the processing result as the execution result of the first task.

[0153] The output module 11035 is used to generate third scheduling information for triggering the lower-level task scheduler based on the execution result of the first task and the first scheduling information.

[0154] The task sending module 11036 is used to send the third scheduling information to the scheduling bus.

[0155] 15 is a structural schematic diagram of a third task scheduler according to an exemplary embodiment of the present disclosure. As shown in FIG. 15, the third task scheduler 1105 includes a task receiving module 11051, a precondition determination module 11052, and a task trigger module 11053, which are coupled in sequence, and an interrupt response module 11054, an output module 11055, and a task transmission module 11056, which are coupled in sequence. The task receiving module 11051 and the task transmission module 11056 are both coupled to a scheduling bus, and are coupled to other task schedulers (the fourth task scheduler 1107 is shown as an example in FIG. 15) via the scheduling bus. The task trigger module 11053 and the interrupt response module 11054 are both coupled to the second accelerator 1106.

[0156] The task receiving module 11051 is used to receive second scheduling information and third scheduling information from the scheduling bus, where the second scheduling information is the scheduling information from the task sending module 11021 in the first task scheduler 1102 shown in FIG. 13, and the third scheduling information is the scheduling information from the task sending module 11036 in the second task scheduler 1103 shown in FIG. 14.

[0157] The precondition determination module 11052 is used to determine whether the second task satisfies the task execution condition based on the second scheduling information. If the second task satisfies the task execution condition, the second task can be triggered. In one implementation, when the execution results of all predecessor tasks on which the second task depends are received, if it is determined that all of the predecessor tasks on which the second task depends have been executed, the second task is determined to satisfy the task execution condition. Whether the execution results of the predecessor tasks have been received can be determined by analyzing the scheduling information from the upper task scheduler. For example, when third scheduling information including the execution result of the first task is received, it is determined that the first task on which the second task depends has been executed. If the second task depends only on the first task, it can be determined that the predecessor task on which the second task depends has been executed. If the second task depends on other tasks in addition to the first task, it is necessary to further determine whether scheduling information including the execution results of the other tasks has been received.

[0158] The task trigger module 11053 is used to convert the second task that satisfies the task execution condition into configuration information corresponding to the second accelerator 1106. The second accelerator 1106 executes the second task based on the corresponding configuration information. In one implementation, the task trigger module 11053 can analyze the second scheduling information to determine second configuration information required to execute the second task, and use the corresponding second configuration information and the execution results of all preceding tasks of the second task as configuration information corresponding to the second accelerator 1106.

[0159] The interrupt response module 11054 is used to locally process the interrupt of the second accelerator 1106, convert the interrupt into a processing result, and make the processing result the execution result of the second task.

[0160] The output module 11055 is used to generate lower-level scheduling information for triggering a lower-level task scheduler based on the execution result of the second task and the third scheduling information. In some examples, if there is a subsequent task dependent on the second task, the lower-level scheduling information is used to schedule the lower-level task scheduler, which is a task scheduler for scheduling a lower-level accelerator, which is an accelerator capable of executing the subsequent task of the second task. The number of subsequent tasks of the second task may be one or more. If there is no subsequent task dependent on the second task, the lower-level scheduling information is used to schedule the first task scheduler 1102, which can send the execution result of the second task to the processor 1101.

[0161] The task sending module 11056 is used to send the low-level scheduling information to the scheduling bus.

[0162] In some examples, if there is a special task (hereinafter referred to as a third task) in the task set that cannot be executed by the hardware accelerator and needs to be executed by the processor 1101, the first task scheduler 1102 is also used to schedule the processor 1101 to execute the third task.

[0163] 16 is a structural schematic diagram of a first task scheduler according to another exemplary embodiment of the present disclosure. As shown in FIG. 16, the first task scheduler 1102 includes a task sending module 11021, a task receiving module 11022, a precondition determination module 11023, an interrupt trigger module 11024, a result trigger module 11025, and an output module 11026. The task sending module 11021 and the task receiving module 11022 are coupled to a scheduling bus and are coupled to other task schedulers (the second task scheduler 1103 and the third task scheduler 1105 are shown as examples in FIG. 16, respectively) via the scheduling bus. The task sending module 11021, the interrupt trigger module 11024, and the result trigger module 11025 are all coupled to the processor 1101.

[0164] The task receiving module 11022 is used to receive fifth scheduling information of the third task from the processor 1101, and is also used to receive fourth scheduling information from the scheduling bus, where the fourth scheduling information is scheduling information sent to the scheduling bus by the task scheduler corresponding to the preceding task on which the third task depends.

[0165] The precondition determination module 11023 is used to determine whether the third task satisfies the task execution condition based on the fifth scheduling information, and when all preceding tasks on which the third task depends are executed and it is determined that the third task satisfies the task execution condition, the third task can be triggered.

[0166] The interrupt trigger module 11024 is used to convert the third task that satisfies the task execution condition into interrupt configuration information corresponding to the processor 1101. The processor 1101 executes the third task based on the interrupt configuration information. In one implementation, the interrupt trigger module 11024 can analyze the fourth scheduling information to determine third configuration information required for executing the third task, and use the third configuration information and the execution results of all preceding tasks of the third task as the interrupt configuration information corresponding to the processor 1101.

[0167] The result trigger module 11025 is used to receive a trigger from the processor 1101 and obtain the execution result of the third task executed by the processor 1101 .

[0168] The output module 11026 is used to generate lower-level scheduling information for triggering the lower-level task scheduler based on the execution result of the third task and the fifth scheduling information.

[0169] The task sending module 11021 is used to send the lower-level scheduling information to the scheduling bus, and send the lower-level scheduling information to the lower-level task scheduler via the scheduling bus.

[0170] The above description of the exemplary embodiments of the apparatus is similar to the description of the above method, and has the same beneficial effects as the corresponding exemplary embodiments of the method. Those skilled in the art can understand the technical details and corresponding beneficial technical effects not disclosed in the exemplary embodiments of the apparatus of the present disclosure by referring to the description of the exemplary embodiments of the method of the present disclosure, and will not be described here.

[0171] (Example Electronic Devices) FIG. 17 is a structural diagram of an electronic device according to one embodiment of the present disclosure. An electronic device 1700 includes at least one processor 1701 and a memory 1702.

[0172] The processor 1701 may be a central processing unit (CPU) or other type of processing unit having data processing and / or instruction execution capabilities, and may control other components within the electronic device 1700 to perform desired functions.

[0173] The memory 1702 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. The computer-readable storage media may store one or more computer program instructions, and the processor 1701 may execute the one or more computer program instructions to implement the task scheduling method of each embodiment of the present disclosure and / or other desired functions.

[0174] In one example, the electronic device 1700 may further include input devices 1703 and output devices 1704 connected to each other via a bus system and / or other type of connection mechanism (not shown).

[0175] The input device 1703 may include, for example, a keyboard, a mouse, and the like.

[0176] The output device 1704 can output various information to the outside, and can include, for example, a display, a speaker, a printer, a communication network, and remote output devices connected thereto.

[0177] 17 shows only some of the components related to the present disclosure in the electronic device 1700, and omits components such as buses, input / output interfaces, etc. In addition, the electronic device 1700 may further include any appropriate components according to specific application requirements.

[0178] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the above-described methods and apparatuses, embodiments of the present disclosure may provide a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the SoC-based task scheduling method according to the embodiments of the present disclosure described in the "Exemplary Method" section above.

[0179] The computer program product may have program code for carrying out operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and traditional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on the remote computing device or a server.

[0180] Additionally, the embodiments of the present disclosure may further provide a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps of the SoC-based task scheduling method according to the embodiments of the present disclosure described in the "Exemplary Method" section above.

[0181] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more conductors, a mobile hard drive, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0182] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the benefits, advantages, and effects mentioned in the present disclosure are merely illustrative and not limiting, and these benefits, advantages, and effects are not necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details of the above disclosure are merely illustrative and easy-to-understand functions and are not limiting, and the above details do not necessarily limit the present disclosure to those realized by the above specific details.

[0183] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. determining a set of tasks that need to be executed by the system on chip and dependencies between tasks in the set of tasks; determining, based on the task set and the dependency relationships, first scheduling information for a first task executable by a first accelerator in the system-on-chip; a step of transmitting the first scheduling information by a first task scheduler in the system-on-chip to a second task scheduler in the system-on-chip for scheduling the first accelerator, the first task scheduler and the second task scheduler scheduling each other via a scheduling bus, and the second task scheduler and the first accelerator having a correspondence relationship; scheduling the first accelerator by the second task scheduler based on the first scheduling information, and executing a first task by the first accelerator.

2. determining first scheduling information for a first task executable by a first accelerator in the system-on-chip based on the task set and the dependency relationships, determining a first task from the task set that is executable by the first accelerator; determining, from the task set, a related task that has a dependency relationship with the first task based on the dependency relationship; and determining first scheduling information for the first task based on the first task and the related task.

3. The step of scheduling the first accelerator by the second task scheduler based on the first scheduling information includes: determining, based on the first scheduling information, that the first task satisfies a task execution condition; analyzing the first scheduling information by the second task scheduler to determine first configuration information required for executing the first task; and scheduling the first accelerator by the second task scheduler based on the first configuration information.

4. determining, by a third task scheduler for scheduling a second accelerator in the system-on-chip, second scheduling information of a second task executable by the second accelerator in the system-on-chip; determining, by the second task scheduler, an execution result of the first task; sending third scheduling information to the third task scheduler by the second task scheduler based on the execution result of the first task and the first scheduling information; 4. The system-on-chip-based task scheduling method according to claim 1, further comprising: scheduling the second accelerator by the third task scheduler based on the second scheduling information and the third scheduling information, and executing a second task that is a next task of the first task by the second accelerator.

5. The step of scheduling the second accelerator by the third task scheduler based on the second scheduling information and the third scheduling information includes: determining, by the third task scheduler based on the second scheduling information, a predecessor task that has a dependency relationship with the second task; determining an execution result of the preceding task based on the third scheduling information; and scheduling the second accelerator by the third task scheduler based on the execution result of the preceding task and the second scheduling information.

6. The step of scheduling the second accelerator by the third task scheduler based on the execution result of the preceding task and the second scheduling information includes: analyzing the second scheduling information by the third task scheduler to determine second configuration information required for executing the second task; and scheduling the second accelerator by the third task scheduler based on the execution result of the preceding task and the second configuration information.

7. determining, by the first task scheduler, fourth scheduling information for a third task that needs to be executed by a processor in the system-on-chip; determining, by the second task scheduler, an execution result of the first task; sending fifth scheduling information to the first task scheduler by the second task scheduler based on the execution result of the first task and the first scheduling information; 4. The system-on-chip-based task scheduling method according to claim 1, further comprising the steps of: scheduling the processor by the first task scheduler based on the fourth scheduling information and the fifth scheduling information; and executing the third task by the processor.

8. a processor, a first accelerator, a first task scheduler, and a second task scheduler, wherein the processor is coupled to the second task scheduler via the first task scheduler, the second task scheduler is coupled to the first accelerator, the first task scheduler and the second task scheduler schedule each other via a scheduling bus, and the second task scheduler and the first accelerator have a correspondence relationship; The processor is used to determine a task set that needs to be executed by the system on chip and dependencies between tasks in the task set, and to determine initial scheduling information for a first task that can be executed by the first accelerator based on the task set and the dependencies; the first task scheduler is used to determine first scheduling information for the first task based on the initial scheduling information and send the first scheduling information to a second task scheduler for scheduling the first accelerator; the second task scheduler is used to schedule the first accelerator based on the first task scheduler; The system-on-chip, wherein the first accelerator is used to execute the first task.

9. a second accelerator; and a third task scheduler for scheduling the second accelerator, wherein the first task scheduler is coupled to the second accelerator via the third task scheduler; the third task scheduler is used to determine second scheduling information for a second task executable by the second accelerator; the second task scheduler is also used to determine an execution result of the first task and to send third scheduling information to the third task scheduler based on the execution result of the first task and the first scheduling information; the third task scheduler is also used to schedule the second accelerator based on the second scheduling information and the third scheduling information; 9. The system-on-chip of claim 8, wherein the second accelerator is used to execute the second task, which is a subsequent task to the first task.

10. 10. A computer-readable storage medium having stored thereon a computer program for executing the system-on-chip based task scheduling method according to claim 1.

11. a processor; a memory for storing instructions executable by the processor; The electronic device according to claim 1 , wherein the processor implements the task scheduling method based on a system-on-chip according to claim 1 by reading and executing the instructions from the memory.

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