Display panel and display device including the same

Abstract

To provide a display panel that offers an improved aperture ratio of each pixel, and a display device including the same.SOLUTION: In order to accomplish the above challenge, a display panel disclosed herein includes a first pixel PXL1 and a second pixel PXL2 arranged next to each other in a first direction. Each of the first pixel and the second pixel includes first through third sub-pixels. The first pixel and the second pixel share a plurality of white sub-pixels. A plurality of gate lines GLn is arranged along the first direction, and two gate lines sandwiching two light-emitting areas for respectively emitting light of different colors in a second direction are connected to each other. Each scan line for driving only a sensor transistor of each of the first pixel and the second pixel may be disposed between the two light-emitting areas of different colors and between the two gate lines that are connected to each other.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present specification relates to a display panel and a display device, and more particularly to a display panel that can improve the aperture ratio of each pixel without any restrictions, and a display device including the same. [Background technology]

[0002] Organic light emitting display devices include organic light emitting diodes (hereinafter referred to as "OLEDs") that emit light themselves, and have the advantages of a fast response time, luminous efficiency, brightness, and a wide viewing angle. Organic light emitting display devices not only have excellent response time, luminous efficiency, brightness, and viewing angle, but also have excellent contrast ratio and color reproduction rate because they can display black gradations as perfect black.

[0003] Although various studies have been conducted to improve the aperture ratio of organic light-emitting display devices, it is difficult to achieve a design that improves the aperture ratio due to the large number of wirings required to drive the pixels.Furthermore, it is even more difficult to achieve a high aperture ratio when each pixel consists of four colors, including red, green, blue, and white. The description of related art should not be considered prior art merely because it is described in or related to this section. The description of related art includes information that describes one or more aspects of the subject technology; the description in this section does not limit the invention. Summary of the Invention [Problem to be solved by the invention]

[0004] The inventors of the present specification recognized the problems and needs of the related art and conducted extensive research and experimentation to invent a display panel in which a separate scan line is arranged between existing gate lines to drive only the sensor transistor of each pixel, and a display device including the same. One or more aspects of the present specification relate to an apparatus that substantially eliminates one or more problems due to limitations and drawbacks of the related art.

[0005] The problem to be solved by the embodiments of the present specification is to provide a display panel in which, between two gate lines arranged through two light-emitting areas of different colors, a scan line is arranged between each of the two light-emitting areas of different colors to drive only the sensor transistor of each pixel. One or more aspects of the present disclosure provide a display device including the display panel defined above.

[0006] The object of the present specification is not limited to the object mentioned above, and other unmentioned objects and advantages of the present specification can be understood from the following description and can be more clearly understood from the embodiments of the present specification. Furthermore, it can be easily understood that the object and advantages of the present specification can be achieved by the means and combinations thereof set forth in the claims. [Means for solving the problem]

[0007] According to an embodiment of the present disclosure, there may be provided a display panel including a first pixel and a second pixel adjacent to the first pixel in a first direction, each of the first pixel and the second pixel including a first sub-pixel, a second sub-pixel, and a third sub-pixel having different colors and arranged in a second direction intersecting the first direction, the first pixel and the second pixel sharing a plurality of white sub-pixels, each of the first sub-pixels of the first pixel and the second pixel including a first pixel circuit and a first light-emitting region connected to the first pixel circuit, each of the second sub-pixels of the first pixel and the second pixel including a second pixel circuit and a second light-emitting region connected to the second pixel circuit, and each of the third sub-pixels of the first pixel and the second pixel including a third pixel circuit and a second light-emitting region connected to the third pixel circuit. a third light-emitting region connected to the fourth pixel circuit; each of the plurality of white sub-pixels shared by the first pixel and the second pixel includes a fourth pixel circuit and a fourth light-emitting region connected to the fourth pixel circuit; a plurality of gate lines extend along the first direction and are arranged in the second direction, each emitting a different color; two light-emitting regions adjacent to each other in the second direction are provided between two gate lines of the plurality of gate lines that are connected to each other; each scan line emits a different color and is provided between the two light-emitting regions adjacent to each other in the second direction and between the two gate lines that are connected to each other; and the scan lines are configured to drive only the sensor transistors of the first pixel and the second pixel.

[0008] According to an embodiment of the present disclosure, there is provided a display device including a display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels, a data driver configured to convert pixel data into data voltages and supply the data voltages to the plurality of data lines, a gate driver configured to sequentially supply gate pulses to the plurality of gate lines, and a timing controller configured to transmit the pixel data to the data driver and control the data driver and the gate driver, wherein the plurality of pixels include a first pixel and a second pixel adjacent to the first pixel in a first direction, each of the first pixel and the second pixel including a first sub-pixel, a second sub-pixel, and a third sub-pixel having different colors and arranged in a second direction intersecting the first direction, the first pixel and the second pixel sharing a plurality of white sub-pixels, each of the first sub-pixels of the first pixel and the second pixel including a first pixel circuit and a first light-emitting region connected to the first pixel circuit, Each of the second sub-pixels of the first pixel and the second pixel includes a second pixel circuit and a second light-emitting region connected to the second pixel circuit, each of the third sub-pixels of the first pixel and the second pixel includes a third pixel circuit and a third light-emitting region connected to the third pixel circuit, each of the white sub-pixels shared by the first pixel and the second pixel includes a fourth pixel circuit and a fourth light-emitting region connected to the fourth pixel circuit, a plurality of gate lines extend along the first direction and are arranged in the second direction, each emitting a different color, two light-emitting regions adjacent to each other in the second direction are disposed between two gate lines of the plurality of gate lines that are connected to each other, and each scan line emits a different color and is disposed between the two light-emitting regions adjacent to each other in the second direction and between the two gate lines that are connected to each other, and the scan linesThe display device is configured to drive only the sensor transistors of the first pixel and the second pixel. [Effects of the Invention]

[0009] According to an embodiment of the present specification, scan lines for driving only the sensor transistor of each pixel may be arranged between subpixels where there is no gate line for driving the existing scan transistor.

[0010] According to an embodiment of the present specification, in order to form an efficient two-scan structure, the layout of the existing pixel drive voltage (EVDD) wiring and reference voltage (Vref) wiring may be swapped with each other, and a sensor transistor (Sensor Tr) may be placed between the pixel drive voltage (EVDD) wirings and extend to both branches.

[0011] According to the embodiment of the present specification, it is possible to form a two-scan structure capable of driving a normal four-sub pixel (DRD) double rate driving method by increasing the white sub-pixel area.

[0012] Furthermore, according to the embodiments of the present specification, it is possible to drive pixels with high efficiency and high brightness using four sub-pixel driving, so that the display panel can be driven with low power consumption.

[0013] Furthermore, according to the embodiments of the present specification, it is possible to provide a display panel that improves the aperture ratio and allows for easy repair design.

[0014] Furthermore, according to the embodiments of the present specification, since the light-emitting regions that generate white light are not continuous, images can be reproduced on the display panel without white horizontal or vertical stripes, thereby improving display quality.

[0015] In addition, according to the embodiments of the present specification, adjacent pixels alternately drive four sub-pixels and three sub-pixels, thereby increasing the brightness of the image reproduced on the display panel and improving the color reproduction ratio.

[0016] Furthermore, according to the embodiments of the present specification, the light-emitting area of ​​the white subpixel can be enlarged without bending the wiring pattern.

[0017] Furthermore, according to the embodiments of the present specification, pixel circuits for driving subpixels of the same color are adjacent to each other in the horizontal direction without any light-emitting area, so that there is almost no reduction in aperture ratio due to repair patterns disposed between them.

[0018] Furthermore, according to the embodiments of the present specification, it is possible to improve the color reproduction rate and improve the display quality, thereby preventing a decrease in the lifespan of the display panel.

[0019] Furthermore, according to the embodiments of the present specification, there is an effect that the display quality is improved, thereby reducing power consumption and improving the life span.

[0020] Furthermore, according to the embodiments of the present specification, there is an effect that the life span can be improved by reducing power consumption, and a display device with a long life span can be provided.

[0021] The display device according to the present disclosure can reduce power consumption, thereby mitigating the reduction in panel lifespan and improving the quality of the display device.

[0022] The effects of this specification are not limited to those mentioned above, and other effects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0023] The above-mentioned effects as well as the specific effects of this specification will be described in conjunction with the following description of the preferred embodiment of the invention. Additional features, advantages, and aspects of the specification will be set forth in part in the description that follows, and in part will be apparent from the specification or may be learned by practicing the inventive concepts provided herein. Other features, advantages, and aspects of the specification will be realized and attained by the description provided herein or derived therefrom, and by the claims and drawings herein. All of these features, advantages, and aspects are intended to be included within this description, be within the scope of the specification, and be protected by the following claims. Nothing in this section should be construed as a limitation on the claims. Additional aspects and advantages will be discussed below with respect to embodiments of the specification. It is to be understood that both the foregoing description and the following description herein are examples, and are intended to provide further explanation as set forth in the claims. [Brief explanation of the drawings]

[0024] The accompanying drawings, which are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this disclosure, illustrate aspects and embodiments of the disclosure, and together with the description, serve to explain the principles and examples of the disclosure. [Figure 1] 1 is a diagram schematically illustrating a configuration of a display device according to an embodiment of the present specification. [Figure 2] FIG. 2 is a diagram illustrating a first and a second pixel according to an embodiment of the present invention. [Figure 3] FIG. 3 is an equivalent circuit diagram showing in detail an example of the pixel circuit shown in FIG. 2. [Figure 4] FIG. 2 is a circuit diagram illustrating an example of a unit pixel circuit. [Figure 5] FIG. 1 shows a luminous region of 22 pixels. [Figure 6] FIG. 10 is a diagram illustrating an example of a hybrid driving method. [Figure 7] 10 is a diagram illustrating an example in which gate lines are arranged in a two-scan structure in a display panel according to an embodiment of the present specification. FIG. [Figure 8a]FIG. 10 is a diagram showing an example in which the second power supply wiring (RL) is swapped with the first power supply wiring (VL) in a display panel according to an embodiment of the present specification. [Figure 8b] FIG. 10 is a diagram showing an example in which the width of the first power supply wiring (VL) is formed to be greater than the width of the second power supply wiring (RL) in a display panel according to an embodiment of the present specification. [Figure 9a] 3A and 3B are diagrams illustrating exemplary arrangements of first and second scan lines in a display panel according to an embodiment of the present specification. [Figure 9b] 9b is an enlarged view of area A of FIG. 9a in a display panel according to an embodiment of the present specification. [Figure 9c] 9b in accordance with an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating an example in which gate lines and scan lines are arranged in a third light-emitting region (ER) in a display panel according to an embodiment of the present specification. [Figure 11] 11 is a cross-sectional view of a display panel according to an embodiment herein taken along cut line AA' of FIG. 10. [Figure 12a] 2A and 2B are diagrams illustrating exemplary arrangements of gate lines and scan lines in a display panel according to an embodiment of the present specification. [Figure 12b] 12a is a cross-sectional view of a display panel according to an embodiment herein taken along cut line B-B' in FIG. 12a. Unless otherwise noted throughout the drawings and detailed description, like drawing reference numbers should be understood to refer to like elements, features, and structures. Sizes, lengths, and thicknesses of layers, regions, and elements, and their depictions, may be exaggerated for clarity, explanation, and / or convenience. DETAILED DESCRIPTION OF THE INVENTION

[0025] The above-mentioned objects, features, and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the technical concept of the present invention. In describing the present invention, if a detailed description of known technologies according to the present invention is deemed to obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings are used to indicate the same or similar components.

[0026] Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it should be understood that the components may be directly coupled or connected to each other, but that other components may be "intervening" between the components, or that each component may be "coupled," "coupled," or "connected" via other components.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification can be used in the sense that they can be commonly understood by a person having ordinary skill in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries should not be interpreted ideally or excessively unless they are clearly and specifically defined.

[0028] In the following, a display device that obtains energy to provide AR or VR and further increases the usage time of power consumption according to an embodiment of the present specification will be described.

[0029] FIG. 1 is a diagram schematically illustrating the configuration of a display device according to an embodiment of the present specification.

[0030] Referring to FIG. 1, a display device according to the present specification may include a display panel 100, a display panel drive circuit for writing pixel data to pixels of the display panel 100, and a power supply unit 140 for generating power necessary to drive the pixels and the display panel drive circuit.

[0031] The display panel 100 may include a display area (active area; AA) and a non-active area (non-active area; NA).

[0032] The display panel 100 may include a substrate and a number of sub-pixels arranged on the substrate, and may further include various signal lines for driving the number of sub-pixels.

[0033] The display area (AA) may include a number of data lines (DL) that transmit data signals (also called data voltages or video signals) and a number of gate lines (GL) that transmit gate signals (also called scan signals).

[0034] The plurality of data lines and the plurality of gate lines may cross each other. Each of the plurality of data lines may be arranged to extend in a first direction. Each of the plurality of gate lines may be arranged to extend in the first direction. Here, the first direction may be a row direction and the second direction may be a column direction. The first direction may be a column direction and the second direction may be a row direction.

[0035] The non-display area (NA) may be the outer periphery of the display area (AA) and may include a bezel area. The non-display area (NA) may be entirely or partially visible from the front of the display device, or may be curved and not visible from the front of the display device.

[0036] The display panel 100 may be a rectangular panel having a length in the X-axis direction (or first direction), a width in the Y-axis direction (or second direction), and a thickness in the Z-axis direction (or third direction). The X-axis and Y-axis may be linear axes that are perpendicular to each other on the XY plane. The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. The display panel 100 also includes a power supply line commonly connected to the pixels. The power supply line is connected to a constant voltage node of the pixel circuit to supply a constant voltage required to drive the pixels PXL to the pixels PXL. The power supply line PXL may be implemented as a stripe or mesh wiring and commonly connected to the pixels of the display panel 100.

[0037] Each pixel (PXL) includes a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, each having a different color to realize a color. The color arrangement of the subpixels may be changed. The first subpixel may be a blue (B) subpixel, the second subpixel may be a green (G) subpixel, the third subpixel may be a red (R) subpixel, and the fourth subpixel may be a white (W) subpixel, but is not limited to this. Each subpixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit is connected to a data line, a gate line, and a power line. Each subpixel is divided into a circuit area and a light-emitting area. The pixel circuit is arranged in the circuit area. The light-emitting area is an area where light is emitted from a light-emitting element electrically connected to the pixel circuit.

[0038] The pixel array includes a plurality of pixel lines (L1 to LN). Each of the pixel lines (L1 to LN) includes one line of pixels arranged along the line direction (X-axis direction) of the pixel array of the display panel 100. The pixels arranged in one pixel line share a gate line (GL). The sub-pixels arranged in the column direction (Y) along the data line direction share the same data line (DL). One horizontal period is the time obtained by dividing one frame period by the total number of pixel lines (L1 to LN).

[0039] The power supply unit 140 uses a DC-DC converter to output a voltage required to drive the pixels of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc.

[0040] The display panel driving circuit writes pixel data of an input image to pixels of the display panel 100 under the control of a timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0041] The display panel driver circuit can drive pixels in a DRD (Double Rate Driving) mode. In a display panel driven in the DRD mode, a data line (DL) is connected to adjacent sub-pixels on the left and right, which reduces the number of channels of the data driver 110 and the number of data lines (DL), which is advantageous in ensuring the aperture ratio of the pixel.

[0042] The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensor. The touch sensor driving unit is omitted in Fig. 1. The data driving unit 110 and the touch sensor driving unit may be integrated together into one source drive integrated circuit (IC).

[0043] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage for each frame period using a digital-to-analog converter (DAC) and outputs the data voltage. The data voltage is output through an output buffer in each channel of the data driver 110.

[0044] The gate driver 120 may be formed on the display panel 100 together with the TFT array and wiring of the pixel array. The gate driver 120 may be disposed on the non-display area (NA) of the display panel 100, or at least a portion of the gate driver 120 may be disposed within the display area (AA) where an input image is reproduced.

[0045] The gate driver 120 is disposed in non-display areas (NA) on both sides of the display panel 100 across the display area (AA) of the display panel 100 and can supply gate pulses to both sides of the gate lines (GL) in a double-feed manner. In another embodiment, the gate driver 120 is disposed on either the left or right non-display area (NA) of the display panel 100 and can supply gate signals to the gate lines (GL) in a single-feed manner. The gate driver 120 sequentially outputs gate signal pulses to the gate lines under the control of the timing controller 130. The gate driver 120 can sequentially supply gate signal pulses to the gate lines (GL) by shifting the gate signal pulses (hereinafter referred to as gate pulses) using a shift register. The gate driver 120 may include a plurality of shift registers that output gate signal pulses.

[0046] The timing controller 130 receives digital video data of an input image and timing signals synchronized with the data from the host system 200. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a clock, and a data enable signal. The vertical synchronization signal and the horizontal synchronization signal can be omitted because the vertical period and the horizontal period can be determined by counting the data enable signal. The data enable signal has a period of one horizontal period (1H). The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals received from the host system 200.

[0047] The timing controller 130 may add white data to three-primary-color pixel data (RGB) input from the host system to convert it into four-color sub-color data (RGBW) and transmit it to the data driver 110. A known color conversion algorithm may be used to convert the three-primary-color pixel data (RGB) into four-color sub-color data (RGBW) including white color data. For example, the timing controller 130 may generate W data of first pixel data based on the minimum grayscale value among R data, G data, and B data of first pixel data received in the input image data, and convert the first pixel data into four-color sub-color data (RGBW). The timing controller 130 may also generate W data of second pixel data based on the minimum grayscale value among R data, G data, and B data of second pixel data received in the input image data, and convert the second pixel data into four-color sub-color data (RGBW). In each of the first and second pixel data, the grayscale values ​​of the R, G, and B data may be lowered by the W data. Here, R data is data written to the red subpixels, G data is data written to the green subpixels, B data is data written to the blue subpixels, and W data is data written to the white subpixels.

[0048] The level shifter 150 receives a gate timing control signal from the timing controller 130, generates a start pulse and a shift clock, and provides the start pulse and shift clock to the gate driver 120. The start pulse and shift clock output from the level shifter 150 swing between a gate high voltage and a gate low voltage.

[0049] The host system 200 may include a main board of a TV (television) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, or a wearable terminal. The host system can scale a video signal from a video source to match the resolution of the display panel 100 and transmit the scaled video signal together with a timing signal to the timing controller 130.

[0050] The display device according to the embodiment of the present specification may be a liquid crystal display device, and the display panel 100 may be a self-emitting light-emitting display device. When the display device according to the embodiment of the present specification is a self-emitting light-emitting display device, each of the plurality of sub-pixels may include a light-emitting element.

[0051] For example, the display device according to the embodiment of the present specification may be an organic light emitting display device in which the light emitting elements are organic light emitting diodes (OLEDs). Alternatively, the display panel 100 according to the embodiment of the present specification may be an inorganic light emitting display device in which the light emitting elements are inorganic light emitting diodes. Alternatively, the display panel 100 according to the embodiment of the present specification may be a quantum dot display device in which the light emitting elements are quantum dots, which are semiconductor crystals that emit light themselves.

[0052] The structures of the subpixels vary depending on the type of display device. For example, if the display panel 100 is a self-emitting display device in which the subpixels emit light themselves, each subpixel may include a light-emitting element that emits light itself, one or more transistors, and one or more capacitors.

[0053] The display device according to the embodiments of this specification may include a touch sensor to provide not only an image display function but also a touch sensor circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, or to detect the touch position.

[0054] The touch sensor circuit may include a touch drive circuit that drives and senses the touch sensor and generates and outputs touch sensor data, and a touch controller that can sense the occurrence of a touch or detect the touch position using the touch sensor data.

[0055] The touch sensor may include a plurality of touch electrodes, and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to a touch driving circuit.

[0056] The touch sensor may be present outside the display panel 100 in the form of a touch panel, or may be present inside the display panel 100 .

[0057] When the touch sensor is in the form of a panel and is present outside the display panel 100, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 100 can be manufactured separately and combined during an assembly process. The external type touch panel may include a touch panel substrate and a number of touch electrodes on the touch panel substrate.

[0058] When the touch sensor is present inside the display panel 100, the touch sensor may be formed on the substrate (SUB) together with signal lines and electrodes related to driving the display during the manufacturing process of the display panel 100.

[0059] The touch drive circuit may supply a touch drive signal to at least one of the plurality of touch electrodes, sense the at least one of the plurality of touch electrodes, and generate touch sensor data.

[0060] The touch sensor circuit can perform touch sensing using a self-capacitance sensor method or a mutual-capacitance sensor method.

[0061] When the touch sensor circuit performs touch sensing using a self-capacitance sensor method, the touch sensor circuit can perform touch sensing based on capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0062] According to the self-capacitance sensor method, each of the plurality of touch electrodes can function as both a driving touch electrode and a sensing touch electrode, and the touch driving circuit can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0063] When the touch sensor circuit performs touch sensing using a mutual-capacitance sensor method, the touch sensor circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0064] According to the mutual-capacitance sensor method, a plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes, and a touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0065] The touch driver circuit and the touch controller included in the touch sensor circuit may be implemented as separate devices or as a single device, and the touch driver circuit and the data driver 110 may be implemented as separate devices or as a single device.

[0066] The display device according to the embodiments of this specification may be a mobile terminal such as a smartphone or a tablet PC, or may be a monitor or television (TV) of various sizes, or may be a display device of various types and sizes that can display information or images, without being limited thereto.

[0067] 2 is a diagram illustrating a first and a second pixel according to an embodiment of the present invention. The pixels of the display panel may be arranged in a form in which the first and second pixel structures are repeated.

[0068] Referring to FIG. 2, the display panel 100 may be arranged in a mirror symmetrical structure with respect to the Y axis and may include first and second pixels (PXL1, PXL2) adjacent to each other in the first direction, i.e., the X axis direction.

[0069] Each of the first pixel (PXL1) and the second pixel (PXL2) may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that are different in color from each other.

[0070] The first pixel (PXL1) and the second pixel (PXL2) can share multiple white sub-pixels.

[0071] The display panel 100 includes a first data line pair (DL10) arranged on wiring aligned in the Y-axis direction on the left side of the first pixel (PXL1), a second data line pair (DL20) arranged on wiring aligned in the Y-axis direction at the boundary between the first pixel (PXL1) and the second pixel (PXL2), a third data line pair (DL30) arranged on wiring aligned in the Y-axis direction on the right side of the second pixel (PXL2), a first power supply line (PL10) arranged on wiring aligned in the Y-axis direction between the first data line pair (DL10) and the second data line pair (DL20), and a second power supply line (PL20) arranged on wiring aligned in the Y-axis direction between the second data line pair (DL20) and the third data line pair (DL30).

[0072] The first power supply line (PL10) and the second power supply line (PL20) may each include a plurality of first power supply wirings (VL) to which a pixel drive voltage (EVDD) is applied and a second power supply wiring (RL) to which a reference voltage (Vref) is applied. The plurality of first power supply wirings (VL) may be arranged on both sides of the second power supply wiring (RL) and connected to each other. The width of each of the plurality of first power supply wirings (VL) may be greater than the width of the second power supply wiring (RL).

[0073] In FIG. 2, the first vertical reference line (VL1) is a virtual line extending in the Y-axis direction between the first data line pair (DL10) and the first power supply line (VL, RL). The second vertical reference line (VL2) is a virtual line extending in the Y-axis direction between the first power supply line (VL, RL) and the second data line pair (DLW, DLR). The third vertical reference line (VL3) is a virtual line extending in the Y-axis direction between the second data line pair (DLW, DLR) and the second power supply line (VL, RL). The fourth vertical reference line (VL4) is a virtual line extending in the Y-axis direction between the second power supply line (VL, RL) and the third data line pair (DL30).

[0074] The first pixel (PXL1) includes a blue subpixel, a green subpixel, and a red subpixel arranged along the Y-axis direction so as to pass through virtual first and second vertical reference lines (VL1, VL2). The second pixel (PXL2) includes a blue subpixel, a green subpixel, and a red subpixel arranged along the Y-axis direction so as to pass through virtual third and fourth vertical reference lines (VL3, VL4). The blue subpixel, green subpixel, and red subpixel are separated from each other between the first and second pixels (PXL1, PXL2). Independent R, G, and B data are written to the first and second pixels (PXL1, PXL2).

[0075] The first and second pixels (PXL1, PXL2) share a plurality of white sub-pixels, whose emissive areas (EW) include the areas where the second and third vertical reference lines (VR2, VR3) intersect with the virtual fourth horizontal reference line (HR4).

[0076] Each of the first and second pixels (PXL1, PXL2) may have four subpixels or three subpixels driven. The four subpixels include a red subpixel, a green subpixel, a blue subpixel, and a shared white subpixel. The three subpixels include a red subpixel, a green subpixel, and a blue subpixel excluding the white subpixel.

[0077] When the first pixel (PXL1) is driven with four sub-pixels, the W data generated from the R, G, and B data of the first pixel (PXL1) is written to the white sub-pixel. When the second pixel (PXL2) is driven with four sub-pixels, the W data generated from the R, G, and B data of the second pixel (PXL2) is written to the white sub-pixel.

[0078] The first and second pixels (PXL1, PXL2) can be driven in a hybrid manner. For example, when the first pixel (PXL1) is driven with four subpixels, the second pixel (PXL2) can be driven with three subpixels. When the second pixel (PXL2) is driven with four subpixels, the first pixel (PXL1) can be driven with three subpixels.

[0079] The timing controller 130 analyzes whether the input image is a pure color or the saturation of the input image, and when the saturation is equal to or greater than a predetermined reference value, it can simultaneously drive three sub-pixels (PXL1, PXL2) and not drive the white sub-pixel.

[0080] The blue subpixel includes a first pixel circuit (CB) and a first light-emitting region (EB) connected to the first pixel circuit (CB) and emitting blue light. The green subpixel includes a second pixel circuit (CG) and a second light-emitting region (EG) connected to the second pixel circuit (CG) and emitting green light. The red subpixel includes a third pixel circuit (CR) and a third light-emitting region (ER) connected to the third pixel circuit (CR) and emitting red light. The white subpixel includes a fourth pixel circuit (CW1, CW2) and a fourth light-emitting region (EW1, EW2) connected to the fourth pixel circuit (CW1, CW2) and emitting white light. An anode electrode of a light-emitting element (EL) may be disposed in each of the light-emitting regions (EB, EG, ER, EW). The pixel circuits (CB, CG, CR, CW1, CW2) are connected to the anode electrodes of the corresponding light-emitting areas. When a current is generated from the driving element of the pixel circuit, the light-emitting area can emit light. The 4-1st light-emitting area (EW1) is connected to the 4-1st pixel circuit (CW1), and the 4-2nd light-emitting area (EW2) is connected to the 4-2nd pixel circuit (CW2).

[0081] In the white subpixel, the fourth light-emitting region (EW1, EW2) can be driven by two fourth pixel circuits (CW1, CW2). The 4-1st pixel circuit (CW1) and the 4-2nd pixel circuit (CW2) are connected to different gate lines as shown in FIG. 3, and gate pulses are input sequentially to drive the light-emitting element of the white subpixel. Here, the fourth light-emitting region (EW1, EW2) includes the 4-1st light-emitting region (EW1) and the 4-2nd light-emitting region (EW2), but is not limited thereto. For example, as shown in Figures 5 and 6, one fourth light-emitting region (EW) may be arranged for each pixel, and the first pixel (PXL1) and the second pixel (PLX2) may share one fourth light-emitting region (EW), or the third pixel (PXL3) and the fourth pixel (PLX4) may share one fourth light-emitting region (EW).

[0082] On the first vertical reference line (VR1), the first pixel circuit (CB) of the first pixel (PXL1), the left side of the first light-emitting area (EB), the left side of the second light-emitting area (EG), the second pixel circuit (CG), and the left side of the third light-emitting area (ER) are arranged from top to bottom.

[0083] On the second vertical reference line (VR2), the right side of the first light-emitting area (EB) of the first pixel (PXL1), the right side of the second light-emitting area (EG), the third pixel circuit (CR), the right side of the third light-emitting area (ER), the 4-1st light-emitting area (EW1), and the 4-1st pixel circuit (CW1) are arranged from top to bottom.

[0084] On the third vertical reference line (VR3), the left side of the first light-emitting area (EB) of the second pixel (PXL2), the left side of the second light-emitting area (EG), the third pixel circuit (CR), the left side of the third light-emitting area (ER), the 4-2 light-emitting area (EW2), and the 4-2 pixel circuit (CW2) are arranged from top to bottom.

[0085] On the fourth vertical reference line (VR4), the first pixel circuit (CB) of the second pixel (PXL2), the right side of the first light-emitting area (EB), the right side of the second light-emitting area (EG), the second pixel circuit (CG), and the right side of the third light-emitting area (ER) are arranged from top to bottom.

[0086] The first and second pixels (PXL1, PXL2) have light-emitting regions of the same color arranged along the X-axis direction. For example, the first light-emitting region (EB) of the first and second pixels (PXL1, PXL2) is arranged on a virtual first horizontal reference line (HR1) aligned in the X-axis direction, and the second light-emitting region (EG) of the first and second pixels (PXL1, PXL2) is arranged below the first light-emitting region (EB) on a virtual second horizontal reference line (HR2) aligned in the X-axis direction. The upper part of the third light-emitting region (ER) of the first and second pixels (PXL1, PXL2) is arranged below the second light-emitting region (EG) on a virtual third horizontal reference line (HR3) aligned in the X-axis direction, and the lower part of the third light-emitting region (ER) of the first and second pixels (PXL1, PXL2) and the fourth light-emitting region (EW) are arranged on a virtual fourth horizontal reference line (HR4) below the third horizontal reference line (HR3). In order to improve color reproduction ratio, the size of the third light-emitting region (ER) that emits red light may be larger than the first and second light-emitting regions (EB, EG).

[0087] The fourth light-emitting region (EW) that emits white light is not continuous on the display panel 100. This prevents the phenomenon of white horizontal or vertical stripes being visible when the entire display region (AA) of the display panel 100 displays a single color or a specific gray.

[0088] The third light-emitting region (ER) may be an "L"-shaped light-emitting region with one side removed from a square. The top of the third light-emitting region (ER) includes a narrow portion 20 adjacent to the top of the fourth light-emitting region (EW). The fourth light-emitting region (EW) is located in an area created by removing a portion of the bottom of the red light-emitting region (ER) of the first pixel (PXL1) and the red light-emitting region (ER) of the second pixel (PXL2), which are mirror-symmetrically adjacent to each other. The top and left and right sides of the fourth light-emitting region (EW1, EW2) are surrounded by the third light-emitting regions (ER) of the first and second pixels (PXL1, PXL2), and the first light-emitting regions (EB) of the third and fourth pixels (PXL3, PXL4; see FIG. 5) are located below the fourth light-emitting region (EW1, EW2). The third and fourth pixels (PXL3, PXL4) are adjacent to each other. Therefore, the fourth light-emitting regions (EW1, EW2) are not adjacent to other fourth light-emitting regions (EW1, EW2).

[0089] The power supply lines (PL10, PL20) can supply the pixel circuits (CB, CG, CR, CW1, CW2) with constant voltages required to drive the pixels (PXL1, PX2). A pixel drive voltage may be applied to the EVDD power supply line (VL), and a reference voltage may be applied to the REF power supply line (RL). The EVDD power supply line (VL) is connected to all pixel circuits (CB, CG, CR, CW1, CW1) adjacent in the X-axis direction via the EVDD power supply line (VL) and supplies pixel drive voltages to these pixel circuits (CB, CG, CR, CW1, CW1). The REF power supply lines (RL) may be arranged on both sides via relatively wider EVDD power supply lines and connected to each other in the non-display area (NA). The REF power supply line (VR) is connected to all pixel circuits (CB, CG, CR, CW1, CW1) adjacent in the X-axis direction via the REF power supply line (VR) to supply a reference voltage to these pixel circuits (CB, CG, CR, CW1, CW1).

[0090] The power supply lines (VL, RL) cross the first light-emitting region (EB), the second light-emitting region (EG), and the third light-emitting region (ER) in each of the first and second pixels (PXL1, PXL2) and overlap with the light-emitting regions (EB, EG, ER). The power supply lines (VL, RL) avoid the fourth light-emitting region (EW) and do not overlap with the fourth light-emitting region (EW).

[0091] The first data line pair (DL10) includes a first data line (DLB1) to which a data voltage of B data is applied and a second data line (DLG1) to which a data voltage of G data is applied. The first data line (DLB1) is commonly connected to first pixel circuits (CB) of adjacent pixels in the X-axis direction via the first data line (DLB1) and supplies a data voltage of B data to the first pixel circuits (CB). The second data line (DLG1) is commonly connected to second pixel circuits (CG) of adjacent pixels in the X-axis direction via the second data line (DLG1) and supplies a data voltage of G data to the second pixel circuits (CG).

[0092] The first data line (DLB1) is connected to a plurality of first pixel circuits (CB) arranged along the Y-axis direction. The first data line (DLB1) transmits a data voltage of B data to be written to a blue sub-pixel from the data driver 110 to the first pixel circuit (CB). Only the data voltage of B data is applied to the first data line (DLB1). The second data line (DLG1) is connected to a plurality of second pixel circuits (CG) arranged along the Y-axis direction. The second data line (DLG1) transmits a data voltage of G data to be written to a green sub-pixel from the data driver 110 to the second pixel circuit (CG). Only the data voltage of G data is applied to the second data line (DLG1).

[0093] The second data line pair (DL20) includes a third data line (DLR) to which a data voltage of R data is applied and a fourth data line (DLW) to which a data voltage of W data is applied. The third data line (DLR) is commonly connected to the third pixel circuits (CR) of adjacent pixels (PXL1, PXL2) in the X-axis direction via the third data line (DLR) and supplies the data voltage of R data to the third pixel circuits (CR). The fourth data line (DLW) is commonly connected to the fourth pixel circuits (CW1, CW2) of adjacent pixels (PXL1, PXL2) in the X-axis direction via the fourth data line (DLW) and supplies the data voltage of W data to the fourth pixel circuits (CW1, CW2).

[0094] The third data line (DLR) is connected to a plurality of third pixel circuits (CR) arranged along the Y-axis direction. The third data line (DLR) transmits a data voltage of R data to be written to the red sub-pixel from the data driver 110 to the third pixel circuit (CR). Only the data voltage of R data is applied to the third data line (DLR). The fourth data line (DLW) is connected to a plurality of fourth pixel circuits (CW1, CW2) arranged along the Y-axis direction. The fourth data line (DLW) transmits a data voltage of W data to be written to the white sub-pixel from the data driver 110 to the fourth pixel circuits (CW1, CW2). Only the data voltage of W data is applied to the fourth data line (DLW).

[0095] The second data line pair (DL20) crosses the fourth light-emitting region (EW) and overlaps with the fourth light-emitting region (EW). The second data line pair (DL20) avoids the other light-emitting regions (EB, EG, ER) and pixel circuits (CB, CG, CR, CW1, CW2) so as not to overlap with these components (EB, EG, ER, CB, CG, CR, CW1, CW2).

[0096] The third data line pair (DL30) includes a fifth data line (DLB2) to which a data voltage of B data is applied and a sixth data line (DLG2) to which a data voltage of G data is applied. The fifth data line (DLB2) receives only the data voltage of B data, which is supplied from the data driver 110 to the blue subpixels. The sixth data line (DLG2) receives only the data voltage of G data, which is supplied from the data driver 110 to the green subpixels. The fifth data line (DLB2) is commonly connected to the first pixel circuits (CB) of adjacent pixels in the X-axis direction via the fifth data line (DLB2) and supplies the data voltage of B data to the first pixel circuits (CB). The sixth data line (DLG2) is commonly connected to the second pixel circuits (CG) of adjacent pixels in the X-axis direction via the sixth data line (DLG2) and supplies the data voltage of G data to the second pixel circuits (CG).

[0097] Although multiple gate lines are arranged along the first direction (X), two gate lines arranged between two light-emitting regions (EB, EG or ER, EW) having different colors in the second direction (Y) may be connected to each other.

[0098] Each gate line is arranged for each pixel line, and two adjacent gate lines are commonly connected to one output terminal of the gate driver 120. For example, as shown in FIGS. 2 and 3, two gate lines arranged through two different color light-emitting regions may be connected to each other and connected to a specific output terminal of the gate driver 120. Therefore, a gate pulse may be applied to two pixel lines simultaneously. The nth gate line (GLn) may simultaneously apply gate pulses to pixel circuits (CB, CG, CR, CW1, CW2) distributed across the two pixel lines. In FIG. 2, some pixel circuits (CW2) connected to the nth gate line (GLn) are omitted. Gate pulses are applied sequentially to the gate lines (GLn-1 to GLn+2) in the order of GLn-1, GLn, GLn+1, and GLn+2.

[0099] Between two gate lines (GLn) connected to each other, and between two light-emitting areas (EB, EG or ER, EW) of different colors, scan lines (SCn, SCn+1) may be arranged to drive only the sensor transistors (T2) of the first pixel (PXL1) and the second pixel (PXL2), respectively.

[0100] That is, the scan lines (SCn, SCn+1) may be arranged such that the nth scan line (SCn) is arranged between the first light-emitting region (EB) and the second light-emitting region (EG) which are different in color, and the n+1th scan line (SCn+1) is arranged between the third light-emitting region (ER) and the fourth light-emitting region (EW1, EW2) which are different in color.

[0101] For example, the nth scan line (SCn) may be arranged between two gate lines of the nth gate line (GLn) in the first direction (X) and between the first light-emitting region (EB) and the second light-emitting region (EG) of the first pixel (PXL1) and the second pixel (PXL2) that have different colors in the second direction (Y).

[0102] In addition, the n+1th scan line (SCn+1) may be arranged between two gate lines of the n+1th gate line (GLn+1) in the first direction (X) and between the third light-emitting region (ER) and the fourth light-emitting region (EW1, EW2) of the first pixel (PXL1) and the second pixel (PXL2) which have different colors in the second direction (Y).

[0103] The first to third light-emitting regions (EB, EG, ER) of the first pixel (PXL1) and the first to third light-emitting regions (EB, EG, ER) of the second pixel (PXL2) may be arranged in mirror symmetry with respect to the first direction (X).

[0104] A fourth light-emitting region (EW1, EW2) may be disposed between the third light-emitting region (ER) of the first pixel (PXL1) and the third light-emitting region (ER) of the second pixel (PXL2) in the first direction (X). The third light-emitting region (ER) may include a third sub-pixel, and the fourth light-emitting region (EW1, EW2) may include a white sub-pixel.

[0105] The distribution of the light-emitting areas of the subpixels for each color can be appropriately selected taking into consideration color gamut and high brightness. For example, in an image or display model where high brightness relative to color gamut is important, the area of ​​the fourth light-emitting region (EW) can be further increased, thereby increasing the driving voltage of the three subpixels excluding the white subpixel. The structure of the third and fourth light-emitting regions (ER, EW) shown in FIG. 2 is a structure that allows the size of the fourth light-emitting region (EG) parallel to the horizontal reference line to be easily expanded or reduced, making it easy to distribute the areas of the third and fourth light-emitting regions (ER, EW) without changing the wiring shape. In a display model where pure colors are important, the fourth light-emitting region (EG) can be reduced. To increase brightness, the fourth light-emitting region (EG) may be enlarged.

[0106] Figure 3 is an equivalent circuit diagram showing in detail an example of the pixel circuit shown in Figure 2. Figure 4 is a circuit diagram showing a single pixel circuit.

[0107] Referring to FIGS. 3 and 4, each of the pixel circuits (CB, CG, CR, CW1, CW2) is connected to a data line (DL) to which a data voltage (Vdata) of pixel data is applied, a gate line (GL) to which a gate pulse (SCAN) is applied, a power supply line (VL) to which a pixel drive voltage (EVDD) is applied, a VDD power supply line to which a cathode voltage (EVSS) is applied, and a reference voltage (Vref) is connected to a REF power supply line (RL).

[0108] The display panel 100 has a plurality of gate lines arranged along the first direction (X), but two gate lines arranged via two light-emitting regions (EB, EG or ER, EW) having different colors in the second direction (Y) may be connected to each other.

[0109] The display panel 100 may have an nth scan line (SCn) arranged between a first light-emitting region (EB) and a second light-emitting region (EG) that are different in color, and an n+1th scan line (SCn+1) arranged between a third light-emitting region (ER) and a fourth light-emitting region (EW1, EW2) that are different in color.

[0110] The nth scan line (SCn) and the n+1th scan line (SCn+1) are wirings for applying a scan signal (SCAN) to drive only the sensor transistors (T2) of the first pixel (PXL1) and the second pixel (PXL2).

[0111] Each of the pixel circuits (CB, CG, CR, CW1, CW2) includes a light emitting element (EL), a plurality of transistors (DT, T1, T2), and a capacitor (C).

[0112] The light emitting element (EL) may be an inorganic light emitting element such as an organic light emitting diode (OLED) or a micro LED. The light emitting element (EL) may include, but is not limited to, a red light emitting element, a green light emitting element, and a blue light emitting element. The anode electrode of the light emitting element (EL) is electrically connected to the driving element (DT) and disposed in a corresponding light emitting area in each pixel. The light emitting element (EL) is driven to emit light when a current is generated from the driving element (DT), and the light is emitted to the outside of the display panel 100 through the light emitting area.

[0113] The driving element (DT) generates a current according to a voltage between its gate and source to drive the light emitting element (EL). The driving element (DT) includes a gate electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3). The capacitor (C) is connected between the first node (N1) and the third node (N3). The second node (N2) is connected to the EVDD power supply line (VL). The third node (N3) is connected to the anode electrode of the light emitting element (EL). The cathode electrode of the light emitting element (EL) is connected to a power supply line to which a cathode voltage (EVSS) is applied.

[0114] The first switch element (T1) is connected between the data line (DL) and a first node (N1). The first switch element (T1) may be, for example, a scan transistor. The first switch element (T1) is turned on in response to a gate pulse (SCAN). When the first switch element (T1) is turned on, a data voltage (Vdata) of pixel data is applied to the first node (N1), and the pixel data is written to the subpixel. The first switch element (T1) includes a gate electrode connected to the gate line (GL), a first electrode connected to the data line (DL), and a second electrode connected to the first node (N1).

[0115] The second switch element (T2) is connected between the third node (N3) and the REF power supply line (RL). The second switch element (T2) may be, for example, a sensor transistor. The second switch element (T2) is turned on in response to a gate pulse (SCAN). When the second switch element (T2) is turned on, the third node (N3) is connected to the REF power supply line (RL). The second switch element (T2) includes a gate electrode connected to the scan line (SCn, SCn+1), a first electrode connected to the third node (N3), and a second electrode connected to the REF power supply line (RL).

[0116] Although the driving elements (DT) should have uniform electrical characteristics in all subpixels, differences can occur between subpixels due to process variations and variations in element characteristics, and these differences can become larger as the subpixels are driven over time. To compensate for these variations in the electrical characteristics of the driving elements (DT), an external compensation circuit can be applied to the display panel driving circuit.

[0117] In FIG. 3, for example, the first pixel circuit (CB) may have a gate electrode of the sensor transistor (T2) connected to the nth scan line (SCn), a first electrode connected to the driving element (DT), and a second electrode connected to the REF power supply line (RL).

[0118] In addition, the second pixel circuit (CG) may have a gate electrode of the sensor transistor (T2) connected to the (n+1)th scan line (SCn+1), a first electrode connected to the driving element (DT), and a second electrode connected to the REF power supply line (RL).

[0119] The external compensation circuit senses and compensates for the electrical characteristics of the driver element (DT) in real time in sensing mode. Sensing mode is divided into pre-production and post-production. Before product shipment, the electrical characteristics of the driver element (DT) in each sub-pixel are sensed via the reference power line (RL) connected to the pixel, and the sensing results are used to compensate for deviations in the electrical characteristics of the driver element (DT) for each sub-pixel.

[0120] After product shipment, the sensing modes are divided into ON RF mode performed during the power-on sequence, RT mode performed during the vertical blank period (VB) during the display driving period, and OFF RS mode performed during the power-off sequence.

[0121] In the ON RF mode, the external compensation circuit senses the mobility of the driver element (DT) that drives the light-emitting element via the REF power line (RL) in each pixel when the display device is powered on, compares the mobility sensing result with the driver element mobility compensation value measured for each subpixel before product shipment, and updates the mobility compensation value based on the difference. Before product shipment, the threshold voltage and mobility of the driver element (DT) for each subpixel are sensed in sensing mode, and the driver element threshold voltage compensation value and mobility compensation value are set in a look-up table. The driver element mobility is compensated for for each subpixel using a mobility compensation value that reflects the driver element mobility sensing result.

[0122] In the RT mode, during a display driving period in which an image is displayed, the mobility of the driving element (DT) is sensed in real time via the REF power line (RL) during the vertical blank period (VB) of each frame period, and the mobility compensation value is updated for each subpixel according to the mobility sensing result. The vertical blank period is a period in which no data is input to the timing controller 130 between the active period of the (N-1)th frame period and the active period of the Nth frame period.

[0123] In the OFF RS mode, when the display device is powered off, the external compensation circuit senses the threshold voltage of the driving element (DT) in each pixel via the REF power line (RL) and updates the threshold voltage compensation value for each subpixel based on the threshold voltage sensing result. In the OFF RS mode, before the power is completely turned off, the display panel driving circuit and the external compensation circuit are driven for a predetermined delay time to sense the threshold voltage of the driving element (DT) in each subpixel and update the threshold voltage compensation value for the driving element (DT) in each subpixel.

[0124] The external compensation circuit includes an analog-to-digital converter (ADC) electrically connected to the REF power line (RL) and a compensation circuit for compensating data from the ADC. A lookup table of the compensation circuit stores compensation values ​​for compensating for the threshold voltage and mobility of a driving element that drives a light emitting element for each subpixel. The compensation circuit inputs sensing data output from the ADC to the lookup table and adds or multiplies the compensation value output from the lookup table to pixel data of an input image to modulate the pixel data, thereby compensating for changes in the electrical characteristics of the driving element. An ADC may be provided for each sensing channel set in a source drive IC integrated in the data driver 110. The compensation circuit may be implemented in a logic circuit of the timing controller 130.

[0125] Figure 5 is a diagram showing a light emitting area of ​​22 pixels, and Figure 6 is a diagram showing an example of a hybrid driving method.

[0126] Referring to Figures 5 and 6, third and fourth pixels (PXL3, PXL4) having substantially the same structure as the first and second pixels (PXL1, PXL2) may be arranged below the first and second pixels (PXL1, PXL2).

[0127] The first to fourth pixels (PXL1 to PXL4) can be hybrid-driven as shown in FIG. 6. In a predetermined time unit, the first to fourth pixels (PXL1 to PXL4) can be alternately driven as four subpixels and three subpixels. For example, during an odd-numbered frame period (Fodd), the first and fourth pixels (PXL1, PXL4) can be driven as four subpixels, and the second and third pixels (PXL2, PXL3) can be driven as three subpixels, as shown in FIG. 6. During an even-numbered frame period (Feven), the first and fourth pixels (PXL1, PXL4) can be driven as three subpixels, and the second and third pixels (PXL2, PXL3) can be driven as four subpixels, as shown in FIG. 6. When the first pixel (PXL1) is driven as four subpixels, the W data written to the white subpixel is generated from the R, G, and B data of the first pixel (PXL1). When the second pixel (PXL2) is driven with four sub-pixels, the W data written to the white sub-pixel is generated from the R, G, and B data of the second pixel (PXL2). When the third pixel (PXL3) is driven with four sub-pixels, the W data written to the white sub-pixel is generated from the R, G, and B data of the third pixel (PXL3). When the fourth pixel (PXL4) is driven with four sub-pixels, the W data written to the white sub-pixel is generated from the R, G, and B data of the fourth pixel (PXL4).

[0128] FIG. 7 is a diagram showing an example in which gate lines are arranged in a two-scan structure on a display panel according to an embodiment of the present specification.

[0129] Referring to FIG. 7, the display panel 100 according to an embodiment of the present specification has a plurality of gate lines arranged along a first direction (X), but two gate lines arranged through two light-emitting regions (EB, EG or ER, EW) of different colors in a second direction (Y) can be connected to each other to form a two-scan structure.

[0130] Here, the power supply line may further include a first power supply wiring (VL) to which a pixel drive voltage (EVDD) is applied, and a plurality of second power supply wirings (RL) arranged on both sides of the first power supply wiring (VL).

[0131] In this case, the width of the first power supply wiring (VL) may be greater than the width of each of the plurality of second power supply wirings (RL).

[0132] The display panel 100 according to an embodiment of this specification may have an nth scan line (SCn) arranged between a first light-emitting region (EB) and a second light-emitting region (EG) that are different in color, and an n+1th scan line (SCn+1) arranged between a third light-emitting region (ER) and a fourth light-emitting region (EW1, EW2) that are different in color.

[0133] That is, the display panel 100 may be provided with an nth scan line (SCn) and an n+1th scan line (SCn+1) for driving only the sensor transistors (T2) of the first pixel (PXL1) and the second pixel (PXL2).

[0134] 8a is a diagram showing an example of a display panel according to an embodiment of the present specification in which the second power supply wiring (RL) is swapped with the first power supply wiring (VL), and FIG. 8b is a diagram showing an example of a display panel according to an embodiment of the present specification in which the width of the first power supply wiring (VL) is formed larger than the width of the second power supply wiring (RL).

[0135] Referring to FIG. 8a, a display panel 100 according to an embodiment of the present specification can have a plurality of first power supply wirings (VL) to which a pixel drive voltage (EVDD) is applied, arranged on both sides of a second power supply wiring (RL) to which a reference voltage (Vref) is applied.

[0136] The plurality of first power supply wirings (VL) may be arranged on both sides of the second power supply wiring (RL) and may be coupled to each other.

[0137] Referring to FIG. 8b, the width of each of the plurality of first power supply wirings (VL) may be formed to be greater than the width of the second power supply wiring (RL).

[0138] In this case, the display panel 100 can form a two-scan structure by connecting two gate lines arranged through two light-emitting regions (EB, EG or ER, EW) in the second direction (Y) having different colors.

[0139] However, in the display panel 100, the wiring for driving the sensor transistor T2 must pass through the aperture region, which may result in a decrease in aperture ratio.

[0140] Therefore, in order to compensate for such a drawback, the display panel 100 may be configured such that the second power supply wiring (RL) is swapped with the first power supply wiring (VL), so that multiple first power supply wirings (VL) are arranged on both sides of the second power supply wiring (RL).

[0141] Therefore, by placing the sensor transistor (T2) between the first power supply wiring (VL) and the second power supply wiring (RL), the driving result of the sensor transistor (T2) can be transmitted between the second power supply wiring (RL).

[0142] 9a is a diagram showing an example of the arrangement of first and second scan lines in a display panel according to an embodiment of the present specification, FIG. 9b is a diagram showing an enlarged view of region A in FIG. 9a in a display panel according to an embodiment of the present specification, and FIG. 9c is a diagram showing an enlarged view of region B in FIG. 9b in a display panel according to an embodiment of the present specification.

[0143] Referring to FIG. 9a, the display panel 100 according to an embodiment of the present specification may have scan lines (SCn, SCn+1) arranged between two gate lines (GLn) connected to each other and between two light-emitting areas (EB, EG or ER, EW) of different colors to drive only the sensor transistor (T2) of each pixel (PXL1, PXL2).

[0144] For example, the scan lines (SCn, SCn+1) may be arranged such that the nth scan line (SCn) is arranged between a first light-emitting region (EB) and a second light-emitting region (EG) which are different in color, and the n+1th scan line (SCn+1) is arranged between a third light-emitting region (ER) and a fourth light-emitting region (EW1, EW2) which are different in color.

[0145] In addition, the n+1th scan line (SCn+1) arranged between the third light-emitting region (ER) and the fourth light-emitting region (EW1, EW2) which are different in color from each other may branch between the first pixel (PXL1) and the second pixel (PXL2) and be formed in a shape surrounding a terminal overlapping with the second power supply line (RL).

[0146] 9b, the nth scan line (SCn) arranged between the first light-emitting region (EB) and the second light-emitting region (EG) of different colors in region A may branch off between the first pixel (PXL1) and the second pixel (PXL2) in region B and be formed in a shape surrounding a contact hole overlapping with the second power wiring (RL) that applies the reference voltage (Vref). The nth scan line (SCn) branching off between the first pixel (PXL1) and the second pixel (PXL2) may be further combined into one scan line arranged between the first light-emitting region (EB) and the second light-emitting region (EG) of the second pixel (PXL2).

[0147] Referring to FIG. 9b, in the B region, one connecting line may extend upward in the second direction (Y) and then be connected to the source node 910 of the driving transistor (DT) of the first subpixel (B) of the first light-emitting region (EB).

[0148] In addition, in region B, another connecting line may extend downward in the second direction (Y) and then be connected to the source node 920 of the driving transistor (DT) of the third subpixel (R) of the third light-emitting region (ER).

[0149] Referring to FIG. 9c, the nth scan line (SCn) branches off in the B region and then forms a single line, and the branched upper wiring can overlap with the sensor transistor 912 and the second power wiring (RL) of the first subpixel (B) in the first light-emitting region (EB).

[0150] In addition, the nth scan line (SCn) has a lower wiring branched in the B region that can overlap with the sensor transistor 922 of the third subpixel (R) in the third light-emitting region (ER) and the second power supply wiring (RL).

[0151] 10 is a diagram illustrating an example in which gate lines and scan lines are arranged in a third light-emitting region (ER) in a display panel according to an embodiment of the present disclosure. FIG. 11 is a cross-sectional view of the display panel according to an embodiment of the present disclosure taken along line A-A' in FIG.

[0152] Referring to Figures 10 and 11, the display panel 100 according to an embodiment of the present specification may have an nth gate line (GLn) arranged along the first direction (X) above the third light-emitting region (ER), and an n+1th scan line (SCn+1) arranged between the lower side of the third light-emitting region (ER) and the next light-emitting region.

[0153] In this case, the display panel 100 may have a light-shielding layer 103 (LS) arranged on the substrate 101, a buffer layer 105 arranged on the substrate 101 and the light-shielding layer 103, and a gate insulating layer (GI) and a semiconductor layer (ACT) arranged on the buffer layer 105.

[0154] The semiconductor layer (ACT) is a semiconductor layer of the drive transistor (DT) and can be made of an oxide semiconductor layer (for example, IGZO).

[0155] The light-shielding layer 103 is formed corresponding to the channel region of the driving transistor (DT) or the semiconductor layer 153. The light-shielding layer 103 is made of a metal such as copper (Cu) and not only blocks external light but also connects to other electrodes or lines, and can be used as an electrode for constituting a capacitor, etc.

[0156] In the semiconductor layer 153, the portions corresponding to the source and drain regions, excluding the portion corresponding to the channel region, are made conductive to become the metal electrode 109 or wiring (metalization). The process of making the portions corresponding to the source and drain regions conductive can be, but is not limited to, O2 plasma or etching.

[0157] A metal electrode 109 (MoTi) may be disposed on the semiconductor layer (ACT), a gate insulating layer (GI; SiO2) may be disposed on the metal electrode 109, and a gate metal (GM) may be disposed on the gate insulating layer (GI). The gate metal (GM) may be made of a metal such as copper (Cu).

[0158] An insulating layer 107 may be disposed on the gate metal (GM), and a red pigment (ER) and an overcoat layer (OC) may be disposed on the insulating layer 107. The overcoat layer (OC) may contain an organic material.

[0159] An anode electrode (AE) may be disposed on the overcoat layer (OC), and may be connected to the gate metal (GM) through a contact hole. The anode electrode (AE) may include an ITO (Indium Tin Oxide) material.

[0160] The light-emitting layer (OLED) may be disposed on the anode electrode (AE), and the cathode electrode (CE) may be disposed on the light-emitting layer (OLED). The cathode electrode (CE) may include a metal such as aluminum (Al).

[0161] FIG. 12a is a diagram showing an example of the arrangement of gate lines and scan lines in a display panel according to an embodiment of the present specification, and FIG. 12b is a cross-sectional view of a display panel according to an embodiment of the present specification taken along the B-B' cutting line in FIG. 12a.

[0162] 12a and 12Bb, a display panel 100 according to an embodiment of the present specification may have a light-shielding layer 103 disposed on a substrate 101, and a buffer layer 105 disposed on the light-shielding layer 103.

[0163] An electrode region 111 and a semiconductor region (ACT) constituting a drive transistor (DT) may be disposed on the buffer layer 105, and a gate insulating layer (GI) may be disposed on the electrode region 111 and the semiconductor region (ACT). A metal electrode 109 (MoTi) may be disposed on the electrode region 111. The metal electrode 109 may be a source electrode or a drain electrode.

[0164] The semiconductor region (ACT) is a semiconductor region of the drive transistor (DT) and can be made of an oxide semiconductor layer (e.g., IGZO). The portions corresponding to the source and drain regions adjacent to the semiconductor region (ACT) are made conductive to become electrode regions 111 or wiring (metalization). The conductive process for the portions corresponding to the source and drain regions can be, but is not limited to, O2 plasma or etching.

[0165] A drive transistor (DT) may be disposed on the gate insulating layer (GI) overlapping the semiconductor region (ACT).

[0166] Additionally, an nth gate line (GLn), an nth scan line (SCn), an (n-1)th gate line (GLn-1), and a gate metal (GM) may be disposed on the gate insulating layer (GI).

[0167] An insulating layer 107 may be disposed on the drive transistor (DT), the nth gate line (GLn), the nth scan line (SCn), the (n-1)th gate line (GLn-1), and the gate metal (GM).

[0168] A first light emitting region (EB) and a second light emitting region (EG) may be disposed on the insulating layer 107. The first light emitting region (EB) and the second light emitting region (EG) may be disposed adjacent to each other.

[0169] An overcoat layer (OC) may be disposed on the first light-emitting region (EB) and the second light-emitting region (EG).

[0170] An anode electrode (AE) may be disposed on the overcoat layer (OC). The anode electrode (AE) may contain an ITO (Indium Tin Oxide) material. A plurality of anode electrodes (AE) may be disposed on the overcoat layer (OC) so as to correspond to the first light-emitting region (EB) and the second light-emitting region (EG), respectively.

[0171] A bank layer (BK) may be disposed on the overcoat layer (OC) and a part of the anode electrode (AE).

[0172] The light-emitting layer (OLED) may be disposed on the anode electrode (AE) and the bank layer (BK), and the cathode electrode (CE) may be disposed on the light-emitting layer (OLED). The cathode electrode (CE) may include a metal such as aluminum (Al).

[0173] As described above, according to the embodiments of the present specification, it is possible to provide a display panel in which scan lines are arranged between two gate lines that are arranged between two light-emitting regions of different colors, and between each of the two light-emitting regions of different colors, for driving only the sensor transistor of each pixel, and a display device including the same.

[0174] As described above, this specification has been described with reference to illustrative drawings, but this specification is not limited to the embodiments and drawings disclosed in this specification, and it is obvious that various modifications can be made by those skilled in the art within the scope of the technical concept of this specification. Furthermore, even if the effects of the configurations of the embodiments of this specification have not been explicitly described and explained, it is natural that the effects that can be predicted by the configurations should also be recognized. The scope of protection of the present disclosure should be interpreted by the following claims, and all technical features within the equivalent range thereof should be interpreted as being included in the scope of the present disclosure. [Explanation of symbols]

[0175] 100 Display Panel 110 Data Drive Unit 120 Gate driver 130 Timing Controller 140 Power supply section 150 Level Shifter 200 host systems VL, RL power supply lines AA display area NA hidden area PXL1, PXL Pixel GL Gate Line SC scanline CB 1st pixel circuit EB First light-emitting region CG Second pixel circuit EG Second light-emitting area CR 3rd pixel circuit ER Third emission region CW 4th pixel circuit EW Fourth Light Region T1 scan transistor T2 sensor transistor DT drive transistor EVDD Pixel drive voltage Vref Reference voltage

Claims

1. a first pixel; a second pixel adjacent to the first pixel in a first direction; Including, each of the first pixel and the second pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that are different in color from each other and are arranged in a second direction intersecting the first direction, and the first pixel and the second pixel share a plurality of white sub-pixels; each of the first sub-pixels of the first pixel and the second pixel includes a first pixel circuit and a first light-emitting region coupled to the first pixel circuit; each of the second sub-pixels of the first pixel and the second pixel includes a second pixel circuit and a second light-emitting region coupled to the second pixel circuit; each of the third sub-pixels of the first pixel and the second pixel includes a third pixel circuit and a third light-emitting region coupled to the third pixel circuit; each of the plurality of white sub-pixels shared by the first pixel and the second pixel includes a fourth pixel circuit and a fourth light-emitting region coupled to the fourth pixel circuit; A plurality of gate lines extend along the first direction and are arranged in the second direction; two light-emitting regions that emit light of different colors and are adjacent to each other in the second direction are provided between two gate lines that are connected to each other and are two of the plurality of gate lines; Each scan line emits a different color, and is disposed between the two light-emitting areas adjacent to each other in the second direction and between the two gate lines connecting to each other, and the scan line is configured to drive only the sensor transistors of each of the first pixel and the second pixel. Display panel.

2. The scan line is an n-th scan line disposed between the first light-emitting region and the second light-emitting region, which have different colors; and an n+1-th scan line disposed between the third light-emitting region and the fourth light-emitting region, which have different colors; The display panel according to claim 1 .

3. the first to third light-emitting regions of the first pixel and the first to third light-emitting regions of the second pixel are disposed between the first and second pixels and are disposed in mirror symmetry with each other around an imaginary line extending in the second direction; the fourth light-emitting region of the white sub-pixel arranged in the first direction is provided between a portion of the third light-emitting region of the first pixel and a portion of the third light-emitting region of the second pixel, which are arranged in the first direction; The display panel according to claim 1 .

4. a power supply line for supplying a constant voltage to the first to fourth pixel circuits; The power supply lines are provided in the first and second pixels, respectively, and are arranged in the first direction; each of the power supply lines extends along the second direction so as to overlap with the first light-emitting region, each of the second light-emitting regions, and each of the third light-emitting regions in each of the first and second pixels; The display panel according to claim 1 .

5. The power supply lines provided in the first and second pixels respectively include: a plurality of first power supply wirings to which pixel drive voltages are applied; a second power supply wiring to which a reference voltage is applied; Including, the plurality of first power supply wirings are arranged on both sides of the second power supply wiring and are connected to each other; The width of each of the plurality of first power supply wirings is greater than the width of the second power supply wiring. The display panel according to claim 4 .

6. further comprising a plurality of data line pairs for supplying data voltages of pixel data to the first to fourth pixel circuits; the plurality of data line pairs include first and second data line pairs; The first data line pair is a first data line extending along the second direction and connected to a plurality of first pixel circuits arranged along the second direction; a second data line extending along the second direction and connected to a plurality of second pixel circuits arranged along the second direction; Including, The second data line pair is a third data line extending along the second direction and connected to a plurality of third pixel circuits arranged along the second direction; a fourth data line extending along the second direction and connected to a plurality of fourth pixel circuits arranged along the second direction; Including, The display panel according to claim 4 .

7. the second data line pair extends so as to overlap with a region between the fourth light-emitting regions; The display panel according to claim 6 .

8. The fourth light-emitting region is a 4-1 light-emitting region adjacent to the third light-emitting region in the first pixel in the second direction; a 4-2 light-emitting region adjacent to the third light-emitting region in the second pixel in the second direction; Further comprising: The display panel according to claim 1 .

9. the fourth pixel circuit a fourth-1st pixel circuit connected to the fourth-1st light-emitting area; a second pixel circuit connected to the second light-emitting area; Including, The display panel according to claim 8 .

10. The 4-1 pixel circuit and the 4-2 pixel circuit are connected to different gate lines and sequentially receive gate pulses; The display panel according to claim 9 .

11. the 4-1 light-emitting region includes both sides opposing each other in the first direction and both sides opposing each other in the second direction, the 4-2 light-emitting region includes both sides opposing each other in the first direction and both sides opposing each other in the second direction, one of the two sides of the 4-1 light-emitting region in the first direction and one of the two sides of the 4-1 light-emitting region in the second direction are connected to each other and are surrounded by the third light-emitting region in the first pixel; one of the two sides of the 4-2 light-emitting region in the first direction and one of the two sides of the 4-2 light-emitting region in the second direction are connected to each other and surrounded by the third light-emitting region in the second pixel; The display panel according to claim 8 .

12. the first subpixel is a blue subpixel; the second subpixel is a green subpixel; the third subpixel is a red subpixel; The display panel according to claim 1 .

13. a display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels; a data driver that converts pixel data into data voltages and supplies the data voltages to the plurality of data lines; a gate driver configured to sequentially supply gate pulses to the plurality of gate lines; a timing controller configured to transmit the pixel data to the data driver and control the data driver and the gate driver; Including, The plurality of pixels include: a first pixel; a second pixel adjacent to the first pixel in a first direction; Including, each of the first pixel and the second pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that are different in color from each other and are arranged in a second direction intersecting the first direction; the first pixel and the second pixel share a plurality of white sub-pixels; each of the first sub-pixels of the first pixel and the second pixel includes a first pixel circuit and a first light-emitting region coupled to the first pixel circuit; each of the second sub-pixels of the first pixel and the second pixel includes a second pixel circuit and a second light-emitting region coupled to the second pixel circuit; each of the third sub-pixels of the first pixel and the second pixel includes a third pixel circuit and a third light-emitting region coupled to the third pixel circuit; each of the white sub-pixels shared by the first pixel and the second pixel includes a fourth pixel circuit and a fourth light-emitting region coupled to the fourth pixel circuit; A plurality of gate lines extend along the first direction and are arranged in the second direction; two light-emitting regions that emit light of different colors and are adjacent to each other in the second direction are provided between two gate lines that are connected to each other and are two of the plurality of gate lines; Each scan line emits a different color, and is disposed between the two light-emitting areas adjacent to each other in the second direction and between the two gate lines connecting to each other, and the scan line is configured to drive only the sensor transistors of each of the first pixel and the second pixel. Display device.

14. The scan lines include an nth scan line and an n+1th scan line, the nth scan line is provided between the first light-emitting region and the second light-emitting region, which are different in color from each other and adjacent to each other in the second direction, and is branched into two portions extending to surround a contact hole overlapping with a second power supply line that applies a reference voltage in a region between the first pixel and the second pixel; the (n+1)th scan line is provided between the third light-emitting region and the fourth light-emitting region, which are different in color from each other and adjacent to each other in the second direction, and is branched into two portions extending to surround a contact hole overlapping with a second power supply line that applies a reference voltage in a region between the first pixel and the second pixel; The display device according to claim 13.

15. a plurality of first power supply lines to which a pixel driving voltage is applied are provided on both sides of the second power supply line and are connected to each other; a width of each of the plurality of first power supply lines is greater than a width of the second power supply line; each of the plurality of first power supply lines has a narrow width in a region between the first pixel and the second pixel, and overlaps with two branched portions of the nth scan line and the (n+1)th scan line; The display device according to claim 14.

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