Drive Module

Abstract

To provide a drive module.SOLUTION: A drive module according to the present invention includes a voltage mode driver and a current mode driver. The voltage mode driver converts a positive input signal to a positive output signal at a positive output end, and converts a negative input signal to a negative output signal at a negative output end. The current mode driver comprises a first current source, a second current source, and a third current source. The first current source supplies a first current toward the positive output end and the negative output end. The second current source supplies a second current that is supplied by one of the positive output end and the negative output end. The third current source supplies a third current that is supplied by one of the positive output end and the negative output end.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to a driving module, and more particularly to a driving module having a voltage-mode driver and a current-mode driver. [Background technology]

[0002] High-speed standards that use serializer / deserializer (SerDes) interfaces for high-speed communication, such as Peripheral Component Interconnect Express (PCIe), Universal Serial Bus (USB), Double Data Rate (DDR), and Synchronous DRAM (SDRAM), are on the rise. As data communication speeds continue to increase, standards for high-speed systems are becoming increasingly important.

[0003] Figure 1 shows a schematic diagram of an example of a conventional high-speed system. The high-speed system 10 includes a transmitter (Tx) 11 and a receiver (Rx) 13. The transmitter (Tx) 11 transmits a signal to the receiver (Rx) 13, but the transmitted signal is attenuated as it passes through a channel (e.g., cable) 15 due to various factors such as the length of the transmission cable and vibration. Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above-mentioned conventional technology, the signal actually received by the receiver (Rx) 13 is attenuated, and therefore it is required to eliminate the distortion and improve the quality of the signal.

[0005] Therefore, the inventors of the present invention believed that the above drawbacks could be improved, and as a result of extensive research, they came up with the proposal of the present invention, which rationally and effectively improves the problems.

[0006] The present invention has been made in consideration of the above problems through intensive research by the inventors, and its purpose is to provide a driving module that includes a voltage-mode driver and a current-mode driver, thereby combining the advantages of the voltage-mode driver and the current-mode driver. [Means for solving the problem]

[0007] According to one embodiment of the present invention, there is provided a drive module. The drive module of the present invention includes a voltage-mode driver and a current-mode driver. The voltage-mode driver is electrically connected to a positive output terminal and a negative output terminal. The voltage-mode driver converts a positive input signal to a positive output signal at the positive output terminal and converts a negative input signal to a negative output signal at the negative output terminal. The positive input signal and the negative input signal are differential signals. The current-mode driver is electrically connected to the voltage-mode driver. The current-mode driver includes a first current source, a second current source, and a third current source. The first current source supplies a first current toward one of the positive output terminal and the negative output terminal. The second current source supplies a second current toward one of the positive output terminal and the negative output terminal. The third current source supplies a third current toward one of the positive output terminal and the negative output terminal. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows a schematic diagram of an example of a conventional high-speed system. [Figure 2] FIG. 2 is a schematic diagram illustrating an exemplary output signal of a transmitter. [Figure 3A] FIG. 1 is a schematic diagram illustrating a transmitter that combines a voltage-mode driver and a current-mode driver according to an embodiment of the present disclosure. [Figure 3B] FIG. 1 is a schematic diagram illustrating a transmitter that combines a voltage-mode driver and a current-mode driver according to an embodiment of the present disclosure. [Figure 4] 1 illustrates an example of an exemplary circuit diagram of a voltage-mode driver (vmDRV). [Figure 5] 5A and 5B are schematic diagrams of an example of a circuit diagram of a voltage-mode driver (vmDRV) in state 1 (ST1) and state 2 (ST2), respectively. [Figure 6] 6A is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a de-emphasis voltage (Va). FIG. 6B is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a de-emphasis voltage (Va). [Figure 7] 7A is a circuit diagram illustrating an example in which source currents IC-1, IC+1, and a sink current IC0 flow to generate a de-emphasis voltage (Va). FIG. 7B is a circuit diagram illustrating an example in which source currents IC-1, IC+1, and a sink current IC0 flow to generate a de-emphasis voltage (Va). [Figure 8] 8A is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a flat-level voltage (Vb). FIG. 8B is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a flat-level voltage (Vb). [Figure 9] 9A is a circuit diagram illustrating an example in which a flat-level voltage (Vb) is generated by flowing source currents IC-1, IC+1, and a current sink IC0. FIG. 9B is a circuit diagram illustrating an example in which a flat-level voltage (Vb) is generated by flowing source currents IC-1, IC+1, and a current sink IC0. [Figure 10] 10A is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a preshoot voltage (Vc), and FIG. 10B is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a preshoot voltage (Vc). [Figure 11] 11A is a circuit diagram illustrating an example in which source currents IC-1, IC+1, and IC0 flow to generate a flat-level voltage (Vc). FIG. 11B is a circuit diagram illustrating an example in which source currents IC-1, IC+1, and IC0 flow to generate a flat-level voltage (Vc). [Figure 12] 12A is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a maximum boost voltage (Vd). FIG. 12B is a circuit diagram illustrating an example in which source currents IC-1, IC0, and IC+1 flow to generate a maximum boost voltage (Vd). [Figure 13] 13A is a circuit diagram illustrating an example in which source currents IC-1, IC+1, and IC0 flow to generate a maximum boost voltage (Vd). FIG. 13B is a circuit diagram illustrating an example in which source currents IC-1, IC1, and IC0 flow to generate a maximum boost voltage (Vd). [Figure 14] FIG. 2 is a schematic diagram illustrating an example circuit diagram of a current source SRCC-1 for supplying a power supply current IC-1. [Figure 15A] FIG. 2 is a schematic diagram illustrating an exemplary circuit diagram of a current source SRCC0 for supplying a power supply current IC0. [Figure 15B] FIG. 2 is a schematic diagram illustrating an example circuit diagram of a current source SRCC0 for supplying a sink current IC0. [Figure 16] FIG. 2 is a schematic diagram illustrating an exemplary circuit diagram of a current source SRCC+1 for supplying a power supply current Ic+1. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following describes in detail the embodiments of the present invention, but the present invention is not limited to these, and various modifications are possible within the scope of the description. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

[0010] To improve signal quality, transmitters and receivers perform equalization. Provided herein is a transmitter with pre-emphasis equalization to improve the quality of electrical signals transmitted at gigabit rates.

[0011] Pre-emphasis equalization is a method of slightly modifying the mode of a transmitted signal before transmission, thereby boosting the high frequency components of the transmitted signal and / or reducing the low frequency components of the transmitted signal.

[0012] Pre-emphasis equalization reduces the artifacts caused by inter-symbol interference (ISI) and improves the quality of the eye diagram of the received signal. In this specification, pre-emphasis equalization is performed using a feed-forward equalizer (FFE), which includes a finite impulse response filter (FIR) with tap coefficients.

[0013] For ease of understanding, an exemplary 3-tap FIR filter integrated as a current-mode driver (cmDRV) is described below. A 3-tap FIR filter is used to filter three consecutive pulses with their respective coefficients (C -1 , C0, C +1 ) and add them together to generate the filter output. -1 is the precursor, tap coefficient C0 is the cursor, and tap coefficient C +1 is the postcursor. If the current-mode driver (cmDRV) is configured with three current sources SRC C-1 , SRC C0 , SRC C+1 , the tap coefficients C of a 3-tap FIR filter -1 , C0, C +1 In practical applications, the number of tap coefficients and the bit length of the tap coefficients are not limited.

[0014] Table 1 summarizes several modes of voltage potential of the transmitted signal for pre-emphasis equalization.

[0015] [Table 1]

[0016] Figure 2 is a schematic diagram showing an example transmission signal of a transmitter having a 3-tap FIR filter. By setting the tap coefficients of the 3-tap FIR filter, a transmission signal with an appropriate amount of de-emphasis and pre-shoot is generated, and the transmission signal is pre-distorted to cancel distortion caused by the channel. Table 2 summarizes the definitions corresponding to the different transmission signal values ​​shown in Figure 2.

[0017] [Table 2]

[0018] See Figure 2 and Tables 1 and 2. De-emphasis waveform (De-emphasis = 20*log 10 Vb / Va) is defined based on the de-emphasis voltage Va and the flat level voltage Vb. The preshoot waveform (preshoot = 20*log 10 Vc / Vb) is defined based on the preshoot voltage Vc and the flat level voltage Vb. The boost waveform (boost = 20*log 10 Vd / Vb) is defined based on the maximum boost voltage Vd and the flat level voltage Vb. The boost waveform (boost = 20*log 10 The tap coefficients are defined based on the maximum boost voltage Vd and the flat-level voltage Vb. The relationship between the tap coefficients and these voltage potentials (de-emphasis voltage Va, flat-level voltage Vb, pre-shoot voltage Vc, and maximum boost voltage Vd) is based on the SerDes standard.

[0019] By carefully configuring the tap coefficients of the SerDes, the SerDes can be made to meet electrical equipment standard specifications while minimizing impact on area and power consumption. To meet these standards, a physical driver module is provided that integrates a voltage-mode driver (vmDRV) and a current-mode driver (cmDRV). An example of the physical driver module is described below.

[0020] In this specification, the termination and termination point signals are denoted by the same symbol, for example, Vdd denotes the power supply voltage and the power supply voltage terminal.

[0021] 3A and 3B are schematic diagrams illustrating an example of a physical driver module used in a transmitter according to an embodiment of the present disclosure. The transmitters 20a and 20b have similar general components. The transmitters (Tx) 20a and 20b include a media access controller (MAC) 21, physical driver modules 23a and 23b, and a load circuit (ldCKT) 25. The physical driver modules 23a and 23b further include a physical coding sublayer (PCS) 231 and a physical media access (PMA) 233a and 233b. For ease of understanding, the physical driver modules 23a and 23b are assumed to have a single lane configuration. In actual applications, the physical driver modules 23a and 23b may have a multi-lane configuration.

[0022] The MAC 21 generates parallel input data inDATp and at least one physical control signal phyCTL, which is sent to the serializer 2311 and the physical control signal phyCTL is sent to the PCS 231. Because the MAC 21 is involved in different aspects of operation, such as upper layer data collection, communication protocols, header addition, and status information, detailed information about how the MAC 21 generates the parallel input data inDATp and the physical control signal phyCTL is omitted.

[0023] The PCS 231 is implemented using digital circuits, while the PMAs 233a and 233b are implemented using analog circuits. The PMAs 233a and 233b are configured to receive signals from the PCS 231, and the configurations depend on different standards. The PCS 231 includes a serializer 2311, a single-ended to differential converter 2313, and a feed-forward equalizer (FFE) 2315. The serializer 2311 and the FFE 2315 are electrically connected to the MAC 21.

[0024] The serializer 2311 and the FFE 2315 receive the parallel input data inDATp and the physical control signal phyCTL, respectively, from the MAC 21. 2311 converts parallel input data inDATp into a sequence of input bits inS. The FFE 2315 further comprises a switch control circuit 2315a and a current control circuit 2315c.

[0025] For the FFE 2315, the physical control signal phyCTL received from the MAC 21 has tap coefficient C -1 , C0, C +1 MAC 21 uses a standard handshake protocol to determine the optimal tap coefficients C during the link training procedure. -1 , C0, C +1 In this specification, the tap coefficient C -1 , C0, C +1 Details regarding the acquisition will be omitted.

[0026] The single-ended to differential conversion circuit 2313 is electrically connected to the serializer 2311 and the PMA 233a. The single-ended to differential conversion circuit 2313 converts the input bit sequence inS into an input differential signal pair including a positive input signal INp and a negative input signal INn.

[0027] When the input bit sequence inS is a logic high potential (H), the positive input signal INp is set as a positive voltage (signal is high potential) and the negative input signal INn is set as a negative voltage (signal is low potential). When the input bit sequence inS is a logic low potential (L), the positive input signal INp is set as a negative voltage (signal is low potential) and the negative input signal INn is set as a positive voltage (signal is high potential).

[0028] PMA 233a, 233b includes voltage-mode driver (vmDRV) 2331 and current-mode drivers (cmDRV) 2333a, 2333b. Voltage-mode driver (vmDRV) 2331 is electrically connected to single-ended to differential conversion circuit 2313 and current-mode drivers (cmDRV) 2333a, 2333b. Current-mode drivers (cmDRV) 2333a, 2333b are electrically connected to load circuit (ldCKT) 25, switch control circuit 2315a, and current control circuit 2315c.

[0029] The voltage-mode driver (vmDRV) 2331 receives the positive input signal INp and the negative input signal INn from the single-ended to differential conversion circuit 2313 and generates the positive output signal OUTp and the negative output signal OUTn correspondingly, so that the positive output signal OUTp and the negative output signal OUTn change dynamically according to the positive input signal INp and the negative input signal INn.

[0030] The switch control circuit 2315a and the current control circuit 2315c receive a physical control signal phyCTL from the MAC 21. Based on the physical control signal phyCTL, the switch control circuit 2315a generates switch control signals Sctl1, Sctl2, and Sctl3 and sends them to the current mode drivers (cmDRV) 2333a and 2333b, and the current control circuit 2315c generates a current setting signal SET C-1 , SET C0 , SET C+1and transmits them to the current mode drivers (cmDRV) 2333a and 2333b. The switch control signal Sctl1 corresponds to the switches SWp1 and SWn1, the switch control signal Sctl2 corresponds to the switches SWp2 and SWn2, and the switch control signal Sctl3 corresponds to the switches SWp3 and SWn3. The current setting signal SET C-1 , SET C0 , SET C+1 is the tap coefficient C -1 , C0, C +1 correspond to the following:

[0031] In the example of Figure 3A, the current-mode driver (cmDRV) 2333a is connected to the current source SRC C-1 , SRC C0 , SRC C+1 The inverter circuit includes inverters INV1, INV2, and INV3, and switches SWp1, SWn1, SWp2, SWn2, SWp3, and SWn3. C-1 , SRC C0 , SRC C+1 is electrically connected to the power supply voltage terminal Vdd and the current control circuit 2315c.

[0032] The switches SWp1, SWp2, and SWp3 are electrically connected to the positive output signal OUTp, and the switches SWn1, SWn2, and SWn3 are electrically connected to the negative output signal OUTn. The inverters INV1, INV2, and INV3 are electrically connected to the switch control circuit 2315a, and the inverters INV1, INV2, and INV3 correspond to the switches SWn1, SWn2, and SWn3, respectively. The inverters INV1, INV2, and INV3 receive the switch control signals Sctl1, Sctl2, and Sctl3, respectively, and generate signals at their output ends that complement the switch control signals Sctl1, Sctl2, and Sctl3.

[0033] Current source SRC C-1 , SRC C0 , SRC C+1 is the source current I C-1 , I C0 ,I C +1(See Figure 3A). C-1 , I C0 , I C+1 The current value is set by the current control circuit 2315c as a current setting signal SET C-1 , SET C0 , SET C+1 The source current I C-1 , I C0 , I C+1 The current value of the tap coefficient C -1 , C0, C +1 By doing this, the current setting signal SET C-1 , SET C0 , SET C+1 is the current source SRC C-1 , SRC C0 , SRC C+1 are set, and the positive output signal OUTp and the negative output signal OUTn are equalized as a combined transmission signal.

[0034] Current source SRC C-1 is electrically connected to the switches SWp1 and SWn1. The switch SWp1 is controlled as a switch control signal Sctl1, and the switch SWn1 is controlled by the output of the inverter INV1, so that the switch states of the switches SWp1 and SWn1 are reversed. When the switch SWp1 is turned on and the switch SWn1 is turned off, the source current I C-1 is conducted to the positive output terminal OUTp. Alternatively, when the switch SWp1 is turned off and the switch SWn1 is turned on, the source current I C-1 is conducted to the negative output terminal OUTn. C0 and the relationship between switches SWp3, SWn3 and current source SRC C+1 The relationship between the switches SWp1 and SWn1 and the current source SRC C-1 Since this is similar to the relationship between

[0035] Current Mode Driver (cmDRV) 2333b is a current source SRC C-1 , SRC C0 , SRC C+1, inverters INV1, INV2, INV3, and switches SWp1, SWn1, SWp2, SWn2, SWp3, SWn3 (see FIG. 3B). The connections between the inverters INV1, INV2, INV3, and the mapping between the inverters INV1, INV2, INV3 and the switches SWn1, SWn2, SWn3 are similar to those in FIG. 3A.

[0036] Current source SRC C-1 , SRC C+1 The connections associated with SRC are similar to those shown in Figure 3A. C0 The connections to the current sources are different from those in FIGS. 3A and 3B.

[0037] Current source SRC shown in Figure 3B C0 is electrically connected to the ground terminal Gnd and is not electrically connected to the power supply voltage terminal Vdd. C-1 , SRC C+1 is the source current I C-1 , I C+1 respectively, where the current source SRC C0 is the sink current I C0 (See Figure 3B.) When switch SWp2 is turned on, it sinks current I C0 is conducted to the positive output terminal OUTp, and the switch SWn2 is turned off. When the switch SWp2 is turned off, the sink current I C0 is conducted to the negative output terminal OUTp, and the switch SWn2 becomes conductive.

[0038] In the example of Figures 3A and 3B, the load circuit (ldCKT) 25 includes a positive load resistor RLp and a negative load resistor RLn. The resistances of the positive load resistor RLp and the negative load resistor RLn are equivalent. The positive load resistor RLp is electrically connected to the positive output terminal OUTp and the ground terminal Gnd. The negative load resistor RLn is electrically connected to the negative output terminal OUTn and the ground terminal Gnd.

[0039] 3A, FIG. 4 shows an example of an exemplary circuit diagram of a voltage-mode driver (vmDRV). The voltage-mode driver (vmDRV) 2331 includes one upper voltage driving path 2331a and one lower voltage driving path 2331c. The upper voltage driving path 2331a receives a positive input signal INp and generates a positive output signal OUTp, while the lower voltage driving path 2331c receives a negative input signal INn and generates a negative output signal OUTn.

[0040] The upper voltage drive path 2331a includes a PMOS transistor MTp1, an NMOS transistor MTn1, a pull-up resistor RTp1, and a pull-down resistor RTn1. The source terminals of the PMOS transistor MTp1 and the NMOS transistor MTn1 are electrically connected to the power supply voltage terminal Vdd and the ground terminal Gnd, respectively. The gate terminals of the PMOS transistor MTp1 and the NMOS transistor MTn1 are electrically connected to the positive input signal INp. The pull-up resistor RTp1 is electrically connected to the drain terminal of the PMOS transistor MTp1 and the positive output terminal OUTp. The pull-down resistor RTn1 is electrically connected to the drain terminal of the NMOS transistor MTn1 and the positive output terminal OUTp.

[0041] The low-voltage drive path 2331c includes a PMOS transistor MTp2, an NMOS transistor MTn2, a pull-up resistor RTp2, and a pull-down resistor RTn2. The source terminals of the PMOS transistor MTp2 and the NMOS transistor MTn2 are electrically connected to the power supply voltage terminal Vdd and the ground terminal Gnd, respectively. The gate terminals of the PMOS transistor MTp2 and the NMOS transistor MTn2 are electrically connected to the negative input signal INn. The pull-up resistor RTp2 is electrically connected to the drain terminal of the PMOS transistor MTp2 and the positive output terminal OUTp. The pull-down resistor RTn2 is electrically connected to the drain terminal of the NMOS transistor MTn2 and the negative output terminal OUTn.

[0042] 4, the upper voltage driving path 2331a and the lower voltage driving path 2331c are inverter-based designs, and their layouts are similar. In this specification, the resistances of the pull-up resistors RTp1 and RTp2 and the pull-down resistors RTn1 and RTn2 are assumed to be equivalent.

[0043] Based on the difference in the input bit sequence inS, the voltage-mode driver (vmDRV) 2331 operates in two states. State 1 (ST1) (see FIG. 5A) indicates that the input bit sequence inS is equivalent to a logic low potential "0" (inS=L). In state 1 (ST1), the positive input signal INp is set to a negative voltage (Inp=L) and the negative input signal INn is set to a positive voltage (INn=H). State 2 (ST2) (see FIG. 5B) indicates that the input bit sequence inS is equivalent to a logic high potential "1" (inS=H). In state 2 (ST2), the positive input signal INp is set to a positive voltage (INp=H) and the negative input signal INn is set to a negative voltage (INn=L).

[0044] 5A shows an example of a schematic circuit diagram of the voltage-mode driver (vmDRV) in state 1 (ST1). The upper voltage drive path 2331a and the lower voltage drive path 2331c are described below.

[0045] When the upper voltage drive path 2331a receives a negative voltage (INp=L), the PMOS transistor MTp1 is turned on and the NMOS transistor MTn1 is turned off, so that the pull-up resistor RTp1 conducts the power supply voltage Vdd to the positive output terminal OUTp, and the pull-down resistor RTn1 is floating.

[0046] When the low-voltage drive path 2331c receives a positive voltage (INn=H), the PMOS transistor MTp2 is turned off and the NMOS transistor MTn2 is turned on, causing the pull-up resistor RTp2 to float and the pull-down resistor RTn2 to conduct the ground voltage Gnd to the negative output terminal OUTn.

[0047] 5B shows an example of a schematic circuit diagram of the voltage-mode driver (vmDRV) in state 2 (ST2). The upper voltage drive path 2331a and the lower voltage drive path 2331c are described below.

[0048] When the upper voltage drive path 2331a receives a positive voltage (INp=H), the PMOS transistor MTp1 is turned off and the NMOS transistor MTn1 is turned on, causing the pull-up resistor RTp1 to float and the pull-down resistor RTn1 to conduct the ground voltage Gnd to the positive output terminal OUTp.

[0049] When the low-voltage drive path 2331c receives a negative voltage (INp=L), the PMOS transistor MTp2 is turned on and the NMOS transistor MTn2 is turned off, so that the pull-up resistor RTp2 conducts the power supply voltage Vdd to the negative output terminal OUTn, and the pull-down resistor RTn2 is floating.

[0050] To summarize the above, when inS=L, the pull-up resistor RTp1 conducts the power supply voltage Vdd to the positive output terminal OUTp, and the pull-down resistor RTn2 conducts the ground voltage Gnd to the negative output terminal OUTn (see FIG. 5A).On the other hand, when the pull-down resistor RTn1 conducts the ground voltage Gnd to the positive output terminal OUTp, and when inS=H, the pull-up resistor RTp2 conducts the power supply voltage Vdd to the negative output terminal OUTn (see FIG. 5B).

[0051] In this specification, the current mode drivers (cmDRV) 2333a and 2333b are assumed to be three current sources SRC C-1 , SRC C0 , SRC C+1 This is realized by the current source SRC C-1 , SRC C0 , SRC C+1 are the three source currents I C-1 , I C0 , I C+1 (see Figure 3A), or two source currents I C-1 , I C+1 and one sink current IC0 (See Figure 3B.)

[0052] The following describes in detail how the voltage-mode driver (vmDRV) and current-mode driver (cmDRV) are configured to perform pre-emphasis equalization and generate the de-emphasis voltage (Va), flat-level voltage (Vb), pre-shoot voltage (Vc), and maximum boost voltage (Vd). Table 3 summarizes the relationship between the current-mode drivers (cmDRV) 2333a, 2333b, the positive input signal INp, the negative input signal INn, and the configuration of the diagram.

[0053] [Table 3]

[0054] In the following description, the components associated with the positive output signal OUTp are defined as upper conduction paths, and the components associated with the negative output signal OUTn are defined as lower conduction paths. For ease of understanding, the upper conduction paths are indicated by thick lines, and the lower conduction paths are indicated by thin lines.

[0055] For ease of understanding, the code uses the double slash symbol " / / " to denote the parallel equivalent resistance of a resistor. For example, RTp1 / / RLp denotes the parallel equivalent resistance of a pull-up resistor RTp1 and a positive load resistor RLp connected in parallel. That is, RTp1 / / RLp = RTp1*RLp / (RTp1+RLp).

[0056] 6A, 6B, 7A, and 7B relate to the generation of the de-emphasis voltage (Va). In FIGS. 6A and 6B, the current source SRC C0 is the source current I C0 In Figures 7A and 7B, the current source SRC C0 is the sink current I C0 is supplied.

[0057] 6A and 6B show a schematic diagram of the circuit, which shows the source current I when the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2). C-1 , I C0 , I C+1 Next, we will explain how to generate the de-emphasis voltage (Va) based on the above.

[0058] Figure 6A corresponds to the situation where the voltage mode driver (vmDRV) 2331 is in state 1 (ST1). See Figures 3A, 5A and 6A in conjunction. Current source SRC C-1 , SRC C0 is conducted to the positive output terminal OUTp, and the current source SRC C+1 is conducted to the negative output terminal OUTn (see FIG. 6A). The relevant parameters of the positive output signal OUTp and the negative output signal OUTn shown in FIG. 6A are listed in Table 4.

[0059] [Table 4]

[0060] In the example of Figure 6A, the upper conduction path is made up of pull-up resistor RTp1 and current source SRC C-1 , SRC C0 and a positive load resistor RLp. The lower conduction path includes a pull-down resistor RTn2 and a current source SRC C+1 and a negative load resistor RLn.

[0061] In the upper conduction path, the positive output signal OUTp includes one DC component Vdc_p and one swing component Vsw_p. When the pull-up resistor RTp1 conducts the power supply voltage Vdd to the positive output terminal OUTp, the DC component Vdc_p of the positive output signal OUTp is obtained by the power supply voltage Vdd and the resistor divider (including the pull-up resistor RTp1 and the positive load resistor RLp) (i.e., Vdc_p=Vdd*RLp / (RTp1+RLp)). Meanwhile, the swing component Vsw_p of the positive output signal OUTp is expressed as the product of the positive load current ILp multiplied by the parallel equivalent resistance of the pull-up resistor RTp1 and the positive load resistor RLp (i.e., Vsw_p=ILp*(RTp1 / / RLp)).

[0062] In the lower conduction path, the pull-down resistor RTn2 conducts the ground voltage Gnd to the negative output terminal OUTn. This causes the DC component Vdc_n of the negative output signal OUTn to correspond to 0V, and the negative output signal OUTn contains only a swing component Vsw_n. The swing component Vsw_n of the negative output signal OUTn can be expressed as the product of the negative load current ILn multiplied by the parallel equivalent resistance of the pull-down resistor RTn2 and the negative load resistor RLn (i.e., Vsw_n=ILn*(RTn2 / / RLn)).

[0063] Figure 6B corresponds to the situation where the voltage-mode driver (vmDRV) 2331 is in state 2 (ST2). See Figures 3A, 5B and 6B in combination. In the example of Figure 6B, the current source SRC C+1 is conducted to the positive output terminal OUTp, and the current source SRC C-1 , SRC C0 is conducted to the negative output terminal OUTn. The parameters related to the generation of the positive output signal OUTp and the negative output signal OUTn shown in FIG.

[0064] [Table 5]

[0065] As shown in FIG. 6B, the upper conduction path includes a pull-down resistor RTn1 and a current source SRC C+1and a positive load resistor RLp. The low conduction path includes a pull-up resistor RTp2 and a current source SRC C-1 and SRC C0 and a negative load resistor RLn.

[0066] In the upper (high) conduction path, the pull-down resistor RTn1 conducts the ground voltage Gnd to the positive output terminal OUTp. This causes the DC component Vdc_p of the positive output signal OUTp to correspond to 0 V, and the positive output signal OUTp contains only a swing component Vsw_p. The swing component Vsw_p of the positive output signal OUTp is expressed as the product of the positive load current ILp multiplied by the parallel equivalent resistance of the pull-down resistor RTn1 and the positive load resistor RLp (i.e., Vsw_p=ILp*(RTn1 / / RLp)).

[0067] In the lower (lower) conduction path, the negative output signal OUTn includes one DC component Vdc_n and one swing component Vsw_n. When the pull-up resistor RTp2 conducts the power supply voltage Vdd to the negative output terminal OUTn, the DC component Vdc_n of the negative output signal OUTn is obtained by the power supply voltage Vdd and the resistor divider (including the pull-up resistor RTp2 and the negative load resistor RLn) (i.e., Vdc_n=Vdd*RLn / (RTp2+RLn)). Meanwhile, the swing component Vsw_n of the negative output signal OUTn is expressed as the product of the negative load current ILn multiplied by the parallel equivalent resistance of the pull-up resistor RTp2 and the negative load resistor RLn (i.e., Vsw_n=ILn*(RTp2 / / RLn)).

[0068] The schematic diagrams shown in FIGS. 7A and 7B show the source current I when the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2). C-1 , I C+1 and sink current I C0 Each of these describes how the de-emphasis voltage (Va) is generated based on the

[0069] Figure 7A corresponds to the situation where the voltage-mode driver (vmDRV) 2331 is in state 1 (ST1). Please refer to Figures 3B, 5A and 7A in combination. In the example of Figure 7A, the current source SRC C-1 , SRC C0 is conducted to the positive output terminal OUTp, and the current source SRC C+1 is conducted to the negative output terminal OUTn. The parameters associated with generating the positive output signal OUTp and the negative output signal OUTn shown in FIG.

[0070] [Table 6]

[0071] In the example of Figure 7A, the upper conduction path is made up of pull-up resistor RTp1 and current source SRC C-1 , SRC C0 and a positive load resistor RLp. The lower conduction path includes a pull-down resistor RTn2 and a current source SRC C+1 and a negative load resistor RLn.

[0072] In the upper conduction path, the positive output signal OUTp includes one DC component Vdc_p and one swing component Vswp. When the pull-up resistor RTp1 conducts the power supply voltage Vdd to the positive output terminal OUTp, the DC component Vdc_p of the positive output signal OUTp is obtained by the power supply voltage Vdd and the resistor divider (including the pull-up resistor RTp1 and the positive load resistor RLp) (i.e., Vdc_p=Vdd*RLp / (RTp1+RLp)). Meanwhile, the swing component Vsw_p of the positive output signal OUTp is expressed as the product of the positive load current ILp multiplied by the parallel equivalent resistance of the pull-up resistor RTp1 and the positive load resistor RLp (i.e., Vsw_p=ILp*(RTp1 / / RLp)).

[0073] In the lower conduction path, the pull-down resistor RTn2 conducts the ground voltage Gnd to the negative output terminal OUTn. This causes the DC component Vdc_n of the negative output signal OUTn to correspond to 0V, and the negative output signal OUTn contains only a swing component Vsw_n. The swing component Vsw_n of the negative output signal OUTn can be expressed as the product of the negative load current ILn multiplied by the parallel equivalent resistance of the pull-down resistor RTn2 and the negative load resistor RLn (i.e., Vsw_n=ILn*(RTn2 / / RLn)).

[0074] Figure 7B corresponds to the situation where the voltage-mode driver (vmDRV) 2331 is in state 2 (ST2). See Figures 3B, 5B, and 7B together. In the example of Figure 7B, the current source SRC C+1 is conducted to the positive output terminal OUTp, and the current source SRC C-1 , SRC C0 is conducted to the negative output terminal OUTn. The parameters associated with generating the positive output signal OUTp and the negative output signal OUTn shown in FIG.

[0075] [Table 7]

[0076] The upper conduction path consists of a pull-down resistor RTn1 and a current source SRC C+1 and a positive load resistor RLp (see FIG. 7B). The lower conduction path includes a pull-up resistor RTp2 and a current source SRC C-1 , SRC C0 and a negative load resistor RLn.

[0077] In the upper conduction path, the pull-down resistor RTn1 conducts the ground voltage Gnd to the positive output terminal OUTp. This causes the DC component Vdcp of the positive output signal OUTp to correspond to 0 V, and the positive output signal OUTp contains only a swing component Vswp. The swing component Vsw_p of the positive output signal OUTp is expressed as the product of the negative load current ILn multiplied by the parallel equivalent resistance of the pull-down resistor RTn1 and the positive load resistor RLp (i.e., Vsw_p=ILp*(RTn1 / / RLp)).

[0078] In the lower conduction path, the negative output signal OUTn includes one DC component Vdc_n and one swing component Vsw_n. When the pull-up resistor RTp2 conducts the power supply voltage Vdd to the negative output terminal OUTn, the DC component Vdc_n of the negative output signal OUTn is obtained by the power supply voltage Vdd and the resistor divider (including the pull-up resistor RTp2 and the negative load resistor RLn) (i.e., Vdc_n=Vdd*RLn / (RTp2+RLn)). Meanwhile, the swing component Vsw_n of the negative output signal OUTn is expressed as the product of the negative load current ILn multiplied by the parallel equivalent resistance of the pull-up resistor RTp2 and the negative load resistor RLn (i.e., Vsw_n=ILn*(RTp2 / / RLn)).

[0079] Please refer to Figures 6A and 7A together. As shown in Figures 6A and 7A, when the voltage-mode driver (vmDRV) operates in state 1 (ST1), the physical driver module outputs a de-emphasis voltage (Va) by adjusting the current-mode driver (cmDRV). The parameters shown in Figures 6A and 7A are listed in Table 8.

[0080] [Table 8]

[0081] As shown in Figures 6A and 7A, when the voltage-mode driver (vmDRV) operates in state 1 (ST1), the positive output signal OUTp includes a DC component Vdc_p and a swing component Vsw_p, and the negative output signal OUTn includes only the swing component Vsw_n.

[0082] 6A and 7A, compare the upper (high) conduction paths in the figures. The DC components Vdc_p of the positive output signal OUTp shown in FIGS. 6A and 7A are equivalent (i.e., Vdc_p=Vdd*RLp / (RTp1+RLp)). Also, the two swing components Vsw_p of the positive output signal OUTp shown in FIGS. 6A and 7A are both expressed as Vsw_p=ILp*(RTp1 / / RLp). It should be noted here that the current value ILp of the positive load current is different in FIGS. 6A and 7A. The positive load current ILp shown in FIG. 6A is the source current I C-1 , I C0 (i.e., ILp = I C-1 +I C0 ), and the positive load current ILp shown in FIG. 7A is the source current I C-1 and sink current -I C0 (i.e., ILp = I C-1 +(-I C0 )=I C-1 -I C0 ).

[0083] Compare the lower conduction paths shown in FIGS. 6A and 7A. The swing component Vsw_n of the negative output signal OUTn shown in FIGS. 6A and 7A is expressed by the formula Vsw_n=ILn*(RTn2 / / RLn), and the negative load current ILn is the source current I C+1 (i.e., ILn = I C+1 ) is equivalent to

[0084] Please refer to Figures 6B and 7B. As shown in Figures 6B and 7B, when the voltage-mode driver (vmDRV) operates in state 2 (ST2), the physical driver module outputs the de-emphasis voltage (Va) by adjusting the current-mode driver (cmDRV). The relevant parameters shown in Figures 6B and 7B are listed in Table 9.

[0085] [Table 9]

[0086] As shown in Figures 6B and 7B, when the voltage driver (vmDRV) operates in state 2 (ST2), the positive output signal OUTp includes only the swing component Vsw_p, and the negative output signal OUTn includes the DC component Vdc_n and the swing component Vsw_n.

[0087] Compare the upper (high) conduction paths shown in FIGS. 6B and 7B. The swing component Vsw_p of the positive output signal OUTp shown in FIGS. 6B and 7B is expressed as Vsw_p = ILn*(RTn1 / RLp), and the positive load current ILp is expressed as the source current I C+1 is equivalent to

[0088] Compare the lower (lower) conduction paths shown in Figures 6B and 7B. The DC components Vdc_n of the negative output signal OUTn shown in Figures 6B and 7B are equivalent (i.e., Vdc_n=Vdd*RLn / (RTp2+RLn)). Also, the two swing components Vsw_n of the negative output signal OUTn shown in Figures 6B and 7B are both expressed as Vsw_n=ILn*(RTp2 / / RLn). It should be noted here that the current values ​​of the negative load current ILn shown in Figures 6B and 7B are different. The negative load current ILn shown in Figure 6B is the source current I C-1 , I C0 (i.e., ILn=I C-1 +I C0 ), the negative load current ILn shown in Figure 7B is the source current I C-1 and sink current -I C0 (i.e., ILn = I C-1 +(-I C0 )= I C-1 -I C0 ).

[0089] The construction and operation of the voltage-mode driver (vmDRV) 2331 for generating the de-emphasis voltage (Va) has been previously described in detail in Figures 6A, 6B, 7A, and 7B. In short, the generation of the flat-level voltage (Vb), pre-shoot voltage (Vc), and maximum boost voltage (Vd) is not similar to the detailed description of the de-emphasis voltage (Va).

[0090] 8A, 8B, 9A, and 9B relate to the generation of a flat-level voltage (Vb). As shown in FIGS. 8A and 8B, a current source SRC C0 is the source current I C0 In the examples of Figures 9A and 8A, the current source SRC C0 is the sink current I C0 The switch states of the switches SWp1, SWn1, SWp2, SWn2, SWp3, and SWn3 correspond to FIGS. 8A, 8B, 9A, and 9B, and are summarized in Table 10.

[0091] [Table 10]

[0092] 8A and 8B show a schematic diagram of the circuit, which shows the source current I when the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2). C-1 , I C0 , I C+1 We will explain how to generate a flat level voltage (Vb) based on these.

[0093] 10, 3A, 5A and 8A in combination. In the example of FIG. 8A, the upper conductive path is connected to a pull-up resistor RTp1 and a current source SRC C-1 , SRC C+1 and a positive load resistor RLp, and the positive load current ILp is C-1 , I C+1 That is, ILp=(I C-1 , I C+1 ) The lower conduction path is made up of a pull-down resistor RTn2 and a current source SRC C0 and a negative load resistor RLn, and a negative load current ILn is supplied to the source current I C0 That is, ILn = I C0 is.

[0094] 10, 3A, 5B, and 8B. In the example of FIG. 8B, the upper conduction path includes a pull-down resistor RTn1 and a current source SRC C0 and a positive load resistor RLp, and the positive load current ILp is C0 That is, ILp = I C0 The lower conduction path is made up of a pull-up resistor RTp2 and a current source SRC C-1 , SRC C+1 and a negative load resistor RLn, and a negative load current ILn is supplied to the source current I C-1 , I C+ 1, that is, ILn=(I C-1 +I C+1 )

[0095] 9A and 9B show a schematic diagram of the circuit, in which the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2), and the source current I C-1 , I C+1 and sink current I C0 We will explain how to generate a flat level voltage (Vb) based on these.

[0096] 10, 3B, 5A, and 9A. In the example of FIG. 9A, the upper conduction path includes a pull-up resistor RTp1 and a current source SRC C-1 , SRC C+1 and a positive load resistor RLp, and the positive load current ILp is C-1 , I C+1 That is, ILp=( I C-1 , I C+1 ) The lower conduction path is made up of a pull-down resistor RTn2 and a current source SRC C0 and a negative load resistor RLn, and a negative load current ILn is supplied to the sink current -I C0 That is, ILn=-I C0 is.

[0097] 10, 3B, 5B, and 9B. In the example of FIG. 9B, the upper conduction path includes a pull-down resistor RTn1 and a current source SRC C0 and a positive load resistor RLp, and the positive load current ILp is C0 That is, ILp = I C0 The lower conduction path is made up of a pull-up resistor RTp2 and a current source SRC C-1 , SRC C+1 and a negative load resistor RLn, and a negative load current ILn is supplied to the source current I C-1 , I C+1 That is, ILn=(I C-1 +I C+1 )

[0098] Please refer to Figures 8A and 9A together. As shown in Figures 8A and 9A, when the voltage-mode driver (vmDRV) operates in state 1 (ST1), the physical driver module outputs a flat level voltage (Vb) by adjusting the current-mode driver (cmDRV). The parameters shown in Figures 8A and 9A are listed in Table 11.

[0099] [Table 11]

[0100] Comparing the upper conduction paths shown in Figures 8A and 9A, the DC components of the positive output signals OUTpVdc_p shown in Figures 8A and 9A are equivalent (i.e., Vdc_p=Vdd*RLp / (RTp1+RLp)). Also, the swing component Vsw_p of the positive output signal OUTp shown in Figures 8A and 9A is expressed using the equation Vsw_p=ILp*(RTp1 / / RLp), and the positive load current ILp is expressed using the equation Vsw_p=ILp*(RTp1 / / RLp). C-1 , I C+1 (i.e., ILp=I C-1 +I C+1 ).

[0101] Compare the low conduction paths shown in Figures 8A and 9A. The swing component Vsw_n of the negative output signal OUTn shown in Figures 8A and 9A can be expressed using the equation Vsw_n=ILn*(RTn2 / / RLn).

[0102] Please refer to Figures 8B and 9B together. As shown in Figures 8B and 9B, when the voltage-mode driver (vmDRV) operates in state 2 (ST2), the physical driver module outputs a flat level voltage (Vb) by adjusting the current-mode driver (cmDRV). The parameters shown in Figures 8B and 9B are listed in Table 12.

[0103] [Table 12]

[0104] Compare the upper conduction paths shown in Figures 8B and 9B. The swing component Vsw_n of the positive output signal OUTp shown in Figures 8B and 9B is expressed as Vsw_n = ILn * (RTn1 / / RLp). It should be noted here that the current value ILp of the positive load current is different between Figures 8B and 9B. The positive load current ILp shown in Figure 8B is the source current I C0 (i.e., ILp = I C0 ), the positive load current ILp shown in Figure 9B is the sink current -I C0 (i.e., ILp=--I C0 ).

[0105] Compare the lower conduction paths shown in Figures 8B and 9B. The DC components Vdc_n of the negative output signal OUTn shown in Figures 8B and 9B are equivalent (i.e., Vdc_n = Vdd * RLn / (RTp2 + RLn)). Also, the swing component Vsw_n of the negative output signal OUTn shown in Figures 8B and 9B is expressed as Vsw_n = ILn * (RTp2 / / RLn), and the negative load current ILn is expressed as the source current I C-1 , I C+1 (i.e., ILn = I C-1 +I C+1 ).

[0106] 10A, 10B, 11A, and 11B are related to the generation of the preshoot voltage (Vc). As shown in FIGS. 10A and 10B, the current source SRC C0 is the source current I C0 As shown in FIGS. 11A and 11B, a current source SRC C0 is the sink current I C0 The switch states of the switches SWp1, SWn1, SWp2, SWn2, SWp3, and SWn3 correspond to FIGS. 10A, 10B, 11A, and 11B and are summarized in Table 13.

[0107] [Table 13]

[0108] 10A and 10B show a schematic diagram of the circuit, in which the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2), and the source current I C-1 , I C0 , I C+1 Next, we will explain how to generate the preshoot voltage (Vc) based on the above.

[0109] See Table 13, Figures 3A, 5A, and Figure 10A. In the example of Figure 10A, the upper conduction path includes pull-up resistor RTp1 and current source SRC C0 , SRC C+1 and a positive load resistor RLp, and the positive load current ILp is C0 , I C+1 That is, ILp=(I C0 +I C+1 ) The lower conduction path is made up of a pull-down resistor RTn2 and a current source SRC C-1 and a negative load resistor RLn, and a source current I C-1 The negative load current ILn is determined by: ILn = I C-1 is.

[0110] See Table 13, Figures 3A, 5B, and 10B. In the example of Figure 10B, the upper conduction path includes a pull-down resistor RTn1 and a current source SRC C-1 and a positive load resistor RLp, and the positive load current ILp is C-1 That is, ILp = I C-1 The lower conduction path is made up of a pull-up resistor RTp2 and a current source SRC C0 , SRC C+1 and a negative load resistor RLn, and a negative load current ILn is supplied to the source current I C0 , I C+1 That is, ILn=( I C0 +I C+1 )

[0111] The circuit schematics 11A and 11B show the source current I when the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2). C-1 , I C+1 and sink current I C0 Next, we will explain how to generate the preshoot voltage (Vc) based on the above.

[0112] See Table 13, Figure 3B, Figure 5A, and Figure 11A. In the example of Figure 11A, the upper conduction path includes pull-up resistor RTp1 and current source SRC C0 , SRC C+1 and a positive load resistor RLp, and a positive load current ILp is supplied to the sink current -I C0 and source current I C+1 That is, ILp=(-I C0 + I C+1 ) The lower conduction path is made up of a pull-down resistor RTn2 and a current source SRC C-1 and a negative load resistor RLn, and a negative load current ILn is supplied to the source current I C-1 That is, ILn = I C-1 is.

[0113] See Table 13, Figures 3B, 5B, and Figure 11B. In the example of Figure 11B, the upper conduction path includes a pull-down resistor RTn1 and a current source SRC C-1 and a positive load resistor RLp, and the positive load current ILp is C-1 That is, ILp = I C-1 The lower conduction path is made up of a pull-up resistor RTp2 and a current source SRC C0 , SRC C+1 and a negative load resistor RLn, and a negative load current ILn is supplied to the sink current -I C0 and source current I C+1 That is, ILn=(-I C0 + I C+1 )

[0114] Please refer to Figures 10A and 11A together. As shown in Figures 10A and 11A, when the voltage-mode driver (vmDRV) operates in state 1 (ST1), the physical driver module outputs a preshoot voltage (Vc) by adjusting the current-mode driver (cmDRV). The parameters shown in Figures 10A and 11A are listed in Table 14.

[0115] [Table 14]

[0116] Compare the upper conduction paths shown in Figures 10A and 11A. The DC components Vdc_p of the positive output signals OUTp shown in Figures 10A and 11A are equivalent (i.e., Vdc_p = Vdd * RLp / (RTp1 + RLp)). Also, the swing component Vsw_p of the positive output signals OUTp shown in Figures 10A and 11A is expressed as Vsw_p = ILp * (RTp1 / / RLp). It should be noted here that the current values ​​of the positive load current ILp shown in Figures 10A and 11A are different. The positive load current ILp shown in Figure 10A is the source current I C0 , I C+1 (i.e., ILp = I C0 +I C+1 ), the positive load current ILp shown in Figure 11A is the sink current -IC0 and source current I C+1 (i.e., ILp=-I C0 +I C+1 ).

[0117] Compare the lower conduction paths shown in Figures 10A and 11A. The swing component Vsw_n of the negative output signal OUTn shown in Figures 10A and 11A is expressed as Vsw_n = ILn * (RTn2 / / RLn), and the negative load current ILn is expressed as the source current I C-1 is equivalent to

[0118] Please refer to Figures 10B and 11B together. As shown in Figures 10B and 11B, when the voltage-mode driver (vmDRV) operates in state 2 (ST2), the physical driver module outputs a preshoot voltage (Vc) by adjusting the current-mode driver (cmDRV). The parameters shown in Figures 10B and 11B are listed in Table 15.

[0119] [Table 15]

[0120] Compare the upper conduction paths shown in Figures 10B and 11B. The swing component Vsw_p of the positive output signal OUTp shown in Figures 10B and 11B is expressed as Vsw_p = ILp * (RTn1 / / RLp). The positive load current ILp is the source current I C-1 (i.e., ILp = I C-1 ).

[0121] 10B and 11B show the lower conduction path. The DC components Vdc_n of the negative output signals OUTn shown in FIGS. 10B and 11B are equivalent (i.e., Vdc_n=Vdd*RLn / (RTp2+RLn)). Also, the swing components Vsw_n of the negative output signals OUTn shown in FIGS. 10B and 11B are expressed as Vsw_n=ILn*(RTp2 / / RLn). It should be noted here that the current values ​​of the negative load current ILn shown in FIGS. 10B and 11B are different. The negative load current ILn shown in FIG. 10B is the source current I C0 , IC+1 (i.e., ILn = I C0 +I C+1 ), the negative load current ILn shown in Figure 11B is the sink current -I C0 and source current I C+1 (i.e., ILn=-I C0 +I C+1 ).

[0122] 12A, 12B, 13A, and 13B relate to generating the maximum boost voltage (Vd). As shown in FIGS. 12A and 12B, the current source SRC C0 is the source current I C0 In the examples of Figures 13A and 13B, the current source SRC C0 is the sink current I C0 The switch states of the switches SWp1, SWn1, SWp2, SWn2, SWp3, and SWn3 correspond to FIGS. 12A, 12B, 13A, and 13B and are summarized in Table 16.

[0123] [Table 16]

[0124] 12A and 12B show a schematic diagram of the circuit, in which the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2), and the source current I C-1 , I C0 , I C+1 This section explains how to generate the maximum boost voltage (Vd) based on the

[0125] See Table 16, Figures 3A, 5A, and Figure 12A. In the example of Figure 12A, the upper conduction path includes pull-up resistor RTp1 and current source SRC C-1 , SRC C0 , SRC C+1 and a positive load resistor RLp. The positive load current ILp is C-1 , I C0 , I C+1 That is, ILp=( I C-1+I C0 +I C+1 ) The lower conduction path includes a pull-down resistor RTn2 and a negative load resistor RLn, and the negative load current ILn corresponds to 0, i.e., ILn=0.

[0126] Referring to Table 16, Figures 3A, 5B, and Figure 12B, in the example of Figure 12B, the upper conduction path includes a pull-down resistor RTn1 and a positive load resistor RLp, and the positive load current ILp corresponds to 0, i.e., ILp=0. The lower conduction path includes a pull-up resistor RTp2 and a current source SRC C-1 , SRC C0 , SRC C+1 and a negative load resistor RLn, and a negative load current ILn is supplied to the source current I C-1 , I C0 , I C+1 That is, ILn=( I C-1 +I C0 +I C+1 )

[0127] 13A and 13B show a schematic diagram of the circuit, in which the voltage-mode driver (vmDRV) is in state 1 (ST1) and state 2 (ST2), and the source current I C-1 , I C+1 and sink current I C0 This section explains how to generate the maximum boost voltage (Vd) based on the

[0128] See Table 16, Figure 3B, Figure 5A, and Figure 13A. In the example of Figure 13A, the upper conduction path includes pull-up resistor RTp1 and current source SRC C-1 , SRC C0 , SRC C+1 and a positive load resistor RLp. The positive load current ILp is C-1 , I C+1 and sink current -I C0 That is, ILp=( I C-1 -I C0 +I C+1) The lower conduction path includes a pull-down resistor RTn2 and a negative load resistor RLn, and the negative load current ILn corresponds to 0, i.e., ILn=0.

[0129] Please refer to Table 16, Figures 3B, 5B, and Figure 13B. In the example of Figure 13B, the upper conduction path includes a pull-down resistor RTn1 and a positive load resistor RLp, and the positive load current ILp corresponds to 0. That is, ILp=0. The lower conduction path includes a pull-up resistor RTp2 and a current source SRC C-1 , SRC C0 , SRC C0+1 and a negative load resistor RLn, and a negative load current ILn is supplied to the source current I C-1 , I C0+1 and sink current -I C0 That is, ILn=(I C-1 -I C0 +I C+1 )

[0130] Please refer to Figures 12A and 13A together. As shown in Figures 12A and 13A, when the voltage-mode driver (vmDRV) operates in state 1 (ST1), the physical driver module outputs the maximum boost voltage (Vd) by adjusting the current-mode driver (cmDRV). The parameters shown in Figures 12A and 13A are listed in Table 17.

[0131] [Table 17]

[0132] Compare the upper conduction paths shown in Figures 12A and 13A. The DC components Vdc_p of the positive output signals OUTp shown in Figures 12A and 13A are equivalent (i.e., Vdc_p = Vdd * RLp / (RTp1 + RLp)). Also, the swing components Vsw_p of the positive output signals OUTp shown in Figures 12A and 13A are expressed as Vsw_p = ILp * (RTp1 / / RLp). It should be noted here that the current values ​​of the positive load currents shown in Figures 12A and 13A are different. The positive load current ILp shown in Figure 12A is the source current IC-1 , I C0 , I C+1 (i.e., ILp = I C-1 +I C0 +I C+1 ), the negative load current ILp shown in Figure 13A is the sink current -I C0 and source current I C-1 , I C+1 (i.e., ILp = I C-1 -I C0 +I C+1 ).

[0133] Compare the lower conduction paths shown in Figures 12A and 13A. As shown in Figures 12A and 13A, the negative load current ILn is equivalent to 0 (ILn=0), so the swing component Vsw_n of the negative output signal OUTn is equivalent to 0V.

[0134] See Figures 12B and 13B together. As shown in Figures 12B and 13B, when the voltage-mode driver (vmDRV) operates in state 2 (ST2), the physical driver module outputs the maximum boost voltage (Vd) by adjusting the current-mode driver (cmDRV). The parameters shown in Figures 12B and 13B are listed in Table 18.

[0135] [Table 18]

[0136] Compare the upper conduction paths shown in Figures 12B and 13B. As shown in Figures 12B and 13B, the positive load current ILp is equivalent to 0 (ILp=0), so the swing component Vsw_p of the positive output signal OUTp is equivalent to 0V.

[0137] Compare the low conduction paths shown in Figures 12B and 13B. The DC components Vdc_n of the negative output signals OUTn shown in Figures 12B and 13B are equivalent (i.e., Vdc_n = Vdd * RLn / (RTp2 + RLn)). The swing components Vsw_n of the negative output signals OUTn shown in Figures 12B and 13B are expressed as Vsw_n = ILn * (RTp2 / / RLn). It should be noted here that the negative load current ILn shown in Figures 12B and 13B is different. The negative load current ILn shown in Figure 12B is the source current I C-1 , I C0 , I C+1 (ILn=I C-1 +I C0 +I C+1 ) and the negative load current ILn shown in FIG. 13B corresponds to the sum of the sink current -I C0 and source current I C-1 , I C+1 (i.e., ILn = I C-1 -I C0 +I C+1 ).

[0138] Figure 14 shows the power supply current I C-1 Current source SRC to supply C-1 FIG. 1 is a schematic diagram illustrating an exemplary circuit diagram of a current source (SRC C-1 The reference voltage Vref and the current setting signal SET are connected to a digital-to-analog converter (DAC) 51, a PMOS transistor M1, and a voltage-to-current conversion circuit 55. C-1 Based on this, DAC 51 generates an analog setting voltage at the inverting input (-) of error amplifier 53. The analog setting voltage is supplied to current setting signal SET C-1 The tap coefficients are displayed as set by the above.

[0139] The voltage-current conversion circuit 55 includes a PMOS transistor MR1, a driving replica resistor RT1, and a loading replica resistor RL1. The driving replica resistor RT1 is electrically connected to the non-inverting input terminal (+) of the error amplifier 53 and the ground terminal Gnd. The resistance of the driving replica resistor RT1 corresponds to the total resistance of the pull-up resistors RTp1 and RTp2 and the pull-down resistors RTn1 and RTn2. The load replica resistor RL1 is electrically connected to the non-inverting input terminal (+) of the error amplifier 53 and the ground terminal Gnd. The resistance of the load replica resistor RL1 corresponds to the total resistance of the positive load resistor RLp and the negative load resistor RLn.

[0140] The source terminals of the PMOS transistors M1 and MR1 are electrically connected to the power supply voltage terminal Vdd, and the gate terminals of the PMOS transistors M1 and MR1 are electrically connected to the output terminal of the error amplifier 53. The drain terminal of the PMOS transistor M1 is electrically connected to the switches SWp1 and SWn1.

[0141] The PMOS transistors M1 and MR1 form a current mirror, and the reference mirror current I MR1 is replicated, and the source current I flows through the PMOS transistor M1. C-1 is generated. The reference mirror current I MR1 changes according to the signal at the non-inverting input terminal (+) of the error amplifier 53. Based on the virtual ground characteristic of the error amplifier 53, the signal at the non-inverting input terminal (+) becomes an equivalent signal at the inverting input terminal (-) of the error amplifier 53.

[0142] The inverting input terminal (-) of the error amplifier 53 receives the analog setting voltage from the DAC 51, and the analog setting voltage is converted into the current setting signal SET C-1 When the tap coefficient set by the error amplifier 53 is displayed, the signal at the non-inverting input terminal (+) of the error amplifier 53 is the current setting signal SET C-1Once the signal at the inverting input terminal (-) of the error amplifier 53 changes, the non-inverting input terminal (+) of the error amplifier 53, the reference mirror current I MR1 , and the source current I C-1 also changes correspondingly.

[0143] As described above, the switches SWp1 and SWn1 are alternately turned on. By doing so, when the switch SWp1 is turned on, the PMOS transistor M1 flows a source current I C-1 is conducted from the power supply voltage terminal Vdd to the positive output terminal OUTp, or to the negative output terminal OUTn when the switch SWn1 is conductive.

[0144] Figure 15A shows the power supply current I C0 Current source SRC to supply C0 FIG. 1 is a schematic diagram illustrating an exemplary circuit diagram of a current source (SRC C0 The converter 60a includes an error amplifier 63a, a DAC 61a, a PMOS transistor M2a, and a voltage-current conversion circuit 65a. The voltage-current conversion circuit 65a includes a PMOS transistor MR2a, a drive replica resistor RT2a, and a load replica resistor RL2a.

[0145] The reference mirror current I flows through the PMOS transistor MR2a. MR2a is the current setting signal SET C0 The source current I that flows through the PMOS transistor M2a is indirectly set by and replicated by C0 Then, when the switch SWp2 is turned on, the source current I C0 is conducted from the power supply voltage terminal Vdd to the positive output terminal OUTp, or to the negative output terminal OUTn when the switch SWn2 is turned on. C-1 )50, (SRC C0 ) 60a has a similar layout. C0 ) 60a, the internal connections and operation thereof will not be described in detail.

[0146] Figure 15B shows the sink current IC0 Current source SRC to supply C0 FIG. 1 is a schematic diagram illustrating an exemplary circuit diagram of a current source (SRC C0 The reference voltage Vref and the current setting signal SET are connected to a power supply 60b. C0 Based on this, DAC 61b generates an analog set voltage at the inverting input terminal (-) of error amplifier 63b.

[0147] The voltage-current conversion circuit 65b includes one NMOS transistor MR2b, one drive replica resistor RT2b, and one load replica resistor RL2b. The drive replica resistor RT2b is electrically connected to the non-inverting input terminal (+) of the error amplifier 63b and the power supply voltage terminal Vdd. The resistance of the drive replica resistor RT2b corresponds to the total resistance of the pull-up resistors RTp1, RTp2 and the pull-down resistors RTn1, RTn2. The load replica resistor RL2b is electrically connected to the non-inverting input terminal (+) of the error amplifier 63b and the power supply voltage terminal Vdd. The resistance of the load replica resistor RL2b corresponds to the total resistance of the positive load resistor RLp and the negative load resistor RLn.

[0148] The source terminals of the NMOS transistors M2b and MR2b are electrically connected to the ground terminal Gnd, and the gate terminals of the NMOS transistors M2b and MR2b are electrically connected to the output terminal of the error amplifier 63b. The drain terminal of the NMOS transistor M2b is electrically connected to the switches SWp2 and SWn2.

[0149] The NMOS transistors M2b and MR2b form a current mirror, and the reference mirror current I MR2b is replicated, and the sink current I flows through the NMOS transistor M2b. C0 is generated. The reference mirror current I MR2bvaries according to the signal at the non-inverting input terminal (+) of the error amplifier 63b. Due to the virtual ground characteristic of the error amplifier 63b, the signal at the non-inverting input terminal (+) becomes equivalent to the signal at the inverting input terminal (-).

[0150] The inverting input terminal (-) of the error amplifier 63b receives the analog setting voltage from the DAC 61b, and the analog setting voltage is converted into the current setting signal SET C0 By displaying the tap coefficient set by the above, the signal at the non-inverting input terminal (+) of the error amplifier 63b is the current setting signal SET C0 Once the signal at the inverting input terminal (-) of the error amplifier 63b changes, the non-inverting input terminal (+) of the error amplifier 63b, the reference mirror current I MR2b , and the sink current I C0 also changes correspondingly.

[0151] As described above, the switches SWp2 and SWn2 are alternately turned on. By doing so, when the switch SWp2 is turned on, the NMOS transistor M2b sinks the current I C0 is conducted from the positive output terminal OUTp to the ground terminal Gnd, or when the switch SWn2 is turned on, the sink current I C0 is conducted from the negative output terminal OUTn to the ground terminal Gnd.

[0152] Figure 16 shows the power supply current I c+1 Current source SRC to supply C+1 1 is a schematic diagram illustrating an exemplary circuit diagram of a current source (SRCC+1) 70. The current source (SRCC+1) 70 includes an error amplifier 73, a DAC 71, a PMOS transistor M3, and a voltage-to-current conversion circuit 75. The voltage-to-current conversion circuit 75 includes a PMOS transistor MR3, a drive replica resistor RT3, and a load replica resistor RL3.

[0153] The reference mirror current I flows through the PMOS transistor MR3. MR3 is the current setting signal SET C+1 The source current I that flows through the PMOS transistor M3 is indirectly set by and replicated byC+1 Then, when the switch SWp3 is turned on, the source current I C+1 is conducted from the power supply voltage terminal Vdd to the positive output terminal OUTp, or to the negative output terminal OUTn when the switch SWn3 is turned on. C-1 )50, (SRC C+1 ) 70 has a similar layout and includes a current source (SRC C+1 A detailed description of the internal connections and operation of the 70 will be omitted.

[0154] An example of a physical driver module equipped with a 3-tap FFE is shown in the figure above. The physical driver module uses a two-stage design (voltage-mode driver vmDRV and current-mode driver cmDRV) to drive a positive input signal INp and a negative input signal INn to generate a positive output signal OUTp and a negative output signal OUTn. The positive output signal OUTp and the negative output signal OUTn jointly constitute the transmission signal.

[0155] In the first stage, the voltage mode driver (vmDRV) 2331 operates at high speed with low power consumption. In the second stage, the current mode drivers (cmDRV) 2333a and 2333b inject sufficient positive load current ILp and negative load current ILn toward the load circuit (ldCKT) 25. By using the current mode drivers (cmDRV) 2333a and 2333b, the output resistances of the physical drive modules 23a and 23b are kept matched, a higher voltage swing (higher than Vdd / 2) is realized, and the tap coefficient C of the current mode drivers (cmDRV) 2333a and 2333b is -1 , C0, C +1 Current source SRC that displays C-1 , SRC C0 , SRC C+1 The settings are easily programmable. The two-stage layout makes the physical drive module applicable to high-speed SerDes such as PCIe, USB, and DDR.

[0156] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0157] 10 High-Speed ​​System 11(Tx) transmitter 13(Rx) Receiver 15 channels (cable) 20a(Tx) transmitter 20b(Tx) transmitter 21 (MAC) Media Access Controller 23a Physical Drive Module 23b Physical Drive Module 231 (PCS) Physical Coding Sublayer 2311 Serializer 2313 Single-ended to differential conversion circuit 2315 (FFE) Feed-forward equalizer 2315a Switch control circuit 2315c Current control circuit 233a (PMA) Physical Media Access 233b (PMA) Physical Media Access 2331(vmDRV) Voltage Mode Driver 2331a Upper voltage drive path 2331c Low Voltage Drive Path 2333a(cmDRV) Current Mode Driver 2333b (cmDRV) Current Mode Driver 25(ldCKT) load circuit 50(SRC C-1 ) current source 51 (DAC) Digital-to-Analog Converter 53 Error amplifier 55 Voltage-current conversion circuit 60a(SRC C0 ) current source 60b(SRC C0 ) current source 61a (DAC) Digital-to-Analog Converter 61b (DAC) Digital-to-Analog Converter 63a Error amplifier 63b Error Amplifier 65a Voltage-to-current conversion circuit 65b Voltage-to-current conversion circuit 70(SRC C+1 ) current source 71 (DAC) Digital-to-Analog Converter 73 Error amplifier 75 Voltage-current conversion circuit C -1 Tap Coefficients C0 tap coefficient C +1 Tap Coefficients Gnd Earth terminal (ground voltage) I C-1 Source Current I C+1 Source Current I C0 Source current (sink current) ILn Negative load current ILp Positive load current I MR1 Reference Mirror Current I MR2a Reference Mirror Current I MR2b Reference Mirror Current I MR3 Reference Mirror Current inDATp Parallel input data INn Negative input signal INp Positive input signal inS Input bit sequence INV1 inverter INV2 inverter INV3 inverter M1 transistor MR1 transistor M2a transistor MR2a transistor M2b transistor MR2b transistor M3 transistor MR3 transistor MTn1 transistor MTp1 transistor MTn2 transistor MTp2 transistor OUTp Positive output terminal (positive output signal) OUTn Negative output terminal (negative output signal) phyCTL Physical control signal RL1 Load replica resistor RL2a Load Replica Resistor RL2b Load replica resistor RL3 Load replica resistor RLn Negative load resistor RLp positive load resistor RT1 Drive replica resistor RT2a Drive Replica Resistor RT2b Drive Replica Resistor RT3 Drive Replica Resistor RTn1 pull-down resistor RTn2 pull-down resistor RTp1 pull-up resistor RTp2 pull-up resistor Sctl1 switch control signal Sctl2 switch control signal Sctl3 switch control signal SET C-1 Current setting signal SET C0 Current setting signal SET C+1 Current setting signal SRC C-1 current source SRC C0 current source SRC C+1 current source SWp1 switch SWn1 switch SWp2 switch SWn2 switch SWp3 switch SWn3 switch Va De-emphasis voltage Vb Flat level voltage Vc Preshoot voltage Vd Maximum boost voltage Vdd Power supply voltage terminal (power supply voltage) Vref Reference voltage

Claims

1. a voltage-mode driver electrically connected to a positive output terminal and a negative output terminal, for converting a positive input signal into a positive output signal at the positive output terminal and converting a negative input signal into a negative output signal at the negative output terminal, wherein the positive input signal and the negative input signal are differential signals; a current-mode driver electrically connected to the voltage-mode driver; The current mode driver a first current source for supplying a first current toward the positive output terminal and the negative output terminal; a second current source for supplying a second current toward the positive output terminal and the negative output terminal; a third current source for supplying a third current toward the positive output terminal and the negative output terminal; further comprising a feedforward equalizer electrically connected to a media access controller and the current-mode driver, the feedforward equalizer receiving a physical control signal from the media access controller and correspondingly performing pre-emphasis equalization, the media access controller generating the physical control signal; the first current source, the second current source, and the third current source are electrically connected to a power supply voltage terminal; or The driving module, wherein the first current source and the third current source are electrically connected to a power supply voltage terminal, and the second current source is electrically connected to a ground terminal.

2. The drive module is electrically connected to a load circuit, the load circuit comprising: a positive load resistor electrically connected to the positive output terminal and a ground terminal; a negative load resistor electrically connected to the negative output terminal and the ground terminal; 2. The driver module of claim 1, wherein a positive load current flows through the positive load resistor and a negative load current flows through the negative load resistor.

3. The voltage mode driver a first voltage driving path electrically connected to the positive output and configured to conduct one of a power supply voltage and a ground voltage toward the positive output in response to the positive input signal; 3. The drive module of claim 2, further comprising: a second voltage drive path electrically connected to a negative output terminal and arranged to conduct the other of the power supply voltage and the ground voltage to the negative output terminal, the second voltage drive path being responsive to the negative input signal.

4. 4. The driving module of claim 3, wherein when the positive input signal is a negative voltage and the negative input signal is a positive voltage, the first voltage driving path conducts the power supply voltage to the positive output terminal and the second voltage driving path conducts the ground voltage to the negative output terminal.

5. 5. The drive module of claim 4, wherein the positive output signal includes a DC component and a swing component, the negative output signal includes a swing component, the swing component of the positive output signal varies with the positive load current, and the swing component of the negative output signal varies with the negative load current.

6. 5. The driving module of claim 4, wherein when the positive load current is set by the first current and the second current, and the negative load current is set by the third current, the positive output signal and the negative output signal jointly form a de-emphasis voltage.

7. 5. The driving module of claim 4, wherein when the positive load current is set by the first current and the third current, and the negative load current is set by the second current, the positive output signal and the negative output signal jointly form a flat-level voltage.

8. 5. The driving module of claim 4, wherein when the positive load current is set by the second current and the third current, and the negative load current is set by the first current, the positive output signal and the negative output signal collectively form a pre-shoot voltage.

9. 5. The driving module of claim 4, wherein the positive load current is set by the first current, the second current, and the third current, and when the negative load current corresponds to 0, the positive output signal and the negative output signal jointly form a maximum boost voltage.

10. 5. The driving module of claim 4, wherein when the positive input signal is the positive voltage and the negative input signal is the negative voltage, the first voltage driving path conducts the ground voltage to the positive output terminal, and the second voltage driving path conducts the power supply voltage to the negative output terminal.

11. 11. The drive module of claim 10, wherein the positive output signal includes a swing component and the negative output signal includes a DC component and a swing component, the swing component of the positive output signal varying with the positive load current and the swing component of the negative output signal varying with the negative load current.

12. 11. The driving module of claim 10, wherein when the positive load current is set by the third current and the negative load current is set by the first current and the second current, the positive output signal and the negative output signal jointly form a de-emphasis voltage.

13. 11. The driving module of claim 10, wherein when the positive load current is set by the second current and the negative load current is set by the first current and the third current, the positive output signal and the negative output signal jointly form a flat-level voltage.

14. 11. The driving module of claim 10, wherein when the positive load current is set by the first current and the negative load current is set by the second current and the third current, the positive output signal and the negative output signal collectively form a pre-shoot voltage.

15. 11. The driving module of claim 10, wherein when the positive load current of the positive output signal and the negative output signal corresponds to 0 and the negative load current is set by the first current, the second current, and the third current, they jointly form a maximum boost voltage.

16. The current mode driver a first switch electrically connected to the first current source and the positive output terminal; the second first switch electrically connected to the first current source and the negative output terminal, the first first switch and the second first switch being alternately conductive; a first switch electrically connected to the second current source and the positive output terminal; the second switch electrically connected to the second current source and the negative output terminal, the first switch and the second switch being alternately conductive; a first third switch electrically connected to the third current source and the positive output terminal; 2. The driving module of claim 1, further comprising: a second third switch electrically connected to the third current source and the negative output terminal, the first third switch and the second third switch alternately conducting.

17. The feedforward equalizer adjusting current values ​​of the first current, the second current, and the third current, and switching the first first switch, the second first switch, the first second switch, the second second switch, the first third switch, and the second third switch; 17. The driver module of claim 16, wherein the driver module performs the pre-emphasis equalization.

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