Switching device and method for controlling switching device

Abstract

To prevent relaying performance for a packet from decreasing by decreasing cache misses of a cache holding transfer path information on packets.SOLUTION: A switch device has at least some of transfer control functions for a packet off-loaded from a virtual switch to a transfer control circuit. The switch device has: a cache which holds at least any one piece of transfer path information on packets held in a memory; a path control part which uses the transfer path information held in the cache to determine a transfer path for received packets; and a prefetch control part which reads a plurality of pieces of transfer path information, including transfer path information corresponding to a received packet, out of the memory, and then stores them in the cache when the corresponding transfer path information is not held in the cache.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a switch device and a control method for the switch device. [Background technology]

[0002] In a hybrid IP communication system, a local configuration management device of an IP packet communication device generates a local IP packet forwarding table and stores the generated local IP packet forwarding table as cache information (see, for example, Patent Document 1). Also, a cache server included in the network system finds a route suitable for performing an automatic cache update operation or a link prefetch operation, and performs the automatic cache update operation or the link prefetch operation using the found route (see, for example, Patent Document 2). A routing control system that controls packet routing in an autonomous network stores a forwarding information base (FIB) in RAM and the cache of a data packet processor (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-244565 [Patent Document 2] Japanese Patent Application Laid-Open No. 2002-44138 [Patent Document 3] Special Publication No. 2017-510197 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, if a portion of the forwarding information base (hereinafter referred to as FIB) is stored in a cache, the time required to retrieve the FIB can be reduced. However, if the desired FIB is not stored in the cache, a cache miss is detected and then the FIB is retrieved by accessing RAM, which reduces the efficiency of FIB retrieval and packet relay performance. Furthermore, if the request queue holding FIB access requests becomes full due to continued access to RAM, subsequent packets will be discarded, further reducing packet relay performance.

[0005] In one aspect, the present invention aims to suppress a decrease in packet relay performance by reducing cache misses in a cache that holds packet forwarding path information. [Means for solving the problem]

[0006] According to one aspect, the switch device is a switch device in which at least a portion of the packet forwarding control function is offloaded from a virtual switch to a forwarding control circuit, and the forwarding control circuit has: a cache that holds at least one of the forwarding path information of packets held in memory; a route control unit that determines the forwarding path of a received packet using the forwarding path information held in the cache; and a prefetch control unit that, if the forwarding path information corresponding to the received packet is not held in the cache, reads out from the memory a plurality of forwarding path information including the corresponding forwarding path information and stores it in the cache. [Effects of the Invention]

[0007] By reducing cache misses in the cache that holds packet forwarding route information, it is possible to suppress degradation of packet relay performance. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating an example of an information processing device including a switch device according to an embodiment. [Figure 2] 2 is an operation sequence diagram showing an example of the operation of the switch device of FIG. 1. FIG. [Figure 3] 1. FIG. 4 is an operational sequence diagram showing another example of the operation of the switch device of FIG. [Figure 4] FIG. 10 is a block diagram illustrating an example of an information processing device including a switch device according to another embodiment. [Figure 5] 5 is an explanatory diagram showing an example of FIB information held in the memory and cache of FIG. 4. [Figure 6] 5 is a block diagram showing an example of a relay control unit in FIG. 4. FIG. [Figure 7] 7 is a block diagram showing an example of a packet conversion unit in FIG. 6. FIG. [Figure 8] 7 is a block diagram showing an example of a prefetch control unit in FIG. 6. [Figure 9] 9 is an explanatory diagram showing an example of an update operation of an issue history queue of the prefetch control unit of FIG. 8; FIG. [Figure 10] 7 is an explanatory diagram showing an example of a metatable generated by the metatable generating unit of FIG. 6; FIG. [Figure 11] FIG. 7 is a block diagram showing an example of an FIB control unit in FIG. 6. [Figure 12] 7 is an explanatory diagram showing an example of the operation of the relay control unit of FIG. 6; FIG. [Figure 13] 7 is an explanatory diagram showing another example of the operation of the relay control unit in FIG. 6.

[0023] FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] 1 shows an example of an information processing device including a switch device according to an embodiment. The switch device 300 shown in FIG. 1 includes a virtual switch 310 and a transfer control circuit 320 implemented by a CPU (Central Processing Unit) 200 mounted on a server 100.

[0011] For example, the switch device 300 is a network switch. The server 100 is an example of an information processing device, and the CPU 200 is an example of an arithmetic processing device. Other computer devices may be used in place of the server 100, and other processors may be used in place of the CPU 200.

[0012] The switch device 300 is constructed by offloading at least a part of the packet PCKT transfer control function from the virtual switch 310 to a transfer control circuit 320 (i.e., hardware). Although not particularly limited, the transfer control circuit 320 is realized by a logic device such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit) mounted on the server 100.

[0013] The CPU 200 can operate as a virtual switch 310 and a virtual machine 210 by executing a program. For example, the virtual switch 310 has a function of registering or updating, in the memory 400, forwarding path information used to determine a forwarding path for the packet PCKT, among other functions for controlling the forwarding of the packet PCKT to the virtual machine 210, etc. Although not particularly limited, the forwarding path information may be, for example, a forwarding information base (FIB).

[0014] For example, the memory 400 is a Synchronous Dynamic Random Access Memory (SDRAM) or the like mounted on the server 100. For example, the transfer path information is stored in the memory 400 and the cache 340 in association with the packet PCKT or a port (not shown) that receives the packet PCKT.

[0015] The transfer control circuit 320 has a prefetch control unit 330, a cache 340, and a route control unit 350. The prefetch control unit 330 issues a plurality of read requests to read a plurality of pieces of transfer route information, including the transfer route information corresponding to the received packet PCKT, from the memory 400, and stores the plurality of pieces of transfer route information transferred from the memory 400 in the cache 340.

[0016] For example, if the cache 340 does not hold transfer path information corresponding to the packet PCKT received by the transfer control circuit 320, the prefetch control unit 330 issues multiple read requests to the memory 400. Furthermore, if the cache 340 holds transfer path information corresponding to the packet PCKT received by the transfer control circuit 320, the prefetch control unit 330 refrains from issuing multiple read requests to the memory 400. This makes it possible to prevent unnecessary prefetching by the prefetch control unit 330.

[0017] The cache 340 holds multiple pieces of transfer path information prefetched from the memory 400 by the prefetch control unit 330 and transfer path information read from the memory 400 by the path control unit 350. The cache 340 holds at least a portion of the multiple pieces of transfer path information held in the memory 400.

[0018] The route control unit 350 determines a forwarding route for the received packet PCKT using the forwarding route information stored in the cache 340. If the forwarding route information corresponding to the received packet PCKT is not stored in the cache 340, the route control unit 350 issues a read request to the memory 400 to read from the memory 400 the forwarding route information corresponding to the received packet PCKT.

[0019] For example, until the transfer path information corresponding to the received packet PCKT is stored in the cache 340 in response to a read request, the cache 340 is in a cache miss state for the transfer path information corresponding to the packet PCKT. When determining the transfer path for the packet PCKT, if the cache 340 is in a cache miss state, the route control unit 350 issues a read request to the memory 400.

[0020] In this embodiment, the prefetch control unit 330 prefetches from the memory 400 forwarding path information corresponding to packets PCKT other than the received packet PCKT and stores it in the cache 340. This reduces the frequency with which the cache 340 is in a cache miss state when the path control unit 350 determines a forwarding path for the packet PCKT. As a result, it is possible to suppress a decrease in the relay performance of the packet PCKT by the switch device 300.

[0021] Fig. 2 shows an example of an operation sequence of the switch device 300 of Fig. 1. That is, Fig. 2 shows an example of a control method of the switch device 300. In Fig. 2, it is assumed that the same forwarding path information is used to determine the forwarding paths of packets PCKT1 and PCKT2 received by the forwarding control circuit 320. It is also assumed that the forwarding path information used to determine the forwarding paths of packets PCKT1 and PCKT2 has been registered or updated in the memory 400 by the virtual switch 310 before receiving packet PCKT1 (Fig. 2(a)).

[0022] 2 shows the operation of the prefetch control unit 330 when the transfer control circuit 320 receives packets PCKT (PCKT1, PCKT2). For example, based on reception of packet PCKT1 from outside the server 100, the prefetch control unit 330 determines that transfer path information corresponding to packet PCKT1 is not held in the cache 340 (cache miss, FIGS. 2(b) and 2(c)).

[0023] Based on the determination of a cache miss, the prefetch control unit 330 issues a plurality of memory access requests MREQ to the memory 400 to transfer the transfer path information corresponding to the packet PCKT1 and other transfer path information from the memory 400 to the cache 340 (FIG. 2(d)). In response to the plurality of memory access requests MREQ, the memory 400 transfers the plurality of transfer path information to the cache 340 (FIG. 2(e)). The memory access requests MREQ are an example of a read request.

[0024] In this way, the prefetch control unit 330 prefetches at least one other piece of transfer path information in addition to the transfer path information corresponding to the received packet PCKT1. This not only puts the transfer path information corresponding to the packet PCKT1 into a cache hit state, but also makes it possible to put at least one other piece of transfer path information into a cache hit state.

[0025] 2, the prefetch control unit 330 issues multiple memory access requests MREQ to the memory 400. However, if the memory 400 has a burst transfer function, the prefetch control unit 330 may issue one memory access request MREQ for burst transfer to the memory 400.

[0026] 2 shows the prefetch operation of the prefetch control unit 330 for the forwarding path information, but in reality, the route control unit 350 in FIG. 1 performs the forwarding operation of the received packet PCKT1. When the forwarding path information corresponding to the received packet PCKT1 is stored in the cache 340, the route control unit 350 determines the forwarding path of the packet PCKT based on the forwarding path information read from the cache 340. Then, the route control unit 350 forwards the packet PCKT1 to the determined forwarding path.

[0027] On the other hand, if the forwarding route information corresponding to the received packet PCKT1 is not stored in the cache 340, the route control unit 350 issues a memory access request to the memory 400 to transfer the forwarding route information corresponding to the received packet PCKT1 from the memory 400 to the cache 340.

[0028] After that, for example, based on reception of packet PCKT2 from outside server 100, prefetch control unit 330 detects that transfer path information corresponding to packet PCKT2 is held in cache 340 (cache hit, FIGS. 2(f) and 2(g)). Therefore, prefetch control unit 330 does not issue a memory access request MREQ for transferring transfer path information corresponding to packet PCKT2 from memory 400 to cache 340. This makes it possible to suppress unnecessary prefetching by prefetch control unit 330.

[0029] Fig. 3 shows another example of the operation sequence of the switch device 300 of Fig. 1. That is, Fig. 3 shows another example of a control method for the switch device 300. In Fig. 3 as well, it is assumed that the same forwarding path information is used to determine the forwarding paths of the packets PCKT1 and PCKT2 received by the forwarding control circuit 320. Also in Fig. 3 as well, it is assumed that the forwarding path information used to determine the forwarding paths of the packets PCKT1 and PCKT2 is registered or updated in the memory 400 by the virtual switch 310 before receiving the packet PCKT1 (Fig. 3(a)).

[0030] 3 shows the operation of the route control unit 350 when the transfer control circuit 320 receives packets PCKT (PCKT1, PCKT2). The route control unit 350 receives packet PCKT1 from outside the server 100, for example (FIG. 3(b)). The route control unit 350 detects that the transfer route information corresponding to the received packet PCKT1 is not held in the cache 340 (cache miss, FIG. 3(c)).

[0031] Therefore, the route control unit 350 issues a memory access request MREQ to the memory 400 to transfer the forwarding route information corresponding to the packet PCKT1 from the memory 400 to the cache 340 (FIG. 3(d)). In response to the memory access request MREQ, the memory 400 transfers the forwarding route information corresponding to the packet PCKT1 to the cache 340 (FIG. 3(e)).

[0032] The route control unit 350 receives forwarding route information corresponding to the packet PCKT1 to be forwarded from the memory 400 to the cache 340 (FIG. 3(f)). Then, the route control unit 350 determines a forwarding route for the packet PCKT1 based on the received forwarding route information. In the example shown in FIG. 3, the forwarding route for the packet PCKT1 includes one of the virtual machines 210. Therefore, the route control unit 350 forwards the packet PCKT1 to one of the virtual machines 210 (FIG. 3(g)). Note that if the forwarding route information corresponding to the packet PCKT1 is not held in the cache 340, the route control unit 350 may suspend or cancel the packet PCKT1 after issuing the memory access request MREQ to the memory 400.

[0033] After that, the route control unit 350 receives a packet PCKT2, for example, from outside the server 100 (FIG. 3(h)). The route control unit 350 detects that the forwarding route information corresponding to the received packet PCKT2 is held in the cache 340 (cache hit, FIG. 3(i)).

[0034] Therefore, the route control unit 350 reads out the forwarding route information corresponding to the packet PCKT2 from the cache 340 (FIG. 3(j)). Then, the route control unit 350 determines the forwarding route of the packet PCKT2 based on the forwarding route information read out from the cache 340. In the example shown in FIG. 3, the forwarding route of the packet PCKT2 includes one of the virtual machines 210, so the route control unit 350 forwards the packet PCKT2 to one of the virtual machines 210 (FIG. 3(k)).

[0035] As described above, in this embodiment, the prefetch control unit 330 prefetches other transfer path information from the memory 400 in addition to the transfer path information corresponding to the received packet PCKT, and stores the other transfer path information in the cache 340. This reduces the frequency with which the cache 340 is in a cache miss state when the path control unit 350 determines the transfer path of the packet PCKT.

[0036] The hit rate of the cache 340 is improved, which reduces the latency required for the route control unit 350 to acquire forwarding route information. As a result, it is possible to prevent a decrease in the relay performance of the packet PCKT by the switch device 300.

[0037] Furthermore, if the transfer path information corresponding to the received packet PCKT is held in the cache 340, the prefetch control unit 330 does not issue a memory access request MREQ to the memory 400. This makes it possible to suppress unnecessary prefetching by the prefetch control unit 330.

[0038] 4 shows an example of an information processing device including a switch device according to another embodiment. The same elements as those in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The switch device 300A shown in FIG. 4 includes a virtual switch 310A implemented by a program executed by a CPU 200A mounted on a server 100A, and a relay control unit 320A implemented by hardware.

[0039] For example, the switch device 300 is a network switch. The server 100A is an example of an information processing device, and the CPU 200A is an example of an arithmetic processing device. Other computer devices may be used in place of the server 100A, and other processors may be used in place of the CPU 200A.

[0040] The virtual switch 310A is realized by a program executed by the CPU 200A. The switch device 300A is constructed by offloading at least a part of the packet PCKT transfer control function from the virtual switch 310A, which is realized by software, to a relay control unit 320A, which is realized by hardware. Although not particularly limited, the relay control unit 320A is realized by a logic device such as an FPGA or ASIC mounted on the server 100A.

[0041] For example, the switch device 300A is implemented in the server 100A as an Open vSwitch (OVS; registered trademark) acceleration, which is an open source implementation of a distributed virtual multi-layer switch. For example, the virtual switch 310A may be built using OVS / Data Plane Development Kit (DPDK). DPDK is a library for high-speed packet processing.

[0042] By executing a program, the CPU 200A can operate as a virtual switch 310A, a virtual machine 210, and a virtual network interface card VNIC. Hereinafter, the virtual network interface card VNIC will also be simply referred to as a VNIC.

[0043] The relay control unit 320A has a prefetch control unit 330A, a cache 340, a FIB (Forwarding Information Base) control unit 350A, and an internal port IPT, and is connected to an external port EPT. Note that the server 100A may have multiple external ports EPT. The internal port IPT of the relay control unit 320A is connected to the VNIC of the virtual switch 310A or the VNIC of the virtual machine 210. The relay control unit 320A is an example of a transfer control circuit. The FIB control unit 350A is an example of a path control unit.

[0044] If the FIB information corresponding to the received packet PCKT is not held in the cache 340, the prefetch control unit 330A reads a plurality of FIB information including the FIB information corresponding to the received packet PCKT from the memory 400. The prefetch control unit 330A stores the plurality of FIB information read from the memory 400 in the cache 340. For example, the FIB information includes KEY information and ACTION information, which will be described later. The FIB information will be described with reference to FIG. 6.

[0045] The FIB control unit 350A determines a transfer path for a packet PCKT received via, for example, the external port EPT or the internal port IPT, using the FIB information held in the cache 340. If the FIB information corresponding to the received packet PCKT is not held in the cache 340, the FIB control unit 350A reads the FIB information corresponding to the received packet PCKT from the memory 400. The FIB control unit 350A determines a transfer path for the packet PCKT using the FIB information read from the memory 400, and stores the FIB information read from the memory 400 in the cache 340.

[0046] Fig. 5 shows an example of FIB information stored in the memory 400 and cache 340 of Fig. 4. The memory 400 and cache 340 have, for example, multiple storage areas that store FIB information for each packet PCKT received by the FIB control unit 350A.

[0047] The FIB information includes a KEY area where KEY information is stored and an ACTION area where ACTION information is stored. The KEY information includes a common part that is independent of the packet PCKT and a unique part that is unique to the packet PCKT. For example, the unique part stores information such as the packet protocol or packet type. The common part stores information corresponding to the information such as the packet protocol stored in the unique part.

[0048] The ACTION information includes a code CODE and a plurality of data areas DT (DT1, DT2, ...). For example, the code CODE has a number of bits corresponding to the number of ACTION information selectable by the match action unit 353A shown in FIG. 11. Each bit of the code CODE is assigned to each of the plurality of ACTION information. Each data area DT stores ACTION information corresponding to a bit set to "1" in the code CODE. Although not particularly limited, the ACTION information is stored in the plurality of data areas DT in the order of the bits set to "1" in the code CODE.

[0049] This makes it possible to detect a valid data area DT based on the bit value of the code CODE, and to determine the specifications of the ACTION information stored in the valid data area DT. The multiple ACTION information that the match action unit 353A can select are transfer control information stored in the header of the packet PCKT or control information for the packet PCKT used at the destination of the packet PCKT. For example, ACTION information stored in the data area may be setting the source address of the packet PCKT, setting the destination address of the packet PCKT, or an instruction to drop the packet PCKT.

[0050] Fig. 6 shows an example of the relay control unit 320A of Fig. 4. The relay control unit 320A has a packet conversion unit 321A, a meta table generation unit 322A, and a register REG0 in addition to the prefetch control unit 330A, cache 340, and FIB control unit 350A shown in Fig. 4.

[0051] The packet conversion unit 321A generates a logical port number LPT-ID used to identify the packet PCKT from the packet PCKT received by the relay control unit 320A, and outputs the generated logical port number LPT-ID together with the packet PCKT to the meta table generation unit 322A. The packet conversion unit 321A also outputs the generated logical port number LPT-ID to the prefetch control unit 330A as a prefetch request PRREQ0. An example of the packet conversion unit 321A is shown in FIG.

[0052] The meta table generation unit 322A extracts, for example, information to be stored in the packet header from the packet PCKT received by the relay control unit 320A, and generates a meta table for each packet PCKT. The meta table includes the logical port number LPT-ID.

[0053] When the metatable generation unit 322A receives match information PRMCH from the prefetch control unit 330A, it stores the match information PRMCH in the metatable generated corresponding to the received packet PCKT. Also, when the metatable generation unit 322A receives issued information PROK from the FIB control unit 350A, it stores the issued information PROK in the metatable generated corresponding to the received packet PCKT.

[0054] Then, the metatable generation unit 322A outputs the metatable information MTINF included in the generated metatable together with the received packet PCKT to the FIB control unit 350A. The metatable MTTBL generated by the metatable generation unit 322A will be described with reference to FIG.

[0055] The FIB control unit 350A calculates the address indicating the area in the cache 340 or memory 400 that holds the FIB information corresponding to the received packet PCKT, based on the metatable information MTINF.

[0056] If the FIB information corresponding to the received packet PCKT is held in the cache 340, the FIB control unit 350A reads the FIB information from the cache 340. If the FIB information corresponding to the received packet PCKT is held in the memory 400, the FIB control unit 350A reads the FIB information from the memory 400.

[0057] The FIB control unit 350A then determines whether the KEY information included in the read FIB information matches the KEY information included in the packet PCKT. If the KEY information matches, the FIB control unit 350A generates a packet header in accordance with the ACTION information read from the cache 340 or the memory 400, and transfers the packet PCKT including the generated packet header to the transfer destination.

[0058] Furthermore, when the FIB control unit 350A receives a write access request UPDT from the virtual switch 310A (CPU 200A) via the register REG0, it performs processing to update the FIB information held in the memory 400 and the cache 340. When writing the FIB information to the memory 400, the virtual switch 310A writes data indicating the write access request UPDT to the register REG0 (REG-WR).

[0059] Fig. 7 shows an example of the packet conversion unit 321A of Fig. 6. The packet conversion unit 321A has registers REG1 and REG2 and selectors SEL1 and SEL2. The values ​​held by the registers REG1 and REG2 are set by the virtual switch 310A of Fig. 4. In this case, the values ​​held by the registers REG1 and REG2 may be set via the register REG0 of Fig. 6.

[0060] The register REG1 holds an offset value PORT-ID-OFST used to generate physical port IDs corresponding to the external port EPT and the internal port IPT, respectively. The selector SEL1 generates a physical port ID by, for example, adding the offset value PORT-ID-OFST to the identification number of the external port EPT or the internal port IPT that received the packet PCKT, and outputs the generated physical port ID to the selector SEL2. That is, the selector SEL1 selects the physical port ID (indicated by a number) that corresponds to the external port EPT or the internal port IPT that received the packet PCKT.

[0061] The register REG2 holds a value PORT-MAPx (where x is one of n integers from 0 to n+1) for each physical port ID. For example, x in the value PORT-MAPx corresponds to the number of the physical port ID.

[0062] The selector SEL2 outputs the value PORT-MAPx corresponding to the number of the physical port ID as the logical port number LPT-ID to the packet conversion unit 321A in Fig. 6. The selector SEL2 also outputs the logical port number LPT-ID as a prefetch request PRREQ0 to the prefetch control unit 330A. The logical port number LPT-ID and the prefetch request PRREQ0 are assigned corresponding to each packet PCKT received by the relay control unit 320A.

[0063] The logical port number LPT-ID is an example of packet identification information that identifies the packet PCKT received by the relay control unit 320 A. The packet conversion unit 321 A is an example of an identification information generation unit that generates packet identification information.

[0064] Fig. 8 shows an example of the prefetch control unit 330A of Fig. 6. The prefetch control unit 330A has a prefetch determination unit 331A, an address calculation unit 332A, an issue history queue 333A, and a register REG3.

[0065] The prefetch determination unit 331A refers to the issuance history queue 333A based on the prefetch request PRREQ0 (i.e., the logical port number LPT-ID) issued from the packet conversion unit 321A in Fig. 7. Then, the prefetch determination unit 331A determines whether or not to prefetch FIB information from the memory 400. The issuance history queue 333A holds a predetermined number of prefetch requests PRREQ1 previously issued by the address calculation unit 332A.

[0066] If a prefetch request PRREQ1 corresponding to the received prefetch request PRREQ0 is not held in the issue history queue 333A, the prefetch determination unit 331A outputs the prefetch request PRREQ0 to the address calculation unit 332A. Furthermore, if the prefetch request PRREQ1 is not held in the issue history queue 333A and the issue history queue 333A is full, the prefetch determination unit 331A outputs an erase instruction ERS to the issue history queue 333A. The issue history queue 333A erases the oldest prefetch request PRREQ1 based on the erase instruction ERS.

[0067] If a prefetch request PRREQ1 corresponding to the received prefetch request PRREQ0 is held in the issuance history queue 333A, the prefetch determination unit 331A suppresses output of the prefetch request PRREQ0 to the address calculation unit 332A. Then, the prefetch determination unit 331A outputs match information PRMCH. The prefetch determination unit 331A is an example of an issuance suppression unit that suppresses issuance of the prefetch request PRREQ1 to the memory 400 if a prefetch request PRREQ1 corresponding to the received packet PCKT is held in the issuance history queue 333A.

[0068] The match information PRMCH is an example of holding information indicating that the FIB information corresponding to the packet PCKT received by the relay control unit 320A is held in the cache 340 (i.e., a cache hit state). For example, match information PRMCH with a logical value of 1 indicates that the data corresponding to the prefetch request PRREQ0 is in a cache hit state. Match information PRMCH with a logical value of 0 indicates that the data corresponding to the prefetch request PRREQ0 is in a cache miss state.

[0069] The match information PRMCH is stored in the meta table MTTBL. For example, the match information PRMCH having a logical value of 1 indicates that the FIB information corresponding to the received packet PCKT is held in the cache 340 (cache hit state). For example, the match information PRMCH having a logical value of 0 indicates that the FIB information corresponding to the received packet PCKT is not held in the cache 340 (cache miss state).

[0070] In this way, the prefetch control unit 330A can determine whether the FIB information corresponding to the received packet PCKT is in a cache hit state or a cache miss state based on the prefetch request PRREQ1 held in the issuance history queue 333A. The prefetch control unit 330A stores match information PRMCH, which indicates whether the FIB information is in a cache hit state or a cache miss state, in the metatable MTTBL corresponding to the received packet PCKT. This allows the FIB control unit 350A to determine whether the cache 340 is in a cache hit or a cache miss by referring to the metatable information MTINF held in the metatable MTTBL.

[0071] The address calculation unit 332A has an adder ADD that adds the prefetch request PRREQ0 (i.e., the logical port number LPT-ID) from the prefetch determination unit 331A to the base address BASE-ADRS as an index. Then, the address calculation unit 332A issues a prefetch request PRREQ1 that accesses a storage area of ​​the memory 400 with an access length LENmax that includes the address obtained by the addition.

[0072] The prefetch request PRREQ1 may be issued multiple times corresponding to the access length LENmax, and if the memory 400 has a burst function, a burst length corresponding to the access length LENmax may be set. The address calculation unit 332A is an example of a request generation unit that generates the prefetch request PRREQ1.

[0073] When the address calculation unit 332A outputs the prefetch request PRREQ1, the FIB control unit 350A outputs issued information PROK, which indicates that a prefetch request has been issued to the memory 400, to the meta table generation unit 322A. For example, issued information PROK with a logical value of 1 indicates that a prefetch request has been issued to the memory 400, and indicates that the data corresponding to the prefetch request will subsequently be in a cache hit state. Issued information PROK with a logical value of 0 indicates that a prefetch request has not been issued to the memory 400, and indicates that the data corresponding to the prefetch request is in a cache miss state.

[0074] The issuance history queue 333A has multiple entries that hold prefetch requests PRREQ1. The issuance history queue 333A is an example of a prefetch request holding unit that holds the prefetch request PRREQ1. As described above, when the issuance history queue 333A receives an erase instruction ERS from the prefetch determination unit 331A, it erases the oldest prefetch request PRREQ1. An example of the update operation of the issuance history queue 333A is described in FIG. 9.

[0075] 9 shows an example of an update operation of the issuance history queue 333A of the prefetch control unit 330A of FIG. 8. In FIG. 9, for ease of explanation, the prefetch request PRREQ0 (LPT-ID) and the prefetch request PRREQ1 are represented by eight-digit numbers. Also, in FIG. 9, the issuance history queue 333A has four entries, and the smaller the entry number, the older the holding time. Although not particularly limited, the issuance history queue 333A may have, for example, 16 or 32 entries.

[0076] (Example 1) shows the operation when the prefetch request PRREQ1 corresponding to the prefetch request PRREQ0(LPT-ID) is not held in the issue history queue 333A and there are free entries. (Example 2) shows the operation when the prefetch request PRREQ1 corresponding to the prefetch request PRREQ0(LPT-ID) is held in the issue history queue 333A and the entries are full. (Example 3) shows the operation when the prefetch request PRREQ1 corresponding to the prefetch request PRREQ0(LPT-ID) is not held in the issue history queue 333A and the entries are full.

[0077] In (Example 1), the address calculation unit 332A issues a prefetch request PRREQ1 corresponding to the prefetch request PRREQ0 (LPT-ID). The FIB control unit 350A issues issued information PROK indicating that the prefetch request PRREQ1 has been issued to the meta table generation unit 322A.

[0078] The prefetch control unit 330A newly registers the prefetch request PRREQ1 (=66667777) corresponding to the prefetch request PRREQ0 (LPT-ID) by storing it in the empty entry 3 of the issue history queue 333A.

[0079] In (Example 2), a prefetch request PRREQ1 (=22223333) corresponding to the prefetch request PRREQ0 (LPT-ID) is held in entry 1 of the issuance history queue 333A. In this case, the address calculation unit 332A suppresses the issuance of the prefetch request PRREQ1 corresponding to the prefetch request PRREQ0 (LPT-ID). The prefetch determination unit 331A issues match information PRMCH.

[0080] The prefetch control unit 330A shifts the prefetch request PRREQ1 (=44445555, 66667777) from entries 2 and 3 to entries 1 and 2. Then, the issue history queue 333A stores the prefetch request PRREQ1 (=22223333) corresponding to the prefetch request PRREQ0 (LPT-ID) in the now-empty entry 3, thereby updating the issue history.

[0081] In (Example 3), the address calculation unit 332A issues a prefetch request PRREQ1 corresponding to the prefetch request PRREQ0 (LPT-ID). The FIB control unit 350A issues issued information PROK indicating that the prefetch request PRREQ1 has been issued to the meta table generation unit 322A.

[0082] Because there are no free entries in the issue history queue 333A, the prefetch control unit 330A expels the oldest prefetch request PRREQ1 (=01234567) held in entry 0 from the issue history queue 333A. Then, the prefetch control unit 330A shifts the prefetch requests PRREQ1 (=44445555, 66667777, 22223333) held in entries 1, 2, and 3 to entries 0, 1, and 2. The issue history queue 333A then stores a new prefetch request PRREQ1 (=88889999) corresponding to the prefetch request PRREQ0 (LPT-ID) in the now-empty entry 0, thereby registering it.

[0083] Fig. 10 shows an example of a metatable MTTBL generated by the metatable generation unit 322A of Fig. 6. The metatable MTTBL is generated for each packet PCKT by the metatable generation unit 322A. Each metatable MTTBL has m+1 entries, including a common part that is independent of the packet protocol and a unique part that differs for each packet protocol. The size of the metatable MTTBL is fixed and does not depend on the packet PCKT.

[0084] For example, the common part includes an entry in which the logical port number LPT-ID is stored and an entry in which the issued information PROK and the match information PRMCH are stored. For example, the specific part has multiple entries in which information is stored for each packet protocol.

[0085] For example, the meta table generation unit 322A extracts, from the packet PCKT, information corresponding to the packet protocol of the packet PCKT received by the virtual switch 310A and converted by the packet conversion unit 321A. Here, the meta table MTTBL generated by the meta table generation unit 322A includes, for example, KEY information corresponding to the packet protocol in at least one of the common part and the unique part.

[0086] The metatable generation unit 322A then stores the extracted information in the metatable MTTBL as metatable information MTINF, thereby generating the metatable MTTBL. At this time, the metatable generation unit 322A stores information specific to the packet protocol in an entry at a predetermined position in the specific part. The metatable generation unit 322A then outputs the generated metatable MTTBL to the FIB control unit 350A. The packet PCKT is transferred to the FIB control unit 350A together with the metatable MTTBL.

[0087] Fig. 11 shows an example of the FIB control unit 350A of Fig. 6. The FIB control unit 350A has a register REG3, an address calculation unit 351A, a request queue 352A, a selector SEL3, arbiters ARB0, ARB1, ARB2, and a match action unit 353A.

[0088] The register REG3 holds the access length LEN and the base address BASE-ADRS when accessing the cache 340 or the memory 400. For example, the access length LEN is set for each packet PCKT based on the metatable information MTINF received from the metatable generation unit 322A.

[0089] The address calculation unit 351A has the same or similar configuration as the address calculation unit 332A shown in Fig. 8, except that the access length LEN is unique for each packet PCKT. The adder ADD of the address calculation unit 351A adds, as an index, the logical port number LPT-ID included in the metatable information MTINF received from the metatable generation unit 322A corresponding to the packet PCKT to the base address BASE-ADRS.

[0090] The address calculation unit 351A issues a memory access request REQ0 of access length LEN including the address obtained by the addition to read FIB information from the cache 340 or memory 400. The memory access request REQ0 includes metatable information MTINF. Note that if the metatable information MTINF received from the metatable generation unit 322A includes issued information PROK or match information PRMCH, the memory access request REQ0 includes the issued information PROK or match information PRMCH.

[0091] The request queue 352A has multiple entries that hold memory access requests REQ0 issued by the address calculation unit 351A. The memory access requests REQ0 include metatable information MTINF. The request queue 352A outputs the memory access requests REQ0 held in the entries to the selector SEL3 as memory access requests REQ1 in the order they were held. The request queue 352A erases the memory access requests REQ0 that it holds, based on FIB information output from the memory 400 in response to a memory access request MREQ corresponding to the memory access request REQ0.

[0092] When the memory access request REQ1 includes issued information PROK=1 or match information PRMCH=1, the selector SEL3 outputs the memory access request REQ1 as a cache read access request CREQR to the cache 340. When the memory access request REQ1 includes issued information PROK=0 and match information PRMCH=0, the selector SEL3 outputs the memory access request REQ1 to the arbiter ARB0 as a memory read access request MREQ0R.

[0093] In this way, the FIB control unit 350A can determine whether the cache 340 is in a cache hit state based on the issued information PROK or the match information PRMCH included in the memory access request REQ1. Then, if the cache 340 is in a cache hit state, the FIB control unit 350A issues a cache read access request CREQR to the cache 340. If the cache 340 is in a cache miss state, the FIB control unit 350A issues a memory read access request MREQ0R to the memory 400. The memory read access request MREQ0R is an example of a read request to the memory 400.

[0094] The arbiter ARB0 arbitrates among a memory read access request MREQ0R, a prefetch request PRREQ1, and a write access request UPDT for update data of FIB information. The arbiter ARB0 generates a memory access request MREQ based on information included in the memory read access request MREQ0R, prefetch request PRREQ1, or write access request UPDT selected through arbitration, and outputs the generated memory access request to the memory 400. The memory access request MREQ includes an address indicating a storage area in the memory 400 that holds the FIB information. The memory access request MREQ is an example of a read request to the memory 400. Furthermore, if the arbiter ARB0 selects the prefetch request PRREQ1 through arbitration, it outputs issued information PROK=1 to the metatable generation unit 322A of FIG. 6.

[0095] The memory access request MREQ generated by the arbiter ARB0 based on the memory read access request MREQ0R or the prefetch request PRREQ1 is an example of a read request to read FIB information from the memory 400. The memory access request MREQ generated by the arbiter ARB0 based on the write access request UPDT is an example of a write request to write FIB information to the memory 400.

[0096] The arbiter ARB1 arbitrates between the FIB information included in the write access request UPDT and the FIB information read from the memory 400. The arbiter ARB1 generates a cache write access request CREQW for writing the FIB information selected through arbitration into the cache 340, and outputs the request to the cache 340. The cache write access request CREQW is an example of a write request for writing into the cache 340 the FIB information included in the write access request UPDT or the FIB information read from the memory 400.

[0097] The arbiters ARB0 and ARB1 are an example of a storage control unit that, when a write access request UPDT including FIB information is received from the virtual switch 310A, stores the FIB information in the memory 400 and also in the cache 340. By storing the FIB information (update data or newly registered data) to be stored in the memory 400 in the cache 340 as well, the corresponding FIB information can be set to a hit state in advance. This can reduce the latency required for the FIB control unit 350A to acquire the FIB information.

[0098] The arbiter ARB2 arbitrates between the FIB information read from the memory 400 and the FIB information read from the cache 340. The arbiter ARB2 outputs one of the FIB information selected by arbitration to the match action unit 353A.

[0099] The match action unit 353A compares the KEY information included in the metatable MTTBL corresponding to the packet PCKT received by the FIB control unit 350A with the KEY information included in the FIB information read from the cache 340 or the memory 400. Here, the comparison of the KEY information is performed, for example, on predetermined KEY information corresponding to the packet protocol included in the metatable MTTBL. The match action unit 353A compares the KEY information to determine whether the FIB information included in the packet PCKT is correct.

[0100] If the KEY information matches, the match action unit 353A determines that the packet PCKT is valid and performs operations such as generating a packet header in accordance with the ACTION information included in the FIB information.The match action unit 353A then transfers the packet PCKT including the generated packet header to the transfer destination.Note that if the KEY information does not match, the match action unit 353A suppresses the transfer of the packet PCKT.

[0101] Fig. 12 shows an example of the operation of the relay control unit 320A of Fig. 6. That is, Fig. 12 shows an example of a control method of the switch device 300A. The operation shown in Fig. 12 corresponds to (Example 1) of Fig. 9, and shows the operation when the prefetch request PRREQ0(LPT-ID)=66667777 is not held in the issuance history queue 333A and there is a free entry.

[0102] The prefetch control unit 330A references the past prefetch request PRREQ1 held in the issue history queue 333A and determines a cache miss for the prefetch request PRREQ0=66667777. Because there is a free entry in the issue history queue 333A, the prefetch control unit 330A stores the prefetch request PRREQ0=66667777 in the entry. Then, the prefetch control unit 330A stores the issued information PROK in the meta table generation unit 322A via the FIB control unit 350A.

[0103] The issued information PROK is stored in a metatable MTTBL generated by the metatable generation unit 322A based on the packet PCKT corresponding to the prefetch request PRREQ0=66667777. The metatable generation unit 322A outputs the generated metatable MTTBL (including the issued information PROK) to the FIB control unit 350A. The FIB control unit 350A outputs a cache read access request CREQR to the cache 340 based on the metatable MTTBL including the issued information PROK.

[0104] The arbiter ARB0 selects the prefetch request PRREQ1 through arbitration and outputs it to the memory 400 as a memory access request MREQ. The memory 400 outputs FIB information as a response RSP to the memory access request MREQ. The arbiter ARB1 selects FIB information read from the memory 400 through arbitration and writes the selected FIB information to the cache 340. As a result, the FIB information corresponding to the packet PCKT received by the relay control unit 320A is written to the cache 340.

[0105] In reality, the prefetch control unit 330A outputs a plurality of prefetch requests PRREQ1 (memory access requests MREQ) to the memory 400, and a plurality of pieces of FIB information corresponding to a plurality of responses RSP from the memory 400 are stored in the cache 340. Also, a plurality of prefetch requests PRREQ0 (LPT-ID) corresponding to a plurality of prefetch requests PRREQ1 are stored in the issue history queue 333A.

[0106] Here, the time taken for the relay control unit 320A to receive the packet PCKT and then output the cache read access request CREQR is longer than the time taken for the relay control unit 320A to receive the packet PCKT and then output the cache write access request CREQW. In other words, the FIB information read from the memory 400 corresponding to the received packet is written to the cache 340 before the cache read access request CREQR is output to the cache 340. Then, the cache 340 outputs the KEY information and ACTION information included in the FIB information corresponding to the cache read access request CREQR.

[0107] Fig. 13 shows another example of the operation of the relay control unit 320A of Fig. 6. That is, Fig. 13 shows an example of a control method of the switch device 300A. The operation shown in Fig. 13 corresponds to (Example 2) of Fig. 9, and shows the operation when the prefetch request PRREQ0(LPT-ID)=22223333 is held in the issuance history queue 333A and the entries are full.

[0108] The prefetch control unit 330A references the past prefetch request PRREQ1 held in the issuance history queue 333A to determine the cache hit status of the prefetch request PRREQ0=22223333. The prefetch control unit 330A moves the prefetch request PRREQ1=22223333 from entry 1 to entry 3 of the issuance history queue 333A. Then, the prefetch control unit 330A stores the match information PRMCH in the meta table generation unit 322A via the FIB control unit 350A.

[0109] The match information PRMCH is stored in a metatable MTTBL generated by the metatable generation unit 322A based on the packet PCKT corresponding to the prefetch request PRREQ0=22223333. The metatable generation unit 322A outputs the generated metatable MTTBL (including the match information PRMCH) to the FIB control unit 350A. The FIB control unit 350A outputs a cache read access request CREQR to the cache 340 based on the metatable MTTBL including the match information PRMCH.

[0110] Then, the cache 340 outputs the KEY information and ACTION information included in the FIB information corresponding to the cache read access request CREQR. Note that, since the FIB information corresponding to the packet PCKT received by the relay control unit 320A is already held in the cache 340 (cache hit state), the memory access request MREQ is not output to the memory 400.

[0111] As described above, this embodiment can also achieve the same effects as the above-described embodiment. For example, the prefetch control unit 330A prefetches other FIB information from the memory 400 in addition to the FIB information corresponding to the received packet PCKT and stores it in the cache 340. This reduces the frequency with which the cache 340 experiences a cache miss when the FIB control unit 350A determines a forwarding path for the packet PCKT. Since the hit rate of the cache 340 can be improved, the latency required for the FIB control unit 350A to acquire FIB information can be reduced, and a decrease in the relay performance of the packet PCKT by the switching device 300A can be suppressed.

[0112] Furthermore, in this embodiment, if a prefetch request PRREQ1 corresponding to the received prefetch request PRREQ0 is held in the issuance history queue 333A, the prefetch control unit 330A suppresses issuance of the prefetch request PRREQ1 to the memory 400. This makes it possible to suppress unnecessary arbitration operations by the arbiter ARB0 and to prevent unnecessary access to the memory 400 and the cache 340. As a result, it is possible to improve the efficiency with which the FIB control unit 350A acquires FIB information and shorten the latency required to acquire the FIB.

[0113] The prefetch control unit 330A can determine whether the FIB information corresponding to the received packet PCKT is in a cache hit state or a cache miss state, based on the prefetch request PRREQ1 held in the issuance history queue 333A.

[0114] If the prefetch request PRREQ1 corresponding to the received prefetch request PRREQ0 is held in the issue history queue 333A, the prefetch control unit 330A stores match information PRMCH=1 in the metatable MTTBL. If the FIB control unit 350A selects the prefetch request PRREQ1 output by the prefetch control unit 330A using the arbiter ARB0, the FIB control unit 350A stores issued information PROK=1 in the metatable MTTBL.

[0115] As a result, the FIB control unit 350A can determine whether there is a cache hit or a cache miss in the cache 340 by referring to the metatable information MTINF held in the metatable MTTBL. Then, based on the determination result, the FIB control unit 350A can issue a cache read access request CREQR to the cache 340 or a memory read access request MREQ0R to the memory 400. In other words, reading of FIB information from the memory 400 can be performed by both the prefetch control unit 330A and the FIB control unit 350A.

[0116] By storing the FIB information (update data or newly registered data) stored in the memory 400 in the cache 340 as well, the corresponding FIB information can be set to a hit state in advance. This further reduces the latency required for the FIB control unit 350A to acquire the FIB information.

[0117] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0118] 100, 100A Server 200, 200A CPU 210 virtual machines 300, 300A switch device 310, 310A Virtual Switch 320 Transfer control circuit 321A Packet Conversion Unit 322A Metatable Generation Unit 320A Relay control unit 330, 330A Prefetch control section 331A Prefetch decision unit 332A Address Calculation Unit 333A Issue History Queue 340 Cash 350 Route control unit 351A Address Calculation Unit 352A Request Queue 353A Match Action Section 350A FIB control unit 400 memory ADD adder ARB0, ARB1, ARB2 arbiters CREQR cache read access request CREQW Cache write access request ERS erasure instruction LEN Access length LPT-ID Logical port number MREQ Memory access request MREQ0R Memory read access request MTINF metatable information PCKT packet PRMCH Match Information PROK Issued Information PRREQ0, PRREQ1 Prefetch request REG0, REG1, REG2, REG3 registers REQ0, REQ1 Memory access request SEL1, SEL2, SEL3 selectors UPDT Write Access Request

Claims

1. A switch device in which at least a part of a packet forwarding control function is offloaded from a virtual switch to a forwarding control circuit, The transfer control circuit a cache that holds at least one piece of packet forwarding route information held in a memory; a route control unit that determines a transfer route for a received packet using the transfer route information stored in the cache; a prefetch control unit that, when transfer path information corresponding to a received packet is not held in the cache, reads out a plurality of pieces of transfer path information including the corresponding transfer path information from the memory and stores the read information in the cache; A switch device having:

2. The prefetch control unit a request generation unit that generates a prefetch request to read the plurality of pieces of transfer path information from the memory and issues the request to the memory; a prefetch request holding unit that holds the prefetch request generated by the request generating unit; an issuance inhibiting unit that inhibits issuance of a corresponding read request to the memory when a read request corresponding to transfer path information corresponding to the received packet is held in the prefetch request holding unit; The switch device according to claim 1 , further comprising:

3. The transfer control circuit an identification information generation unit that generates packet identification information for identifying a received packet; a meta table generating unit that generates, for each packet, a meta table including information to be used in the route control unit among information included in the received packet and the packet identification information; The prefetch control unit stores, in a meta table corresponding to the read request held in the prefetch request holding unit, holding information indicating that the corresponding transfer path information is held in the cache. The switch device according to claim 2 .

4. The route control unit determining a storage area of ​​the cache in which transfer path information of the received packet is held, based on the packet identification information included in the meta table corresponding to the received packet; If the held information is stored in a meta table corresponding to the received packet, a read request is issued to the cache to read the transfer path information from the determined storage area of ​​the cache; If the retained information is not stored in the meta table corresponding to the received packet, a read request is issued to the memory to read from the memory the transfer path information corresponding to the received packet, and the transfer path information read from the memory is stored in the cache. The switch device according to claim 3 .

5. when the prefetch control unit issues a read request to the memory, it stores issued information indicating that the read request has been issued to the memory in the meta table; The route control unit If the issued information is stored in the meta table corresponding to the received packet, a read request is issued to the cache to read the transfer path information from the storage area of ​​the determined cache. The switch device according to claim 4.

6. The route control unit 6. A switch device according to claim 1, further comprising a storage control unit that, when receiving update data for forwarding path information held in the memory from the virtual switch, stores the received update data in the memory and also stores it in the cache.

7. A control method for a switch device in which at least a part of a packet forwarding control function is offloaded from a virtual switch to a forwarding control circuit, comprising: The transfer control circuit determining a transfer route for the received packet using transfer route information held in a cache that holds at least any of the transfer route information for the packet held in the memory; If transfer path information corresponding to the received packet is not held in the cache, a plurality of pieces of transfer path information including the corresponding transfer path information are read from the memory and stored in the cache. A method for controlling a switch device.

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