Electro-optical device and electronic device

Abstract

To provide an electro-optical device of demultiplexing drive type characteristic of high definition realized without increasing the number of control signal input terminals and the number of video signal outputs.SOLUTION: An electro-optical device 1 includes a pixel region 110 having pixel circuits arranged at respective intersections between scan lines and K data lines, a data line drive circuit 140A, and an input terminal group 160. The data line drive circuit 140A includes a demultiplexer having K sample switches that select data lines, which are feed destinations of a video signal, according to a series of K selection signals, and is interposed between the pixel region 110 and input terminal group 160. The data line drive circuit 140A includes a circuit block that generates the series of K selection signals on the basis of J control signals. Video data lines to be connected to a video input terminal and the respective sample switches are interposed between the circuit block and a circuit block adjoining the circuit block. K denotes an integer equal to or larger than 2, and J denotes an integer smaller than K.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an electro-optical device and an electronic device. [Background technology]

[0002] An electro-optical device that displays an image using liquid crystal elements supplies a video voltage based on an image signal that specifies the gradation of each pixel to a pixel circuit corresponding to each pixel via a data line, thereby controlling the transmittance of the liquid crystal in each pixel circuit to the transmittance based on the video voltage. As a result, the gradation of each pixel is set to the gradation specified by the image signal. Patent Document 1 discloses an electro-optical device using a demultiplex drive system. Patent Document 2 discloses an electro-optical device using a phase expansion drive system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-185415 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-242160 Summary of the Invention [Problem to be solved by the invention]

[0004] The demultiplex drive method requires a larger number of video output signals than the phase expansion drive method, and increasing the number of video signal outputs to accommodate higher resolution increases the power consumption of the video output amplifier. Limiting the video output amplifier's capacity to reduce its power consumption makes high-speed drive difficult. Increasing the number of selection signals externally applied for selecting a series is one way to accommodate higher resolution without increasing the number of video signal outputs in the demultiplex drive method. However, increasing the number of selection signals poses the challenges of increasing the panel size in response to an increase in the number of input terminals for the selection signals, and of requiring high-speed drive of the selection signals. [Means for solving the problem]

[0005] In order to solve the above problems, one aspect of the electro-optical device of the present disclosure includes a first substrate having a pixel region in which pixel circuits are provided at each intersection of a scanning line and K data lines divided into K series, and an input terminal group arranged along one side of the pixel region, the input terminal group including a video input terminal to which a video signal obtained by time-division multiplexing data voltages of each series is input and an input terminal to which a control signal is input, the electro-optical device further includes a demultiplexer having K sample switches that selects a data line to which the video signal is to be supplied in response to a K series selection signal, and a data line drive circuit arranged between the pixel region and the input terminal group, the data line drive circuit including a circuit block that generates the K series selection signal, and video data lines arranged between the circuit block and a circuit block adjacent to the circuit block, the video input terminal and the K sample switches, where K is an integer equal to or greater than 2, and J is an integer smaller than K. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a block diagram showing a configuration of an electro-optical device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a block diagram showing the configuration of a panel substrate. [Figure 3] FIG. 2 is a diagram illustrating a configuration example of a selection circuit. [Figure 4] 3A and 3B are explanatory diagrams of the configuration of a selection signal generation circuit and operations in a test mode and a normal mode. [Figure 5] FIG. 2 is an explanatory diagram of wiring on a flexible substrate. [Figure 6] FIG. 10 is a block diagram showing a configuration of an electro-optical device according to a second embodiment of the present disclosure. [Figure 7] FIG. 2 is a diagram illustrating a configuration example of a selection circuit. [Figure 8] FIG. 2 is an explanatory diagram of a configuration of a selection signal generation circuit. [Figure 9] FIG. 2 is an explanatory diagram of a code decoded by a decoder circuit. [Figure 10] FIG. 10 is an explanatory diagram of an example of the operation of a decoder circuit. [Figure 11] FIG. 10 is an explanatory diagram of an example of the operation of a decoder circuit. [Figure 12] FIG. 1 is an explanatory diagram illustrating an example of an electronic device. [Figure 13] FIG. 10 is an explanatory diagram showing another example of an electronic device. [Figure 14] FIG. 10 is an explanatory diagram showing another example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Various technically preferable limitations are applied to the embodiments described below. However, the embodiments of the present disclosure are not limited to the forms described below.

[0008] First Embodiment FIG. 1 is an explanatory diagram of an electro-optical device 1 according to a first embodiment of the present disclosure. The electro-optical device 1 is an electro-optical device having a demultiplexer. The electro-optical device 1 has a panel substrate 100A, a drive substrate 200, and a flexible substrate 300. The flexible substrate 300 is connected to the panel substrate 100A and the drive substrate 200. The panel substrate 100A is connected to a host CPU (Central Processing Unit) device (not shown) via the flexible substrate 300 and the drive substrate 200.

[0009] The drive substrate 200 is provided with a video signal output circuit 210A and a video signal output circuit 210B, such as a driver IC (Integrated Circuit). The video signal output circuit 210A and the video signal output circuit 210B receive image signals and various control signals for drive control from a host CPU device (not shown) and drive each circuit of the panel substrate 100A via the flexible substrate 300. The number of video signal outputs of each of the video signal output circuits 210A and 210B is equivalent to the number of video signal outputs of a video signal output circuit in a general electro-optical device using a phase expansion drive system. Specifically, each of the video signal output circuits 210A and 210B outputs 48 video signals. Hereinafter, when there is no need to distinguish between the video signal output circuits 210A and 210B, they will be referred to as the video signal output circuit 210. Since the number of video signal outputs per video signal output circuit 210 is equivalent to that of a video signal output circuit in a general electro-optical device using a phase-expansion drive system, a high-performance amplifier can be used for each video signal output. For example, the video signal output circuit 210 may be configured using an amplifier capable of writing in approximately 30 nsec to 40 sec. In this embodiment, two video signal output circuits 210 drive each circuit on the panel substrate 100A, but one video signal output circuit 210 may also drive each circuit on the panel substrate 100A.

[0010] As shown in FIG. 1, the panel substrate 100A has a pixel region 110, a scanning line driving circuit 130, a data line driving circuit 140A, a precharge circuit 150, and an input terminal group 160. FIG. 2 is a block diagram showing an example of the configuration of the panel substrate 100A. Note that the input terminal group 160 is not shown in FIG. 2. As shown in FIG. 2, N scanning lines 120, M data lines 122, and N×M pixel circuits PX are arranged in the pixel region 110. Note that N and M are both integers equal to or greater than 2. In this embodiment, N is 1080 and M is 1920 (20×48×2). In other words, the resolution of the electro-optical device 1 is FHD. The M data lines 122 are, for example, classified into a data line group including K data lines 122. Note that K is an integer equal to or greater than 2. In the example shown in FIG. 2, K is 20. Note that K is not limited to 20 as long as it is an integer equal to or greater than 2. Furthermore, the total number of data lines 122 is not limited to 1920. For example, the total number of data lines 122 may be K. In this case, the number of data line groups is 1. The panel substrate 100A is an example of a first substrate in the present disclosure, and the drive substrate 200 is an example of a second substrate in the present disclosure.

[0011] The 1,920 data lines 122 are classified into 96 data line groups, each including 20 data lines 122. Of these 96 data line groups, the left 48 data line groups receive video signals output from the video signal output circuit 210A, and the right 48 data line groups receive video signals output from the video signal output circuit 210B. The region in which pixel circuits PX corresponding to the data line groups to which video signals are supplied from the video signal output circuit 210A are arranged is an example of a first pixel region in the present disclosure. Furthermore, the region in which pixel circuits PX corresponding to the data line groups to which video signals are supplied from the video signal output circuit 210B are arranged is an example of a second pixel region that shares the scanning lines 120 with the first pixel region. Furthermore, the video signal output circuit 210A is an example of a first video signal output circuit in the present disclosure, and the video signal output circuit 210B is an example of a second video signal output circuit in the present disclosure.

[0012] A scanning signal G is supplied to each of the N scanning lines 120, and an image signal S or a precharge signal is supplied to the data lines 122. The number at the end of the symbol for the scanning signal G corresponds to the row number. The number at the end of the symbol for the image signal S and the sample switch SWv (described later) corresponds to the column number.

[0013] Each of the N×M pixel circuits PX is arranged corresponding to an intersection between the N scanning lines 120 and the M data lines 122. In the example shown in FIG. 2, the pixel circuits PX are arranged in a matrix of 1080 rows and 1920 columns. The number of pixel circuits PX is not limited to the example shown in FIG. 2. In FIG. 2, the row of the pixel circuit PX shown at the top of the drawing is referred to as the first row, and the column of the pixel circuit PX shown at the leftmost side of the drawing is referred to as the first column. In the following, the scanning line 120 connected to the pixel circuit PX in the nth row will also be referred to as the nth scanning line 120, and the data line 122 connected to the pixel circuit PX in the mth column will also be referred to as the mth data line 122. In the example shown in FIG. 2, n is an integer greater than or equal to 1 and less than or equal to 1080, and m is an integer greater than or equal to 1 and less than or equal to 1920.

[0014] As shown in FIG. 1 , input terminal group 160 is arranged along one side of pixel region 110 in the row direction, and flexible substrate 300 is connected to input terminal group 160. Input terminal group 160 includes video input terminals equal to the number of data line groups and an input terminal for a control signal for selecting a group. A video signal obtained by time-division multiplexing the data voltages of each group included in the corresponding data line group is input to the video input terminal. The video input terminal to which the video signal is supplied from video signal output circuit 210A is an example of a first video input terminal in the present disclosure, and the video input terminal to which the video signal is supplied from video signal output circuit 210B is an example of a second video input terminal in the present disclosure.

[0015] As shown in FIG. 1, the data line driving circuit 140A is disposed between the pixel region 110 and the input terminal group 160. During a horizontal scanning period, the data line driving circuit 140A sequentially supplies an image signal S to each of the 20 data lines 122 included in each data line group during 20 supply periods based on 20 selection signals SEL1 to SEL20 that sequentially select the 20 data lines 122. Hereinafter, when there is no need to distinguish between the selection signals SEL1 to SEL20, they will be referred to as selection signal SEL. The horizontal scanning period is a period during which a video voltage based on the image signal S supplied to the data lines 122 of each column is written to one row of pixel circuits PX.

[0016] The row to be written is selected by a scanning signal G supplied from a scanning line driving circuit 130 to the scanning line 120. The scanning line driving circuit 130 is not particularly different from the scanning line driving circuit in a conventional electro-optical device using a demultiplex driving method, and therefore a detailed description thereof will be omitted. The precharge circuit 150 supplies a precharge signal to all K data lines 122 during the horizontal scanning period prior to the supply of an image signal S. As a result, the data lines 122 before the supply of the image signal S are charged to a predetermined precharge voltage based on the precharge signal. The precharge circuit 150 is not particularly different from the precharge circuit in a conventional electro-optical device using a phase-expansion driving method, and therefore a detailed description thereof will be omitted.

[0017] As shown in FIG. 1, the data line driving circuit 140A is disposed between the pixel region 110 and the input terminal group 160. As shown in FIG. 2, the data line driving circuit 140A has selection circuits A1 to A8, one for each of the 12 video data lines VID. The selection circuits A1 to A8 have the same configuration. Therefore, FIG. 2 illustrates only the specific configuration of the selection circuit A1. When it is not necessary to distinguish between the selection circuits A1 to A8, they are referred to as selection circuit A. The selection circuit A includes 12 demultiplexers DM1 to DM12, one for each of the 12 corresponding data line groups, and a selection signal generation circuit 1410A. Each of the demultiplexers DM1 to DM12 included in the selection circuit A is connected to a video data line VID to which a video signal obtained by time-division multiplexing a video voltage to be supplied to the data lines 122 included in the corresponding data line group is applied. In FIG. 2, the wiring of the video data line VID is shown in a simplified manner only with respect to the demultiplexer DM1.

[0018] Each of the demultiplexers DM1 to DM12 includes K sample switches SWv that select data lines 122 to which video signals are to be supplied in response to K selection signals SEL. The sample switches SWv are, for example, N-channel transistors formed of thin film transistors (TFTs). The sample switches SWv are set to either a conductive state or a non-conductive state in response to the level of the selection signal SEL received at a control terminal such as a gate. The sample switches SWv may be P-channel transistors or switching elements other than TFTs. As shown in FIG. 2, the selection circuit A has a group selection signal line group 1420 consisting of 20 signal lines to which the selection signals SEL1 to SEL20 are respectively supplied. The group selection signal line group 1420 is wired in the selection circuit A along the row direction of the pixel region 110.

[0019] The selection signal generation circuit 1410A generates K sequences of selection signals SEL based on J control signals provided from the video signal output circuit 210 via the flexible substrate 300. J is an integer smaller than K, and in this embodiment, J is 9. The selection signal generation circuit 1410A is an example of a circuit block in the present disclosure. Also, a demultiplexer corresponding to a group of data lines to which the video signals output from the video signal output circuit 240A are provided is an example of a first demultiplexer in the present disclosure, and the selection signal generation circuit 1410A corresponding to the first demultiplexer is an example of a first circuit block in the present disclosure. Also, a demultiplexer corresponding to a group of data lines to which the video signals output from the video signal output circuit 240B are provided is an example of a second demultiplexer in the present disclosure, and the selection signal generation circuit 1410A corresponding to the second demultiplexer is an example of a second circuit block in the present disclosure.

[0020] In this embodiment, the selection signal generation circuit 1410A generates the selection signals SEL1 to SEL20 based on the control signals ENBX2B, ENBX1B, ENBX2, ENBX1, TEST, CLKX, CLKXB, DIRX, and DX. For example, the control signal ENBX2 and the control signal ENBX1 are output enable signals. The control signal ENBX2B is an inverted signal obtained by logically inverting the control signal ENBX2, and the control signal ENBX1B is an inverted signal obtained by logically inverting the control signal ENBX1. The control signal TEST is a test signal that instructs the execution of a test on the data line driving circuit 140A. The control signal CLKX is a clock signal, and the control signal CLKXB is a signal obtained by logically inverting the control signal CLKX. The control signal DIRX is a scanning direction instruction signal. The control signal DX is a start pulse signal. The control signal ENBX2 and the control signal ENBX1 are examples of first signals in the present disclosure, and the control signals ENBX2B and ENBX1B are examples of second signals in the present disclosure.

[0021] FIG. 3 is an explanatory diagram of an example of the wiring of the video data line VID for the selection circuit A, the control signal line group 1430 to which various control signals are input, and the power supply line that supplies an operating voltage to the selection signal generation circuit 1410A. As shown in FIG. 3, the video data line VID is arranged along the outer edge of the selection signal generation circuit 1410A of the selection circuit A, in other words, so as to pass between the selection signal generation circuit 1410A and the selection signal generation circuit 1410A adjacent to that selection signal generation circuit 1410A. The video data line VID is arranged to pass between the selection signal generation circuits 1410A of adjacent selection circuits A in order to route the video data line VID from the video input terminal included in the input terminal group 160 to the demultiplexer in the shortest possible distance without making any unnecessary detours. The high-potential power supply line PVDDX and the low-potential power supply line PVSSX that supply an operating voltage to the selection signal generation circuit 1410A are arranged along one side in the row direction of the pixel region 110. A potential VSSX, which is the ground potential, is applied to the low-potential power supply line PVSSX from a power supply circuit (not shown). The potential VSSX is a non-selection potential of the sample switch SWv. A potential VDDX is applied to the high-potential power supply line PVDDX from a power supply circuit (not shown). The potential VDDX is a higher potential than the potential VSSX and is a selection potential of the sample switch SWv. The high-potential power supply line PVDDX and the low-potential power supply line PVSSX are examples of high-potential and low-potential power supply lines in this disclosure.

[0022] When the high-potential power supply line PVDDX and the low-potential power supply line PVSSX are arranged along one side of the pixel region 110 in the row direction, the input terminal group 160 is also arranged along one side of the pixel region 110 in the row direction, and the data line driving circuit 140A is arranged between the pixel region 110 and the input terminal group 160, if the video data line VID is routed as short a distance as possible, the high-potential power supply line PVDDX and the low-potential power supply line PVSSX will intersect with the video data line VID. As shown in FIG. 3 , the intersections of the high-potential power supply line PVDDX and the low-potential power supply line PVSSX with the video data line VID are thinner than other intersections. Because the intersections of the high-potential power supply line PVDDX and the low-potential power supply line PVSSX with the video data line VID are thinner than other intersections, superposition of power supply noise on the video signal when driving the selection signal generating circuit 1410A is suppressed, thereby achieving high-quality display. In other words, in this embodiment, a high-quality display can be achieved even if the video data line VID crosses the high-potential power supply line PVDDX and the low-potential power supply line PVSSX, so the video data line VID can be wired as short as possible. Therefore, the wiring resistance and drive load of the video data line VID are smaller than those of conventional electro-optical devices using a phase-expansion drive method, making it suitable for high-speed driving.

[0023] As shown in FIG. 3, the video data line VID also intersects with the control signal line group 1430. The control signals supplied to the control signal line group 1430 include the control signal ENBX2B and the control signal ENBX1B, which are not used to generate the selection signals SEL1 to SEL20, as will be described in detail later. In this embodiment, by intersecting the control signal lines carrying the unnecessary control signals ENBX2B and ENBX1B with the video data line VID, noise superimposed on the video signal from the positive and negative phase signals is canceled out, thereby realizing a high-quality display. In other words, in this embodiment, a high-quality display can be realized even when the video data line VID intersects with the control signal line group 1430, so that the video data can be routed over as short a distance as possible. Of the control signal lines included in the control signal line group 1430, the control signal line to which the control signal ENBX2 is input and the control signal line to which the control signal ENBX1 is input are examples of first signal lines in the present disclosure. Furthermore, among the control signal lines included in the control signal line group 1430, the control signal line to which the control signal ENBX2B is input and the control signal line to which the control signal ENBX1B is input are examples of second signal lines in the present disclosure. Note that this does not prohibit the use of the control signal ENBX2B and the control signal ENBX1B for generating the selection signals SEL1 to SEL20. In addition, an embodiment may be adopted in which the intersections of the signal wiring included in the control signal line group 1430 and the video data lines VID are thinner than other portions.

[0024] FIG. 4 is an explanatory diagram of the configuration of the selection signal generation circuit 1410A and its operation in the test mode and normal mode. The selection signal generation circuit 1410A includes a shift register and a buffer circuit that are sequentially selected and driven by control signals DX, CLKX, and CLKXB. In FIG. 4, the shift register is labeled S / R, and the buffer circuit is labeled BUF. The data line driving circuit 140A includes eight selection signal generation circuits 1410A. The selection signal generation circuit 1410A includes one shift register. Therefore, the data line driving circuit 140A includes eight shift registers. For the sake of explanation, only three of the eight shift registers are shown in FIG. 4. In FIG. 4, the symbol I / O_R indicates the input node of the shift register, and the symbol I / O_L indicates the output node of the shift register. Furthermore, the selection signal generation circuit 1410A has 20 buffer circuits for each shift register, but for the sake of explanation, only four of the 20 buffer circuits are shown in FIG. 4. Specifically, only four buffer circuits corresponding to the selection signals SEL1, SEL2, SEL3, and SEL20 are shown in the figure. The buffer circuits are composed of a logical product circuit of the control signal ENBX2 or ENBX1 and the output signal of each stage of the shift register, and a group of multi-stage inverters that input the output signal of the logical product circuit.

[0025] Each of the eight shift registers included in the data line driving circuit 140A has 20 output stages. The shift direction of the shift registers can be switched by a control signal DIRX. As shown in FIG. 3, the video data lines VID are routed to pass on both sides of the shift registers in the selection signal generation circuit 1410A. This arrangement minimizes the differences in wiring resistance and parasitic capacitance among the 12 video data lines VID, thereby suppressing display irregularities. The 12 video data lines VID can also be arranged together on one side of the shift registers. However, this arrangement can increase the differences in wiring resistance and parasitic capacitance between, for example, the video data line VID corresponding to the demultiplexer DM12 in the selection circuit A1 and the video data line VID corresponding to the demultiplexer DM1 in the selection circuit A2, potentially resulting in display defects such as unevenness at block boundaries.

[0026] The buffer circuits receive the output signal of the corresponding shift register and the control signal ENBX1 or ENBX2. For example, the buffer circuits in odd-numbered columns receive the output signal of the corresponding shift register and the control signal ENBX1, and output the logical product of both signals as the odd-numbered series of selection signals SEL. The buffer circuits in even-numbered columns receive the output signal of the corresponding shift register and the control signal ENBX2, and output the logical product of both signals as the even-numbered series of selection signals SEL. The use of two systems of control signals ENBX1 and ENBX2 is intended to ensure reliable waveform shaping while taking signal distortion into consideration. As described above, in this embodiment, the control signal ENBX1 or the control signal ENBX2 is used to generate the selection signal SEL, but the control signals ENBX1B and ENBX2B are not used. The selection signal generation circuit 1410A may be configured similarly to a data line driving circuit in a conventional electro-optical device using a phase-expansion driving method, with a reduced number of shift register stages.

[0027] The shift registers of all the selection signal generation circuits 1410A included in the data line driving circuit 140A are connected in series via series-connection switches. Of these series-connection switches, only switches SW1A and SW2A are shown in FIG. 4. The input terminals of each shift register are connected to a control signal line through which a control signal DX is supplied via a path-switching switch. Of these path-switching switches, only switches SW1B and SW2B are shown in FIG. 4. Since the control signal DX is always input to the first-stage shift register connected in series via the series-connection switches, no path-switching switch is provided for the first-stage shift register. The output terminal of the final-stage shift register is connected via switch SW3A to a buffer circuit that stores an end pulse EP. The input terminal of this buffer circuit is connected to the low-potential power supply line PVSSX via switch SW3B.

[0028] The data line driving circuit 140A operates in one of two operating modes: a test mode and a normal driving mode, by exclusively turning on or off the series-connection switch and switch SW3A and the path-switching switch and switch SW3B in response to the control signal TEST. The series-connection switch and switch SW3A and the path-switching switch and switch SW3B are examples of switches in the present disclosure. Note that in FIG. 4, the connections between the control signal TEST and the series-connection switch, switch SW3A, path-switching switch, and switch SW3B are abbreviated, but in detail, each switch may be configured, for example, as a CMOS switch. The gate electrodes of the N-channel transistors of the series-connection switch and switch SW3A are connected to a control signal line to which the control signal TEST is applied, and the gate electrodes of the P-channel transistors are connected to a control signal line to which the inverted signal of the control signal TEST is applied. Meanwhile, the gate electrodes of the P-channel transistors of the path-switching switch and switch SW3B are connected to a control signal line to which the control signal TEST is applied, and the gate electrodes of the N-channel transistors are connected to a control signal line to which the inverted signal of the control signal TEST is applied. An inverted signal of the control signal TEST can be easily generated from the control signal TEST using an inverter (not shown). In this way, when the control signal TEST is at H level, the series connection switch and switch SW3A are turned on and the path switching switch and switch SW3B are turned off, resulting in the test mode. On the other hand, when the control signal TEST is at L level, the series connection switch and switch SW3A are turned off and the path switching switch and switch SW3B are turned on, resulting in the normal drive mode. Therefore, the signal supply path in the data line drive circuit 140A differs between the test mode and the normal drive mode.

[0029] In test mode, all shift registers included in the data line driving circuit 140A are connected in series, so if each shift register is normal, an end pulse EP is output from the buffer circuit connected to the final-stage shift register when a control signal DX is input to the data line driving circuit 140A. In other words, it is easy to test all shift registers included in the data line driving circuit 140A. The buffer circuit that outputs the end pulse EP is stationary in normal driving mode, so power consumption is reduced.

[0030] The data line driving circuit 140A is divided into eight selection circuits A1 to A8, and a selection signal SEL is generated in each of the selection circuits A1 to A8. Because the group selection signal line group 1420 is provided in the selection circuit A, the wiring length of the group selection signal line group 1420 in one selection circuit A is 1 / 8 of that in a conventional demultiplex driving electro-optical device with 20 groups without dividing the data line driving circuit. Furthermore, the number of sample switches SWv connected to one group selection signal line in one selection circuit A is 12, whereas the number of sample switches connected to one group selection signal line in a conventional demultiplex driving electro-optical device is 96. Therefore, the number of sample switches connected to one group selection signal line is 1 / 8. According to this embodiment, the wiring resistance is reduced by the shorter wiring length of the group selection signal lines compared to a conventional demultiplex driving electro-optical device. Furthermore, the number of switches connected to one group selection signal line is reduced, resulting in a smaller drive load and a smaller time constant. Therefore, high-speed driving of the sample switch can be achieved by the buffer circuit. The margin created by the smaller time constant can be used to increase the channel width of the sample switch, thereby improving the ability to write to the data line.

[0031] The generation of various control signals for driving the shift register can be achieved by making minor modifications to a conventional phase-expansion driving IC. This is because the shift register included in the selection circuit A according to the present invention is essentially a scaled-down version of the shift register used in a conventional phase-expansion driving electro-optical device. Although the transmission order of the video signals differs, this can be accommodated by changing the output order of the video signals stored in the storage means. In other words, the video signal output circuit 210 can be configured by making minor modifications to a conventional phase-expansion driving IC. As described above, according to this embodiment, the same driving IC can be used to support both the phase-expansion driving method and the demultiplexing driving method, enabling flexible selection of the driving method according to the application and reducing the development and manufacturing costs of the electro-optical device. For example, for electro-optical devices with resolutions below FHD, the conventional phase-expansion driving method can be selected because flexible substrates can be manufactured at low cost. For electro-optical devices with resolutions above FHD, the driving configuration of the present invention, which is suitable for high-speed driving, can be selected. When the number of pixels increases, heat dissipation becomes an issue with the COF mounting used in conventional electro-optical devices using the demultiplex drive method. However, with the configuration of the present disclosure, the video signal output circuit 210 is located on a drive substrate 200 separate from the panel substrate 100A, making it easier to deal with heat.

[0032] 5 is a diagram showing an example of wiring in flexible substrate 300. As shown in FIG. 5, flexible substrate 300 is provided with a group of power lines including a common power line, a plurality of video data lines VID for supplying video signals to panel substrate 100A, and a group of control signal lines for supplying various control signals to panel substrate 100A, which are arranged along edge 300a of flexible substrate 300 on the panel substrate 100A side. FIG. 5 shows characteristic elements of the wiring arrangement by extracting the panel substrate 100A side. External video data line groups, each consisting of six external video data lines VID, are wired to selection circuit A, one group on each side, and a high-potential power supply line PVDDX and a low-potential power supply line PVSSX for supplying operating voltage to selection circuit A are arranged between the groups of external video data lines. The external video data line VID connecting the first video input terminal and the video signal output circuit 210A is an example of the first external video data line in the present disclosure, and the external video data line VID connecting the second video input terminal and the video signal output circuit 210B is an example of the second external video data line in the present disclosure. In this embodiment, the operating voltage is supplied to the data line drive circuit 140A by the high-potential power supply line PVDDX and the low-potential power supply line PVSSX, which are dedicated power supply lines, thereby strengthening the power supply to the data line drive circuit 140A. As a result, the voltage drop in the selection circuit A is suppressed, the ON potential and OFF potential of the sample switch SWv are maintained, and display unevenness is suppressed.

[0033] As shown in FIG. 5 , in this embodiment, the power supply line adjacent to the external video data line VID is a power supply line with the same potential, specifically, a high-potential power supply line PVDDX. By arranging power supply lines with the same potential next to the external video data line, even if there is an influence of power supply noise due to coupling capacitance between the external video data line and the power supply line, the influence of the power supply noise is uniformed in each of the selection circuits A1 to A8, making it easier to correct unevenness by correcting the video signal. The reason for using the high-potential power supply line PVDDX as the power supply line adjacent to the external video data line VID is as follows: For display quality, it is important to suppress power supply noise when writing of the video signal to the data line 122 is completed. When an N-channel transistor is used as the sample switch SWv, turning off the sample switch SWv increases the power consumption of the final-stage inverter in the buffer circuit that controls the sample switch SWv. Because power supply noise on the low-potential side is large when the sample switch SWv is turned off, the power supply line adjacent to the external video data line VID is the selection potential for the sample switch SWv, and it is preferable that the power supply line be a high-potential power supply line with relatively low power supply noise when the sample switch SWv is turned off. For this reason, in this embodiment, the power supply line located next to the external video data line VID is the high-potential power supply line PVDDX. Note that when a P-channel transistor is used as the sample switch SWv, when the sample switch SWv is turned off, power supply noise on the high-potential side is large, so the power supply line located next to the video data line VID is at the selection potential of the sample switch SWv and is preferably a low-potential power supply line with relatively small power supply noise when the sample switch SWv is turned off. In this case, the power supply line located next to the external video data line VID can be the low-potential power supply line PVSSX.

[0034] As described above, according to this embodiment, selection of a series can be achieved with a smaller number of control signals than the number of series, so that in an electro-optical device using a demultiplex drive system, it is possible to accommodate higher definition without increasing the number of input terminals for control signals and the number of output video signals.

[0035] Second Embodiment FIG. 6 is a block diagram showing the configuration of an electro-optical device 1 according to a second embodiment of the present disclosure. In FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals. Comparing FIG. 6 with FIG. 1 makes it clear that the electro-optical device 1 of this embodiment differs from the electro-optical device 1 of the first embodiment in that a panel substrate 100B is provided instead of the panel substrate 100A. The panel substrate 100B differs from the panel substrate 100A in that the precharge circuit 150 is omitted and that a data line drive circuit 140B is provided instead of the data line drive circuit 140A. Although not shown in detail in FIG. 6, the data line drive circuit 140B differs from the data line drive circuit 140A of the first embodiment in that selection circuits B1 to B8 are provided instead of the selection circuits A1 to A8. Hereinafter, when it is not necessary to distinguish between the selection circuits B1 to B8, they will be referred to as selection circuit B. The reason why the precharge circuit 150 can be omitted in this embodiment will be explained later. The following description will focus on the selection circuit B, which is a difference from the first embodiment.

[0036] Fig. 7 is a block diagram showing the configuration of selection circuit B. Selection circuit B is addressed by address data lines D0 to D04. Note that address data lines D2 to D4 are not shown in Fig. 7. Address data line D0B is an inverted signal line for address data line D0, and address data line D1B is an inverted signal line for address data line D1.

[0037] As is clear from comparing FIG. 7 with FIG. 3, selection circuit B differs from selection circuit A in that it includes selection signal generation circuit 1410B instead of selection signal generation circuit 1410A. FIG. 8 is a block diagram showing an example configuration of data line drive circuit 140B. Data line drive circuit 140B includes eight selection circuits B. Therefore, data line drive circuit 140B includes eight decoder circuits. Each of these eight decoder circuits is, for example, a 5-bit decoder circuit and is connected to address data lines D0 to D4. Note that in FIG. 8, the inverted signals of each address data line are omitted. For example, an inverted signal of the signal applied to address data line D0 can be generated by a buffer circuit that receives the signal on address data line D0. The buffer circuit may be configured with an odd number of inverters connected in series.

[0038] The selection signal generation circuit 1410B also includes a total of 20 OR circuits, each corresponding to the first through Kth sequences, for one decoder circuit, and a total of 20 buffer circuits. Each of the 20 OR circuits performs a logical OR on the output signal of the decoder circuit and a control signal ALL, and outputs the result of the logical OR. The control signal ALL is a forced selection signal that instructs the selection of all data lines 122. Each of the address data lines D0 through D4 and the control signal ALL is connected to a low-potential power supply line PVSSX via a pull-down resistor R. The resistance of this pull-down resistor R is, for example, 1 MΩ. This pull-down resistor R is provided to prevent the selection signal SEL from being erroneously generated at the selection potential when the power is turned on or off. Since the selection signal SEL does not unintentionally reach the selection potential when the power is turned on or off, it is possible to suppress, for example, line-like burn-in.

[0039] The buffer circuits calculate the logical product of the output signal of the OR circuit of the same series and the control signal ENBX1 or ENBX2, and output the result. The odd-numbered buffer circuits calculate the logical product of the output signal of the OR circuit of the same series and the control signal ENBX1, and output the result. The even-numbered buffer circuits calculate the logical product of the output signal of the OR circuit of the same series and the control signal ENBX2, and output the result. The control signals ENBX1 and ENBX2 may also be connected to the low-potential power line PVSSX via pull-down resistors. Figure 9 shows an example of code for a 5-bit decoder circuit. The decoder is configured so that the selection signal does not reach the selection potential when all output signals of the address data lines D0 to D4 are 0.

[0040] In this embodiment, the control signal ALL can be used to simultaneously turn on or off all of the selection signals SEL1 to SEL20, allowing precharging to be performed from the data line driving circuit 140B. For this reason, the precharge circuit 150 is omitted in this embodiment. Since the precharge circuit 150 can be omitted, this embodiment makes it possible to reduce the size of the electro-optical device. Note that the electro-optical device 1 of this embodiment may be provided with an inspection circuit that inspects the data line driving circuit 140B, allowing for more detailed inspection.

[0041] This embodiment also achieves the same effects as the first embodiment. In addition, this embodiment makes it easy to set the selection signals to the selection potentials in any order. Therefore, this embodiment makes it possible to select the series while rotating the selection order for the series for each frame or each row, which is effective in eliminating display unevenness. For example, as shown in FIG. 10 , in the first horizontal scanning period, the series are selected in the order of the first series, the third series, ..., the nineteenth series, the second series, the fourth series, ..., the twentieth series, and in the second horizontal scanning period, the series are selected in the order of the third series, the fifth series, ..., the nineteenth series, the first series, the fourth series, ..., the twentieth series, and the second series. 11, during the ninth horizontal scanning period, the sequences are selected in the order of 17th series, 19th series, 1st series... 18th series, 20th series, 2nd series... 16th series, and during the twentieth horizontal scanning period, the sequences are selected in the order of 19th series, 1st series... 17th series, 20th series, 2nd series... 18th series. The drive signal for the decoder circuit included in selection circuit B differs from the drive signal for the shift register, but if the decoder circuit is configured to output address data signals in response to designation signals from a higher-level circuit, for example, the video signal output circuit 210 can be configured by making minor changes to a drive IC using a conventional phase-expansion drive method.

[0042] <Modification> The above-described embodiments can be modified in various ways. Specific modifications are exemplified below. Two or more embodiments selected from the following examples can be combined as long as they are not mutually contradictory. <Variation 1> In the first embodiment, the selection signal generation circuit 1410A may be configured using a ten-stage shift register. Furthermore, while the video data line VID is routed to pass on both sides of the shift register of the selection signal generation circuit 1410A, this is not limiting. For example, the selection signal generation circuit may be divided into multiple sub-circuit blocks, and the video data line VID may be routed between these sub-circuit blocks. In this case, each sub-circuit block may be composed of, for example, one or more latch circuits constituting a shift register. In this case, the number of latch circuits included in each sub-circuit block may not be equal. In the second embodiment, each sub-circuit block may be composed of, for example, one or more unit circuits that select and output sequentially from a decoder circuit. In this case, the number of unit circuits that select and output sequentially included in each sub-circuit block may not be equal. Furthermore, the video data line VID does not necessarily have to completely avoid the transistors that constitute the selection signal generation circuit. Specifically, the video data line VID may be arranged in a wiring layer above the transistors that constitute the selection signal generation circuit, so that a portion of the video data line VID overlaps the transistors. In the second embodiment, the selection signal generation circuit 1410B may be configured using a decoder circuit that supports 10 different outputs, specifically, a 4-bit decoder circuit. Furthermore, in the second embodiment, the power supply connected to the address data lines via resistor R may be set to select a code that does not erroneously generate a selection signal SEL of a selection potential. Therefore, for example, based on FIG. 9, a code that indicates "NO SEL" with no selection series, i.e., all of the address data lines D0 to D4 connected via resistor R, may be set to VDDX. Alternatively, the address data line D0 connected via resistor R may be set to VSSX, and the other address data lines D1 to D4 connected via resistor R may be set to VDDX.

[0043] <Variation 2> In the above-described embodiments, a device using liquid crystal has been exemplified as an electro-optical device, but the present disclosure is not limited thereto. That is, any electro-optical device may be used as long as it uses an electro-optical material whose optical properties change in response to electrical energy. Note that an electro-optical material is a material whose optical properties, such as transmittance or brightness, change in response to the supply of an electrical signal, such as a current signal or a voltage signal. For example, the present disclosure may be applied to a display panel using light-emitting elements, such as organic electroluminescent (EL), inorganic electroluminescent (EL), or light-emitting polymers, in the same manner as in the first and second embodiments described above.

[0044] The present disclosure can also be applied to an electrophoretic display panel that uses, as the electro-optical material, microcapsules containing a colored liquid and white particles dispersed in the liquid, in the same manner as the first and second embodiments. Furthermore, the present disclosure can also be applied to a twist ball display panel that uses, as the electro-optical material, twist balls that are painted in different colors for regions with different polarities, in the same manner as the first and second embodiments. The present disclosure can also be applied to various electro-optical devices, such as a toner display panel that uses black toner as the electro-optical material, in the same manner as the first and second embodiments.

[0045] <Application example> The present invention can be applied to various electronic devices. Figures 12 to 14 show examples of specific forms of electronic devices to which the present invention can be applied. Fig. 12 is an explanatory diagram showing an example of an electronic device. Fig. 12 is a perspective view of a portable personal computer 2000 that employs the electro-optical device 1. The personal computer 2000 has the electro-optical device 1 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed.

[0046] Fig. 13 is an explanatory diagram showing another example of an electronic device. Fig. 13 is a perspective view of a mobile phone 3000. The mobile phone 3000 has a plurality of operation buttons 3001, a scroll button 3002, and an electro-optical device 1 that displays various images. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled.

[0047] Fig. 14 is an explanatory diagram showing another example of an electronic device. Fig. 14 is a schematic diagram showing the configuration of a projection display device 4000 that employs an electro-optical device 1. The projection display device 4000 is, for example, a three-plate projector. The electro-optical device 1R shown in Fig. 14 is an electro-optical device 1 that corresponds to the red display color, the electro-optical device 1G is an electro-optical device 1 that corresponds to the green display color, and the electro-optical device 1B is an electro-optical device 1 that corresponds to the blue display color.

[0048] That is, the projection display device 4000 has three electro-optical devices 1R, 1G, and 1B corresponding to the display colors red, green, and blue, respectively. An illumination optical system 4001 supplies a red component r of light emitted from an illumination device 4002, which is a light source, to the electro-optical device 1R, a green component g to the electro-optical device 1G, and a blue component b to the electro-optical device 1B. Each of the electro-optical devices 1R, 1G, and 1B functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 in accordance with a display image. A projection optical system 4003 combines the light emitted from each of the electro-optical devices 1R, 1G, and 1B and projects the combined light onto a projection surface 4004. That is, the present disclosure is also applicable to liquid crystal projectors.

[0049] Electronic devices to which the present disclosure is applicable include personal digital assistants (PDAs) as well as the devices exemplified in Figures 1 and 12 to 14. Other examples include digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays such as instrument panels, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS terminals. Further examples include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0050] <Aspects grasped from at least one of the embodiment and each modified example> The present disclosure is not limited to the above-described embodiments and modifications, and can be realized in various forms without departing from the spirit thereof. For example, the present disclosure can also be realized in the following forms. The technical features in the above embodiments corresponding to the technical features in each form described below can be replaced or combined as appropriate to solve some or all of the problems of the present disclosure or to achieve some or all of the effects of the present disclosure. Furthermore, if a technical feature is not described as essential in this specification, it can be deleted as appropriate.

[0051] One aspect of the electro-optical device disclosed herein includes a first substrate having a pixel region in which pixel circuits are provided at each intersection of a scanning line and K data lines divided into K series; a group of input terminals arranged along one side of the pixel region, including a video input terminal for receiving a video signal obtained by time-division multiplexing data voltages of each series and an input terminal for receiving a control signal; and a data line driving circuit. The data line driving circuit has a demultiplexer having K switches for selecting a data line to which the video signal is to be supplied in response to a K series selection signal, and is arranged between the pixel region and the group of input terminals. The data line driving circuit also includes a circuit block for generating the K series selection signal, and video data lines arranged between the circuit block and an adjacent circuit block, the video data lines being connected to the video input terminal and the K switches, where K is an integer greater than or equal to 2. According to this aspect, the data line driving circuit is divided into multiple circuit blocks, and a selection signal is generated in each circuit block. Video data lines are wired between the circuit blocks. The wiring resistance and drive load of the video data lines are comparable to conventional circuit blocks. Furthermore, since the wiring resistance and driving load of the selection signal lines are reduced, high-speed driving is possible and the number of video data lines can be reduced, thereby increasing the performance of the output amplifier to the same level as in phase expansion driving.

[0052] In a more preferred embodiment of the electro-optical device, the circuit block may include a shift register, and may generate the K-series selection signal based on an output signal from the shift register. According to this embodiment, a video signal output circuit can be configured by making minor modifications to a conventional phase-expansion driver IC, enabling flexible selection of a drive method depending on the application. In a more preferred embodiment of the electro-optical device, the circuit block may have two operating modes: a normal mode in which the K-series selection signal is generated based on an output signal from the shift register, and an inspection mode in which the output signal from the shift register is output; and may include a switch for switching between the two operating modes. According to this embodiment, testing of the data line driver circuit can be easily performed.

[0053] In another preferred embodiment of the electro-optical device, the circuit block may include a decoder circuit, and may generate the K-series selection signal based on an output signal from the decoder circuit. This embodiment makes it possible to select the series while rotating the series selection order for each frame or each row, which is effective in eliminating display unevenness.

[0054] In another preferred embodiment of the electro-optical device, high-potential and low-potential power supply lines for supplying operating power to the circuit blocks may intersect with the video data lines, and the power supply lines may be thinner at the points where they intersect with the video data lines than at other points. According to this embodiment, the areas of the power supply lines where they intersect with the video data lines are thinner than at other points, thereby suppressing power supply noise from being superimposed on the video signal when the circuit blocks are driven, thereby achieving high-quality display.

[0055] In another preferred embodiment of the electro-optical device, the video data lines may intersect with a first signal line to which a first signal is supplied and a second signal line to which a second signal that is an inverted signal of the first signal is supplied. According to this embodiment, noise superimposed on the video data lines is cancelled out by the first signal and the second signal, thereby realizing a high-quality display. In another preferred embodiment of the electro-optical device, the circuit block may generate the K sequences of selection signals based on J control signals, and the first signal and the second signal may be included in the J control signals, where J is an integer smaller than K. According to this embodiment, the K sequences of selection signals can be generated using J control signals, which is fewer than the number of sequences of the selection signals.

[0056] In another preferred embodiment of the electro-optical device, a second substrate may be provided on which a video signal output circuit is disposed that outputs the video signal to the video input terminal. According to this embodiment, the video signal output circuit is disposed on the second substrate, which is different from the first substrate, and therefore, heat countermeasures for the video signal output circuit are facilitated.

[0057] In another preferred embodiment of the electro-optical device, the first substrate may have a first pixel region and a second pixel region that share the scanning lines. In this embodiment, the input terminal group may include a first video input terminal to which the first video signal supplied to the data line of the first pixel region is input, and a second video input terminal to which the second video signal supplied to the data line of the second pixel region is input. The data line driving circuit may include a first demultiplexer and a first circuit block corresponding to the first pixel region, and a second demultiplexer and a second circuit block corresponding to the second pixel region. The electro-optical device may further include a flexible substrate connecting the first substrate and the second substrate, and the flexible substrate may include a first external video data line, a second external video data line, and a power supply line group. The first external video data line connects the first video input terminal and the video signal output circuit. a second external video data line connecting the second video input terminal and the video signal output circuit; a power supply line group arranged between the first external video data line and the second external video data line, including high-potential and low-potential power supply lines for supplying operating power to the first circuit block and high-potential and low-potential power supply lines for supplying operating power to the second circuit block; and a power supply line group arranged between the first external video data line and the second external video data line, including high-potential and low-potential power supply lines for supplying operating power to the second circuit block. According to this aspect, power is supplied to each of the first circuit block and the second circuit block via dedicated power supply lines, thereby suppressing voltage drops in each of the first circuit block and the second circuit block.

[0058] In another preferred embodiment of the electro-optical device, the potential of the power supply line arranged adjacent to the first external video data line and the potential of the power supply line arranged adjacent to the second external video data line in the power supply line group may be the same. According to this embodiment, since the potential of the power supply line arranged adjacent to the first external video data line and the potential of the power supply line arranged adjacent to the second external video data line are the same, even if there is an influence of power supply noise, the influence of the power supply noise is the same in each of the first circuit block and the second circuit block, making it easier to correct unevenness by correcting the video signal.

[0059] In another preferred embodiment of the electro-optical device, the power supply line arranged adjacent to the first external video data line and the power supply line arranged adjacent to the second external video data line may be power supply lines for a selection potential of the sample switch. According to this embodiment, the occurrence of display unevenness due to the switch off operation is suppressed.

[0060] The present disclosure also provides an electronic device that includes the electro-optical device according to any one of the above aspects. According to this aspect, it is possible to drive an electronic device that includes an electro-optical device using a demultiplex driving method at high speed, thereby reducing the number of video data lines. Therefore, the performance of the video signal output amplifier in an electronic device that includes an electro-optical device using a demultiplex driving method can be improved to the same level as that of a phase-expansion driving method. [Explanation of symbols]

[0061] 1, 1B, 1G, 1R... electro-optical device, 100A, 100B... panel substrate, 200... drive substrate, 300... flexible substrate, 110... pixel region, 120... scanning line, 122... data line, 130... scanning line drive circuit, 140A, 140B... data line drive circuit, 150... precharge circuit, 160... input terminal group, 210A, 210B... video signal output circuit, A1 to A8, B1 to B8... selection circuit, 1410A, 1410B... selection signal generation circuit, 1420... series selection signal Group of lines, 1430...group of control signal lines, PVDDX...high potential power supply line, PVSSX...low potential power supply line, 2000...personal computer, 2001...power switch, 2002...keyboard, 2010...main body, 3000...mobile phone, 3001...operation buttons, 3002...scroll button, 4000...projection display device, 4001...illumination optical system, 4002...illumination device, 4003...projection optical system, 4004...projection surface, PX...pixel circuit, SWv...sample switch.

Claims

1. A first shift register that sequentially shifts and outputs an input signal; a second shift register arranged in a first direction next to the first shift register, for sequentially shifting and outputting an input signal; In the first mode, a control signal is commonly supplied as an input signal to the first shift register and an input signal to the second shift register; In the second mode, supplying the last shifted signal among the signals shifted and output from the first shift register as an input signal to the second shift register; A changeover switch and a video data line extending along a second direction intersecting the first direction, disposed between the first shift register and the second shift register in a plan view, and supplied with a video signal of an analog voltage; An electro-optical device comprising:

2. a first signal line extending along the first direction; and a second signal line arranged alongside the first signal line in the second direction and extending along the first direction, a part of the changeover switch is disposed between the first signal line and the second signal line; The electro-optical device according to claim 1 .

3. a part of the changeover switch is disposed between the first shift register and the second shift register in the first direction; The electro-optical device according to claim 1 .

4. 4. An electronic device comprising the electro-optical device according to claim 1.

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