Sequence pattern generator and setting method thereof

Abstract

To provide a sequence pattern generating device which enables a user to arbitrarily set output to be restarted synchronously with the restart of a sequence.SOLUTION: A sequence pattern generating device includes a synchronous setting screen 301 having a primary module selection button 311 and a secondary module selection button 312 for selecting a module to be synchronized, and synchronous selection buttons 313, 314, 315, and 316 provided for each output of the selected module and for selecting whether or not to synchronize when restarting a sequence.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a sequence pattern generator that generates and outputs any sequence pattern set by a user. [Background technology]

[0002] In recent years, various digital communication devices have been required to have higher transmission capacity due to the increase in the number of users and the spread of multimedia communication. As an index for evaluating the quality of digital signals in these digital communication devices, the bit error rate (BER), which is defined as the number of bit errors in received data compared to the total number of received data, is known.

[0003] In the error rate measurement apparatus for measuring the bit error rate described above, a test signal containing fixed data is transmitted to the device under test, and the signal under test input via the device under test is compared bit by bit with a reference signal, thereby measuring the error rate of the signal under test.

[0004] This type of error rate measuring apparatus uses a pulse pattern generator that generates a data signal with a predetermined pulse pattern that is input as a test signal to a device under test that is compatible with recent high-speed data communications.

[0005] Patent Document 1 describes a pulse pattern generator that sets a master-side phase difference target value according to the frequency of a reference clock signal and also sets a slave-side phase difference target value using correction data in a memory unit in order to keep the phase states of multiple data signals constant. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5432352 Summary of the Invention [Problem to be solved by the invention]

[0007] High-speed serial bus standards such as USB (Universal Serial Bus) and PCIe (Peripheral Component Interconnect Express) have a state machine called the Link Training & Status State Machine (LTSSM), which manages the initialization of communication between devices and the adjustment of link speed.

[0008] Furthermore, conventional error rate measurement devices are equipped with a function (sequence pattern function) that controls PCIe GEN1-5 and USB3.1 LTSSM by rapidly switching specific patterns defined by the standard from a pulse pattern generator (PPG) and causes transition to a specific state. The patterns that cause the device under test (DUT) to transition to a specific state are defined by the standard, and the sequence pattern function can combine and output the output order of these patterns.

[0009] The PCIe standard defines the number of lanes as variations such as x1, x2, x4, x8, and x16, and transmits a pattern defined for each lane to cause the DUT to transition states.

[0010] In normal use, PCIe devices only require data synchronization across multiple lanes. However, PCIe device developers have a need to temporarily stop the sequence of multiple or all lanes and then resume the sequence of multiple or all lanes at a specified timing, but this was not possible with the previous sequence pattern function.

[0011] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a sequence pattern generator that allows a user to arbitrarily set an output to be restarted in synchronization when a sequence is restarted. [Means for solving the problem]

[0012] The sequence pattern generator of the present invention is a sequence pattern generator that can be equipped with at least one module having an output of at least one data signal, and the total number of outputs of the data signals is two or more, and in the setting for one of the data signals to be output, the setting for the output to be resumed synchronously when the sequence is resumed is performed. Display the setting screen on the display and let the user set it It is equipped with a device control unit.

[0013] This configuration allows the user to set the output to be synchronized and restarted when the sequence is restarted, in the settings for one of the data signals to be output. This allows the user to freely set the output to be synchronized and restarted when the sequence is restarted.

[0014] In the sequence pattern generator of the present invention, the device control unit causes the user to select the module and select whether or not to resume the output of the selected module in synchronization with the restart of the sequence. A synchronization setting screen is displayed on the display unit to allow the user to make a selection. It is something.

[0015] This configuration allows a module to be selected, and the user can choose whether or not to synchronize the output of the selected module when the sequence is restarted. This prevents confusion for the user because modules other than the selected module are not displayed.

[0016] In the sequence pattern generator of the present invention, when only one module having two outputs is installed, the device control unit allows the user to select whether or not to resume the sequence synchronously when the sequence is resumed. A sequence setting screen is displayed on the display unit to allow the user to make a selection. It is something.

[0017] With this configuration, if only one module with two outputs is installed, the only option available when restarting a sequence is whether or not to synchronize the outputs. Therefore, if there are only a few outputs that can be synchronized, the user can perform the desired settings with fewer operations.

[0018] The setting method for a sequence pattern generator of the present invention is a setting method for a sequence pattern generator that can be equipped with at least one module having an output of at least one data signal, and the total number of outputs of the data signal is two or more, and in the setting for one of the data signals to be output, the setting for the output to be resumed synchronously when the sequence is resumed is performed. Display the setting screen and let the user set it This includes a device control step.

[0019] This configuration allows the user to set the output to be synchronized and restarted when the sequence is restarted, in the settings for one of the data signals to be output. This allows the user to freely set the output to be synchronized and restarted when the sequence is restarted.

[0020] In the method for setting a sequence pattern generator of the present invention, the device control step includes selecting the module and selecting whether or not to restart the output of the selected module in synchronization with the restart of the sequence. Display the sync settings screen and let the user select It involves a selection step.

[0021] This configuration allows a module to be selected, and the user can choose whether or not to synchronize the output of the selected module when the sequence is restarted. This prevents confusion for the user because modules other than the selected module are not displayed.

[0022] In the setting method for the sequence pattern generator of the present invention, the device control step allows the user to select whether or not to restart the sequence synchronously when only one module having two outputs is installed. Display the sequence setting screen and let the user select It is something.

[0023] With this configuration, if only one module with two outputs is installed, the only option available when restarting a sequence is whether or not to synchronize the outputs. Therefore, if there are only a few outputs that can be synchronized, the user can perform the desired settings with fewer operations. [Effects of the Invention]

[0024] The present invention can provide a sequence pattern generator that allows a user to arbitrarily set an output to be restarted in synchronization when a sequence is restarted. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a block diagram of a sequence pattern generator according to one embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing an example of a sequence output from a sequence pattern generator according to an embodiment of the present invention. [Figure 3] FIG. 3 is a diagram showing an example of a sequence setting screen when only one module of the sequence pattern generating device according to one embodiment of the present invention is installed. [Figure 4] FIG. 4 is a diagram showing an example of a sequence setting screen when two modules of a sequence pattern generating device according to an embodiment of the present invention are installed. [Figure 5] FIG. 5 is a diagram showing an example of a synchronization setting screen of the sequence pattern generator according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0026] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A sequence pattern generator according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] 1, a sequence pattern generator 1 according to one embodiment of the present invention includes a primary module 2 and a secondary module 3, each capable of outputting two data signals. The primary module 2 and the secondary module 3 are connected by wiring via a bridge route 4. The primary module 2 and the secondary module 3 may each output one data signal, or two or more data signals.

[0028] The primary module 2 and secondary module 3 are detachably mounted in slots (not shown) in the main body of the measurement device 11. In the slots (not shown) of the measurement device 11, multiple modules such as the primary module 2, secondary module 3, clock module 12, and measurement module 13 are detachably mounted, as shown in FIG.

[0029] As shown in Figure 1, the measuring device 11 is equipped with an operation unit 14, a display unit 15, and a device control unit 16, and multiple modules (primary module 2, secondary module 3, clock module 12, measurement module 13, etc.) selected according to the measurement content can be freely added, removed, or rearranged in slots not shown, allowing various measurements of the object to be measured based on standards in a variety of forms.

[0030] The clock module 12 is configured by a clock generator, and generates a reference clock signal (a half-rate clock or a full-rate clock) to be input to the primary module 2 and the secondary module 3.

[0031] The clock module 12 is not limited to a configuration that can be attached to and detached from a slot (not shown) of the measuring device 11, and an external clock generator separate from the measuring device 11 can also be used.

[0032] The measurement module 13 performs various measurements of the object to be measured based on the set values ​​of the measurement parameters set by operating the operation unit 14 .

[0033] Operation unit 14 includes, for example, a pointing device such as a mouse or touch screen that operates a pointer or icons on the display screen of display unit 15, and keys, switches, buttons, etc. that are provided on the main body of measuring device 11. Operation unit 14 performs initial settings such as the initial value (minimum or maximum value) of the bit rate that can be generated by sequence pattern generator 1, the initial division ratios of primary frequency divider 21 and secondary frequency divider 31 (described later) of primary module 2 and secondary module 3, the initial delay amounts of delay circuit units 22, 23, and 24 of primary module 2 and delay circuit units 32, 33, and 34 of secondary module 3, and the allowable ranges of phase difference target values ​​of primary phase comparator 25 and secondary phase comparator 35, as well as various measurement-related operations such as starting and stopping measurement, specifying a measurement channel for setting measurement parameters, and setting / changing / referencing measurement parameters on the setting screen.

[0034] It is preferable to set the initial value of the bit rate to the minimum value of the bit rate range in which the phase margin is large, but the maximum value of the bit rate range may also be set as the initial value of the bit rate.

[0035] The display unit 15 is composed of, for example, an LCD display provided on the main body of the measuring device 11, and displays on the display screen a setting screen for performing initial settings on the operation unit 14, a setting screen for a specified measurement channel, a measurement screen, etc.

[0036] The device control unit 16 is composed of a microcomputer equipped with, for example, a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc., and controls the primary module 2, secondary module 3, clock module 12, measurement module 13, operation unit 14, and display unit 15, including setting control of each module based on the operation of operation unit 14, variable control of the bit rate, output control of the reference clock signal, various measurement controls of the object to be measured based on the measurement signal, and display control of the setting screen and measurement screen.

[0037] Next, the configurations of the primary module 2 and secondary module 3 that make up the sequence pattern generator 1 will be described.

[0038] As shown in FIG. 1, the primary module 2 is configured to include a primary frequency dividing unit 21, a primary first delay circuit unit 22, a primary second delay circuit unit 23, a primary third delay circuit unit 24, a primary phase comparing unit 25, a primary data generating unit 26, a primary first data multiplexing unit 27, a primary second data multiplexing unit 28, and a primary control unit 29.

[0039] The primary frequency divider 21 is composed of a 1 / N frequency divider (N: a positive integer of 2 or more), divides the reference clock signal generated by the clock module 12 or an external clock source by 1 / N, and inputs this 1 / N divided frequency-divided clock signal to the primary first delay circuit 22 and the primary phase comparator 25.

[0040] The reference clock signal is a half-rate clock or full-rate clock of a frequency (e.g., 1.25 GHz to 16 GHz) at which sequence pattern generator 1 can operate, and is generated, for example, by a clock source prepared by the user, an internal synthesizer built into measuring device 11 together with sequence pattern generator 1, or an external synthesizer separate from measuring device 11. Then, a reference clock signal of the same phase is input to primary module 2 and secondary module 3.

[0041] Primary first delay circuit unit 22 is configured by, for example, an IQ modulator, and adjusts the delay amount by varying the phase angle of the frequency-divided clock signal from primary frequency divider unit 21 under the control of primary control unit 29 so that an optimal phase relationship is established between the reference clock signal and the data signal (parallel data) input from primary data generator 26 to primary first data multiplexer 27 and primary second data multiplexer 28. The frequency-divided clock signal with the delay amount adjusted is input to primary phase comparator 25 via primary second delay circuit unit 23, and is also input to secondary second delay circuit unit 33 and secondary third delay circuit unit 34 of secondary module 3 via bridge route 4.

[0042] The primary second delay circuit unit 23 is configured with an electronic delay in which delay elements (gate delays) that adjust the delay amount of the frequency-divided clock signal by electrically switching in units of several picoseconds are connected in multiple stages. The primary second delay circuit unit 23 functions as a bypass circuit that passes the frequency-divided clock signal whose delay amount has been adjusted by the primary first delay circuit unit 22 as is and inputs it to the primary phase comparator unit 25.

[0043] Primary third delay circuit unit 24 is configured with electronic delays similar to those of primary second delay circuit unit 23, and is provided with the same number of electronic delays as the number of transmission lanes of the parallel data generated by primary data generation unit 26. For example, if the number of transmission lanes of parallel data is eight, primary third delay circuit unit 24 is configured with eight electronic delays. This primary third delay circuit unit 24 adjusts the delay amount appropriately for each piece of data under the control of primary control unit 29 in order to adjust the skew of each piece of parallel data input from primary data generation unit 26 to primary first data multiplexing unit 27 and primary second data multiplexing unit 28.

[0044] The primary phase comparison unit 25 compares the phases of the divided clock signal P1 input from the primary frequency dividing unit 21 and the divided clock signal P2 input from the primary frequency dividing unit 21, passing through the primary first delay circuit unit 22 and input from the primary second delay circuit unit 23 via the bridge route 4, treating these signals as clock and data input to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28, and outputs a phase difference signal (voltage signal) P2-P1 corresponding to the phase difference to the primary control unit 29.

[0045] The primary data generating unit 26 is provided on a single FPGA (Field Programmable Gate Array) that is partially configurable, and generates parallel data for a predetermined number of transmission lanes (e.g., 4 Gbps x 8 lanes) as a data signal of any pulse pattern set by the user, at the timing of the divided clock signal from the primary third delay circuit unit 24, and outputs it to the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28.

[0046] The primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 are composed of, for example, a multiplexer (MUX) or a D-type flip-flop circuit, and multiplex the parallel data input from the primary data generating unit 26 into serial data at the timing of a reference clock signal and output it.

[0047] The primary control unit 29 controls the primary frequency dividing unit 21, the delay circuit units 22, 23, and 24 of the primary module 2, the primary phase comparison unit 25, the primary data generating unit 26, the primary first data multiplexing unit 27, and the primary second data multiplexing unit 28 in order to synchronize the phases of multiple data signals based on any pulse pattern set by the user and output them.

[0048] The primary control unit 29 stores the primary side phase difference target value targeted by the primary phase comparison unit 25 of the primary module 2 as correction data in a table that corresponds to each predetermined step of the frequency (bit rate) of the reference clock signal.

[0049] The primary control unit 29 sets a primary-side phase difference target value that the primary phase comparison unit 25 of the primary module 2 aims at, in accordance with the frequency (bit rate) of the reference clock signal.

[0050] The primary-side phase difference target value has a one-to-one correspondence with each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, the maximum and minimum allowable values ​​are a fixed tolerance range of ±1 cycle (for example, ±31.25 psec for 32 Gbit / s, which corresponds to the cycle in which the phase of the primary frequency divider 21 changes) from the center voltage value. Also, if the reference clock signal is a full-rate clock, the maximum and minimum allowable values ​​are a fixed tolerance range of ±0.5 cycles from the center voltage value.

[0051] Furthermore, when setting a primary-side phase difference target value at a reference clock signal frequency (bit rate) that is not stored in the primary control unit 29, the value is calculated by linear interpolation from two points of correction data at reference clock signal frequencies (bit rates) before and after the reference clock signal frequency (bit rate).

[0052] The primary control unit 29 adjusts and controls the delay amount of each delay circuit unit 22, 23, 24 of the primary module 2. Specifically, when initial settings are performed by the operation unit 14, the primary control unit 29 adjusts and controls each delay circuit unit 22, 23, 24 of the primary module 2 to the initial delay amount.

[0053] In addition, when outputting the four data signals while keeping the pattern generation timing constant, the primary control unit 29 adjusts and controls the delay amount of the primary second delay circuit unit 23 so that the voltage reading value of the primary phase comparison unit 25 (the voltage value according to the phase difference signal P2-P1) becomes approximately equal to the center voltage value.

[0054] Similar to the primary module 2, the secondary module 3 is configured to include a secondary frequency dividing unit 31, a secondary first delay circuit unit 32, a secondary second delay circuit unit 33, a secondary third delay circuit unit 34, a secondary phase comparison unit 35, a secondary data generating unit 36, a secondary first data multiplexing unit 37, a secondary second data multiplexing unit 38, and a secondary control unit 39.

[0055] The secondary frequency divider 31, like the primary frequency divider 21 of the primary module 2, is composed of a 1 / N divider (N: a positive integer of 2 or more), and divides a reference clock signal that is in phase with the reference clock signal input to the primary frequency divider 21 of the primary module 2 by 1 / N, and inputs this 1 / N divided frequency-divided clock signal to the secondary first delay circuit 32 and the secondary phase comparator 35.

[0056] The secondary first delay circuit unit 32 is configured with an IQ modulator, similar to the primary first delay circuit unit 22 of the primary module 2. This secondary first delay circuit unit 32 is essentially an unnecessary component, but is provided to allow commonality between the primary module 2 and the secondary module 3. The output of the secondary first delay circuit unit 32 here is open so that even if a divided clock signal is input from the secondary frequency divider unit 31, it is not output anywhere.

[0057] Similar to primary second delay circuit unit 23 of primary module 2, secondary second delay circuit unit 33 is composed of an electronic delay in which delay elements (gate delays) are connected in multiple stages, which adjust the delay amount of the frequency-divided clock signal by electrically switching in units of several picoseconds, for example. Secondary second delay circuit unit 33 adjusts the delay amount of the frequency-divided clock signal received from primary module 2 under the control of secondary control unit 39 so that the phase relationship between the reference clock signal and the data signal (parallel data) input from secondary data generation unit 36 ​​to secondary first data multiplexing unit 37 and secondary second data multiplexing unit 38 becomes equivalent to the phase relationship between the reference clock signal and the data signal (parallel data) input to primary first data multiplexing unit 27 and primary second data multiplexing unit 28 of primary module 2.

[0058] The secondary third delay circuit unit 34 is configured with electronic delays, similar to the primary third delay circuit unit 24 of the primary module 2, and has the same number of electronic delays as the number of transmission lanes of the parallel data generated by the secondary data generation unit 36. In order to adjust the skew of each piece of parallel data input from the secondary data generation unit 36 ​​to the secondary first data multiplexing unit 37 and secondary second data multiplexing unit 38, the secondary third delay circuit unit 34 adjusts the delay amount appropriately for each piece of data under the control of the secondary control unit 39.

[0059] The secondary phase comparator 35 compares the phase of the divided clock signal S1 from the secondary divider 31 with the divided clock signal S2 input from the secondary second delay circuit 33 via the bridge route 4 from the primary first delay circuit 22 of the primary module 2, and outputs a phase difference signal (voltage signal) corresponding to the phase difference S2-S1 to the secondary control unit 39.

[0060] The secondary data generating unit 36, like the primary data generating unit 26 of the primary module 2, is provided on a single FPGA that is partially configurable, and generates parallel data of a predetermined number of transmission lanes (e.g., 4 Gbps x 8 lanes) as a data signal of any pulse pattern set by the user, at the timing of the divided clock signal from the secondary third delay circuit unit 34, and outputs it to the secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38.

[0061] The secondary first data multiplexing unit 37 and the secondary second data multiplexing unit 38, like the primary first data multiplexing unit 27 and the primary second data multiplexing unit 28 of the primary module 2, are composed of, for example, a multiplexer (MUX) or a D-type flip-flop circuit, and multiplex the parallel data input from the secondary data generating unit 36 ​​into serial data at the timing of the reference clock signal and output it.

[0062] The secondary control unit 39 controls the secondary frequency dividing unit 31, the delay circuit units 32, 33, and 34 of the secondary module 3, the secondary phase comparison unit 35, the secondary data generating unit 36, the secondary first data multiplexing unit 37, and the secondary second data multiplexing unit 38 in order to synchronize the phases of multiple data signals based on any pulse pattern set by the user and output them.

[0063] The secondary control unit 39 stores, as tabular correction data, a secondary-side phase difference target value targeted by the secondary phase comparison unit 35 of the secondary module 3, and correction values ​​for absorbing delay amount errors caused by variations in the characteristics and wiring of each delay circuit unit 22, 23, 24 of the primary module 2 and each delay circuit unit 32, 33, 34 of the secondary module 3, and phase shifts caused by deterioration in the duty ratio of the primary frequency divider unit 21 and the secondary frequency divider unit 31, which are associated with each predetermined step of the frequency (bit rate) of the reference clock signal.

[0064] The correction value is a value obtained by subtracting the primary-side phase difference target value (voltage read value) from the secondary-side phase difference target value (voltage read value).

[0065] The secondary control unit 39 sets a secondary-side phase difference target value that the secondary phase comparison unit 35 of the secondary module 3 aims at, in accordance with the frequency (bit rate) of the reference clock signal.

[0066] The secondary-side phase difference target value has a one-to-one correspondence with each frequency (bit rate) of the reference clock signal. For example, if the reference clock signal is a half-rate clock, the maximum and minimum allowable values ​​are ±1 cycle (e.g., ±31.25 psec for 32 Gbit / s, which corresponds to the period during which the phase of the secondary frequency divider 31 changes) from the center voltage value. If the reference clock signal is a full-rate clock, the maximum and minimum allowable values ​​are ±0.5 cycles from the center voltage value.

[0067] Furthermore, when setting a secondary-side phase difference target value at a frequency (bit rate) of a reference clock signal that is not stored in the secondary control unit 39, the value is calculated by linear interpolation from two points of correction data at the frequencies (bit rates) of the reference clock signal before and after the frequency (bit rate) of the reference clock signal.

[0068] In addition, correction data can be stored in advance, in which the central voltage value, maximum value, and minimum value of the primary side phase difference target value at each predetermined step of the frequency (bit rate) of the reference clock signal are added with a correction value to become the central voltage value, maximum value, and minimum value of the secondary side phase difference target value.

[0069] The secondary control unit 39 adjusts and controls the delay amount of each delay circuit unit 32, 33, 34 of the secondary module 3. Specifically, when initial settings are performed by the operation unit 14, the secondary control unit 39 adjusts and controls each delay circuit unit 32, 33, 34 of the secondary module 3 to the initial delay amount.

[0070] In addition, when outputting the four data signals while maintaining constant pattern generation timing, the secondary control unit 39 adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the voltage reading value (voltage value corresponding to the phase difference S2-S1) of the secondary phase comparison unit 35 becomes approximately equal to the center voltage value.

[0071] Furthermore, when the secondary control unit 39 determines that the voltage reading value (voltage value corresponding to the phase difference signal P2-P1) of the primary phase comparison unit 25 of the primary module 2 and the voltage reading value (voltage value corresponding to the phase difference signal S2-S1) of the secondary phase comparison unit 35 of the secondary module 3 are not equal, it adjusts and controls the delay amount of the secondary second delay circuit unit 33 so that the phase advances or lags by an inverse multiple of the reference clock signal depending on the change state of the voltage reading value of the secondary phase comparison unit 35 of the secondary module 3.

[0072] For example, when the reference clock signal is a half-rate clock, if the voltage read value of the secondary phase comparator 35 is changing in an upward trend, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase is advanced by 2 UI. On the other hand, if the voltage read value of the secondary phase comparator 35 is changing in a downward trend, the delay amount of the secondary second delay circuit unit 33 is adjusted and controlled so that the phase is delayed by 2 UI.

[0073] When the pattern generation timing of the four data signals is kept constant after the initial setting, the secondary control unit 39 inhibits the secondary frequency dividing unit 31 if the bit rate is varied by a predetermined amount.

[0074] When the secondary control unit 39 inhibits the secondary frequency divider unit 31 by varying the bit rate from the initial value (the minimum or maximum value of the bit rate range) in increments of a predetermined amount, it compares the voltage reading (voltage value corresponding to the phase difference signal P2-P1) of the primary phase comparator unit 25 of the primary module 2 with the voltage reading (voltage value corresponding to the phase difference signal S2-S1) of the secondary phase comparator unit 35 of the secondary module 3, and determines whether the two voltage readings are equal (whether P2-P1=S2-S1).

[0075] In the configuration of Figure 1 described above, the primary module 2 and the secondary module 3 have the same internal configuration in order to standardize them, but the secondary first delay circuit section 32 of the secondary module 3 may be omitted.

[0076] In the sequence pattern generator 1 of this embodiment, the primary module 2 and secondary module 3 each have two outputs (Data1 and Data2), and can output a maximum of four data signals. However, by adding modules, the number of outputs can be increased without being limited to this number.

[0077] As shown in FIG. 2, the sequence pattern generator 1 of this embodiment can synchronize and output four data signals, or synchronize and output two or more of the four data signals.

[0078] In Fig. 2, at the start of the sequence at time 3, the sequence is progressing in all lanes, and at time 7, the output of the set sequence ends and is paused due to the pause setting. After that, at time 10, when the sequence is resumed by the user operating the operation unit 14, the sequence is resumed only in the set lanes 0 and 2.

[0079] The following describes a setting for synchronizing a plurality of data signals and restarting output after such a sequence has been temporarily stopped.

[0080] When a setting for a data signal output by any one of the primary first data multiplexing unit 27, the primary second data multiplexing unit 28, the secondary first data multiplexing unit 37, and the secondary second data multiplexing unit 38 is selected by operating the operation unit 14, the device control unit 16 causes the display unit 15 to display a sequence setting screen 101 as shown in Figure 3.

[0081] 3 shows the sequence setting screen 101 in the case where there are two outputs using either the primary module 2 or the secondary module 3. The sequence setting screen 101 allows the setting of a sequence for one output.

[0082] 3, sequence display section 111 displays the set sequence pattern. The set sequence pattern is output for each row in numerical order of the "Block No." column of sequence display section 111. If a value is set in the "Break" column of sequence display section 111, the sequence is paused after processing of that row is completed.

[0083] The sequence edit button 112, when selected by operating the operation unit 14, allows the contents of the sequence display unit 111 to be edited. By selecting the sequence edit button 112, the order of the sequence, the contents of the data to be output, etc. can be set.

[0084] The send button 113 starts the sequence when selected by operating the operation unit 14 .

[0085] The synchronization button 114 is a toggle button, and by selecting it through the operation of the operation unit 14, it is possible to select whether or not to synchronize when resuming sequences within the same module.

[0086] When the synchronization button 114 is set to "Sync OFF," synchronization is not performed and the sequence of only the corresponding output is resumed. When the synchronization button 114 is set to "Sync ON," the two outputs in the same module are synchronized and the sequence is resumed.

[0087] 4 shows the sequence setting screen 201 when the total number of outputs is four using both the primary module 2 and the secondary module 3. The sequence setting screen 201 allows the setting of a sequence for one output.

[0088] 4, sequence display section 211 displays the set sequence pattern, similar to sequence display section 111 in Fig. 3. The set sequence pattern is output for each row in numerical order of the "Block No." column of sequence display section 211. If a value is set in the "Break" column of sequence display section 211, the sequence is paused after processing of that row is completed.

[0089] The sequence edit button 212, when selected by operating the operation unit 14, allows the contents of the sequence display section 211 to be edited. By selecting the sequence edit button 212, the order of the sequence, the contents of the data to be output, etc. can be set.

[0090] The send button 213 starts the sequence when selected by operating the operation unit 14.

[0091] The synchronization setting button 214 is a button for setting the outputs to be synchronized, and when selected by operating the operation unit 14, a synchronization setting screen 301 as shown in FIG. 5 is displayed.

[0092] 5, primary module selection button 311 and secondary module selection button 312 are used to select the module to be synchronized, and are in the form of a combo box, allowing selection from a list or direct input by operating operation unit 14. By allowing the module to be synchronized to be selected in this way using a combo box, unnecessary buttons other than the selected module are not displayed, preventing user confusion.

[0093] The synchronization selection buttons 313, 314, 315, and 316 are used to select the output to be synchronized, and are toggle buttons. By selecting the button by operating the operation unit 14, it is possible to select whether or not to synchronize the output of the corresponding slot when the sequence is resumed.

[0094] If the display of the synchronization selection buttons 313, 314, 315, and 316 is "OFF," synchronization is not performed and the sequence is not output when the sequence is restarted. If the display of the synchronization selection buttons 313, 314, 315, and 316 is "ON," the corresponding output is synchronized when the sequence is restarted and the sequence is output.

[0095] In this way, in the above-described embodiment, the setting of the data signal to be output is made so that the output to be resumed in synchronization when the sequence is resumed is set, thereby allowing the user to arbitrarily set the output to be synchronized.

[0096] Furthermore, the synchronization setting screen 301 allows a module to be selected, and outputs to be synchronized from among the outputs of the selected module can be arbitrarily set.

[0097] This prevents user confusion because even if three or more modules are inserted but only two modules are to be synchronized, buttons other than those for the selected modules are not displayed.

[0098] Furthermore, the setting for synchronization of outputs within one module is limited to whether or not to synchronize, while the setting for synchronization of outputs from multiple modules is set for each output individually.

[0099] In this way, by providing a setting screen according to the maximum number of items that can be synchronized, the user can perform the desired settings with fewer operations.

[0100] In this embodiment, the measuring device 11 is shown as being equipped with an operation unit 14, a display unit 15, and a device control unit 16, but a personal computer connected to the measuring device 11 may also be configured to perform the functions of the operation unit 14, the display unit 15, and the device control unit 16.

[0101] While an embodiment of the present invention has been disclosed, it will be apparent to one skilled in the art that modifications may be made thereto without departing from the scope of the present invention, and it is intended that all such modifications and equivalents be included in the following claims. [Explanation of symbols]

[0102] 1 Sequence pattern generator 2 Primary Module 3 Secondary Modules 14 Control section 15 Display 16 Device control section 27 Primary 1st Data Multiplexing Unit 28 Primary Secondary Data Multiplexing Unit 29 Primary control section 37 Secondary 1st Data Multiplexing Unit 38 Secondary data multiplexing unit 39 Secondary control section 101 Sequence setting screen 111 Sequence display section 112 Sequence Edit Button 113 Send button 114 Sync button 201 Sequence setting screen 211 Sequence display section 212 Sequence Edit Button 213 Send button 214 Sync Settings Button 301 Sync settings screen 311 Primary module selection button 312 Secondary module selection button 313, 314, 315, 316 Sync selection buttons

Claims

1. A sequence pattern generator (1) capable of mounting at least one module (2, 3) having at least one data signal output, the total number of data signal outputs being two or more, A sequence pattern generating device having a device control unit (16) that displays a setting screen on a display unit (15) for allowing a user to set an output to be resumed synchronously when a sequence is resumed, in a setting for one of the data signals to be output.

2. 2. The sequence pattern generating device according to claim 1, wherein the device control unit allows a user to select the module and displays a synchronization setting screen (301) on the display unit to allow the user to select whether or not to resume the output of the selected module in synchronization when the sequence is resumed.

3. 3. The sequence pattern generating device according to claim 1, wherein, when only one module having two outputs is installed, the device control unit displays a sequence setting screen (101) on the display unit to allow the user to select only whether or not to resume the sequence synchronously when the sequence is resumed, thereby allowing the user to make the selection.

4. A setting method for a sequence pattern generator (1) capable of mounting at least one module (2, 3) having at least one data signal output, the total number of the data signal outputs being two or more, comprising: A method for setting a sequence pattern generator, comprising a device control step (S1) of displaying a setting screen for prompting a user to set an output to be resumed synchronously when a sequence is resumed, in setting one of the data signals to be output.

5. 5. The method for setting a sequence pattern generator according to claim 4, wherein the device control step includes a selection step (S2) of displaying a synchronization setting screen (301) for allowing a user to select the module and select whether or not to resume the output of the selected module in synchronization when the sequence is resumed, thereby allowing the user to make the selection.

6. 6. The method for setting a sequence pattern generator according to claim 4, wherein the device control step, when only one module having two outputs is installed, displays a sequence setting screen (101) that allows the user to select only whether or not to resume the sequence synchronously when the sequence is resumed, thereby allowing the user to make the selection.

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