Display device

Abstract

To provide a display device capable of forming an overlap pattern superimposed on or arranged adjacent to a wiring and improving a driving speed by reducing resistance of the wiring.SOLUTION: A display device includes a gate line formed integrally with a first gate electrode of a plurality of first thin film transistors displayed on a display region, a second active layer of a plurality of second thin film transistors arranged on the first thin film transistors, a second gate electrode, and an overlap pattern connected to the gate line. The overlap pattern includes a first overlap pattern arranged on an isolation insulation layer and formed of substantially the same material as the second active layer, and a second overlap pattern arranged on the first overlap pattern.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] Image display devices, which display various information on a screen, are a key technology in the information and communications era and are evolving toward thinner, lighter, more portable, and higher performance. As a result, various display devices such as liquid crystal displays (LCDs), electroluminescence displays (ELs), and quantum dot displays (QDs) are now being used.

[0003] Among electroluminescence (EL) displays, organic light-emitting displays (OLEDs) that use organic materials as light-emitting layers are widely used. OLEDs are self-emitting devices that have low power consumption, fast response speeds, high luminous efficiency, high brightness, and a wide viewing angle. OLEDs display images through a number of sub-pixels arranged in a matrix. Each of the sub-pixels includes a pixel circuit consisting of a light-emitting element and a number of transistors that independently drive the light-emitting element.

[0004] The organic light emitting display (OLED) has been increasing in resolution and area in order to provide high quality image information.

[0005] However, as the resolution increases and the area becomes larger, the wiring resistance within the panel increases, which makes it difficult to support high-speed driving. Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention provides a display device that can reduce the resistance of the high-resistance wiring and improve driving speed by further forming an overlapping pattern that overlaps or is adjacent to the high-resistance wiring and connecting the high-resistance wiring to the overlapping pattern. [Means for solving the problem]

[0007] A display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area, a first active layer disposed on the display area, a first gate electrode disposed overlapping the first active layer with the first active layer and a first gate insulating layer sandwiched therebetween, and a first transistor including a first source electrode and a first drain electrode passing through the first gate insulating layer and connected to the first active layer, a gate line formed integrally with the first gate electrode, an isolation insulating layer disposed on the first gate insulating layer, a second active layer disposed on the display area and on the isolation insulating layer, and a second transistor including a first gate electrode and a first source electrode and a first drain electrode connected to the first active layer. a second gate electrode overlapping the second active layer with a second gate insulating layer sandwiched therebetween, a second interlayer insulating layer disposed on the second gate insulating layer, and a second source electrode and a second drain electrode connected to the second active layer through the second gate insulating layer and the second interlayer insulating layer; and an overlapping pattern disposed on the isolation insulating layer and connected to the gate line, the overlapping pattern including a first overlapping pattern disposed on the isolation insulating layer and made of the same material as the second active layer, and a second overlapping pattern disposed on the first overlapping pattern.

[0008] Here, a contact hole connecting the first overlapping pattern and the gate line may be disposed in the isolation insulating layer.

[0009] At least one contact hole may be disposed on the display area.

[0010] The first overlapping pattern and the second active layer may be formed of an oxide semiconductor.

[0011] The metal forming the second overlapping pattern may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0012] The overlapping pattern may be arranged to be smaller than the width of the gate line so as to completely overlap the gate line.

[0013] The overlapping pattern may include an overlapping pattern line and an overlapping pattern electrode, the overlapping pattern electrode being disposed overlapping the first gate electrode, and the overlapping pattern line being disposed overlapping the gate line.

[0014] The gate line may be arranged to be smaller than the width of the overlapping pattern so as to completely overlap the overlapping pattern.

[0015] Meanwhile, the overlap pattern and the gate line may be arranged parallel to each other and spaced apart from each other, the gate line may include gate branches protruding toward the overlap pattern in a longitudinal direction of the gate line, and contact holes connecting the gate branches and the overlap pattern may be arranged on overlapping regions where the gate branches overlap a portion of the overlap pattern.

[0016] Meanwhile, the overlapping pattern and the gate line may be disposed parallel to each other and spaced apart from each other, and the gate line may include gate branches protruding from a longitudinal direction of the gate line toward the overlapping pattern and a connecting pattern formed in the same layer as the second gate electrode, and the connecting pattern may be connected to the gate branches through first contact holes formed in a first overlapping region arranged to overlap the gate branches, and may be connected to the overlapping pattern through second contact holes formed in a second overlapping region arranged to overlap the overlapping pattern.

[0017] Here, one side of the connecting pattern may be connected to the second overlapping pattern on the second overlapping region.

[0018] The first contact hole may be formed through the second gate insulating layer and the isolation insulating layer disposed in the first overlapping region.

[0019] A second contact hole may be formed through the second gate insulating layer disposed in the second overlapping region.

[0020] The second gate electrode and the connecting pattern may be disposed on the second gate insulating layer.

[0021] The connection pattern may connect the gate line and the overlapping pattern.

[0022] Meanwhile, the display panel may include the gate line disposed in the display area, first and second extension lines formed by extending the gate line to the non-display area, the overlap pattern disposed overlapping the gate line in the display area, an extended overlap pattern disposed overlapping the first extension line in the non-display area, and a link line disposed overlapping the second extension line disposed in a link area of ​​the non-display area, wherein in the link area, the second extension line is connected to the link line via a third contact hole, and the first extension line is connected to the extended overlap pattern via a fourth contact hole.

[0023] The third and fourth contact holes may be formed through the isolation insulating layer.

[0024] The first extension line may be disposed adjacent to the gate line, and the second extension line may be disposed adjacent to the first extension line.

[0025] A first interlayer insulating layer may be further disposed between the first gate electrode and the isolation insulating layer.

[0026] Further details of the embodiments are included in the detailed description and accompanying drawings. [Effects of the Invention]

[0027] A display device according to an embodiment of the present invention further forms an overlapping pattern that overlaps or is adjacent to the wiring whose resistance increases, and by connecting the wiring whose resistance increases and the overlapping pattern, the resistance of the wiring whose resistance increases can be reduced, thereby improving the driving speed.

[0028] In addition, the display device according to the embodiment of the present invention has an advantage that the resistance of the wiring having an increased resistance is reduced by extending and arranging the gate line so as to be connected to the overlapping pattern and the link line, thereby improving the driving speed and reducing the bezel size.

[0029] The effects of the present invention are not limited to the above examples, and more diverse effects are included within the present specification. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a plan view showing a schematic structure of a display device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view showing a display device according to an embodiment of the present invention. [Figure 3] FIG. 2 is an enlarged plan view of area “A” in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line II' in FIG. [Figure 5] FIG. 10 is a plan view showing a display device according to another embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view taken along line II-II' in FIG. 5. [Figure 7] FIG. 10 is a plan view showing a display device according to still another embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view taken along line III-III' in FIG. 7. [Figure 9]FIG. 10 is a plan view showing a display device according to still another embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view taken along line IV-IV' in FIG. [Figure 11] FIG. 10 is a plan view showing a display device according to still another embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view taken along line VV' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The same reference numerals refer to substantially the same components throughout the specification. In the following description, if it is determined that a detailed description of known techniques or configurations related to the present invention may unnecessarily obscure the gist of the present invention, such detailed description will be omitted. In describing some embodiments, the same components will be typically described at the beginning and may be omitted in other embodiments.

[0032] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited to these terms. These terms are used only to distinguish one component from another.

[0033] The features of the various embodiments of this specification may be partially or fully combined or combined with each other, and various technical interlocking and driving mechanisms may be possible, and each embodiment may be implemented independently of the others, or may be implemented together in a linked relationship.

[0034] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0035] FIG. 1 is a plan view showing the schematic structure of a display device according to one embodiment of the present invention, FIG. 2 is a cross-sectional view showing a display device according to one embodiment of the present invention, FIG. 3 is an enlarged plan view of region "A" in FIG. 1, and FIG. 4 is a cross-sectional view along II' in FIG. 3.

[0036] 1 to 4, a display device 100 according to an embodiment of the present invention includes a display panel 10 for displaying images and a panel driver for driving the display panel 10. The panel driver includes a data driver 20, gate drivers 40A and 40B, and a timing controller 30.

[0037] The timing controller 30 generates a data control signal and a gate control signal for controlling the driving timing of the data driver 20 and the gate drivers 40A and 40B, respectively, and supplies them to the data driver 20 and the gate drivers 40A and 40B. The timing controller 30 processes image data and supplies it to the data driver 20.

[0038] The data driver 20 is controlled in response to a data control signal supplied from the timing controller 30, and can convert the image data supplied from the timing controller 30 into an analog data signal and supply it to the data lines DL of the display panel 10.

[0039] The gate drivers 40A and 40B may be implemented as a GIP (Gate in Panel) circuit formed directly on the non-display area NA in the form of a thin film transistor. The gate drivers 40A and 40B may be disposed in the non-display area NA on at least one of the left and right sides of the display panel 10.

[0040] The gate drivers 40A and 40B can output gate signals while shifting the level of the gate voltage in response to a gate control signal supplied from the timing controller 30. The gate drivers 40A and 40B can output gate signals through gate lines GL.

[0041] Here, a link region LK may be disposed to connect the gate drivers 40A and 40B to the gate lines GL of the display panel 10. Specifically, the output lines (see 45 in FIG. 11) of the gate drivers 40A and 40B may extend to the link region LK, and the gate lines GL may also extend to the link region LK. The output lines of the gate drivers 40A and 40B and the gate lines GL may be connected to each other via link lines Ln in the link region LK, but this is not limiting, and the output lines and the gate lines GL may be integrally formed.

[0042] The display panel 10 includes a display area AA that embodies a screen for displaying an input image, and a non-display area NA located on at least one side of the display area AA.

[0043] The non-display area NA is an area where an input image is not displayed, and sub-pixels SP are not arranged therein, but signal lines and gate drivers 40A and 40B can be arranged therein.

[0044] In the display area AA, sub-pixels SP connected to intersecting data lines DL and gate lines GL may be arranged in a matrix. Each of the sub-pixels SP may include a light emitting element 500, at least one driving transistor 100 electrically connected to the light emitting element 500, and at least one switching transistor 200, as shown in FIG.

[0045] The substrate 101 supporting the switching transistor 200 and the driving transistor 100 may be made of a plurality of polyimides (PI). When the substrate 101 is made of polyimide (PI), the display device manufacturing process may be performed with a support substrate made of glass disposed under the substrate 101, and the support substrate may be released after the display device manufacturing process is completed. After the support substrate is released, a back plate for supporting the substrate 110 may be disposed under the substrate 101. The substrate may be made of glass or a flexible plastic material.

[0046] A multi-buffer layer 112 and a lower buffer layer 115 may be disposed on the substrate 101 as the buffer layer 110. The multi-buffer layer 112 may retard the diffusion of moisture and / or oxygen that has penetrated into the substrate 101. The multi-buffer layer 112 may be formed by stacking silicon nitride (SiNx) and silicon oxide (SiOx) on each other at least once.

[0047] The lower buffer layer 115 can protect the second active layer 220 and block various types of defects from entering from the substrate 101. The lower buffer layer 115 can be made of a-Si, silicon nitride (SiNx), silicon oxide (SiOx), or the like.

[0048] The driving transistor 100 may be disposed on the buffer layer 110. The driving transistor 100 may operate such that a driving current flows between a high voltage supply line and a low voltage supply line according to a data voltage stored in the storage capacitor. As shown in FIG. 2 , the driving transistor 100 may include a first gate electrode 130 electrically connected to a second drain electrode 245 of the switching transistor 200, a first source electrode 142 connected to the high voltage supply line, a first drain electrode 145 connected to the light emitting element 500, and a first active layer 120 forming a channel between the first source electrode and the first drain electrode 142, 145.

[0049] In other words, the driving transistor 100 may include a first active layer 120, a first gate electrode 130, a first source electrode 142, and a first drain electrode 145. The first gate electrode 130 is located in the same layer as the gate line GL. Gate Line GL electrically connected 1000 duplicate patterns can overlap with.

[0050] A first active layer 120 of the driving transistor 100 may be disposed on the buffer layer 110. The first active layer 120 may include low temperature polysilicon (LTPS). Polysilicon material has high mobility (100 cm 2 / Vs or more), low energy consumption and excellent reliability, it can be applied to a gate driver and / or multiplexer (MUX) for a driving element that drives a thin film transistor for a display element, and can be applied as an active layer of a driving thin film transistor in a display device according to an embodiment. Polysilicon can be formed by depositing an amorphous silicon (a-Si) material on the buffer layer 110 and performing a dehydrogenation process and a crystallization process, and the polysilicon can be patterned to form the first active layer 120.

[0051] The first active layer 120 may include a first channel region 120a in which a channel is formed when the driving transistor 100 is driven, and a first source region 120b and a first drain region 120c on either side of the first channel region 120a. The first source region 120b refers to a portion of the first active layer 120 connected to the first source electrode 142, and the first drain region 120c refers to a portion of the first active layer 120 connected to the first drain electrode 145. The first channel region 120a, the first source region 120b, and the first drain region 120c may be formed by ion doping (impurity doping) of the first active layer 120. The first source region 120b and the first drain region 120c may be formed by ion doping a polysilicon material. Here, the first channel region 120a may refer to a portion of the polysilicon material that is not ion doped.

[0052] A first gate insulating layer 125 may be disposed on the first active layer 120 of the driving transistor 100. The first gate insulating layer 125 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the first gate insulating layer 125 to connect the first source electrode 142 and the first drain electrode 145 of the driving transistor 100 to the first source region 120b and the first drain region 120c of the first active layer 120 of the driving transistor 100, respectively.

[0053] The first gate electrode 130 of the driving transistor 100 is disposed on the first gate insulating layer 125. The first gate electrode 130 can be formed by forming a metal layer such as molybdenum (Mo) on the first gate insulating layer 125 and patterning the metal layer. The first gate electrode 130 can be disposed on the first gate insulating layer 125 so as to overlap the first channel region 120a of the first active layer 120 of the driving transistor 100.

[0054] Here, while forming the first gate electrode 130 on the first gate insulating layer 125, a light-shielding pattern 210 may be further disposed on the region where the switching transistor 200 is disposed. The light-shielding pattern 210 may be disposed to prevent the second active layer 220, which will be described later, from being exposed to light and being activated.

[0055] The first interlayer insulating layer 305 may be disposed on the first gate insulating layer 125 and the first gate electrode 130. The first interlayer insulating layer 305 may be used as an insulating layer for separating the first gate electrode 130 from the first active layer 120 disposed on the first gate electrode 130. The first interlayer insulating layer 305 may be stabilized by a hydrogenation heat treatment process of the first active layer 120. The first interlayer insulating layer 305 may be made of, for example, silicon nitride (SiNx). The first interlayer insulating layer 305 may be made of silicon nitride (SiNx) to provide hydrogen to the first active layer 120 of the driving transistor 100 during a hydrogenation process on the first active layer 120.

[0056] An isolation insulating layer 300 may be further disposed on the first interlayer insulating layer 305. The isolation insulating layer 300 may be made of, for example, silicon oxide (SiOx). The isolation insulating layer 300 may be made of silicon oxide (SiOx) to prevent hydrogen ions from flowing into the second active layer 220. If the second active layer 220 is formed of an oxide semiconductor layer, the inflow of hydrogen ions may cause a problem of degrading normally-off characteristics. Therefore, an isolation insulating layer 300 made of oxide may be further disposed to prevent hydrogen ions from flowing into the second active layer 220. The isolation insulating layer 300 may also be used as a buffer film for forming the switching transistor 200. Contact holes may be formed in the isolation insulating layer 300, the first interlayer insulating layer 305, and the first gate insulating layer 125 to expose the first source region 120b and the first drain region 120c of the first active layer 120 of the driving transistor 100.

[0057] The second active layer 220 of the switching transistor 200 may be disposed on the isolation insulating layer 300. In addition, an overlapping pattern 1000 may be disposed on the isolation insulating layer 300 in a region where the driving transistor 100 is formed.

[0058] The overlapping pattern 1000 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 that are arranged to overlap the gate line GL and / or the first gate electrode 130 .

[0059] The first overlapping pattern 1010 may be formed on the isolation insulating layer 300 from the same material as the second active layer 220. The second overlapping pattern 1020 may be formed on the first overlapping pattern 1010 from a single metal or multiple metals.

[0060] 3 and 4, the overlap pattern 1000 may be arranged to overlap the gate line GL and the first gate electrode 130. The overlap pattern 1000 may include an overlap pattern line 1100 and an overlap pattern electrode 1200. The overlap pattern electrode 1200 may be arranged to correspond to the first gate electrode 130. Alternatively, in another embodiment described later, the overlap pattern electrode 1200 may not be arranged to overlap the first gate electrode 130, but may be arranged to serve as a branch for connecting to the gate line GL. Here, the overlap pattern electrode 1200 may be selectively formed.

[0061] The overlap pattern 1000 is disposed on the display area AA and may be narrower than the width of the gate line GL, so that the overlap pattern 1000 can be disposed to completely overlap the gate line GL.

[0062] The overlap pattern 1000 may be connected to the first gate line GL through a contact hole CNT. The contact hole CNT may be formed through the isolation insulating layer 300 and the first interlayer insulating layer 305 in an area where the overlap pattern 1000 and the gate line GL overlap. A plurality of contact holes CNT may be arranged to connect the overlap pattern 1000 to the gate line GL. Although the first interlayer insulating layer 305 is shown in the drawing, the first interlayer insulating layer 305 may be selectively arranged on the isolation insulating layer 300.

[0063] The gate line GL is arranged to connect to the first overlap pattern 1010, and the second overlap pattern 1020 may be arranged on the first overlap pattern 1010. The first overlap pattern 1010 may be made of an oxide semiconductor, similar to the second active layer 220. The metal forming the second overlap pattern 1020 may be at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0064] Therefore, the overlap pattern 1000 of the display device according to the embodiment of the present invention can be connected to the gate line GL to serve as redundancy, i.e., the overlap pattern 1000 can reduce the resistance of the gate line GL to accommodate high-speed driving of the display device.

[0065] In turn, the switching transistor 200 may include a second active layer 220 , a second gate electrode 230 , a second gate insulating layer 225 , a second source electrode 242 and a second drain electrode 245 .

[0066] The second active layer 220 disposed on the isolation insulating layer 300 may be made of an oxide semiconductor. Because oxide semiconductor materials have a wider band gap than silicon materials, electrons cannot cross the band gap in the off state, resulting in a low off-current. Therefore, a thin film transistor including an active layer made of an oxide semiconductor can maintain a short on-time and a long off-time. Therefore, it is suitable for switching purposes. Furthermore, its low off-current reduces the amount of storage capacitance, making it suitable for high-resolution display devices. Specifically, the second active layer 220 may be made of a metal oxide, such as various metal oxides, such as IGZO (indium-gallium zinc-oxide).

[0067] The second active layer 220 may be formed by depositing a metal oxide on the isolation insulating layer 300, performing a heat treatment for stabilization, and then patterning the metal oxide. The second active layer 220 may include a second channel region 220a in which a channel is formed when the switching transistor 200 is driven, a second source region 220b on either side of the second channel region 220a, and a second drain region 220c on either side of the second channel region 220a. The second source region 220b refers to a portion of the second active layer 220 connected to the second source electrode 242, and the second drain region 220c refers to a portion of the second active layer 220 connected to the second drain electrode 245. The second channel region 220a, the second source region 220b, and the second drain region 220c are defined by ion doping (impurity doping) of the second active layer 220. The second source region 220b and the second drain region 220c may be formed by ion doping a polysilicon material.

[0068] The second gate insulating layer 225 may be disposed on the second active layer 220, the overlapping pattern 1000, and the isolation insulating layer 300. The second gate insulating layer 225 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). As another example, the second gate insulating layer 225 may be patterned to overlap the second channel region 220a of the second active layer 220.

[0069] The second gate electrode 230 may be disposed on the second gate insulating layer 225. The second gate electrode 230 may be formed by forming and patterning a metal layer, such as molybdenum (Mo), on the second gate insulating layer 225. The second gate electrode 230 may be patterned to overlap the second channel region 220a of the second active layer 220 and the second gate insulating layer 225.

[0070] The second interlayer insulating layer 405 may be disposed on the second gate electrode 230 and the second gate insulating layer 225. The second interlayer insulating layer 405 may be a passivation layer. Contact holes may be formed on the second gate insulating layer 225 and the second interlayer insulating layer 405 to expose the first source electrode 142, the first drain electrode 145, the second source electrode 242, and the second drain electrode 245.

[0071] The light emitting element 500 includes an anode electrode 510 , a cathode electrode 550 , and a light emitting stack 530 formed between the anode electrode 510 and the cathode electrode 550 .

[0072] The anode electrode 510 may be independently disposed on the second planarization layer 420 for each subpixel. The anode electrode 510 may be connected to the pixel connecting electrode 450 exposed through a second pixel contact hole CH2 penetrating the second planarization layer 420. Here, the pixel connecting electrode 450 may be connected to the first drain electrode 145 exposed through a first pixel contact hole CH1 penetrating the first planarization layer 410.

[0073] The anode electrode 510 is disposed on the second planarization layer 420 so as to overlap not only the light-emitting area defined by the bank 570 but also at least one of the driving transistor and the switching transistor 100, 200, thereby increasing the light-emitting area.

[0074] The bank 570 may be formed to expose the anode electrode 510 and have a light-emitting area. The bank 570 may be formed in the active area using an opaque material (e.g., black) to prevent light interference between adjacent subpixels, or may be formed in the non-display area NA to overlap not only the display area AA but also the gate drivers 40A and 40B. In this case, the bank 570 may include a light-blocking material made of at least one of color pigment, organic black, and carbon.

[0075] The light-emitting stack 530 may be formed by stacking a hole-related layer, an organic light-emitting layer, and an electron-related layer, in this order or in reverse order, on the anode electrode 510. The light-emitting stack 520 is formed by a manufacturing process using a fine metal mask (FMM). Here, to prevent damage to adjacent light-emitting stacks 520 and / or banks 570 due to the fine metal mask (FMM), spacers may be further disposed on the banks 570. The spacers may be formed of the same material as the banks 570 and the first and second planarization layers 410 and 420.

[0076] The cathode electrode 530 may be formed on the top and side surfaces of the light emitting stack 520 to face the anode electrode 510 across the light emitting stack 520. The cathode electrode 530 may be formed to be shared by all sub-pixels arranged in the display area AA. An encapsulation unit 600 is disposed on the substrate 101 on which the cathode electrode 530 is formed.

[0077] The encapsulating unit 600 can prevent external moisture or oxygen from penetrating into the light emitting device 500, which is vulnerable to external moisture or oxygen. To this end, the encapsulating unit 600 includes a plurality of inorganic encapsulating layers 610, 620 and an organic encapsulating layer 650 disposed between the plurality of inorganic encapsulating layers 610, 620, with the inorganic encapsulating layer 620 being disposed as the uppermost layer. Here, the encapsulating unit 600 may include at least two inorganic encapsulating layers 610, 630 and at least one organic encapsulating layer 650. In the present invention, a structure of the encapsulating unit 600 in which the organic encapsulating layer 650 is disposed between the first and second inorganic encapsulating layers 610, 620 will be described as an example.

[0078] The organic encapsulation layer 650 is disposed between the inorganic encapsulation layers 610 and 620 and serves as a buffer to relieve stress between the layers, thereby enhancing planarization performance. In some embodiments, the organic encapsulation layer 650 may also serve to buffer stress caused by bending of the substrate 101 of the bending-type display device. The organic encapsulation layer 650 may be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, PCL, or silicon oxycarbonate (SiOC).

[0079] The first inorganic encapsulation layer 610 is formed on the substrate 101 on which the cathode electrode 530 is formed, so as to be closest to the light emitting element 500. The first inorganic encapsulation layer 610 may be formed of an inorganic insulating material that can be deposited at low temperatures, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Therefore, since the first inorganic encapsulation layer 610 is deposited in a low temperature atmosphere, it is possible to prevent the light emitting stack 520, which is vulnerable to high temperature atmospheres, from being damaged during the deposition process of the first inorganic encapsulation layer 610.

[0080] The second inorganic encapsulation layer 620 is formed on the substrate 101 on which the organic encapsulation layer 650 is formed, covering the top and side surfaces of the organic encapsulation layer 650 and the first inorganic encapsulation layer 610. As a result, the second inorganic encapsulation layer 620 minimizes or blocks external moisture and oxygen from penetrating into the first inorganic encapsulation layer 610 and the organic encapsulation layer 650. The second inorganic encapsulation layer 620 is formed from an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0081] In this manner, the display device according to the embodiment of the present invention can provide redundancy for the gate line GL by overlapping the overlap pattern 1000 on the gate line GL and connecting the overlap pattern 1000 to the gate line GL. Therefore, by overlapping the overlap pattern 1000 on the gate line GL and connecting the overlap pattern 1000 to the gate line GL, the wiring resistance of the gate line GL can be reduced, thereby improving the driving speed.

[0082] FIG. 5 is a plan view showing a display device according to another embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line II-II' in FIG.

[0083] Here, in order to avoid redundant explanation and to simplify the explanation, FIGS. 5 and 6 will be explained with reference to FIGS. 1 to 4.

[0084] 5 and 6, according to another embodiment of the present invention, the overlap pattern 1000-1 may be arranged in an area larger than the width of the gate line GL. The gate line GL may be arranged narrower than the width of the overlap pattern 1000-1 so as to completely overlap with the overlap pattern 1000-1. In other words, the overlap pattern 1000-1 may be arranged wider than the width of the gate line GL, so that the gate line GL may completely overlap with the overlap pattern 1000-1.

[0085] On the isolation insulating layer 300, a second active layer 220 may be disposed on the region where the switching transistor 200 is formed, and an overlap pattern 1000-1 may be disposed on the region where the driving transistor 100 is formed so as to be formed in an area larger than the width of the gate line GL.

[0086] The overlapping pattern 1000-1 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 that are arranged to overlap the first gate line GL and the first gate electrode 130.

[0087] The first overlap pattern 1010 may be formed on the isolation insulating layer 300 from the same material as the second active layer 220. The first overlap pattern and the second active layer may be formed from an oxide semiconductor. The second overlap pattern 1020 may be formed on the first overlap pattern 1010 from a single metal or multiple metals. The second overlap pattern 1020 may be formed from at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0088] The overlapping pattern 1000-1 may be disposed to overlap the gate line GL and the first gate electrode 130. The overlapping pattern 1000-1 may be disposed to correspond to a portion of the first gate electrode 130.

[0089] The overlap pattern 1000-1 may be connected to the gate line GL through a contact hole CNT. A plurality of contact holes CNT may be disposed in the isolation insulating layer 300 and the first interlayer insulating layer 305 in the region where the overlap pattern 1000-1 and the gate line GL overlap, thereby connecting the overlap pattern 1000-1 to the gate line GL. Although the first interlayer insulating layer 305 is shown in the drawing, the first interlayer insulating layer 305 may be selectively disposed on the isolation insulating layer 300.

[0090] The gate line GL is connected to the first overlap pattern 1010 through a contact hole CNT, and a second overlap pattern 1020 may be disposed on the first overlap pattern 1010 .

[0091] In this manner, the overlap pattern 1000-1 of the display device according to the embodiment of the present invention is connected to the gate electrode (GL) and serves as a redundancy. That is, by forming the width of the overlap pattern 1000-1 larger than that of the gate line (GL), the overlap pattern 1000-1 can further reduce the resistance of the gate line (GL) and can accommodate high-speed driving of the display device.

[0092] Furthermore, since an area larger than the width of the gate line GL is secured above the area where the gate electrode 130 is to be formed in the gate line GL, it is easy to form the contact hole CNT.

[0093] Therefore, in a display device according to another embodiment of the present invention, the overlap pattern 1000-1 on the driving transistor 100 is arranged to be wider than the gate line, and the overlap pattern 1000-1 is connected to the gate line GL, thereby further reducing the wiring resistance of the gate line GL and improving the driving speed.

[0094] FIG. 7 is a plan view showing a display device according to still another embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along line III-III' in FIG.

[0095] Here, in order to avoid redundant explanation and to simplify the explanation, FIGS. 7 and 8 will be explained with reference to FIGS. 1 to 4.

[0096] 7 and 8, according to another embodiment of the present invention, a duplicate pattern 1000-3 may be disposed spaced apart from a gate line GL and may be disposed parallel to the gate line GL, where the gate line GL may include a gate branch GL-1 protruding in the longitudinal direction of the gate line GL toward the duplicate pattern 1000-3.

[0097] The gate branch GL-1 may have an overlapping region OVA that overlaps a portion of the overlapping pattern 1000-3. A contact hole CNT that connects the gate branch GL-1 and the overlapping pattern 1000-3 may be disposed on the overlapping region OVA.

[0098] Specifically, on the isolation insulating layer 300, a second active layer 220 may be disposed in a region where the switching transistor 200 is disposed, and a first overlap pattern 1010 may be disposed in a region where the driving transistor 100 is disposed. The overlap pattern 1000-3 may be spaced apart from the gate line GL on the isolation insulating layer 300 so as not to overlap with the gate line GL in a plan view. In other words, the gate line GL and the overlap pattern 1000-3 may be disposed parallel to each other in a plan view. The gate line GL may include a gate branch GL-1 protruding toward the overlap pattern 1000-3 in a longitudinal direction of the gate line GL.

[0099] The overlapping pattern 1000-3 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 disposed on the isolation insulating layer 300. A portion of the overlapping pattern 1000-3 is disposed overlapping the gate branch portion GL-1.

[0100] The first overlapping pattern 1010 may be formed of the same material as the second active layer 220 disposed on the isolation insulating layer 300. The first overlapping pattern 1010 and the second active layer 220 may be formed of an oxide semiconductor. The second overlapping pattern 1020 may be formed of a single metal or multiple metals on the first overlapping pattern 1010. The second overlapping pattern 1020 may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0101] The gate line GL and the overlap pattern 1000-3 may be arranged parallel to each other on a plane, and thus spaced apart from each other. Here, a gate branch GL-1 may be disposed protruding from the gate line GL to connect the gate line GL and the overlap pattern 1000-3. Specifically, the gate branch GL-1 may be disposed to protrude toward the overlap pattern 1000-3 in the longitudinal direction of the gate line GL. The gate branch GL-1 may be disposed to overlap a portion of the overlap pattern 1000-3.

[0102] The overlap pattern 1000-3 may have an overlap region OVA that overlaps a portion of the gate branch portion GL-1. The overlap pattern 1000-3 may be connected to the gate line GL through a contact hole CNT. The contact hole CNT may be formed by penetrating the isolation insulating layer 300 and the first interlayer insulating layer 305 in the overlap region OVA, which is the region where the overlap pattern 1000-3 and the gate line GL overlap. A plurality of the contact holes CNT may be arranged to connect the overlap pattern 1000-3 and the gate branch portion GL-1. Although the first interlayer insulating layer 305 is shown in the drawing, the first interlayer insulating layer 305 may be selectively arranged on the isolation insulating layer 300.

[0103] The gate branch GL-1 is arranged to be connected to the first overlapping pattern 1010 through the contact hole CNT, and the second overlapping pattern 1020 may be arranged on the first overlapping pattern 1010.

[0104] In this manner, in the display device according to the embodiment of the present invention, the overlap pattern 1000-3 is connected to the gate line GL through the contact hole CNT in the overlap region OVA where the overlap pattern 1000-3 and the gate branch portion GL-1 overlap, so that the overlap pattern 1000-3 can serve as a redundancy for the gate line GL. That is, by separating the overlap pattern 1000-3 so as not to overlap the gate line GL and selectively arranging the gate branch portion GL-1 to overlap the overlap pattern 1000-3, the resistance of the gate line GL can be reduced while ensuring flexibility in the formation of the overlap pattern 1000-3, thereby enabling high-speed driving of the display device.

[0105] Therefore, in a display device according to another embodiment of the present invention, the overlap pattern 1000-3 is disposed at a distance from the gate line GL and is connected to the gate line GL via the gate branch portion GL-1, thereby reducing the wiring resistance of the gate line GL and improving the driving speed.

[0106] FIG. 9 is a plan view showing a display device according to still another embodiment of the present invention, and FIG. 10 is a cross-sectional view taken along line IV-IV' in FIG.

[0107] Here, in order to avoid redundant explanation and to simplify the explanation, FIGS. 1 to 4 will be cited to explain FIGS. 9 and 10. FIG.

[0108] 9 and 10, according to another embodiment of the present invention, a duplicate pattern 1000-4 may be disposed spaced apart from the gate line GL and may be disposed parallel to the gate line GL. Here, the gate line GL may include a gate branch GL-2 protruding in the longitudinal direction of the gate line GL toward the duplicate pattern 1000-4.

[0109] In addition, in a display device according to yet another embodiment of the present invention, a connecting pattern 1500 may be disposed to overlap the gate branch GL-2 and the overlapping pattern 1000-4. Here, the connecting pattern 1500 may be formed in the same layer as the second gate electrode 230. In other words, the connecting pattern 1500 may be formed on the second gate insulating layer 225 simultaneously with the second gate electrode 230.

[0110] The gate branch GL-2 may have an overlapping region that partially overlaps with the overlapping pattern 1000-4, but may not overlap. Although the drawing shows a partial overlapping region, the overlapping region may not be present.

[0111] The connecting pattern 1500 may have a first overlapping region OVA1 that is arranged to overlap the gate branch portion GL-2. A first contact hole CNT1 may be formed on the first overlapping region OVA1. The first contact hole CNT1 may connect the gate branch portion GL-2 and the connecting pattern 1500.

[0112] The connecting pattern 1500 may have a second overlapping region OVA2 that is arranged to overlap the overlapping pattern 1000-4. A second contact hole CNT2 may be formed on the second overlapping region OVA2. The second contact hole CNT2 may connect the overlapping pattern 1000-4 and the connecting pattern 1500.

[0113] Specifically, on the isolation insulating layer 300, a second active layer 220 may be disposed in a region where the switching transistor 200 is disposed, and a first overlap pattern 1010 may be disposed in a region where the driving transistor 100 is disposed. The overlap pattern 1000-4 may be spaced apart from the gate line GL on the isolation insulating layer 300 so as not to overlap with the gate line GL in a plan view. In other words, the gate line GL and the overlap pattern 1000-4 may be disposed parallel to each other in a plan view. The gate line GL may include a gate branch GL-2 protruding toward the overlap pattern 1000-4 in a longitudinal direction of the gate line GL.

[0114] The overlapping pattern 1000-4 may include a first overlapping pattern 1010 and a second overlapping pattern 1020 disposed on the isolation insulating layer 300. A portion of the overlapping pattern 1000-4 may overlap the connecting pattern 1500 and be connected to each other.

[0115] The first overlapping pattern 1010 may be formed of the same material as the second active layer 220 disposed on the isolation insulating layer 300. The first overlapping pattern 1010 and the second active layer 220 may be formed of an oxide semiconductor. The second overlapping pattern 1020 may be formed of a single metal or multiple metals on the first overlapping pattern 1010. The second overlapping pattern 1020 may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0116] The gate line GL and the overlapping pattern 1000-4 may be arranged parallel to each other on a plane, and thus spaced apart from each other. Here, to connect the gate line GL and the overlapping pattern 1000-4, a connecting pattern 1500 may be further disposed on the second gate insulating layer 225. One side of the connecting pattern 1500 may be arranged to overlap the overlapping pattern 1000-4, and the other side of the connecting pattern 1500 may be arranged to overlap the gate branch GL-2.

[0117] The connecting pattern 1500 can be arranged in various shapes depending on the arrangement structure of the gate line GL and the overlapping pattern 1000-4. In the drawings of the present invention, the overlapping pattern 1000-4 and the gate branch GL-2 are arranged perpendicular to each other, so the connecting pattern 1500 is shown arranged in a structure in which bent regions are formed to connect to each of the overlapping pattern 1000-4 and the gate branch GL-2.

[0118] The connection pattern 1500 may have a first overlapping region OVA1 overlapping a portion of the gate branch portion GL-2. In the first overlapping region OVA1, the gate branch portion GL-2 may be connected to the connection pattern 1500 through a first contact hole CNT1.

[0119] The connecting pattern 1500 may have a second overlapping region OVA2 that overlaps a portion of the overlapping pattern 1000-4. In the second overlapping region OVA2, the overlapping pattern 1000-4 may be connected to the connecting pattern 1500 through a second contact hole CNT2. Here, the connecting pattern 1500 may be connected to the second overlapping pattern 1020 of the overlapping pattern 1000-4.

[0120] Therefore, the gate branch GL-1 and the overlapping pattern 1000-4 can be connected to each other through the connecting pattern 1500.

[0121] The first contact hole CNT1 may be formed by penetrating the second gate insulating layer 225, the isolation insulating layer 300, and the first interlayer insulating layer 305, which are disposed in a first overlapping region OVA1, which is a region where the gate branch portion GL-2 and the connecting pattern 1500 overlap. The connecting pattern 1500 and the gate branch portion GL-2 may be connected through the first contact hole CNT1. Although the first interlayer insulating layer 305 is shown in the drawing, the first interlayer insulating layer 305 may be selectively disposed on the isolation insulating layer 300.

[0122] The second contact hole CNT2 may be formed by penetrating the second gate insulating layer 225 disposed in the first overlapping region OVA1, which is a region where the overlapping pattern 1000-4 and the connecting pattern 1500 overlap. The connecting pattern 1500 and the overlapping pattern 1000-4 may be connected to each other through the second contact hole CNT2.

[0123] In this manner, in the display device according to the embodiment of the present invention, the overlap pattern 1000-4 and the gate branch GL-2 are connected via the connection pattern 1500, so that the overlap pattern 1000-4 can serve as a redundancy for the gate line GL. That is, the overlap pattern 1000-4 is spaced apart from the gate line GL without overlapping it, and the connection pattern 1500 is arranged to overlap and connect the overlap pattern 1000-4 and the gate branch GL-2. This ensures flexibility in the formation of the overlap pattern 1000-4, reduces the resistance of the gate line GL, and enables high-speed driving of the display device.

[0124] Therefore, in a display device according to yet another embodiment of the present invention, the overlap pattern 1000-4 is disposed at a distance from the gate line GL, and the gate branch GL-1 and the overlap pattern 1000-4 are connected via the connection pattern 1500, thereby reducing the wiring resistance of the gate line GL and improving the driving speed.

[0125] FIG. 11 is a plan view showing a display device according to still another embodiment of the present invention, and FIG. 12 is a cross-sectional view taken along line IV-IV' in FIG.

[0126] Here, in order to avoid redundant explanation and to facilitate the explanation, FIGS. 11 and 12 will be explained with reference to FIGS. 1 to 4.

[0127] 11 and 12, a display device according to another embodiment of the present invention may include an overlap pattern 1000-5 arranged in the display area AA and an extended overlap pattern 1000-6 arranged in the non-display area NA, where the non-display area NA may include a link area LN connecting the gate driver 40A and the display panel 10.

[0128] Link lines LK connected to output lines 45 extending from the gate driver 40A may be disposed in the link region LN. The output lines 45 may be disposed on the first gate insulating layer 125, similar to the gate lines GL. The link lines LK may be disposed on the isolation insulating layer 300 in the non-display area NA.

[0129] The gate line GL may be integrally formed with a first extension line GL-5 and a second extension line GL-6, which are arranged to extend to the link area LN of the non-display area NA.

[0130] The overlapping pattern 1000-5 arranged on the display area AA can be arranged to overlap with the gate line GL.

[0131] In the link region LN of the non-display area NA, the overlap pattern 1000-5 may have an extended overlap pattern 1000-6 extending to the link region LN, and the extended overlap pattern 1000-6 may be arranged to overlap the first extension line GL-5. To connect the extended overlap pattern 1000-6 to the first extension line GL-5, a fourth contact hole CNT4 may be arranged in the area where the extended overlap pattern 1000-6 and the first extension line GL-5 overlap.

[0132] The first extension line GL-5 is disposed adjacent to the gate line GL, and the second extension line GL-6 is disposed adjacent to the first extension line GL-5.

[0133] In addition, the link line LK and the second extension line GL-6 may be arranged to overlap in the link area LN of the non-display area NA, and a third contact hole CNT3 may be arranged in the overlapping area to connect the link line LK and the second extension line GL-6.

[0134] Specifically, on the isolation insulating layer 300 in the display area AA, a second active layer 220 may be disposed on a region where the switching transistor 200 is disposed, and a first overlap pattern 1010 may be disposed on a region where the driving transistor 100 is disposed. In other words, an overlap pattern 1000-5 may be disposed on the isolation insulating layer 300 in the display area, overlapping with the gate line GL.

[0135] Then, on the isolation insulating layer 300 in the non-display area NA, the link line LK and the second extension line GL-6 can be connected via a third contact hole CNT3, and the extended overlap pattern 1000-6 and the first extension line GL-5 can be connected via a fourth contact hole CNT4.

[0136] The first overlapping pattern 1010 may be formed of the same material as the second active layer 220 disposed on the isolation insulating layer 300. The first overlapping pattern 1010 and the second active layer 220 may be formed of an oxide semiconductor. The second overlapping pattern 1020 may be formed of a single metal or multiple metals on the first overlapping pattern 1010. The second overlapping pattern 1020 may be formed of at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

[0137] In this manner, the overlap pattern 1000-5 of the display device according to the embodiment of the present invention is disposed overlapping the gate line GL, and the extended overlap pattern 1000-6 and the link line LK are connected to the first and second extension lines GL-5 and GL-6 disposed in the link region LN, which is the non-display region NA, via the third and fourth contact holes CNT3 and CNT4, respectively, so that the overlap pattern 1000-5 can serve as redundancy for the gate line GL. That is, by disposing the overlap pattern 1000-5 overlapping the gate line GL and connecting the link line LK and the extended overlap pattern 1000-6 in the non-display region NA via the first and second extension lines GL-5 and GL-6, the bezel size can be reduced and the resistance of the gate line GL can be reduced, thereby enabling high-speed driving of the display device.

[0138] Therefore, in a display device according to yet another embodiment of the present invention, the overlap pattern 1000-5 is extended to the non-display area NA, and the gate line GL is also extended to the non-display area NA, and the gate line GL and the overlap pattern 1000-5 are connected in the non-display area NA, thereby reducing the wiring resistance of the gate line GL and improving the driving speed.

[0139] From the above description, those skilled in the art will be able to make various changes and modifications within the scope of the technical concept of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims. [Explanation of symbols]

[0140] 100 Drive transistor 125 First gate insulating layer 130 gate electrode 200 Switching Transistor 300 Separation insulating layer 500 light-emitting elements 1000 duplicate patterns 1010 First overlapping pattern 1020 Second overlapping pattern 1100 overlapping pattern lines 1200 overlapping pattern electrodes 1500 Connecting Patterns GL Gate Line

Claims

1. A display device, a flexible substrate including a plurality of polyimide layers; a drive transistor including a first active layer having a low temperature polysilicon layer; a switching transistor including a second active layer having an oxide semiconductor layer; a first interlayer insulating layer disposed between the first active layer and the second active layer; an isolation insulating layer disposed on the first interlayer insulating layer; a first planarization layer disposed on the driving transistor and the switching transistor, the first planarization layer having a first contact hole connecting the driving transistor and an anode disposed in a light-emitting region; a second planarization layer disposed on the first planarization layer, the second planarization layer having a second contact hole connecting the driving transistor and the anode disposed in the light-emitting region; a bank disposed on the second planarization layer to expose the anode, the bank having different step structures on one side and the other side of the light emitting region; an overlapping pattern disposed on the isolation insulating layer and comprising the same material as the second active layer; Equipped with the first active layer is located under the isolation insulating layer, and the second active layer is located over the isolation insulating layer; The overlapping pattern is connected to a gate line.

2. The display device of claim 1 , wherein the banks comprise an opaque material.

3. 3. The display device of claim 2, wherein the opaque material is black.

4. The display device according to claim 1 , further comprising a spacer disposed on the bank.

5. The display device according to claim 4 , wherein the spacers are formed from the same material as the banks, the first planarization layer, or the second planarization layer.

6. The display device according to claim 1 , wherein the step structure of the bank overlaps with the first contact hole.

7. 2. The display device according to claim 1, wherein the bank comprises a light-shielding material containing at least one of a color pigment, organic black, and carbon.

8. 2. The display device according to claim 1, wherein the first interlayer insulating layer is made of silicon nitride, and the isolation insulating layer is made of silicon oxide.

9. a light-shielding pattern disposed under the switching transistor; The display device according to claim 1 , wherein the light-shielding pattern is disposed on the same layer as the gate electrode of the driving transistor.

10. 2. The display device of claim 1, wherein the driving transistor comprises a first gate electrode disposed under the isolation insulating layer, and a first source electrode and a first drain electrode respectively connected to the first active layer.

11. The overlapping pattern is a first overlapping pattern disposed on the isolation insulating layer and formed of the same material as the second active layer; a second overlapping pattern disposed on the first overlapping pattern; The display device of claim 1 , comprising:

12. The display device of claim 11 , wherein the first overlapping pattern and the second active layer are formed from an oxide semiconductor.

13. The display device of claim 11 , wherein the second overlapping pattern is formed from at least one of Mo / Ti, MoTi / Cu / MoTi, Mo / Al / Mo, and Ti / Al / Ti.

14. The display device of claim 1 , wherein the overlapping pattern has a width smaller than a width of the gate line so as to completely overlap the gate line.

15. the overlapping pattern and the gate line are spaced apart from each other so as to be arranged parallel to each other; the gate line includes gate branches configured to protrude from a length direction of the gate line toward the overlapping pattern, 2. The display device of claim 1, wherein third contact holes configured to connect each of the gate branches to the overlapping pattern are formed in regions where each of the gate branches overlaps a portion of the overlapping pattern.

16. the overlapping pattern further includes overlapping pattern lines and overlapping pattern electrodes; The overlapping pattern electrode is arranged to overlap the gate electrode of the driving transistor; and The display device according to claim 1 , wherein the overlapping pattern lines are arranged to overlap the gate lines.

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