Display circuit and display device for irregularly shaped screens

Abstract

This application discloses a display circuit and a display device for an irregular-shaped screen. The display circuit for the irregular-shaped screen includes a plurality of pixel circuits 10 arranged in a non-rectangular array in the irregular region of the irregular-shaped screen. The pixel circuits 10 located at both ends of each row of the pixel circuits 10 are edge pixel circuits, in which one of two adjacent edge pixel circuits is connected to the gate signal line of the Nth stage, and the other edge pixel circuit is connected to the gate signal line of the N+1th stage, where N is a natural number greater than 0. The voltage divider circuits are respectively connected to the two adjacent edge pixel circuits so that the accumulated voltages of the two adjacent edge pixel circuits are equal, and the control end of the voltage divider circuit is connected to the gate signal line of the N+Mth stage, where M is a natural number greater than 2. Based on the above method, the jagged effect when the irregular-shaped screen is displayed can be effectively weakened, and the display effect of the irregular-shaped screen can be improved.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority from a Chinese patent application entitled "DISPLAY CIRCUIT AND DISPLAY DEVICE FOR VARIOUS SCREENS" filed on September 8, 2022, and bearing application number 2022110952316, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the field of display technology, and in particular to a display circuit and display device for irregular screens. [Background technology]

[0003] With the development of the times, people's requirements for display screens are becoming higher and higher. In some specific applications, a special shaped screen with a special shaped screen display function needs to be adopted as the display screen to meet the specific needs of users.

[0004] The drawback of the prior art is that irregular-shaped screens generally have arc-shaped or other unconventional shaped edges, and therefore the display area of ​​the irregular-shaped screen is also generally composed of pixel circuits arranged in an array, which makes the jagged effect of the display screen corresponding to the edges of the irregular-shaped screen more severe than that of a rectangular screen, thereby resulting in a poor display effect of the irregular-shaped screen. Summary of the Invention

[0005] The main technical problem that this application aims to solve is how to reduce the jagged effect when an irregular-shaped screen is displayed and improve the display effect of the irregular-shaped screen.

[0006] In order to solve the above technical problems, the first technical solution adopted by this application is as follows: a display circuit for an irregular-shaped screen, the display circuit comprising a plurality of pixel circuits arranged in a non-rectangular array in an irregular-shaped area of ​​the irregular-shaped screen, the pixel circuits located at both ends of each row of pixel circuits are edge pixel circuits, one of two adjacent edge pixel circuits is connected to a gate signal line of an Nth stage and the other pixel circuit is connected to a gate signal line of an N+1th stage, N is a natural number greater than 0, voltage divider circuits are respectively connected to the two adjacent edge pixel circuits so that the accumulated voltages of the two adjacent edge pixel circuits are equal, and control terminals of the voltage divider circuits are connected to the gate signal line of the N+Mth stage, M is a natural number greater than 2.

[0007] Here, the display circuit includes a plurality of pixel circuits arranged in a rectangular array in a rectangular region of the irregular-shaped screen and a plurality of pixel circuits arranged in a non-rectangular array in the irregular-shaped screen.

[0008] Here, the edge pixel circuits located at each end of the pixel circuits in each row include a first edge pixel circuit and a second edge pixel circuit, the first edge pixel circuit and the second edge pixel circuit are adjacent to each other, the first edge pixel circuit is connected to the Nth stage gate signal line, and the second edge pixel circuit is connected to the N+1th stage gate signal line.

[0009] Here, pixel circuits other than the edge pixel circuits among the plurality of pixel circuits are referred to as non-edge pixel circuits, and non-edge pixel circuits located in the same row as and adjacent to the first edge pixel circuit or the second edge pixel circuit are referred to as adjacent edge pixel circuits, and adjacent first edge pixel circuits, second edge pixel circuits, and adjacent edge pixel circuits are connected to data signal lines of the same row.

[0010] Here, the pixel circuit located at one end of the pixel circuits in the Nth row is defined as the first edge pixel circuit, and the pixel circuit located at one end of the pixel circuits in the N+1th row and adjacent to the first edge pixel circuit is defined as the second edge pixel circuit, and the first edge pixel circuit is connected to the gate signal line of the Nth stage, and the second edge pixel circuit is connected to the gate signal line of the N+1th stage.

[0011] Here, pixel circuits other than the edge pixel circuits among the multiple pixel circuits are referred to as non-edge pixel circuits, a non-edge pixel circuit located in the same row as and adjacent to a first edge pixel circuit is referred to as a first adjacent edge pixel circuit, a non-edge pixel circuit located in the same row as and adjacent to a second edge pixel circuit is referred to as a second adjacent edge pixel circuit, and the adjacent first edge pixel circuit, second edge pixel circuit, first adjacent edge pixel circuit and second adjacent edge pixel circuit are connected to data signal lines of the same row.

[0012] where M is equal to 2.

[0013] Here, the pixel circuit includes a first switch transistor and a storage capacitor, a driving end of the first switch transistor is connected to a corresponding gate signal line, a first end of the first switch transistor is connected to a corresponding data signal line, a second end of the first switch transistor is connected to a first end of the storage capacitor, and a second end of the storage capacitor is connected to a corresponding common electrode.

[0014] Here, the voltage divider circuit includes a second switch transistor, a first terminal of the second switch transistor is connected to a first terminal of a storage capacitor in one of the two adjacent edge pixel circuits, a second terminal of the second switch transistor is connected to a first terminal of a storage capacitor in another of the two adjacent edge pixel circuits, and a drive terminal of the second switch transistor is connected to the gate signal line of the N+Mth stage.

[0015] Here, in order to solve the above technical problems, the second technical solution adopted by this application is as follows: A display device, which includes a backlight module and the display circuit.

[0016] The beneficial effects of the present application are as follows: Different from the prior art, in the technical solution of the present application, the pixel circuits located at both ends of the pixel circuits in each row are edge pixel circuits, so that one of two adjacent edge pixel circuits is connected to the Nth stage gate signal line to receive the Nth stage gate signal, and the other of the two adjacent edge pixel circuits is connected to the N+1th stage gate signal line to receive the N+1th stage gate signal line, and the voltage divider circuit connected to the N+Mth stage gate signal line via the control end neutralizes the voltages of the storage capacitors in the two adjacent edge pixel circuits when receiving the N+Mth stage gate signal, so that the storage voltages of the two adjacent edge pixel circuits are equal, and the two adjacent edge pixel circuits can both display with the brightness corresponding to the storage voltages after the voltages are neutralized, thereby reducing the jagged effect caused by the pixel circuits at the edge of the irregular-shaped screen when displaying, and improving the display effect of the irregular-shaped screen. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a structural schematic diagram of an embodiment of a display circuit of the irregular screen of the present application; [Figure 2] FIG. 10 is a structural schematic diagram of another embodiment of the display circuit of the irregular screen of the present application; [Figure 3] 1 is a structural schematic diagram of an embodiment of a display device of the present application; [Figure 4] 1 is a schematic diagram of a display area of ​​an embodiment of the irregularly shaped screen of the present application. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, the present application will be described in more detail in conjunction with the accompanying drawings and embodiments. It is particularly pointed out that the following embodiments are only used to explain the present application and do not limit the scope of the present application. It should be understood that the following embodiments are only a part of the embodiments of the present application, but are not all of them. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can obtain without inventive work are all included in the protection scope of the present application.

[0019] References to "embodiments" in this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present application. Appearances of the term in various places in this specification do not necessarily refer to the same embodiment, nor are they exclusive independent or alternative embodiments to other embodiments. Those skilled in the art will understand, both explicitly and implicitly, that the embodiments described herein can be combined with other embodiments.

[0020] It should be noted that in the description of this application, unless otherwise clearly stated and limited, the terms "mounting," "installing," "connecting," and "connecting" should be understood broadly. For example, they may be fixed, detachable, or integral connections, mechanical or electrical connections, direct connections, or spaced connections via intermediate media. Those skilled in the art can understand the specific meanings of the above terms depending on the specific case.

[0021] First, it should be noted that the total display area D of the irregular-shaped screen can include an irregular-shaped area and a rectangular area. Referring to FIG. 4, FIG. 4 is a schematic diagram of the display area of ​​one embodiment of the irregular-shaped screen of the present application. As shown in FIG. 4, the total display area D of the irregular-shaped screen may include the irregular-shaped area A shown in the figure. Pixel circuits arranged in an array in the irregular-shaped area A constitute a non-rectangular display area, and the total display area D of the irregular-shaped screen may also include the rectangular area B shown in the figure, and pixel circuits arranged in an array in the rectangular area B constitute a rectangular display area.

[0022] This application first discloses a display circuit for an irregular-shaped screen, and reference is made to Figure 1, which is a structural schematic diagram of one embodiment of the display circuit for an irregular-shaped screen of this application. As shown in Figure 1, the display circuit includes a plurality of pixel circuits 10 arranged in a non-rectangular array in the irregular-shaped area of ​​the irregular-shaped screen, and the structure of the liquid crystal layer, electrode layer, etc. corresponding to the pixel circuits 10 is not shown in the figure.

[0023] The pixel circuits 10 located at both ends of each pixel circuit 10 in each row can be recorded as edge pixel circuits, that is, the edge pixel circuits are pixel circuits located at the edges of the irregular-shaped screen.

[0024] One of two adjacent edge pixel circuits in every row of pixel circuits 10 is connected to the gate signal line of the Nth stage, and the other of the two adjacent edge pixel circuits is connected to the gate signal line of the N+1th stage, where N is a natural number greater than 0, so that the two adjacent edge pixel circuits can be displayed according to the gate signals transmitted by the corresponding gate signal lines.

[0025] Specifically, each pixel circuit 10 may include a first switch transistor 101 and a storage capacitor 102 .

[0026] The driving terminal of the first switch transistor 101 is connected to a corresponding gate signal line, the first terminal of the first switch transistor 101 is connected to a corresponding data signal line, the second terminal of the first switch transistor 101 is connected to a first terminal of the storage capacitor 102, and the second terminal of the storage capacitor 102 is connected to a corresponding common electrode.

[0027] The driving end of the first switch transistor 101 is used to receive a corresponding gate signal (e.g., a signal transmitted by the gate signal line of the Nth stage in FIG. 1), the first end of the first switch transistor 101 is used to receive a corresponding data signal (e.g., a signal transmitted by the data signal line of the M+2th stage in FIG. 1), the second end of the first switch transistor 101 is connected to a first end of the storage capacitor 102, and the second end of the storage capacitor 102 is used to receive a corresponding common electrode voltage signal (e.g., a signal transmitted by the common electrode in FIG. 1). The storage capacitor 102 can store electrical energy according to a voltage difference between the received data signal and the common electrode voltage signal, thereby operating the liquid crystal layer in the pixel circuit 10 based on the stored electrical energy, and the pixel circuit 10 can perform a corresponding display operation. Here, the data signal can also be referred to as a pixel voltage signal.

[0028] One of the two adjacent edge pixel circuits may be a first edge pixel circuit 11, and the other of the two adjacent edge pixel circuits may be a second edge pixel circuit 12. Both the first edge pixel circuit 11 and the second edge pixel circuit 12 are pixel circuits 10, i.e., as shown in FIG. 1 , in the first edge pixel circuit 11 or the second edge pixel circuit 12, the switch transistor shown is the first switch transistor 101 in the first edge pixel circuit 11 or the second edge pixel circuit 12, and the capacitor shown is the storage capacitor 102 of the first edge pixel circuit 11 or the second edge pixel circuit 12.

[0029] The display circuit further includes a voltage divider circuit 13, which is respectively connected to the two adjacent edge pixel circuits, and whose control ends are connected to the gate signal line of the (N+M)th stage, where M is a natural number greater than 2. The voltage divider circuit is used to neutralize the voltages of the storage capacitors 102 of the two adjacent edge pixel circuits when receiving a gate signal from the gate signal line of the (N+M)th stage, thereby making the storage voltages of the two adjacent edge pixel circuits equal to each other and allowing the two adjacent edge pixel circuits to display with brightness corresponding to the neutralized voltage.

[0030] Specifically, in a display circuit, the gate signals of all gate signal lines are output one by one according to the normal stage number, from smallest to largest, so that the pixel circuits of each row on the display screen (e.g., irregularly shaped screen) can receive the corresponding gate signals one by one, so that a plurality of pixel circuits are displayed one by one on the display screen until one image is displayed, that is, the signal transmitted by the gate signal line of the Nth stage, the signal transmitted by the gate signal line of the N+1th stage, and the signal transmitted by the gate signal line of the N+Mth stage are output sequentially from front to back.

[0031] The voltage divider circuit 13 further includes a second switch transistor 131, a first terminal of which is connected to a first terminal of the storage capacitor 102 in one of the two adjacent edge pixel circuits, a second terminal of which is connected to a first terminal of the storage capacitor 102 in the other of the two adjacent edge pixel circuits, and a drive terminal of the second switch transistor 131 is connected to the gate signal line of the N+Mth stage.

[0032] Based on the gate signal output manner, the first edge pixel circuit 11 can first receive the signal transmitted by the gate signal line of the Nth stage and charge the storage capacitor 102 in the first edge pixel circuit 11 according to the corresponding data signal; the second edge pixel circuit 12 can then receive the signal transmitted by the gate signal line of the (N+1)th stage and charge the storage capacitor 102 of the second edge pixel circuit 12 according to the corresponding data signal; then the second switch transistor 131 is turned on after receiving the signal transmitted by the gate signal line of the (N+M)th stage, and the storage capacitor 102 of the first edge pixel circuit 11 and the storage capacitor 102 of the second edge pixel circuit 12 are connected in parallel, so that the higher-voltage capacitor of the two storage capacitors 102 discharges / charges the lower-voltage capacitor, and the voltages of the two storage capacitors 102 can be neutralized after being connected in parallel.

[0033] Assuming that the display brightness displayed by the first edge pixel circuit 11 based on the initial voltage after the storage capacitor 102 therein is charged is a first brightness, and the display brightness displayed by the first edge pixel circuit 11 based on the initial voltage after the storage capacitor 102 therein is charged is a second brightness, then based on the above display circuit and gate signal output method, both the first edge pixel circuit 11 and the second edge pixel circuit 12 can be made to display at a third brightness, where the third brightness is between the first brightness and the second brightness.

[0034] Specifically, as shown in Figure 1, M may be 2, i.e., the signal transmitted by the gate signal line of the (N+M)th stage is the signal transmitted by the gate signal line of the (N+2)th stage. Regarding the output order of the signals transmitted by the gate signal lines, the signal transmitted by the gate signal line of the (N+2)th stage comes after the signal transmitted by the gate signal line of the (N+1)th stage, and the signal transmitted by the gate signal line of the (N+1)th stage comes after the signal transmitted by the gate signal line of the (N)th stage.

[0035] Based on the above method, after the storage capacitors 102 in the first edge pixel circuit 11 and the second edge pixel circuit 12 have both completed charging, the parallel connection of the two storage capacitors 102 can be immediately promoted, thereby completing the voltage neutralization between the capacitors. This prevents the first pixel circuit 11 and the second pixel circuit 12 from displaying for an excessively long time based on the initial voltage of the corresponding storage capacitor 102, thereby further shortening the time when the irregular screen jagged effect appears and improving the display effect of the irregular screen.

[0036] Specifically, the first switch transistor 101 and the second switch transistor 131 are both thin film field effect transistors.

[0037] Specifically, the thin film field effect transistor may include a substrate layer, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and an electrode layer.

[0038] Different from the prior art, in the technical solution of the present application, the pixel circuits located at both ends of the pixel circuits in each row are edge pixel circuits, so that one of two adjacent edge pixel circuits is connected to the N-th stage gate signal line to receive the N-th stage gate signal, and the other of the two adjacent edge pixel circuits is connected to the N+1-th stage gate signal line to receive the N+1-th stage gate signal line, and the voltage divider circuit connected to the N+M-th stage gate signal line via the control end neutralizes the voltages of the storage capacitors of the two adjacent edge pixel circuits when receiving the N+M-th stage gate signal, so that the storage voltages of the two adjacent edge pixel circuits are equal, and the two adjacent edge pixel circuits can both display with the brightness corresponding to the storage voltages after the voltage neutralization, thereby reducing the jagged effect caused by the pixel circuits at the edges of the irregular-shaped screen when displaying, and improving the display effect of the irregular-shaped screen.

[0039] In one embodiment, the display circuitry can include a plurality of pixel circuits 10 arranged in a non-rectangular array within an irregular region of the irregular screen, as well as a plurality of pixel circuits 10 arranged in a rectangular array within a rectangular region of the irregular screen.

[0040] Specifically, as shown in Fig. 4, the display circuit not only includes pixel circuits 10 located in the irregular-shaped area A, but also includes pixel circuits 10 located in the rectangular area B. That is, whether it is two adjacent edge pixel circuits in the irregular-shaped area A or two adjacent edge pixel circuits in the rectangular area B, one of them can be connected to the Nth stage gate signal line and the other of them can be connected to the N+1th stage gate signal line, thereby improving the display effect of the irregular-shaped screen.

[0041] In one embodiment, as shown in FIG. 1, in a plurality of pixel circuits 10, an edge pixel circuit located at one end of the Nth row of pixel circuits 10 includes a first edge pixel circuit 11 and a second edge pixel circuit 12, and the first edge pixel circuit 11 and the second edge pixel circuit 12 are installed adjacent to each other.

[0042] The first edge pixel circuit 11 is connected to the gate signal line of the Nth stage, and the second edge pixel circuit 12 is connected to the gate signal line of the (N+1)th stage.

[0043] Specifically, in the irregular screen, the edge pixel circuit located at one end (e.g., the left end) of each row of pixel circuits may include a first edge pixel circuit 11 and a second edge pixel circuit 12, and the first edge pixel circuit 11 and the second edge pixel circuit 12 may be arranged vertically, with the first edge pixel circuit 11 adjacent to the pixel circuit 10 in the previous row and the second edge pixel circuit 12 adjacent to the pixel circuit 10 in the next row.

[0044] Based on the above method, each group of first edge pixel circuits 11 and second edge pixel circuits 12 in all pixel circuits 10 can be displayed with the corresponding third brightness, thereby reducing the jagged edge effect on the irregular screen and improving the display effect of the irregular screen.

[0045] Optionally, pixel circuits 10 other than edge pixel circuits among the plurality of pixel circuits 10 are designated as non-edge pixel circuits, and a non-edge pixel circuit located in the same row as and adjacent to the first edge pixel circuit 11 or the second edge pixel circuit 12 is designated as an adjacent edge pixel circuit 14.

[0046] The first edge pixel circuit 11, the second edge pixel circuit 12 and the adjacent edge pixel circuit 14 are connected to the data signal line of the same stage.

[0047] The adjacent edge pixel circuits 14 are located at the non-edges of the irregular screen.

[0048] Specifically, the first ends of the first switch transistors 101 of the adjacent first edge pixel circuit 11, second edge pixel circuit 12 and adjacent edge pixel circuit 14 are all connected to the same data line, thereby receiving the corresponding data signal (the signal transmitted by the data signal line of the (M+1)th stage, as shown in FIG. 1).

[0049] Based on the above method, the first edge pixel circuit 11 / the second edge pixel circuit 12 and the adjacent edge pixel circuit 14 are displayed with different but similar brightness, which further reduces the jagged effect of the irregular screen and improves the display effect of the irregular screen.

[0050] In one embodiment, as shown in FIG. 1, in a plurality of pixel circuits 10, the edge pixel circuit located at one end of the pixel circuits 10 in the Nth row is defined as the first edge pixel circuit 11, and the edge pixel circuit located at one end of the pixel circuits in the N+1th row and adjacent to the first edge pixel circuit 11 is defined as the second edge pixel circuit 12.

[0051] The first edge pixel circuit 11 is connected to the gate signal line of the Nth stage, and the second edge pixel circuit 12 is connected to the gate signal line of the (N+1)th stage.

[0052] Specifically, in the irregular-shaped screen, the number of pixel circuits located at one end (for example, the left side) of each row of pixel circuits is one.

[0053] Referring to Figure 2, Figure 2 is a structural schematic diagram of another embodiment of a display circuit for a irregular screen of the present application. As shown in Figure 2, in all pixel circuits 10, the edge pixel circuit located at the left end of the Nth row is the first edge pixel circuit 11, and the edge pixel circuit located at the left end of the N+1th row is the second edge pixel circuit 12, and the first edge pixel circuit 11 is located adjacent to the second edge pixel circuit 12.

[0054] Based on the above method, the first edge pixel circuits 11 and the second edge pixel circuits 12 of each group in all pixel circuits 10 can be made to display with the corresponding third brightness, thereby reducing the jagged edge effect on the irregular screen and improving the display effect of the irregular screen.

[0055] Optionally, pixel circuits 10 other than the edge pixel circuits among the plurality of pixel circuits 10 are designated as non-edge pixel circuits, a non-edge pixel circuit located in the same row as and adjacent to the first edge pixel circuit 11 is designated as a first adjacent edge pixel circuit 15, and a non-edge pixel circuit located in the same row as and adjacent to the second edge pixel circuit 12 is designated as a second adjacent edge pixel circuit 16.

[0056] Adjacent first edge pixel circuit 11, second edge pixel circuit 12, first adjacent edge pixel circuit 15, and second adjacent edge pixel circuit 16 are connected to data signal lines in the same row.

[0057] 2, the pixel circuit located in the same row as and adjacent to the left edge pixel circuit of the Nth row pixel circuit is the first adjacent edge feeding circuit 15, and the pixel circuit located in the same row as and adjacent to the left edge pixel circuit of the N+1th row pixel circuit is the second adjacent edge feeding circuit 16. The first adjacent edge feeding circuit 15 and the second adjacent edge feeding circuit 16 are respectively located at the non-edges of the irregular-shaped screen.

[0058] Specifically, the first ends of the first switch transistors 101 of the first edge pixel circuit 11, the second edge pixel circuit 12, the first adjacent edge feeding circuit 15 and the second adjacent edge feeding circuit 16 are all connected to the same data line, thereby receiving the corresponding data signal (the signal transmitted by the data signal line of the (M+1)th stage shown in FIG. 2).

[0059] According to the above method, the first adjacent edge feeding circuit 15 can be displayed at a first brightness, the second adjacent edge feeding circuit 16 can be displayed at a second brightness, and the first edge pixel circuit 11 / second edge pixel circuit 12 can be displayed at a third brightness, where the third brightness is between the first brightness and the second brightness, thereby further reducing the jagged edge effect of the irregular screen and improving the display effect of the irregular screen.

[0060] The present application further discloses a display device, and reference is made to Fig. 3, which is a structural schematic diagram of one embodiment of the display device of the present application. As shown in Fig. 3, the display device 20 includes a backlight module 21 and a display circuit 22. The display circuit 22 may be any display circuit described in the above embodiments, and the description thereof will be omitted here.

[0061] Different from the prior art, in the technical solution of the present application, the pixel circuits located at both ends of each row of pixel circuits are edge pixel circuits, so that one of two adjacent edge pixel circuits is connected to the N-th stage gate signal line to receive the N-th stage gate signal, and the other of the two adjacent edge pixel circuits is connected to the N+1-th stage gate signal line to receive the N+1-th stage gate signal line, and the voltage divider circuit connected to the N+M-th stage gate signal line via the control end neutralizes the voltages of the storage capacitors of the two adjacent edge pixel circuits when receiving the N+M-th stage gate signal, so that the storage voltages of the two adjacent edge pixel circuits are equal, and the two adjacent edge pixel circuits can both display with the brightness corresponding to the storage voltages after the voltages are neutralized, thereby reducing the jagged effect caused by the pixel circuits at the edges of the irregular-shaped screen when displaying, and improving the display effect of the irregular-shaped screen.

[0062] In the description of this application, reference to the reference terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that the particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, general expressions of the above terms are not necessarily limited to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more examples or examples. Furthermore, unless mutually inconsistent, those skilled in the art may combine different embodiments or examples described herein, and may combine features from different embodiments or examples.

[0063] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance or the number of technical features indicated. Thus, features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of this application, "plurality" means at least two, e.g., two, three, etc., unless otherwise clearly and specifically defined.

[0064] Any process or method description in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing specific logical functions or process steps. Furthermore, the scope of the preferred embodiments of the present application may include alternative implementations in which functions are not performed in the order shown or described, but are performed substantially simultaneously or in reverse order, depending on the function, as will be understood by those skilled in the art to which the embodiments of the present application pertain.

[0065] The logic and / or steps depicted in the flowcharts or otherwise described herein may be considered, for example, as a particular ordered listing of executable instructions for performing logical functions, and may be embodied in any computer-readable medium for use by or in combination with an instruction execution system, apparatus, or device (such as a personal computer, server, network device, or other system that fetches and executes instructions from an instruction execution system, device, or appliance). For purposes of this specification, a "computer-readable medium" may refer to a device that includes, or is used in combination with, an instruction execution system, apparatus, or device that can contain, store, communicate, propagate, or transmit a program. More specific examples (non-exhaustive list) of computer-readable media include an electrical connection having one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), a fiber device, and a portable optical disk read-only memory (CD-ROM). Furthermore, the computer readable medium may be paper or other suitable medium on which the program is printed, for example via optical scanning of the paper or other medium, and subsequently edited, interpreted or processed in any other suitable manner as required to obtain said program electronically, and then stored in the memory of a computer.

[0066] The above are embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by utilizing the contents of the specification and drawings of the present application, or any directly or indirectly applicable to other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display circuit for an irregular screen including a plurality of pixel circuits and a voltage dividing circuit, the plurality of pixel circuits are arranged in a non-rectangular array in the irregular-shaped area of ​​the irregular-shaped screen, and pixel circuits located at both ends of each row of the pixel circuits are edge pixel circuits, wherein one of two adjacent edge pixel circuits is connected to an Nth stage gate signal line, and the other edge pixel circuit is connected to an N+1th stage gate signal line, where N is a natural number greater than 0; the voltage divider circuits are connected to two adjacent edge pixel circuits so that the accumulated voltages of the two adjacent edge pixel circuits are equal, and a control terminal of the voltage divider circuit is connected to a gate signal line of an N+Mth stage, where M is a natural number greater than 2; the pixel circuit includes a first switch transistor and a storage capacitor, a driving end of the first switch transistor is connected to a corresponding gate signal line, a first end of the first switch transistor is connected to a corresponding data signal line, a second end of the first switch transistor is connected to a first end of the storage capacitor, and a second end of the storage capacitor is connected to a corresponding common electrode; the voltage divider circuit includes a second switch transistor, a first end of the second switch transistor is connected to a first end of the storage capacitor in one of the two adjacent edge pixel circuits, a second end of the second switch transistor is connected to a first end of the storage capacitor in another of the two adjacent edge pixel circuits, and a driving end of the second switch transistor is connected to a gate signal line of the N+M stage.

2. 2. The display circuit for the irregular-shaped screen according to claim 1, wherein the display circuit includes a plurality of the pixel circuits arranged in a rectangular array in a rectangular area of ​​the irregular-shaped screen and a plurality of the pixel circuits arranged in a non-rectangular array on the irregular-shaped screen.

3. The edge pixel circuit located at one end of the pixel circuit of the Nth row includes a first edge pixel circuit and a second edge pixel circuit, and the first edge pixel circuit and the second edge pixel circuit are disposed adjacent to each other; 2. The display circuit of claim 1, wherein the first edge pixel circuit is connected to the gate signal line of the Nth stage, and the second edge pixel circuit is connected to the gate signal line of the N+1th stage.

4. a pixel circuit other than the edge pixel circuit among the plurality of pixel circuits is defined as a non-edge pixel circuit, and a non-edge pixel circuit located in the same row as and adjacent to the first edge pixel circuit or the second edge pixel circuit is defined as an adjacent edge pixel circuit; 4. The display circuit for a irregular screen according to claim 3, wherein the first edge pixel circuit, the second edge pixel circuit and the adjacent edge pixel circuit are connected to data signal lines of the same stage.

5. 4. The display circuit for a irregular screen according to claim 3, wherein the first edge pixel circuit of a current row is located adjacent to the pixel circuit of a previous row, and the second edge pixel circuit of the current row is located adjacent to the pixel circuit of a next row.

6. the edge pixel circuit located at one end of the pixel circuits in the Nth row is a first edge pixel circuit, and the edge pixel circuit located at one end of the pixel circuits in the (N+1)th row and adjacent to the first edge pixel circuit is a second edge pixel circuit; 2. The display circuit of claim 1, wherein the first edge pixel circuit is connected to the gate signal line of the Nth stage, and the second edge pixel circuit is connected to the gate signal line of the N+1th stage.

7. Among the plurality of pixel circuits, pixel circuits other than the edge pixel circuit are defined as non-edge pixel circuits, and the non-edge pixel circuit located in the same row as the first edge pixel circuit and adjacent thereto is defined as a first adjacent edge pixel circuit, and the non-edge pixel circuit located in the same row as the second edge pixel circuit and adjacent thereto is defined as a second adjacent edge pixel circuit, 7. The display circuit for a irregular screen according to claim 6, wherein the adjacent first edge pixel circuit, the second edge pixel circuit, the first adjacent edge pixel circuit and the second adjacent edge pixel circuit are connected to data signal lines of the same stage.

8. 2. The irregular-shaped screen display circuit according to claim 1, wherein the signals transmitted by the N-th stage gate signal lines, the N+1-th stage gate signal lines, and the N+M-th stage gate signal lines are output in order from front to back.

9. 2. The irregular-shaped screen display circuit of claim 1, wherein said M is equal to 2.

10. 10. The irregular-shaped screen display circuit of claim 9, wherein the signal transmitted by the gate signal line of the N+Mth stage is the signal transmitted by the gate signal line of the N+2th stage, and in terms of signal output order, the signal transmitted by the gate signal line of the N+2th stage is later than the signal transmitted by the gate signal line of the N+1th stage, and the signal transmitted by the gate signal line of the N+1th stage is later than the signal transmitted by the gate signal line of the Nth stage.

11. 2. The display circuit for a multi-shaped screen as claimed in claim 1, wherein the first switch transistor and the second switch transistor are both thin film field effect transistors.

12. 12. The display circuit of claim 11, wherein the thin film field effect transistor comprises a substrate layer, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer and an electrode layer.

13. A display device comprising a backlight module and the display circuit of claim 1.

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