Method and system for determining parasitics for semiconductor or flat panel display manufacturing

Abstract

Some embodiments provide a method for calculating parasitic parameters of a pattern fabricated on an integrated circuit (IC) substrate. The method receives as input a definition of a wire structure. The method rasterizes the wire structure to generate several images. Before rasterizing the wire structure, the method, in some embodiments, decomposes the wire structure into several components and then rasterizes them individually. The method then uses the images as input to a neural network, which then calculates the parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include undesirable parasitic capacitance effects on the wire structure. Additionally or alternatively, these parameters include undesirable parasitic resistance and / or inductance effects on the wire structure.

Description

[Technical Field]

[0001] The present disclosure relates to methods and systems for determining parasitics for semiconductor or flat panel display manufacturing. [Background technology]

[0002] Three common types of charged particle beam lithography are unshaped (Gaussian) beam lithography, shaped charged particle beam lithography, and multi-beam lithography. In all types of charged particle beam lithography, a charged particle beam delivers energy to a resist-coated surface, exposing the resist.

[0003] In the production or manufacturing of semiconductor devices, such as integrated circuits, optical lithography can be used to fabricate semiconductor devices. Optical lithography is a printing process that uses a lithography mask, or photomask, fabricated from a reticle to form patterns on a substrate, such as a semiconductor or silicon wafer, to create integrated circuits. Other substrates can include flat panel displays or even other reticles. Extreme ultraviolet (EUV) or X-ray lithography is also considered a type of optical lithography. One or more reticles can contain circuit patterns corresponding to individual layers of an integrated circuit, and this pattern can be imaged onto an area on a substrate coated with a layer of radiation-sensitive material known as photoresist or resist. Once a patterned layer is created, the layer can undergo various other processes, such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes are used to finish individual layers within the substrate. If several layers are required, the entire process, or variations thereof, is repeated for each new layer. Ultimately, multiple devices or combinations of integrated circuits will be present on the substrate. These integrated circuits may then be separated from one another by dicing or sawing and then packaged in individual packages. In the more general case, patterns on the substrate may be used to define artifacts such as display pixels or magnetic recording heads.

[0004] In the production or manufacturing of semiconductor devices, such as integrated circuits, semiconductor devices can also be manufactured using maskless direct write. Maskless direct write is a printing process in which charged particle beam lithography is used to form patterns on substrates, such as semiconductor or silicon wafers, to create integrated circuits. Other substrates can include flat panel displays, imprint masks for nanoimprinting, or even reticles. The desired pattern for a layer is written directly onto a surface, which in this case is also the substrate. Once the patterned layer is created, the layer can undergo various other processes, such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes are used to finish individual layers within the substrate. If several layers are required, the entire process, or variations thereof, is repeated for each new layer. Some of the layers may be written using optical lithography, while other layers may be written using maskless direct write to produce the same substrate. Ultimately, a combination of multiple devices or integrated circuits will be present on the substrate. These integrated circuits are then separated from each other by dicing or sawing and then packaged into individual packages. In the more general case, patterns on a surface can be used to define artifacts such as display pixels or magnetic recording heads.

[0005] Modeling parasitic effects in IC designs is very important. Parasitic effects refer to unwanted parasitic capacitance, resistance, and inductance on components (e.g., on wire segments) in an IC design. Various parasitic effects can affect circuit delay, energy consumption, and power distribution. They can also introduce noise sources and other effects that affect reliability. To evaluate the effect of interconnect parasitics on circuit performance, they need to be accurately modeled.

[0006] As manufacturing technologies have become more complex, various techniques have evolved over time to model parasitic components, including unwanted capacitance, resistance, and inductance. However, in recent years, modeling and extracting parasitic components has become more difficult at smaller process geometries and newer process nodes. Many of the difficulties arise from the increased effects of manufacturing process variations and other types of manufacturability issues at smaller geometries. Existing techniques are also relatively slow at calculating parasitic parameters. Summary of the Invention

[0007] Some embodiments provide a method for calculating parasitic parameters of a pattern fabricated on an integrated circuit (IC) substrate. The method receives as input a definition of a wire structure. The method rasterizes the wire structure (e.g., generates a pixel-based definition of the wire structure) to generate several images. Before rasterizing the wire structure, the method, in some embodiments, decomposes the wire structure into several components (e.g., several wires, wire segments, or wire structure portions) and then rasterizes them individually. The method then uses the images as input to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include undesired parasitic capacitance effects on the wire structure. Additionally or alternatively, these parameters include undesired parasitic resistance and / or inductance effects on the wire structure.

[0008] Some embodiments provide a method for training a neural network to extract parasitic capacitances from a semiconductor design. The method receives as input a semiconductor design including several wire structures. The method performs a rasterization operation that rasterizes each wire structure into several 2D images. For each wire structure, the method uses these images as input to a machine-trained network (e.g., a neural network) that generates one or more curve shapes to represent the wire structure. The method then trains the neural network using the set of curve shapes for each wire segment.

[0009] The above Summary is intended to serve as a brief introduction to some embodiments of the present invention. It is not intended to be an introduction or summary of all inventive subject matter disclosed herein. The following Detailed Description and the Drawings referenced in the Detailed Description further describe the embodiments described in the Summary as well as other embodiments. Therefore, to understand all embodiments described herein, the Summary, Detailed Description, Drawings, and Claims should be thoroughly considered. Furthermore, claimed subject matter is not limited by the illustrative details in the Summary, Detailed Description, and Drawings.

[0010] The novel features of the invention are set forth in the appended claims. However, for purposes of illustration, certain embodiments of the invention are set forth in the following figures. [Brief explanation of the drawings]

[0011] [Figure 1] 1 illustrates a digital design flow as known in the art. [Figure 2] 1 illustrates an exemplary bus structure known in the art. [Figure 3] 1 shows a detailed flow for calculating parasitics, as known in the art. [Figure 4A] 1 illustrates a wire structure known in the art. [Figure 4B] 1 illustrates a wire structure known in the art. [Figure 5] 1 shows a flow for calculating parasitics as known in the art. [Figure 6A] 1 illustrates a flow for calculating parasitics according to some embodiments. [Figure 6B] 1 illustrates a flow for calculating parasitics according to some embodiments. [Figure 7] 1 illustrates a flow for calculating parasitics according to some embodiments. [Figure 8] 1 illustrates a neural network architecture, according to some embodiments. [Figure 9] 1 illustrates the generation of training data, according to some embodiments. [Figure 10] 1 illustrates a flow for calculating parasitics using tiles, according to some embodiments. [Figure 11] 1 illustrates tiled data according to some embodiments. [Figure 12] 1 illustrates a flow for training a neural network to generate tiles, according to some embodiments. [Figure 13] 1 illustrates a neural network for computing parasitics using tiles, according to some embodiments. [Figure 14] FIG. 1 is a schematic diagram of a GPU system diagram, according to some embodiments. [Figure 15] FIG. 1 is a schematic diagram of a GPU system diagram, according to some embodiments. [Figure 16] 1 illustrates a capacitance matrix for a 3x3 bus structure according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and explained. However, it will be clear and apparent to those skilled in the art that the invention is not limited to the described embodiments, and that the invention may be practiced without some of the specific details and examples described.

[0013] Semiconductor wiring, more commonly referred to as interconnects, forms complex 3D geometries that introduce unwanted parasitic capacitance, resistance, and inductance. Effectively addressing these unwanted parasitic effects is a process that typically requires circuit and mask designers to perform multiple iterations to create a manufacturable design that meets specifications, has high yield, and offers good reliability. Therefore, electronic design automation (EDA) requires accurate and proper extraction and modeling of parasitic effects (e.g., unwanted capacitance, inductance, and / or resistance effects) in IC designs. As manufacturing technologies have become more complex, various techniques have evolved over time to model parasitics, including unwanted capacitance, resistance, and inductance.

[0014] This extraction / modeling step becomes increasingly difficult at smaller process geometries / newer process nodes. Many of the difficulties arise from the increasing effects of manufacturing process variations and other types of manufacturability issues at smaller geometries. Although advances in processing technology have reduced the effects of resistance over the years and low-k dielectric materials have reduced the effects of capacitance, parasitic effects continue to dominate or become increasingly dominant due to the continued shrinking of feature sizes (e.g., wire widths).

[0015] Various parasitic effects can affect circuit delay, energy consumption, and power distribution. They can also introduce noise sources and other effects that affect reliability. To evaluate the effect of interconnect parasitics on circuit performance, they must be accurately modeled. Figure 1 shows a simplified digital design flow traditionally used, in which parasitics are extracted from the circuit layout in the back-end portion of the flow and considered in gate-level simulation in the front-end portion of the flow. Typically, interconnect parasitics affect delay / timing, leading to changes in the gate-level netlist and necessitating additional iterations through floorplanning and / or place and route, resulting in a modified circuit layout. More complex digital design flows can replace the back-end portion with other steps, such as virtual prototyping, power grid synthesis, placement, power routing, clock tree synthesis (CTS), post-CTS optimization, routing, post-routing timing and signal integrity optimization, and final signoff extraction, timing signal integrity, and power signoff. Parasitics must also be considered in these additional design steps.

[0016] Analog design flows also require detailed simulations after the layout is complete and parasitics are extracted, and layout changes are required as the parasitics affect the simulation results. More complex analog design flows also include forms of layout prototyping, floorplanning, place and routing, and attempts to account for layout-dependent effects (LDE) and density-gradient effects (DGE). In both analog and digital flows, routing must be aware of multi-patterning, and pattern density, which affects printability, is addressed by separating the layout into sparse patterns and exposing them separately. Similar to digital flows, various steps in the analog design flow must accurately account for parasitics.

[0017] In both analog and digital flows, multiple iterations are typically required until a layout is achieved that meets the design constraints for timing, power, performance, and area in the presence of parasitics. Detailed simulations need to be repeated not only for parasitics at nominal process conditions, but also for parasitic variations representing various manufacturing process corners to ensure that these circuit-level matrices are met across manufacturing process variations.

[0018] Although the following discussion focuses primarily on capacitance extraction techniques, the methods described herein also apply to resistance and inductance extraction. FastCAP is an existing 3D capacitance extraction program that calculates the self- and mutual capacitance between ideal conductors of any shape, orientation, and size. Figure 2 provides an example illustrating the operation of such an extraction program. It shows a bus structure 200 from which parasitic capacitance needs to be extracted. As shown, bus structure 200 includes four conductors, each with six faces represented as patches. The conductors are divided into sections based on where they overlap. The input file for FastCap specifies the discretization of the conductor surfaces into panels, with edges being meshed more finely for accuracy. For the example in Figure 2, FastCAP generates the 4x4 capacitance matrix shown in the table below.

[0019] [Table 1]

[0020] After solving Maxwell's equations for a given structure, a symmetric capacitance matrix is ​​generated as output by the field solver, listing the conductor self-capacitances along the main diagonal, and the off-diagonal terms are the coupling capacitances between the various conductors.

[0021] Technology pre-characterization can use a variety of methods to simulate several structures using field solvers, from which the coupling capacitance coefficients are ultimately calculated. Figure 3 shows, at a high level, that a typical pre-characterization process begins by constructing several multi-layer 2D circuit wire structures 300 containing conductor wires of various widths and spacings. These 2D wire structures are then combined with wire height information from a process technology file and extruded (via an extrusion process 302) to form a 3D structure.

[0022] The 3D structure is then converted into a format for processing by field solver 304. For example, the 3D structure is converted into N conductors using a set of panels, which are then consumed by field solver 304 to generate an N×N capacitance matrix 306. The capacitance matrix is ​​filtered by filter process 308 to generate a set of self-capacitance values ​​and a set of coupling capacitance values. These capacitance values ​​are then post-processed into component values, i.e., capacitance coefficients.

[0023] In a paper entitled "Analysis and Justification of a Simple, Practical 2 1 / 2D Capacitance Extraction Methodology" by Cong et al., five fundamentals for capacitance extraction techniques are presented.

[0024] The first fundamental is that "ground and adjacent wires on the same layer have significant shielding effects, so both must be considered for accurate modeling."

[0025] The second fundamental is that if the metal density on layer i exceeds a certain threshold, the coupling between the wires in layer i+1 and the wires on layer i-1 is negligible. Third, "during capacitance extraction of a wire on layer i, layer i+ / -2 can be treated as a ground plane with negligible error. There is no need to look beyond layer i+ / -2."

[0026] Fourth, the coupling analysis for wires within the same layer only needs to consider the nearest neighbor wires independently, and the effect of the width of adjacent wires in the same layer on coupling can be ignored.

[0027] The fifth and final principle is that orthogonal crossover and crossunder corrections can be performed incrementally because the joint interaction of layers i-1 and i+1 on layer i is negligible.

[0028] These fundamentals, as well as terminology from the above-mentioned papers, are used in the parasitic extraction techniques of some embodiments of the present invention. For example, Figure 4A shows a single-layer structure that allows for the extraction of lateral (C1), areal (C1), and fringe (C1) capacitance coefficients for wires of width W on layer i with same-layer neighbor spacing S. The structure on the left shows three wires of the same width W, while the structure on the right shows three slightly different wires of the same width W' (W prime), i.e., wires with widths that differ only slightly from those in the structure on the left.

[0029] During pre-characterization, a 2D bus structure corresponding to both patterns is created. Wire heights from the process technology file are used to generate a 3D structure from the 2D structure. The 3D structure is then meshed to create a series of 2D surface panels, and the panel information is used as input to a field solver. The 3D structure is simulated by a field solver (e.g., FastCAP), resulting in two capacitance matrices. A system of equations relating the capacitance matrix values ​​to the Cl, Ca, and Cf capacitance component values ​​is constructed and solved to generate the Cl, Ca, and Cf component values ​​for that particular wire width and spacing, i.e., W, S pair. This approach is then repeated for various values ​​of W and S.

[0030] Figure 4B shows a top view of the geometric structure for calculating crossover capacitance. The left side of this figure contains a 3x3 bus intersection structure 420, and the right side contains a 3x2 bus intersection structure 425. Both structures are extruded into 3D using wire heights from the process technology file and then converted to surface panels. The surface panel information is then used as input and solved (independently) by a field solver (FastCAP) to generate 3x3 and 3x2 capacitance matrices, respectively. The resulting capacitance matrices are then post-processed to generate values ​​for the crossover capacitance.

[0031] In this approach, the process is repeated with different values ​​of the crossover wire width and spacing Wc and Sc, along with different values ​​of the width W and spacing S of the layer of interest. The various capacitance matrices are then post-processed to allow for the determination of the crossover capacitance coefficient as a function of the 4-tuple (W, S, Wc, Sc). A similar approach is used to determine the cross-under capacitance (using layer i-1 instead of layer i+1). Other approaches can use a three-layer bus crossover structure or other structure, with appropriate post-processing techniques to determine the capacitance coefficient.

[0032] Various different values ​​of W, S, Wc, and Sc are then used to calculate various values ​​of Cl, Ca, Cf, the crossover capacitance factor Co, and the crossunder capacitance factor Cu. These values ​​are then used to calculate a lookup table that allows Cl, Ca, Cf, Co, and Cu to be looked up as values ​​for W, S, Wc, and Sc in a later capacitance extraction stage. The lookup table is stored as part of the extractor's pattern library.

[0033] During the capacitance extraction stage, the geometric parameters for the wire segments of the target IC design are determined, and the capacitance component coefficient values ​​are found by consulting lookup tables in the pattern library. Linear interpolation in W and 1 / S is used when the wire values ​​generated during the capacitance extraction stage do not exactly match the values ​​used to generate the lookup tables during the pre-characterization stage.

[0034] Note that this approach and others are related to geometric parameters. Models and tables are stored with the pattern library during pre-characterization as a function of geometric parameters such as width and spacing. During the extraction stage, the layout is decomposed into a set of geometric parameters (more widths and spacings) and capacitance values ​​are calculated by referencing / looking up the models / tables from the pre-characterization stage, linearly interpolating as needed.

[0035] To model the effects of parasitic capacitance across process generations, methods for calculating parasitic capacitance from layout data have evolved from 1D, 2D, 2.5D to full 3D-based solutions to meet the required accuracy.

[0036] Regardless of the accuracy level, capacitance extraction is generally performed in two stages. FIG. 5 shows a conventional flow for performing capacitance extraction. The first stage, known as "pre-characterization," requires process technology information but not the layout of the actual IC being extracted. This first stage is performed once per process technology node. This first stage is shown above dashed line 500 in FIG. 5. The second stage, known as the extraction stage, requires the information generated in the pre-characterization stage as well as the actual IC layout design database of the chip from which the parasitic parameters are to be extracted. This stage is shown below line 500 in FIG. 5. This stage is required once per IC design and produces a parasitic file or database as output.

[0037] During pre-characterization, a CPU-intensive but highly accurate field solver is used to determine the capacitance for a particular structure. The resulting capacitance is then post-processed in conjunction with a particular capacitance model to obtain a set of various model parameters or look-up tables that represent the manufacturing process technology. The model and / or look-up tables are then stored as the output of the pre-characterization stage. The parameterized model and / or look-up tables stored in the pre-characterization stage are then combined with geometry information about the IC design in the capacitance extraction stage.

[0038] A typical reticle enhancement technology (RET) method involves optical proximity correction (OPC) verification to identify and correct hot spots. Hot spots are areas that require ideal conditions to print properly and are therefore not resilient to manufacturing variations, or in some cases, do not print properly even under ideal conditions. Hot spots lead to poor yields. Inverse lithography technology (ILT) is a type of OPC technology. ILT is the process of directly calculating the pattern to be formed on a reticle from the pattern desired to be formed on a substrate, such as a silicon wafer. This may involve simulating the optical lithography process backward using the desired pattern on the substrate as input. ILT-calculated reticle patterns may be purely curvilinear, i.e., completely nonlinear, and may include circular, near-circular, annular, near-annular, elliptical, and / or near-elliptical patterns. Many studies and wafer results have shown that ILT, especially unconstrained curved ILT, can provide the best results in terms of wafer pattern fidelity and process window.

[0039] In critical or very high density IC designs, it is essential to model parasitic capacitance values ​​as accurately as possible so that any effects on timing (performance) and power consumption are fully considered. Some embodiments achieve such capacitance extraction accuracy by incorporating a manufacturing process simulator capable of generating curve shapes that include proximity effects directly into both the pre-characterization and extraction stages of capacitance extraction.

[0040] Curved shapes more closely resemble the manufactured shapes of components (e.g., wires) in an IC design. Therefore, performing parasitic extraction using curved shapes improves the accuracy of the extracted parasitic values. FIG. 6A shows an example of a manufacturing process simulator that generates and uses curved shapes during pre-characterization. The manufacturing process simulator in this example includes a RET 605 that generates a curved 2D shape 610 from a 2D shape 600 using information from an IC layout database that informs how the curved shape 610 should be generated. The manufacturing process simulator in this example also includes a semiconductor process model 615, which is a set of parameters that describe the semiconductor manufacturing process. The semiconductor process model 615 includes a process model such as the type of light source used for lithography, the wavelength of light used, etc.

[0041] The generated 2D curve shapes 610 are then fed into a 3D extrusion and meshing process 616, which then uses these shapes and information from a process technology file 618 to generate accurate meshed 3D shapes 620. These 3D shapes 620 are then provided as input to a field solver 622. The description of the 3D shapes 620 is more accurate than those generated using traditional methods. As a result, the field solver 622 generates significantly more accurate capacitance values ​​624.

[0042] In some embodiments, manufacturing process simulators are used to simulate various detailed imperfections in manufacturing, allowing for a detailed plan view of the resulting silicon features. These simulators can account for several proximity effects, line edge roughness, etc. Some embodiments combine the data generated by these simulators with the process technology file information of the technology stack to generate highly accurate 3D models. These 3D models are then used as input to a field solver tool to extract capacitance with a high level of accuracy.

[0043] When run time is not as critical, manufacturing simulation tools can fully account for manufacturing process variations and curvilinear design techniques, allowing for more accurate determination of curvilinear interconnect variability across process corners. However, given that run time is often critical, some embodiments use newer and better capacitance extraction techniques that do not rely on traditional pattern libraries and traditional pattern matching, while accounting for the effects of process variations and the increasing presence of curvilinear shapes in manufactured designs. These embodiments enable accurate parasitic extraction for both curvilinear design shapes and manufactured curvilinear interconnect shapes, while accounting for process variations.

[0044] Conventional capacitance extraction approaches rely primarily on CPU-based processing using a Single Instruction, Single Data Stream (SISD) processing architecture. While it is possible to divide the pre-characterization and extraction problem into domain-based subproblems that can be solved in parallel using a multiple CPU approach, the computation of the subproblems themselves is not as fine-grained as problems typically solved on Graphics Processing Units (GPUs) with Single Instruction, Multiple Data (SIMD) architectures, such as for graphics processing or deep learning applications. Therefore, conventional capacitance extraction approaches require a large number of CPUs to achieve significant performance benefits.

[0045] Therefore, it is desirable to map the capacitance extraction problem onto new SIMD architectures, such as GPU or Tensor Processing Unit (TPU) devices, to obtain a much finer level of parallelism and so that the capacitance extraction problem can be solved more efficiently. Some embodiments improve the speed of parasitic pre-characterization and extraction by performing these operations in the pixel domain, thereby enabling these operations to be performed by SIMD architectures, such as GPU or Tensor Processing Unit (TPU) devices. These embodiments use machine-trained networks (e.g., neural networks) to process pixel-based definitions of IC design components (e.g., wire structures) analyzed during pre-characterization and extraction.

[0046] For example, some embodiment systems and methods use a field solver to determine capacitance values, and the input conductor structure used as input to the solver is a curve (e.g., in plan view). Some embodiments generate these curve shapes using a trained curve shape prediction convolutional neural network (CNN). Some embodiment systems and methods perform a technology pre-characterization to train the capacitance prediction CNN, then store the capacitance prediction network structure and trained weights in a pattern library. Some embodiments provide systems and methods that train multiple track capacitance prediction CNNs during technology pre-characterization, then store the capacitance prediction CNN structure and trained weights in a pattern library.

[0047] The use of a trained curve shape prediction CNN enables some embodiments to rapidly generate accurate representations of 3D fabricated curved conductor shapes during extraction. These 3D fabricated curved conductor shapes are then provided as input to a field solver. This approach improves the accuracy of critical net extraction, especially in the presence of significant manufacturing process variations.

[0048] Some embodiments use deep learning techniques instead of geometric approaches to perform capacitance coefficient modeling in pattern-based extraction of non-critical nets. For example, some embodiments use a capacitance component prediction CNN architecture to predict capacitance or capacitance coefficient values ​​by using 2D rasterized images of conductor structures as inputs instead of using geometric parameters as inputs. Therefore, certain limitations of model-based or table-based approaches (such as those used in 2.5D and 3D pattern matching techniques) are removed, thereby expanding the applicability and scope of pattern-based techniques.

[0049] Some embodiments perform full capacitance extraction by using a trained CNN instead of using traditional pattern matching or field solvers for parasitic extraction. For example, in some embodiments, the design to be extracted is rasterized into the pixel domain and divided into image tiles. The capacitance of conductors, represented as pixels within each tile, is quickly estimated by a trained capacitance prediction CNN and integrated over the tiles associated with a given conductor to obtain a final capacitance value. Embodiments using neural networks can execute quickly because they can be efficiently processed by the SIMD underlying architecture of today's GPU and TPU devices.

[0050] 6B illustrates using a curve shape prediction neural network 650 trained in a capacitance extraction flow to generate highly accurate parasitic capacitance values ​​for curved conductors resulting after manufacturing an IC using the IC design. The neural network 650 is trained to generate several 2D curve shapes 654 for several manufacturing process variations of a 2D shape 652 defined after the EDA stage (e.g., after routing). In some embodiments, the neural network processes a pixel definition of the 2D shape 652 and generates the curved 2D shape 654 in the pixel domain. Thus, for the neural network, the input 2D shape 652 is rasterized into the pixel domain.

[0051] 6B, the 2D curve shapes 654 generated for manufacturing process variations are then fed into a 3D extrusion and meshing process 656, which then uses these shapes and information from a process technology file 658 to generate an accurate meshed 3D shape (as defined by the 3D surface description) 660. To perform the extrusion, the 2D curve shape definitions are converted from a pixel domain to a geometric contour domain where the shape is defined by their contour definition.

[0052] These 3D shapes 660 are then provided as input to a field solver 662. The description of the 3D shapes 660 is much more accurate than those generated using traditional methods. As a result, the field solver 662 generates significantly more accurate capacitance values ​​364.

[0053] Instead of simply running one neural network 650 to generate several 2D curve shapes 654 for several manufacturing process variations, other embodiments use several single-output neural networks running in parallel, each for a different manufacturing process variation. These simultaneously running neural networks generate several process corner-specific 2D wafer contours for several process variations. In some embodiments, each such neural network uses a predetermined set of weights corresponding to one manufacturing process variation.

[0054] On the other hand, a neural network 650 generating several 2D curve shapes 654 for several manufacturing process variations takes as input a set of IC layout drawing shapes, but generates multiple outputs of curve shapes instead of one, one for each process manufacturing corner. Examples of multiple 2D curve shapes for multiple manufacturing process variations (generated by one neural network 650 or multiple single process variation networks) include an average curve image, a maximum curve image, and a minimum curve image corresponding to different extremes in processing conditions.

[0055] Details regarding these examples, and details regarding how raster images derived from IC designs can be provided as input to train a curved shape prediction neural network that can then be used to generate detailed 2D images of curved silicon wafer shapes, are disclosed in "Methods and Systems to Determine Shapes for Semiconductor or Flat Panel Display Fabrication," U.S. Application Publication No. 2022 / 0128899, and U.S. Provisional Application No. 63 / 283520, filed November 28, 2021, both of which are incorporated herein by reference.

[0056] As described above, the 2D curve shape 654 across the process variations is extruded and meshed in parallel by a 3D extrusion and meshing process 656 to form a set of corner-specific or limit-specific 3D surface meshed volumes 660, which are then input to a field solver 662. In some embodiments, the field solver is a single field solver, while in other embodiments, it is multiple field solvers. The field solving operations performed by the field solver generate a corresponding set of parasitic capacitance values ​​(e.g., a set of matrix values) across the manufacturing process variations. In some embodiments, the parasitic capacitance values ​​are filtered and converted into a DSPF / SPEF file (Detailed Standard Parasitic Format / Standard Parasitic Exchange Format) or other industry-standard parasitic representation, such as the Synopsys Galaxy Parasitic Database (GPD).

[0057] Therefore, corrections to curvature due to various manufacturing process variations are accurately incorporated into the capacitance values ​​for the various process corners generated by the solver. For each 2D feature in the IC design being analyzed, the above-described embodiments calculate multiple 2D curve features across multiple process variations. However, other embodiments use the flow and neural network shown in FIG. 6B to generate 2D and 3D curve features for only one process condition (one specific manufacturing process variation), and therefore generate only parasitic capacitance values ​​for this one process condition.

[0058] 7 shows a novel non-geometric approach 700 to replace or complement the geometric approach for calculating capacitance coefficients during the pre-characterization process that generates capacitance coefficients for later use during extraction. The geometric approach takes a portion of the layout and reduces it to geometric features such as wire lengths, spacing, etc., as described above with reference to FIG.

[0059] On the other hand, during technology pre-characterization, the approach shown in FIG. 7 replaces the simplified capacitance model / lookup table with a more universal function approximator: a trained capacitance prediction neural network 740. In this approach, image rasterization 720 is performed on the wire structure 710 to generate several 2D images, hereinafter referred to as multi-channel 2D images 730. Image rasterization 720 defines the multi-channel 2D images 730 in the pixel domain (i.e., generates a pixel-based definition of the multi-channel 2D images 730). Thus, instead of quantifying geometric attributes and then calculating capacitance using these attributes along with pre-characterized lookup table values, the approach shown in FIG. 7 uses a pixel representation of the design to generate capacitance coefficients, from which parasitic capacitance is calculated (e.g., after multiplying the coefficients by wire segment lengths and / or wire segment overlap lengths).

[0060] In some embodiments, image rasterization generates white pixels for fully filled pixels (e.g., pixels that are completely covered by a shape such as a wire segment), black pixels for fully empty pixels (e.g., pixels that do not cover any shape such as a wire segment), and gray pixels for partially filled pixels. In some of these embodiments, fully filled pixels are represented by the number 1.0, fully empty pixels are represented as 0.0, and partially filled pixels are represented by a value in the range [0,1] that represents the area of ​​the pixel that is filled by the wire (e.g., a 50% filled pixel has a value of 0.5). Before rasterizing a wire structure, some embodiments decompose the wire structure into several components (e.g., several wires, wire segments, or wire structure portions) and then rasterize them individually.

[0061] The multi-channel 2D image 730 is then used as a primary input to a capacitance prediction neural network 740, which generates a capacitance vector 750. In some embodiments, the capacitance vector values ​​750 generated by the trained capacitance neural network 740 are further post-processed into capacitance coefficients. To this end, the capacitance vector 750 is provided to a post-processor 755, which generates as output capacitance coefficients 760. As shown, these capacitance coefficients include Cl, Ca, Cf, Co, and Cu in some embodiments, although in other embodiments they are post-processed into other coefficients for other capacitance models.

[0062] To generate the capacitance coefficients 760, the post-processor 755, in some embodiments, constructs a system of equations relating the capacitance matrix values ​​to the Cl, Ca, and Cf capacitance component values ​​and solves the equations to generate the Cl, Ca, and Cf component values ​​for that particular wire width and spacing, i.e., W, S, pair. This approach is then repeated for various values ​​of W, S. In some embodiments, the generated capacitance coefficients 760 are parasitic unit lengths. Thus, during extraction, the generated capacitance coefficients 760 are then used to calculate the parasitic capacitance, for example, by multiplying these coefficients by the length of the overlapping wire segments.

[0063] Using a trained neural network 740 as the mapping mechanism is advantageous because it removes the need for external linear interpolation during the extraction phase when wire widths and spacings differ from those used during training. This is because neural networks, when properly designed and trained, act as universal function approximators, removing the need for such external interpolation when operating on unfamiliar data. Another advantage of this method over conventional approaches is that the multi-channel 2D images 730 input to the neural network 740 can represent arbitrary conductor shapes, including curvilinear shapes.

[0064] For example, in some embodiments, one or more of the wire structures are generated from a curved shape by a second neural network trained for shape prediction (e.g., the curved shape prediction neural network of FIG. 6B ). In some embodiments, the input semiconductor design includes several wire structures. Each of these wire structures is rasterized, and a curved shape is calculated from each rasterized wire structure. Rasterizing each wire structure can generate several images, e.g., each image in some embodiments corresponds to one layer of wiring in the wire structure. The fabricated curved wire structure can include multiple wire tracks that cross each other and can be subsegmented into smaller structures. Before rasterizing each wire structure, some embodiments decompose the wire structure into several components (e.g., several wires, wire segments, or wire structure portions) and then rasterize them individually.

[0065] 7, the neural network output (i.e., capacitance vector 750) in some embodiments represents a vector of capacitance values ​​for the geometric structure. The input wire structure 710 may be rasterized into a multi-channel 2D image 730 representing three conductors each on a target layer i, a crossover layer i+1 above it, and a cross-under layer i−1 below it. During rasterization 720, the wire structure is rasterized onto the multi-channel 2D image 730. In some embodiments, different image channels represent different interconnect layers of an IC fabrication process.

[0066] For a 3x3 bus crossover structure, as shown in Figure 16, nine capacitances are of interest: the self-capacitance for center conductor segment 5 in center layer i ("Metal 2") and eight capacitance values ​​of this segment to its eight neighboring segments. These neighboring segments include (1) the lateral capacitance from the center conductor to its left and right neighboring segments 4 and 6 on center layer i, (2) three crossover capacitances from center conductor segment 5 on center layer i to three conductor segments 1, 2, and 3 on layer i+1 (i.e., the upper layer, "Metal 3"), and (3) three crossunder capacitances from center conductor segment 5 on center layer i to three conductor segments 7, 8, and 9 on layer i-1 (i.e., the lower layer, "Metal 1").

[0067] To train neural network 740, some embodiments use a known input set (e.g., a known wire structure) with a known output set (e.g., a known capacitance coefficient). To generate these known input / output sets, some embodiments use a field solver approach, described below with reference to FIG. 9. During training, groups of known input sets are rasterized, fed through neural network 740, and post-processed to generate groups of output sets (as shown in FIG. 7). The difference between each generated group of output sets and the known output set for each group of known input sets is an error value that is back-propagated through neural network 740 to train its trainable parameters (e.g., its weight values). Some embodiments perform training once per process technology and then perform the operations of FIG. 7 to perform extraction one or more times during IC design.

[0068] In other embodiments, the capacity prediction neural network may be trained to directly output the capacity coefficient values ​​themselves, e.g., the output may be the capacity coefficients (Cl, Ca, Cf, Co, Cu). In this approach, the post-processing steps themselves are also learned by the neural network. Figure 8 shows the architecture of a CNN 800 of some embodiments that can be used to directly output the capacity coefficient values.

[0069] In this figure, a three-channel input image 805 is processed by a convolutional base 810 that includes two pairs of convolutional layers 815 and 820 (e.g., each with a 5x5 kernel). Each of the convolutional layers has a subsequent 2D max-pooling 825 or 830 to downsample the image. Each convolutional layer uses a filter depth of 32. The input image dimensions are 60x60 pixels, with each pixel representing a 10 nm square of IC design data. Thus, each image represents a 600x600 nm region of the IC design.

[0070] In the neural network model, the convolutional base 810 is followed by a 16-neuron wide fully-connected bottleneck layer 835, which serves to reduce the overall number of model parameters. The output from this narrow layer is then fed into a regression network 840, which includes a 100-neuron wide fully-connected layer followed by a 9-neuron fully-connected output layer.

[0071] All layers except the final output layer use ReLU activation, and all convolutional layers use zero padding to ensure that the output image size is the same as the input image size. Because this is a recursive CNN application, the final output layer uses a linear activation function. The final output layer is as wide as the number of capacities, N, to be predicted. Once training is complete, in some embodiments, the set of trained weights for each process technology is saved for use in a neural network, such as capacity prediction neural network 740. In other embodiments, the final output layer is as wide as the number of capacity coefficients to be predicted. Those skilled in the art will appreciate that other embodiments use a different neural network structure to generate the parasitic component values ​​than the structure shown in FIG. 8 .

[0072] To train CNN 800 or another neural network to generate parasitic values, some embodiments use a training data set with known input and output values. These embodiments iteratively (1) successively feed a set of known input values ​​to the neural network to generate a set of output values, (2) calculate an error value between each set of generated output values ​​and the known output value corresponding to the input values, and (3) back-propagate each computed error value through the neural network to adjust configurable parameters of the neural network (e.g., its weight values) to reflect knowledge gained through training.

[0073] FIG. 9 illustrates a data flow diagram for creating the training data set (X and Y data) required to train a neural network, e.g., a 3×3 bus intersection structure. The X training data represents the rasterized wire structure input, and the Y training data represents the capacitance vector output. In this example, several three-layer 2D rectangular wire intersection structures 900 are generated with different wire widths and spacings. Some embodiments use different wire widths down to 30 nm, with a unit wire length of 90 nm. Also, spacings up to four routing track widths are used, as spacings greater than this are assumed to result in relatively insignificant changes in capacitance values.

[0074] Image rasterizer 910 performs a rasterization operation on each wiring structure 900 to generate a 2D image defined in pixel terms for the wiring structure. Each 2D image has three channels, each containing a 2D rasterized image representing layer i having a first preferred routing direction (e.g., vertical) and the layer above and below having an orthogonal second preferred routing direction (e.g., horizontal). In some embodiments, a pixel size of 10 nm is used during rasterization, such that, for example, a 30 nm wide wire is rendered as 3 pixels wide in the image. A fully filled pixel is represented by the number 1.0, a completely empty pixel is represented as 0.0, and a partially filled pixel is represented by a value in the range [0,1] representing the area of ​​the pixel filled by the wire (e.g., a 50% filled pixel has a value of 0.5).

[0075] Each wire crossing structure thus rasterized for input to the neural network is then fed to an extrusion and mesh modeling process 920, which generates a 3D representation of the structure. As described above, to perform an extrusion operation that uses a contour definition of a shape, some embodiments convert the 2D curve shape definition from a pixel domain to a geometric contour domain, where the shape is defined by their contour definition.

[0076] The generated 3D representation is suitable for input to a field solver 925. To create the field solver input representation, the extrusion and mesh modeling process 920 uses 2D wire dimensions from a wire structure with various layer-specific wire heights and dielectric thicknesses as specified in a process technology file 915 for the manufacturing process. This allows the 2D wire shapes to be extruded in the "height" dimension to form a 3D volume. The set of process technology information in the process technology file may include, for example, wire height and dielectric information.

[0077] For each resulting 3D interconnected volume, some embodiments calculate surface panels. In some embodiments, these panels are calculated simply as rectangles. In more complex embodiments, these panels are calculated by applying more complex meshing algorithms before extrusion, such as those described above for calculating curvilinear 3D interconnected shapes. For example, some embodiments generate triangular or quadrilateral meshes. Ground planes are then inserted above and below the top and bottom layers.

[0078] The 3D surface panel representation, including added ground planes above and below the layer of interest, is then solved by field solver 925 to generate an N×N capacitance matrix, where N is the total number of conductors. For a 3×3 bus crossover structure, there are nine conductors in total, so the field solver generates a 9×9 matrix with 81 capacitance values. Filter 930 then narrows these values ​​down to only the primary capacitance component values ​​of interest, such as the self-capacitance of the center layer, the center conductor, and the capacitance between that conductor and each of its eight adjacent conductors, as shown in FIG. 16.

[0079] For each candidate geometric wire structure, the training data generation flow of FIG. 9 generates sample wire structures using different widths and / or spacing ranges. Each generated wire structure is a known input X. To generate a corresponding known output Y for this input, the training data generation flow (1) generates a three-channel rasterized image for each generated wire structure, (2) generates an extruded 3D representation of this image, and then (3) generates a filtered capacitance vector that is output by the field solver and filter. The filtered capacitance vector is the known output Y for the training set with the known input X. The large set of samples so generated is then divided into a training set (e.g., 80% of the samples) and a validation set (e.g., 20% of the samples) according to deep learning best practices.

[0080] 10 shows a data flow diagram of the CNN-based total capacitance extraction method. An IC design 1002, which includes 2D layout shapes on multiple layouts, has its shapes rasterized by an image rasterizer 1003. The rasterized image (defined in the pixel domain) is then provided as input to a trained curve prediction neural network 1004 running on a GPU / TPU device (for simplicity, shown as a single corner-specific set of curve shapes). The neural network 1004 performs a fast inference operation to generate a set of process corner-specific curve 2D shapes representing what will be fabricated on the substrate at each process corner.

[0081] The curve prediction network may be trained using the methods disclosed in the above-incorporated U.S. Patent Application Publication No. 2022 / 0128899. The resulting wafer shape contours are calculated and stored in database 1006. For each corner-specific set of curved wafer shapes stored in database 1006, the corresponding curved interconnect wire segments of the extracted net are located via shape tracking process 1008. As shown, this process also uses the originally drawn wafer shapes and their corresponding connectivity in the IC layout.

[0082] Process 1008 also divides the curved wire segment into subsegments, each representing an interconnect wire that is 2T+1 track widths long, where T is the number of tracks. In some embodiments, the number of tracks, T, equals 4, while other embodiments use a different number of tracks (e.g., 5). Each subsegment is then searched in the X and Y directions within a square region to find the nearest neighboring wires on the same layer and crossover / crossunder wires on the interconnect layers above and below that are within + / - T tracks of the interconnect of interest.

[0083] In some embodiments, process 1008 generates a square tile three-channel raster image 1012 representing each interconnect subsegment, its nearest neighboring wires on the same layer within + / -T tracks to the left and right, and up to 2T+1 nearby crossover / crossunder wires on the layers above and below. * Each such subsegment tile contains (2T+1)+3 slots (e.g., 21 slots for four tracks). Each such subsegment tile is rendered as a three-channel two-dimensional image. In other embodiments, the tile image of hidden layer i captures up to T lateral neighbors on either side of the conductor being extracted, i.e., not just the two nearest lateral neighbors. In this case, the estimated capacitance array is 3 * It contains (2T+1) slots (eg, 27 slots, 9 for each of the three layers when four tracks are used).

[0084] The generated subsegment tiles, representing interconnect subsegments, are then passed to a trained capacitance prediction neural network 1014, which predicts / infers coupling capacitance values. In some embodiments, neural network 1014 has an architecture similar to neural network 800 of FIG. 8, but with a different number of outputs (e.g., 23 or 27 outputs when four tracks are used). Neural network 1014 calculates all relevant capacitances for each subsegment tile (also referred to below as subsegment area). In summary, FIG. 10 includes a first neural network 1004 for generating predicted curve shapes from a rasterized image of an IC design shape, and a second neural network 1014 for calculating predicted parasitic capacitances of the curve shapes using a set of process technology information.

[0085] As shown, the output of the second neural network 1014 is sub-segment, tile-specific capacitance 1016, which is provided as input to an integration process 1018. For each interconnect segment from the original layout, process 1018 collects the segment's associated sub-segment-specific capacitance and integrates it over all associated sub-segment tiles. This flow sums the calculated capacitances according to the interconnect connectivity. This integration is further described below with reference to FIG. 11. Process 1018 outputs the integrated capacitance values ​​for all interconnects in a standard parasitic format 1020, such as a DSPF / SPEF file or a Synopsys GPD file.

[0086] FIG. 11 provides an example to illustrate the tiling and rasterization process used in some embodiments. This example shows the fabricated curved shapes of several conductors of interest. In this example, the method extracts the capacitance for a central vertical conductor 1102 on layer "1 / 0" in the design. Intuitively, conductor 1102 has a large lateral capacitance with neighboring conductors 1104 and 1106 on the same layer to the left and right, which run substantially parallel to conductor 1102 but at different spacings. Conductor 1102 also has fringing / overlap capacitance with respect to shapes on the layer above (layer "2 / 0" in this design) and the layer below (layer "0 / 0" in this design).

[0087] Thus, the tiling process of some embodiments tiles the vertical conductor 1102 into multiple sub-segments. In this example, the tiling process results in three tiles 1112, 1114, and 1116, each containing a portion of the center vertical conductor. Each tile also contains the two nearest adjacent lateral conductor sub-segments of the same layer. Furthermore, the three conductor shapes within the four-track window are also present on the upper and lower orthogonal routing layers.

[0088] Each three-layer tile from the tiling process is then rasterized into a three-channel 2D 60x60 pixel raster image 1120, with pixels at 10 nm. Figure 11 shows the three-channel image of tile 1112. Here, the three-channel image is separately divided so that each channel image 1122-1126 shows pixels representing interconnect subsegments on a respective interconnect layer.

[0089] During inference, the three-channel 2D tile raster image is input to a capacitance prediction convolutional neural network 1014, and up to 27 capacitance values ​​are predicted for each of the three tiles, representing the self-capacitance of the center layer center conductor, its coupling capacitance to conductors in laterally adjacent tracks, and its coupling capacitance to each of the crossover / crossunder tracks represented in the top / bottom channels of the tile image. As noted above, for the example described in Figure 10, quantities other than 27 may be used in other embodiments.

[0090] After inference, the resulting capacitances are summed across all tiles, i.e., summed according to the connectivity of the interconnects. For example, to obtain the total self-capacitance per corner of the central vertical conductor 1102 on layer "1 / 0," the self-capacitance of the central conductor across each of the three tiles 1112-6 is summed.

[0091] 12 shows a flow for generating training data for training a neural network for tile-based capacitance extraction. In this example, various multi-layer (e.g., three-layer) 2D interconnect structures are generated that fit into a square of N×N track slots, such as 9×9. The structures are stored in an IC design database 1202 and divided into their individual layers. An image rasterizer 1204 then rasterizes the structural content of each layer as a single-channel 2D image, and then combines the individual layers across the three layers into a three-channel 2D image.

[0092] These raster images are then consumed by a curve prediction neural network 1206. Examples of such neural networks are the neural networks described above or one of the neural networks disclosed in U.S. Patent Application Publication No. 2022 / 0128899. This neural network 1206 outputs a curve image 1210 for each process corner that corresponds to the output of the manufacturing process. For each process corner, the curvilinear 2D wafer shapes for the three interconnect layers are collected and fed to an extrusion process 1212.

[0093] This process 1212 uses layer-specific wire height and dielectric information in process technology file 1214 to extrude the curvilinear 2D wafer shape into 3D, and the resulting 3D interconnect structure is input to field solver 1216. The field solver produces as output an NxN capacitance matrix 1218 for each process corner, which is then filtered by filter 1222 to the capacitances of interest, i.e., the coupling capacitances between the center layer central conductor of interest and the conductors on other tracks on all three layers.

[0094] For each interconnect structure sample, a corner-by-corner 3-channel 2D curve image tile to be used as output from the curve shape prediction neural network 1206 and a corresponding corner-by-corner capacitance vector output by the filter 1222 are collected as input X and output Y, respectively, to be used in training the capacitance prediction neural network.

[0095] During the generation of 2D3-layer structures, each structure may contain wire segments of various lengths that appear at any of the valid track locations. Wires may extend the full width or height of the tile, or they may extend over a partial width or length. In some embodiments, wires are placed at available track locations using a set range of wire lengths. For any track location except the location of the center layer center conductor, the wire length may be as short as zero length, i.e., the wire may not be present at a particular track location. Non-zero wire lengths may be very short (e.g., one track width) or may extend the full nine track widths of the structure. The start / end locations of each wire within that track may be snapped to a set range of locations, such as routing track intersections.

[0096] Some embodiments allow the training space to be sampled in a structured grid-like manner. In other embodiments, a Monte Carlo approach is employed to populate the training space, where the wire start and wire end positions for each wire are randomly generated for each track. Again, the wire length at any track position (except the center layer center conductor) may be as short as zero. Training samples with empty track positions are assigned a capacitance value of 0 at those positions, and non-empty positions use the capacitance value generated by the solver.

[0097] 13 illustrates a training data set used in some embodiments to train a neural network that generates parasitic capacitance values. As shown, these embodiments use curved wire shapes as input values ​​for each training set and known capacitance values ​​associated with these curved wire shapes as output values ​​for each training set. Training samples using a set of process technology information generates a set of trained weights that are stored for each process technology.

[0098] FIG. 14 illustrates an example of a computing hardware device 1400 that may be used to perform the computations described in this disclosure. The computing hardware device 1400 includes a central processing unit (CPU) 1402 with a main memory 1404 attached. The CPU may include, for example, eight processing cores, thereby improving the performance of any portion of computer software that is multithreaded. The main memory 1404 may be, for example, 64 gigabytes in size. The CPU 1402 is connected to a Peripheral Component Interconnect Express (PCIe) bus 1420. A graphics processing unit (GPU) 1414 is also connected to the PCIe bus. In the computing hardware device 1400, the GPU 1414 may or may not be connected to a graphics output device, such as a video monitor. When not connected to a graphics output device, the GPU 1414 may be used purely as a high-speed parallel computation engine. Computing software can achieve significantly higher performance by using the GPU for part of its computations compared to using the CPU 1402 for all of its computations. CPU 1402 communicates with GPU 1414 via PCIe bus 1420. In other embodiments (not shown), GPU 1414 may be integrated with CPU 1402 rather than connected to PCIe bus 1420. Disk controller 1408 may also be attached to the PCIe bus, with, for example, two disks 1410 connected to disk controller 1408. Finally, a local area network (LAN) controller 1412 may also be attached to the PCIe bus, providing Gigabit Ethernet (GbE) connectivity to other computers. In some embodiments, computer software and / or design data are stored on disk 1410.In other embodiments, either the computer program or the design data, or both the computer program and the design data, may be accessed from other computers or file serving hardware via GbE Ethernet.

[0099] FIG. 15 illustrates another embodiment of a system for performing the computations of this embodiment. System 1500, sometimes referred to as CDP, includes a master node 1510, an optional viewing node 1520, an optional network file system 1530, and a GPU-enabled computing node 1540. The viewing node 1520 may be absent, or may instead include only one node, or may include other numbers of nodes. GPU-enabled computing node 1540 may include one or more GPU-enabled nodes forming a cluster. Each GPU-enabled computing node 1540 may include, for example, a GPU, a CPU, a GPU and CPU pair, multiple GPUs for a CPU, or other combinations of GPUs and CPUs. The GPU and / or CPU may be on a single chip, such as a GPU chip with a CPU accelerated by the GPU on that chip, or a CPU chip with a GPU accelerating the CPU. The GPU may be replaced by another coprocessor.

[0100] The master node 1510 and the viewing nodes 1520 may be connected to the network file system 1530 and the GPU-enabled computing nodes 1540 via switches and high-speed networks, such as networks 1550, 1552, and 1554. In an exemplary embodiment, network 1550 may be a 56 Gbps network, 1552 may be a 1 Gbps network, and 1554 may be a management network. In various embodiments, there may be fewer or more of these networks, and there may be various combinations of network types, such as high-speed and low-speed. The master node 1510 controls the CDP 1500. External systems may connect to the master node 1510 from an external network 1560. In some embodiments, jobs may be initiated from external systems. Data for a job is loaded onto the network file system 1530 before launching the job, and a program is used to dispatch and monitor tasks on the GPU-enabled computing nodes 1540. The progress of the job can be viewed via a graphical interface, such as the viewing node 1520, or by a user on the master node 1510. Tasks are performed on the CPU using scripts that run appropriate executables on the CPU. The executables connect to the GPU, perform various computational tasks, and then disconnect from the GPU. The master node 1510 may also be used to disable a failed GPU-enabled computing node 1540 and then operate as if the node were not present.

[0101] While certain embodiments have been described in detail herein, those skilled in the art will understand that, upon understanding the foregoing, they may readily conceive of modifications, variations, and equivalents to these embodiments. These and other modifications and variations to the method may be implemented by those skilled in the art without departing from the scope of the present subject matter, as more particularly described in the appended claims. For example, while curved shapes are referred to as being used by some embodiments, those skilled in the art will understand that linear or arbitrary shapes may be used to represent designs in other embodiments.

[0102] Furthermore, those skilled in the art will appreciate that the above description is merely exemplary and is not intended to be limiting. Steps may be added, removed, or modified from the steps herein without departing from the scope of the present invention. Generally, any flowchart presented is intended to illustrate only one possible sequence of basic operations to achieve a function, and many variations are possible. Therefore, the present subject matter is intended to cover such modifications and variations provided they come within the scope of the appended claims and their equivalents. The technical concepts that can be understood from the above embodiments will be described below. [Appendix 1] 1. A method for calculating parasitic parameters of a wire structure fabricated on a substrate, comprising: receiving the wire structure; performing a rasterization operation on the wire structure to generate a pixel-based definition for each of a plurality of images collectively representing the wire structure; calculating parasitic parameters of the wire structure using the pixel-based definitions of the plurality of images as inputs to a neural network; A method comprising: [Appendix 2] 2. The method of claim 1, wherein the neural network accounts for variations in process technology. [Appendix 3] 3. The method of claim 2, wherein the neural network uses a set of predetermined weights corresponding to each variation in process technology. [Appendix 4] 2. The method of claim 1, wherein each image in the plurality of images corresponds to a layer in the wire structure. [Appendix 5] 2. The method of claim 1, wherein the wire structure includes a plurality of linear shapes. [Appendix 6] 2. The method of claim 1, wherein the wire structure includes a plurality of curved shapes. [Appendix 7] 7. The method of claim 6, wherein the neural network is a first neural network and the curve shape is generated by a second neural network trained for shape prediction. [Appendix 8] 8. The method of claim 7, wherein the curved shape is generated from a plurality of wire tracks that intersect with each other. [Appendix 9] 9. The method of claim 8, wherein the generating further comprises sub-segmenting the curve shape. [Appendix 10] 2. The method of claim 1, wherein the parasitic parameters include at least one parasitic capacitance value representing a predicted undesirable parasitic capacitance imparted to at least one wire of the wire structure. [Appendix 11] 11. The method of claim 10, wherein the parasitic parameters include a plurality of parasitic capacitance values ​​representing a plurality of predicted undesired parasitic capacitances experienced by a plurality of wires of the wire structure. [Appendix 12] 1. A non-transitory machine-readable medium storing a program for calculating parasitic parameters of a wire structure fabricated on a substrate, the program comprising: receiving the wire structure; performing a rasterization operation on the wire structure to generate a pixel-based definition for each of a plurality of images collectively representing the wire structure; using the pixel-based definitions of the plurality of images as inputs to a neural network to calculate parasitic parameters of the wire structure; A non-transitory machine-readable medium containing a set of instructions for: [Appendix 13] 13. The non-transitory machine-readable medium of claim 12, wherein the neural network accounts for process technology variations. [Appendix 14] 14. The non-transitory machine-readable medium of claim 13, wherein the neural network uses a predetermined set of weights corresponding to each variation in process technology. [Appendix 15] 13. The non-transitory machine-readable medium of claim 12, wherein each image in the plurality of images corresponds to a layer in the wire structure. [Appendix 16] 13. The non-transitory machine-readable medium of claim 12, wherein the wire structure includes a plurality of linear shapes. [Appendix 17] 13. The non-transitory machine-readable medium of claim 12, wherein the wire structure includes a plurality of curved shapes. [Appendix 18] 1. A method for training a first neural network to extract parasitic capacitances from a semiconductor design, the method comprising: receiving a semiconductor design including a plurality of wire structures; rasterizing the plurality of wire structures; calculating a curve shape from the rasterized plurality of wire structures; receiving a set of process technology information; calculating a parasitic capacitance of each of the curve shapes by using the set of process technology information, generating a set of trained weights for the set of process technology information; outputting the set of trained weights for the set of process technology information; A method comprising: [Appendix 19] 13. The method of claim 12, wherein calculating the curve shape is performed by a second neural network.

Claims

1. 1. A method for calculating parasitic parameters of a wire structure fabricated on a substrate, comprising: receiving the wire structure; performing a rasterization operation on the wire structure to generate a pixel-based definition for each of a plurality of images collectively representing the wire structure; using the pixel-based definitions of the plurality of images to provide inputs to a neural network to calculate parasitic parameters of the wire structure; A method comprising:

2. The method of claim 1 , wherein the neural network accounts for variations in a process technology used to fabricate the wire structures on a substrate.

3. 3. The method of claim 2, wherein the neural network uses a set of predetermined weights corresponding to each variation in the process technology.

4. The method of claim 1 , wherein each image in the plurality of images corresponds to a layer in the wire structure.

5. The method of claim 1 , wherein the wire structure comprises a plurality of linear features.

6. The method of claim 1 , wherein the wire structure includes a plurality of curved shapes.

7. The method of claim 6 , wherein the neural network is a first neural network and the curve shape is generated by a second neural network trained for shape prediction.

8. The method of claim 7 , wherein the curvilinear shape is generated from a plurality of wire tracks that intersect with one another.

9. The method of claim 8 , wherein the generating further comprises sub-segmenting the curved shape.

10. The method of claim 1 , wherein the parasitic parameters include at least one parasitic capacitance value representing a predicted undesired parasitic capacitance experienced by at least one wire of the wire structure.

11. The method of claim 10 , wherein the parasitic parameters include a plurality of parasitic capacitance values ​​representing a plurality of predicted undesired parasitic capacitances experienced by a plurality of wires of the wire structure.

12. The method of claim 1 , wherein the pixel-based definitions for the images include a plurality of values ​​for a plurality of pixels forming each image.

13. 2. The method of claim 1, wherein the wire structure is a first wire structure that a second neural network generates as a predicted manufacturing shape of a second wire structure defined in a circuit layout.

14. A non-transitory machine-readable medium storing a program for causing a computer to calculate parasitic parameters of a wire structure fabricated on a substrate, the program comprising: receiving the wire structure; performing a rasterization operation on the wire structure to generate a pixel-based definition for each of a plurality of images collectively representing the wire structure; using the pixel-based definitions of the plurality of images to provide inputs to a neural network to calculate parasitic parameters of the wire structure; A non-transitory machine-readable medium containing a set of instructions for causing said computer to carry out a process.

15. 15. The non-transitory machine-readable medium of claim 14, wherein the neural network accounts for variations in a process technology used to fabricate the wire structures on a substrate.

16. 16. The non-transitory machine-readable medium of claim 15, wherein the neural network uses a predetermined set of weights corresponding to each variation in the process technology.

17. The non-transitory machine-readable medium of claim 14 , wherein each image in the plurality of images corresponds to a layer in the wire structure.

18. The non-transitory machine-readable medium of claim 14 , wherein the wire structure comprises a plurality of linear shapes.

19. The non-transitory machine-readable medium of claim 14 , wherein the wire structure includes a plurality of curved shapes.

20. a set of processing units; a machine-readable medium storing a program which, when executed by at least one of said processing units, performs the method of any one of claims 1 to 13; An electronic device comprising:

Images