Electronic device and control method

Abstract

To provide an electronic device which, when write access and readout access compete with each other, can efficiently process the readout access.SOLUTION: An electronic device includes: a memory 106; a memory control unit 105; a first bus master which issues a write transaction to the memory; and a second bus master which issues a readout transaction to the memory. The memory control unit includes an arbitration unit 205 which, when the write transaction issued by the first bus master and the readout transaction issued by the second bus master compete with each other, controls write processing of writing data in the memory and readout processing of reading out data from the memory so as to repeat the write processing and the readout processing alternately for each clock cycle.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an electronic device and a control method thereof. [Background technology]

[0002] Known types of SRAM (static random access memory) are dual-port SRAM (2-port SRAM) and single-port SRAM (1-port SRAM). Dual-port SRAM has a write port and a read port, allowing simultaneous write and read accesses. Single-port SRAM performs write and read accesses exclusively. Single-port SRAM has the advantage of being smaller in circuit scale than dual-port SRAM, but has the limitation that write and read accesses cannot be performed simultaneously within the same cycle. Therefore, the memory control unit of single-port SRAM arbitrates between write and read accesses when they occur simultaneously.

[0003] Patent Document 1 describes an arbitration circuit that arbitrates memory accesses from two access sources to a single-port RAM (Random Access Memory). The arbitration circuit described in Patent Document 1 delays the memory access from the second access source so that the memory access from the second access source can be performed after the memory access from the first access source has finished. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-104486 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the arbitration circuit described in Patent Document 1 delays the memory access of the second access source, and therefore cannot efficiently process the memory access of the second access source. For example, if the second access source attempts to perform a read access while the first access source is performing a write access, the read access of the second access source will have to wait a long time. Therefore, the arbitration circuit described in Patent Document 1 cannot efficiently process the read access of the second access source.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to enable efficient processing of read access when there is a conflict between write access and read access. [Means for solving the problem]

[0007] The electronic device according to the present invention includes a memory and a write burst transfer length a first bus master that issues a write transaction; For read burst transfer length a second bus master issuing a read transaction; an arbitration unit that, when there is no conflict between the write transaction issued by the first bus master and the read transaction issued by the second bus master, performs a write process of writing write data of a length corresponding to the write burst transfer length to the memory by burst transfer in response to the write transaction issued by the first bus master, and, when there is no conflict between the write transaction issued by the first bus master and the read transaction issued by the second bus master, performs a read process of reading read data of a length corresponding to the read burst transfer length from the memory by burst transfer in response to the read transaction from the second bus master, wherein the arbitration unit The first bus master issues did Write Transactions Write processing of data of the first write burst transfer length by and the second bus master issues did Read Transaction A read process of data having a read burst transfer length of a second length different from the first length by If there is a conflict between Based on the write transaction The memory to data of The writing process and Based on the read transaction From the memory of data of The readout process is controlled to be repeated alternately. [Effects of the Invention]

[0008] According to the present invention, when a conflict occurs between a write access and a read access, the read access can be processed efficiently. [Brief explanation of the drawings]

[0009] [Figure 1]FIG. 2 is a block diagram illustrating components of the electronic device 100. [Figure 2] FIG. 2 is a block diagram illustrating components of a memory control unit 105. [Figure 3] 10 is a timing chart for explaining a control method of a memory control unit 105. [Figure 4] 10 is a flowchart illustrating a control method of a memory control unit 105. [Figure 5] 10 is a timing chart for explaining a control method of a memory control unit 105. [Figure 6] FIG. 6 is a block diagram illustrating components of electronic device 600. [Figure 7] FIG. 6 is a block diagram illustrating components of a memory control unit 605. [Figure 8] 10 is a flowchart for explaining a control method of the memory control unit 605. [Figure 9] 10 is a timing chart for explaining a control method of the memory control unit 605. [Figure 10] 10 is a flowchart illustrating a control method of a memory control unit 105. [Figure 11] 10 is a timing chart for explaining a control method of a memory control unit 105. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

[0011] [Embodiment 1] FIG. 1 is a block diagram illustrating components of an electronic device 100 according to the first embodiment.

[0012] 1, electronic device 100 has a CPU (central processing unit) 101, an image processing unit 102, an image processing unit 103, a data bus 104, a memory control unit 105, and a memory 106. Each component of electronic device 100 has an electronic circuit for realizing a function described below.

[0013] The CPU 101, the image processing unit 102, and the image processing unit 103 are each a bus master. The memory control unit 105 is a bus slave. The data bus 104 interconnects the CPU 101, the image processing unit 102, the image processing unit 103, and the memory control unit 105.

[0014] The CPU 101 operates as a control unit that controls the components of the electronic device 100 and the operation of the electronic device 100. The CPU 101 is connected to a data bus 104. The CPU 101 writes data to a memory 106 and reads data from the memory 106 via the data bus 104 and the memory control unit 105.

[0015] Image processing unit 102 and image processing unit 103 are each connected to data bus 104 and perform image processing. Image processing unit 102 writes data to memory 106 and reads data from memory 106 via data bus 104 and memory control unit 105. Image processing unit 103 also writes data to memory 106 and reads data from memory 106 via data bus 104 and memory control unit 105.

[0016] The memory 106 is, for example, a static random access memory (SRAM). The memory 106 is a memory that stores data used by the CPU 101, the image processing unit 102, or the image processing unit 103. The memory 106 is also a single-port SRAM (one-port SRAM) in which data writing and data reading are performed exclusively.

[0017] The memory control unit 105 controls memory access to the memory 106 based on a write transaction or a read transaction issued by the CPU 101, the image processing unit 102, or the image processing unit 103. When processing a write transaction and a read transaction in parallel, the memory control unit 105 arbitrates contention among multiple memory accesses and writes and reads data.

[0018] FIG. 2 is a block diagram illustrating the components of memory control unit 105. As shown in FIG.

[0019] 2, the memory control unit 105 has a write address interface unit 201, a write data interface unit 202, a read address interface unit 203, a read data interface unit 204, and an arbitration unit 205. Each component of the memory control unit 105 has an electronic circuit for realizing the functions described below.

[0020] The write address interface unit 201 is connected between the data bus 104 and the arbitration unit 205. The write address interface unit 201 outputs a ready signal WAr to the data bus 104, indicating that write address information can be input. The write address interface unit 201 also inputs a write address WA of the memory 106, a write burst transfer length WL, and a valid signal WAv from the data bus 104. The valid signal WAv indicates that the write address WA and the write burst transfer length WL are valid information.

[0021] The write data interface unit 202 is connected between the data bus 104 and the arbitration unit 205. The write data interface unit 202 outputs a ready signal WDr, which indicates that write data information can be input, to the data bus 104. The write data interface unit 202 also inputs, from the data bus 104, write data WD for the memory 106 and a valid signal WDv, which indicates that the write data WD is valid information.

[0022] The read address interface unit 203 is connected between the data bus 104 and the arbitration unit 205. The read address interface unit 203 outputs a ready signal RAr to the data bus 104, indicating that read address information can be input. The read address interface unit 203 also inputs a read address RA of the memory 106, a read burst transfer length RL, and a valid signal RAv from the data bus 104. The valid signal RAv indicates that the read address RA and the read burst transfer length RL are valid information.

[0023] The read data interface unit 204 is connected between the data bus 104 and the arbitration unit 205. The read data interface unit 204 outputs the read data RD read from the memory 106 by the arbitration unit 205 and a valid signal RDv indicating that the read data RD is valid information to the data bus 104. The read data interface unit 204 also inputs a ready signal RDr indicating that the data bus 104 is ready to input data.

[0024] The arbitration unit 205 controls the process of writing data to the memory 106 based on write address information, and controls the process of reading data from the memory 106 based on read address information. The arbitration unit 205 has a priority flag for determining whether to prioritize a write transaction when a conflict occurs between multiple memory accesses. The arbitration unit 205 outputs a chip enable signal CE, a write enable signal WE, a memory address MA, and write data MWD to the memory 106, and inputs read data MRD from the memory 106. The chip enable signal CE is a signal that enables writing or reading. The write enable signal WE is a signal that indicates writing of data. The memory address MA indicates a write address or a read address on the memory 106.

[0025] 3A and 3B are timing charts for explaining a control method of the memory control unit 105. The memory control unit 105 is a synchronous circuit that operates at the rising edge of the synchronous clock signal CK.

[0026] 3A is a timing chart for explaining a control method of the memory control unit 105 when the memory control unit 105 receives write address information and write data information. For example, the memory control unit 105 receives a write transaction issued by the image processing unit 102 via the data bus 104.

[0027] At time T301, when the ready signal WAr and the valid signal WAv are 1, the write address interface unit 201 receives the write address WA and the write burst transfer length WL from the image processing unit 102. For example, the write burst transfer length WL is 128. The write address interface unit 201 outputs the write address WA and the write burst transfer length WL to the arbitration unit 205.

[0028] When the ready signal WDr and the valid signal WDv are 1, the write data interface unit 202 receives write data WD for the memory 106 from the image processing unit 102. The write data interface unit 202 then outputs the write data WD to the arbitration unit 205.

[0029] At time T302, the arbitration unit 205 starts outputting the chip enable signal CE, write enable signal WE, memory address MA, and write data MWD based on the write address WA, write burst transfer length WL, and write data WD. The memory address MA is incremented sequentially from the start address indicated by the write address WA to the end address corresponding to the write burst transfer length WL. The write data MWD corresponds to the write data WD. When the chip enable signal CE and write enable signal WE are 1, the memory 106 writes the write data MWD to the memory address MA in the memory 106.

[0030] At time T303, the write data interface unit 202 finishes inputting the final write data WA, which has a length corresponding to the write burst transfer length WL that the write address interface unit 201 started inputting at time T301. Then, in the next clock cycle, the write data interface unit 202 writes the final write data MWD of the burst transfer.

[0031] 3B is a timing chart for explaining a control method of the memory control unit 105 when the memory control unit 105 receives read address information and read data information. For example, the memory control unit 105 receives a read transaction issued by the image processing unit 103 via the data bus 104.

[0032] At time T311, when the ready signal RAr and the valid signal RAv are 1, the read address interface unit 203 receives the read address RA and the read burst transfer length RL from the image processing unit 103. For example, the read burst transfer length RL is 4. The read address interface unit 203 outputs the read address RA and the read burst transfer length RL to the arbitration unit 205.

[0033] At time T312, the arbitration unit 205 starts outputting a chip enable signal CE of 1 and a write enable signal WE of 0 based on the read address RA and the read burst transfer length RL. When the chip enable signal CE is 1 and the write enable signal WE is 0, the memory 106 reads data stored at a memory address MA in the memory 106 and outputs the read data to the arbitration unit 205 as read data MRD. The memory address MA is incremented sequentially from the start address indicated by the read address RA to the end address corresponding to the read burst transfer length RL. The arbitration unit 205 outputs the read data MRD to the read data interface unit 204.

[0034] In the next clock cycle, the read data interface unit 204 outputs the read data RD and a valid signal RDv of 1 to the image processing unit 103 via the data bus 104 based on the read data MRD. The valid signal RDv of 1 indicates that the read data MRD is valid information. The read data RD corresponds to the read data MRD.

[0035] At time T313, the read data interface unit 204 ends the process of outputting the read data RD having a length corresponding to the read burst transfer length RL to the image processing unit 103.

[0036] 4 is a flowchart illustrating a control method of the memory control unit 105 performed in units of clocks. Hereinafter, a method of arbitrating conflicts between multiple memory accesses by the memory control unit 105 will be described with reference to FIG. 4. When a write transaction or a read transaction is input, the memory control unit 105 controls a write process for writing data to the memory 106 and a read process for reading data from the memory 106.

[0037] The priority flag of the arbitration unit 205 is a flag indicating whether or not a write transaction is to be prioritized, and is initially set to "1", for example. A priority flag of "1" means that a write transaction is to be prioritized. A priority flag of "0" means that a read transaction is to be prioritized.

[0038] The memory control unit 105 sets the ready signal WAr to 1 and waits to input a write transaction from the bus master, and sets the ready signal RAr to 1 and waits to input a read transaction. The bus master is the CPU 101, the image processing unit 102, or the image processing unit 103. An input of a write transaction is, for example, an input of a valid signal WAv, a write address WA, and a write burst transfer length WL at time T301 in FIG. 3A. An input of a read transaction is, for example, an input of a valid signal RAv, a read address RA, and a read burst transfer length RWL at time T311 in FIG. 3B. When a write transaction or a read transaction is input, the memory control unit 105 starts the write transaction or the read transaction.

[0039] In step S401, the memory control unit 105 determines whether at least one of a write transaction and a read transaction is currently being processed. If neither a write transaction nor a read transaction is currently being processed, the memory control unit 105 repeats step S401 (NO in S401). If at least one of a write transaction and a read transaction is currently being processed, the memory control unit 105 proceeds to step S402 (YES in S401).

[0040] In step S402, the memory control unit 105 determines whether a write transaction is being processed. If the memory control unit 105 determines that a write transaction is being processed, the process proceeds to step S403 (YES in S402). If the memory control unit 105 determines that a write transaction is not being processed, the process proceeds to step S408 (NO in S402).

[0041] In step S403, the memory control unit 105 determines whether a read transaction is being processed. If the memory control unit 105 determines that a read transaction is being processed, the process proceeds to step S404 (YES in S403). If the memory control unit 105 determines that a read transaction is not being processed, the process proceeds to step S407 (NO in S403).

[0042] Step S404 is a process performed when a write transaction and a read transaction conflict. In step S404, the arbitration unit 205 determines whether the priority flag is 1. If the arbitration unit 205 determines that the priority flag is 1, the process proceeds to step S405 (YES in S404), and if the arbitration unit 205 determines that the priority flag is 0, the process proceeds to step S406 (NO in S404).

[0043] In step S405, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. Furthermore, the arbitration unit 205 controls the process of writing the write data MWD to the memory 106. Then, the arbitration unit 205 sets the priority flag to 0, and the flowchart in FIG. 4 ends.

[0044] In step S406, the write data interface unit 202 stops the input of the write data WD by setting the ready signal WDr to 0. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. Furthermore, the arbitration unit 205 controls the process of reading the read data MRD from the memory 106. Then, the arbitration unit 205 sets the priority flag to 1, and the flowchart in FIG. 4 ends.

[0045] In step S407, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. Furthermore, the arbitration unit 205 controls the process of writing the write data MWD to the memory 106. This process corresponds to the process in FIG. 3(A). Then, the arbitration unit 205 sets the priority flag to 0, and the flowchart in FIG. 4 ends.

[0046] In step S408, the arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. Furthermore, the arbitration unit 205 controls the process of reading the read data MRD from the memory 106. This process corresponds to the process in FIG. 3(B). Then, the arbitration unit 205 sets the priority flag to 1, and the flowchart in FIG. 4 ends.

[0047] 5 is a timing chart for explaining a control method of the memory control unit 105 when a write transaction and a read transaction conflict with each other. The memory control unit 105 receives the write transaction issued by the image processing unit 102 and the read transaction issued by the image processing unit 103, and performs control based on the flowchart of FIG.

[0048] At time T501, when the ready signal WAr and valid signal WAv are 1, the write address interface unit 201 inputs the write address WA and write burst transfer length WL from the image processing unit 102. For example, the write burst transfer length WL is 128. The write address interface unit 201 outputs the write address WA and write burst transfer length WL to the arbitration unit 205. The write data interface unit 202 maintains the ready signal WDr at 1 and starts inputting write data WD. Since the memory control unit 105 is processing a write transaction and not a read transaction, the memory control unit 105 proceeds to step S407 (NO in S403).

[0049] At time T502, the arbitration unit 205 performs the process of step S407. In step S407, the arbitration unit 205 sets the chip enable signal CE to 1 and sets the write enable signal WE to 1. Furthermore, the arbitration unit 205 controls the process of writing the write data MWD to the memory address MA of the memory 106. Then, the arbitration unit 205 sets the priority flag to 0.

[0050] Time T503 is a time during the write process by burst transfer. At time T503, when the ready signal RAr and the valid signal RAv are 1, the read address interface unit 203 inputs the read address RA and the read burst transfer length RL from the image processing unit 103 and sets the ready signal RAr to 0. For example, the read burst transfer length RL is 4. The read address interface unit 203 outputs the read address RA and the read burst transfer length RL to the arbitration unit 205. Since the memory control unit 105 is processing a write transaction and a read transaction, the process proceeds to step S404 (YES in S403). Since the priority flag is 0 in step S404, the arbitration unit 205 proceeds to step S406 (NO in S404).

[0051] At time T504, the arbitration unit 205 performs the process of step S406. In step S406, the write data interface unit 202 stops the input of the write data WD by setting the ready signal WDr to 0. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. Furthermore, the arbitration unit 205 controls the process of reading the read data MRD from the memory 106. Then, the arbitration unit 205 sets the priority flag to 1.

[0052] At time T505, the memory control unit 105 is processing a write transaction and a read transaction, so the process proceeds to step S404 (YES in S403). In step S404, the arbitration unit 205 has the priority flag set to 1, so the process proceeds to step S405 (YES in S404). In step S405, the write data interface unit 202 sets the ready signal WDr to 1, thereby resuming input of the write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. Furthermore, the arbitration unit 205 controls the process of writing the write data MWD to the memory 106. Then, the arbitration unit 205 sets the priority flag to 0.

[0053] Similarly, the arbitration unit 205 controls the write process for writing data to the memory 106 and the read process for reading data from the memory 106 to be alternately repeated for each cycle of the clock signal CK.

[0054] At time T506, the arbitration unit 205 completes the read transaction and sets the ready signal RAr to 1. Since the memory control unit 105 is processing a write transaction and not a read transaction, the process proceeds to step S407 (NO in S403). In step S407, the arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1, thereby restarting the process of writing the write data MWD to the memory 106. Then, the arbitration unit 205 sets the priority flag to 0.

[0055] Time T507 is a time during the write process by burst transfer. At time T507, when the ready signal RAr and the valid signal RAv are 1, the read address interface unit 203 inputs the read address RA and the read burst transfer length RL from the image processing unit 103 and sets the ready signal RAr to 0. For example, the read burst transfer length RL is 4. The read address interface unit 203 outputs the read address RA and the read burst transfer length RL to the arbitration unit 205. Since the memory control unit 105 is processing a write transaction and a read transaction, the process proceeds to step S404 (YES in S403). Since the priority flag is 0 in step S404, the arbitration unit 205 proceeds to step S406 (NO in S404).

[0056] In step S406, the write data interface unit 202 sets the ready signal WDr to 0, thereby stopping the input of the write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. Furthermore, the arbitration unit 205 controls the process of reading the read data MRD from the memory 106. Then, the arbitration unit 205 sets the priority flag to 1. Thereafter, as from time T503 onwards, the arbitration unit 205 controls the write process of writing data to the memory 106 and the read process of reading data from the memory 106 to be repeated alternately for each cycle of the clock signal CK.

[0057] For example, the image processing unit 102 is a bus master that issues write transactions, and the image processing unit 103 is a bus master that issues read transactions.

[0058] If there is a conflict between the write transaction issued by the image processing unit 102 and the read transaction issued by the image processing unit 103, the memory control unit 105 proceeds to step S404 (YES in S403). In this case, the arbitration unit 205 controls the write process of writing data to the memory 106 and the read process of reading data from the memory 106 to be alternately repeated for each clock cycle.

[0059] In the case of the above-mentioned conflict, the arbitration unit 205 controls to perform a read process if the previous process was a write process, and controls to perform a write process if the previous process was a read process. In addition, in the case of the above-mentioned conflict, the arbitration unit 205 controls to perform a write process or a read process according to the priority flag.

[0060] As described above, according to the first embodiment, the arbitration unit 205 sets the priority flag to 0 after performing a write process, and sets the priority flag to 1 after performing a read process. This allows the arbitration unit 205 to efficiently process the read process even when there is a conflict between the write process and the read process.

[0061] In the first embodiment, the bus masters are the CPU 101, the image processing unit 102, and the image processing unit 103, and are connected to the data bus 104, but the number of bus masters is not limited. A configuration in which more bus masters are connected to the data bus 104 and each bus master performs memory access to the memory 106 is also possible. The functions and number of signals input or output between the data bus 104 and the memory control unit 105 described in FIG. 2 are merely an example and are not limited to the above example.

[0062] 3A, 3B, and 5 may have clock cycle shifts due to buffers depending on the circuit configuration of the memory control unit 105 and the memory 106. Furthermore, the polarity of the signal logic may have different meanings, and the signal waveforms are not limited.

[0063] [Embodiment 2] 6 is a block diagram for explaining the components of the electronic device 600 according to the second embodiment. Of the components of the electronic device 600 according to the second embodiment, the same components as those of the electronic device 100 according to the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0064] 6, electronic device 600 includes CPU 101, image processing unit 102, image processing unit 103, data bus 104, memory control unit 605, and memory 606. Each component of electronic device 600 includes an electronic circuit for realizing the functions described below.

[0065] The CPU 101, the image processing unit 102, and the image processing unit 103 are each a bus master. The memory control unit 605 is a bus slave. The data bus 104 interconnects the CPU 101, the image processing unit 102, the image processing unit 103, and the memory control unit 605.

[0066] The memory 606 has multiple single-port SRAMs (1-port SRAMs). Data writing and reading are performed exclusively in each of the multiple single-port SRAMs. The memory 606 also divides its address area and sets consecutive address areas for the multiple single-port SRAMs.

[0067] The memory control unit 605 is connected to the data bus 104 and controls memory access to the memory 606 based on a write transaction or a read transaction issued by a bus master. When a conflict occurs between a write transaction and a read transaction, the memory control unit 605 arbitrates the conflict between multiple memory accesses and controls a write process for writing data to the memory 606 and a read process for reading data from the memory 606.

[0068] FIG. 7 is a block diagram illustrating the components of memory control unit 605. As shown in FIG.

[0069] The memory control unit 605 has a write address interface unit 201, a write data interface unit 202, a read address interface unit 203, a read data interface unit 204, an arbitration unit 701, and a selector 702. Each component of the memory control unit 605 has an electronic circuit for realizing the functions described below.

[0070] The memory 606 has a plurality of memory banks 711 to 714. Each of the plurality of memory banks 711 to 714 is a single-port SRAM in which data is written and read exclusively. As an example, the memory 606 divides the addresses on the memory 606 into four, and sets consecutive addresses on the four single-port SRAMs, memory bank 711, memory bank 712, memory bank 713, and memory bank 714.

[0071] The memory bank 711 receives the chip enable signal CE1, the write enable signal WE1, the memory address MA1, and the write data MWD1 from the selector 702, and outputs the read data MRD1 to the selector 702.

[0072] The memory bank 712 receives the chip enable signal CE2, the write enable signal WE2, the memory address MA2, and the write data MWD2 from the selector 702, and outputs the read data MRD2 to the selector 702.

[0073] The memory bank 713 receives the chip enable signal CE3, the write enable signal WE3, the memory address MA3, and the write data MWD3 from the selector 702, and outputs the read data MRD3 to the selector 702.

[0074] The memory bank 714 receives the chip enable signal CE4, the write enable signal WE4, the memory address MA4, and the write data MWD4 from the selector 702, and outputs the read data MRD4 to the selector 702.

[0075] Chip enable signals CE1 to CE4 are the same as the chip enable signal CE in FIG. 2. Write enable signals WE1 to WE4 are the same as the write enable signal WE in FIG. 2. Memory addresses MA1 to MA4 are the same as the memory address MA in FIG. 2. Write data MWD1 to MWD4 are the same as the write data MWD in FIG. 2. Read data MRD1 to MRD4 are the same as the read data MRD in FIG. 2.

[0076] 2, the memory control unit 605 has a different configuration for the arbitration unit 701 and an additional selector 702. When a conflict occurs between a write process for writing data to the memory 606 and a read process for reading data from the memory 106, the arbitration unit 701 determines which of the memory banks 711 to 714 the data is to be written to or read from, based on write address information and read address information, and determines the memory bank. Based on the determination result of the arbitration unit 701, the selector 702 controls the writing and reading of data corresponding to each of the memory banks 711 to 714, in the same way as it controls the memory 106 in the first embodiment.

[0077] When a write transaction and a read transaction conflict, the arbitration unit 701 determines whether the memory bank to be written to and the memory bank to be read from are the same. If the memory bank to be written to and the memory bank to be read from are the same, the arbitration unit 701 performs arbitration in the same manner as in embodiment 1. If the memory bank to be written to and the memory bank to be read from are not the same, the arbitration unit 701 controls the write and read operations independently and in parallel. The memory control unit 605 can process more transactions in a shorter period of time, improving data write and data read performance.

[0078] Fig. 8 is a flowchart for explaining a control method of the memory control unit 605 performed in units of clocks. Hereinafter, a method for arbitrating contention between multiple memory accesses by the memory control unit 605 will be described with reference to Fig. 8. When a write transaction or a read transaction is input, the memory control unit 605 controls a write process for writing data to the memory banks 711 to 714 and a read process for reading data from the memory banks 711 to 714.

[0079] The priority flag of the arbitration unit 701 is a flag indicating whether or not a write transaction is to be prioritized, and is initially set to "1", for example. A priority flag of "1" means that a write transaction is to be prioritized. A priority flag of "0" means that a read transaction is to be prioritized.

[0080] The memory control unit 605 sets the ready signal WAr to 1 and waits to input a write transaction, and sets the ready signal RAr to 1 and waits to input a read transaction.

[0081] In step S801, the memory control unit 605 determines whether at least one of a write transaction and a read transaction is currently being processed. If neither a write transaction nor a read transaction is currently being processed, the memory control unit 605 repeats step S801 (NO in S801). If at least one of a write transaction and a read transaction is currently being processed, the memory control unit 605 proceeds to step S802 (YES in S801).

[0082] In step S802, the arbitration unit 701 determines which of the four memory banks 711 to 714 is the target for writing or reading, based on the input write address WA or read address RA.

[0083] In step S803, the memory control unit 605 determines whether a write transaction is being processed. If the memory control unit 605 determines that a write transaction is being processed, the process proceeds to step S804 (YES in S803). If the memory control unit 605 determines that a write transaction is not being processed, the process proceeds to step S811 (NO in S803).

[0084] In step S804, the memory control unit 605 determines whether a read transaction is being processed. If the memory control unit 605 determines that a read transaction is being processed, the process proceeds to step S805 (YES in S804). If the memory control unit 605 determines that a read transaction is not being processed, the process proceeds to step S810 (NO in S804).

[0085] Step S805 is a process performed when a write transaction and a read transaction conflict. In step S805, the arbitration unit 701 determines whether the memory bank to be written and the memory bank to be read, determined in step S802, are the same. If the arbitration unit 701 determines that they are the same, the write transaction and the read transaction conflict, and therefore the process proceeds to step S806 (YES in S805). If the arbitration unit 701 determines that they are not the same, the write transaction and the read transaction do not conflict, and therefore the process proceeds to step S809 (NO in S805).

[0086] In step S806, the arbitration unit 701 determines whether the priority flag is 1. If the arbitration unit 701 determines that the priority flag is 1, the process proceeds to step S807 (YES in S806), and if the arbitration unit 701 determines that the priority flag is 0, the process proceeds to step S808 (NO in S806).

[0087] In step S807, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 701 sets the chip enable signals CE1 to CE4 of the memory bank to be written that was determined in step S802 to 1, and sets the write enable signals WE1 to WE4 of the memory bank to be written to 1. Furthermore, the arbitration unit 701 controls the process of writing the write data to the memory bank to be written that was determined in step S802. Then, the arbitration unit 701 sets the priority flag to 0, and the flowchart in FIG. 8 ends.

[0088] In step S808, the write data interface unit 202 sets the ready signal WDr to 0, thereby stopping the input of the write data WD. The arbitration unit 701 sets the chip enable signals CE1 to CE4 of the memory bank to be read determined in step S802 to 1, and sets the write enable signals WE1 to WE4 of the memory bank to be read to 0. Furthermore, the arbitration unit 701 controls the process of reading the read data MRD1 to MRD4 from the memory bank to be read determined in step S802. Then, the arbitration unit 701 sets the priority flag to 1, and the flowchart in FIG. 8 ends.

[0089] In step S809, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 701 sets the chip enable signals CE1 to CE4 of the memory bank to be written determined in step S802 to 1, and sets the write enable signals WE1 to WE4 of the memory bank to be written to 1. Furthermore, the arbitration unit 701 controls the process of writing the write data to the memory bank to be written determined in step S802.

[0090] The arbitration unit 701 also sets the chip enable signals CE1 to CE4 of the memory bank to be read determined in step S802 to 1, and sets the write enable signals WE1 to WE4 of the memory bank to be read to 0. Furthermore, the arbitration unit 701 controls the process of reading the read data MRD1 to MRD4 from the memory bank to be read determined in step S802. Then, the flowchart in FIG. 8 ends.

[0091] In step S810, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 701 sets the chip enable signals CE1 to CE4 of the memory bank to be written that was determined in step S802 to 1, and sets the write enable signals WE1 to WE4 of the memory bank to be written to 1. Furthermore, the arbitration unit 701 controls the process of writing the write data to the memory bank to be written that was determined in step S802. Then, the arbitration unit 701 sets the priority flag to 0, and the flowchart in FIG. 8 ends.

[0092] In step S811, the write data interface unit 202 sets the ready signal WDr to 0, thereby stopping the input of write data WD. The arbitration unit 701 sets the chip enable signals CE1 to CE4 of the memory bank to be read that was determined in step S802 to 1, and sets the write enable signals WE1 to WE4 of the memory bank to be read to 0. Furthermore, the arbitration unit 701 controls the process of reading the read data MRD1 to MRD4 from the memory bank to be read that was determined in step S802. Then, the arbitration unit 701 sets the priority flag to 1, and the flowchart in FIG. 8 ends.

[0093] 9 is a timing chart for explaining a control method of the memory control unit 605 when a write transaction and a read transaction conflict with each other. The memory control unit 605 inputs the write transaction issued by the image processing unit 102 and the read transaction issued by the image processing unit 103, and performs control based on the flowchart of FIG.

[0094] At time T901, when the ready signal WAr and valid signal WAv are 1, the write address interface unit 201 inputs the write address WA and write burst transfer length WL from the image processing unit 102. For example, the write burst transfer length WL is 128. The write data interface unit 202 maintains the ready signal WDr at 1 and starts inputting the write data WD. In step S802, the arbitration unit 701 determines, for example, that the memory bank to be written to is memory bank 711 based on the input write address WA. Since the memory control unit 605 is processing a write transaction and not a read transaction, the process proceeds to step S810 (NO in S804).

[0095] At time T902, the arbitration unit 701 performs the process of step S810. In step S810, the arbitration unit 701 sets the chip enable signal CE1 of the memory bank 711 to be written to 1, and sets the write enable signal WE1 to 1. Furthermore, the arbitration unit 701 controls the write process of the write data MWD1 to the memory address MA1 of the memory bank 711. Then, the arbitration unit 701 sets the priority flag to 0.

[0096] Time T903 is a time during the write process by burst transfer. At time T903, when the ready signal RAr and the valid signal RAv are 1, the read address interface unit 203 inputs the read address RA and the read burst transfer length RL from the image processing unit 103 and sets the ready signal RAr to 0. For example, the read burst transfer length RL is 4. In step S802, the arbitration unit 701 determines, for example, that the memory bank to be read is memory bank 712 based on the input read address RA. Since the memory control unit 605 is processing a write transaction and a read transaction, the process proceeds to step S805 (YES in S804). In step S805, the arbitration unit 701 determines that the memory bank to be written to and the memory bank to be read from are not the same, so the process proceeds to step S809 (NO in S805).

[0097] At time T904, the arbitration unit 701 performs the process of step S809. In step S809, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 701 sets the chip enable signal CE1 of the memory bank 711 to be written to 1, sets the write enable signal WE1 to 1, and continues the process of writing the write data MWD1 to the memory bank 711.

[0098] The arbitration unit 701 also sets the chip enable signal CE2 of the memory bank 712 that is the read target to 1 and sets the write enable signal WE2 to 0. This causes the arbitration unit 701 to read the read data MRD2 from the memory bank 712. The arbitration unit 701 starts the process of reading the read data MRD2 from the memory bank 712. As described above, the arbitration unit 701 performs the read process on the memory bank 712 in parallel with the write process on the memory bank 711.

[0099] Time T905 is the time after the read process by burst transfer has ended and is a time during the write process by burst transfer. At time T905, when the ready signal RAr and the valid signal RAv are 1, the read address interface unit 203 inputs the read address RA and the read burst transfer length RL from the image processing unit 103 and sets the ready signal RAr to 0. For example, the read burst transfer length RL is 4. In step S802, the arbitration unit 701 determines, for example, that the memory bank to be read is memory bank 711 based on the input read address RA. Since the memory control unit 605 is processing a write transaction and a read transaction, the process proceeds to step S805 (YES in S804). In step S805, the arbitration unit 701 proceeds to step S806 (YES in S805) because the memory bank to be written and the memory bank to be read are the same. In step S806, the arbitration unit 701 determines that the priority flag is 0, and therefore proceeds to step S808 (NO in S806).

[0100] At time T906, the arbitration unit 701 performs the process of step S808. In step S808, the write data interface unit 202 stops the input of the write data WD by setting the ready signal WDr to 0. The arbitration unit 701 sets the chip enable signal CE1 of the memory bank 711 to be read to 1 and sets the write enable signal WE1 to 0. Furthermore, the arbitration unit 701 controls the process of reading the read data MRD1 from the memory bank 711 to be read. Then, the arbitration unit 701 sets the priority flag to 1. The arbitration unit 701 starts the process of reading the read data MRD1 from the memory bank 711.

[0101] At time T907, the memory control unit 605 is processing a write transaction and a read transaction, and the memory bank to be written to is the same as the memory bank to be read from, so the process proceeds to step S806 (YES in S805). In step S806, the arbitration unit 701 determines that the priority flag is 1, so the process proceeds to step S807 (YES in S806).

[0102] At time T908, the arbitration unit 701 performs the process of step S807. In step S807, the write data interface unit 202 sets the ready signal WDr to 1, thereby restarting the input of the write data WD. The arbitration unit 701 sets the chip enable signal CE1 of the memory bank 711 to be written to 1, and sets the write enable signal WE1 to 1. Furthermore, the arbitration unit 701 controls the process of writing the write data to the memory bank 711 to be written to. Then, the arbitration unit 701 sets the priority flag to 0.

[0103] Similarly, the arbitration unit 701 controls the write process for writing data to the memory bank 711 and the read process for reading data from the memory bank 711 to be alternately repeated for each cycle of the clock signal CK.

[0104] At time T908, the arbitration unit 701 completes the read transaction and sets the ready signal RAr to 1. Since the memory control unit 605 is processing a write transaction and not a read transaction, the process proceeds to step S810 (NO in S804). In step S810, the arbitration unit 701 sets the chip enable signal CE1 of the memory bank 711 to 1 and sets the write enable signal WE1 to 1. This causes the arbitration unit 701 to resume the process of writing the write data MWD1 to the memory bank 711. Then, the arbitration unit 701 sets the priority flag to 0.

[0105] If there is a conflict between the write transaction issued by the image processing unit 102 and the read transaction issued by the image processing unit 103, the memory control unit 605 proceeds to step S805 (NO in S804). If the memory bank that is the target of the write transaction issued by the image processing unit 102 and the memory bank that is the target of the read transaction issued by the image processing unit 103 are the same, the memory control unit 605 proceeds to step S806. In this case, the arbitration unit 701 controls so that a write process for writing data to a memory bank and a read process for reading data from a memory bank are alternately repeated for each clock cycle.

[0106] If the memory bank that is the target of the write transaction issued by the image processing unit 102 is different from the memory bank that is the target of the read transaction issued by the image processing unit 103, the memory control unit 605 proceeds to step S809. In step S809, the arbitration unit 701 controls the write and read operations to be performed in parallel on the different memory banks.

[0107] As described above, according to the second embodiment, when a write transaction and a read transaction are being processed, the arbitration unit 701 determines whether the memory bank to be written to and the memory bank to be read from are the same. If the memory bank to be written to and the memory bank to be read from are the same, the arbitration unit 701 can perform arbitration similar to that of the first embodiment. If the memory bank to be written to and the memory bank to be read from are not the same, the arbitration unit 701 can perform the write and read operations independently and in parallel. This allows the arbitration unit 205 to efficiently process the read operation even when the write operation and the read operation conflict.

[0108] [Embodiment 3] The configuration of the electronic device 100 in the third embodiment is the same as the configuration of the electronic device 100 in the first embodiment. The following describes the differences between the third embodiment and the first embodiment. In the third embodiment, when a write transaction or a read transaction continues, the memory control unit 105 performs arbitration by prioritizing the continuing transaction. Therefore, the memory control unit 105 can efficiently shorten the latency until the memory access of the bus master that issued the transaction is completed, thereby improving data transfer performance. This effect can be expected particularly when there is not a high volume of write transactions and read transactions, or when there are many transactions with short burst transfer lengths.

[0109] 10 is a flowchart illustrating a control method of the memory control unit 105 performed in units of clocks. A method for arbitrating conflicts between multiple memory accesses will be described below with reference to FIG. 10. When a write transaction or a read transaction is input, the memory control unit 105 controls a write process for writing data to the memory 106 and a read process for reading data from the memory 106. In the third embodiment, the setting conditions for the priority flag of the arbitration unit 205 are different from those in the first embodiment.

[0110] For example, the priority flag of the arbitration unit 205 is initially set to "1." The memory control unit 105 sets the ready signal WAr to 1 and waits to input a write transaction, and sets the ready signal RAr to 1 and waits to input a read transaction.

[0111] In step S1001, the memory control unit 105 determines whether at least one of a write transaction and a read transaction is currently being processed. If neither a write transaction nor a read transaction is currently being processed, the memory control unit 105 repeats step S1001 (NO in S1001). If at least one of a write transaction and a read transaction is currently being processed, the memory control unit 105 proceeds to step S1002 (YES in S1001).

[0112] In step S1002, the memory control unit 105 determines whether a write transaction is being processed. If the memory control unit 105 determines that a write transaction is being processed, the process proceeds to step S1003 (YES in S1002). If the memory control unit 105 determines that a write transaction is not being processed, the process proceeds to step S1008 (NO in S1002).

[0113] In step S1003, the memory control unit 105 determines whether a read transaction is being processed. If the memory control unit 105 determines that a read transaction is being processed, the process proceeds to step S1004 (YES in S1003). If the memory control unit 105 determines that a read transaction is not being processed, the process proceeds to step S1007 (NO in S1003).

[0114] Step S1004 is a process performed when a write transaction and a read transaction conflict. In step S1004, the arbitration unit 205 determines whether the priority flag is 1. If the arbitration unit 205 determines that the priority flag is 1, the process proceeds to step S1005 (YES in S1004), and if the arbitration unit 205 determines that the priority flag is 0, the process proceeds to step S1006 (NO in S1004).

[0115] In step S1005, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. Furthermore, the arbitration unit 205 controls the process of writing the write data MWD to the memory 106.

[0116] In step S1006, the write data interface unit 202 stops the input of the write data WD by setting the ready signal WDr to 0. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. Furthermore, the arbitration unit 205 controls the process of reading the read data MRD from the memory 106.

[0117] In step S1007, the write data interface unit 202 sets the ready signal WDr to 1, thereby enabling input of write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. Then, the arbitration unit 205 controls the process of writing the write data MWD to the memory 106.

[0118] In step S1008, the arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. Furthermore, the arbitration unit 205 controls the process of reading the read data MRD from the memory 106.

[0119] In step S1009, the arbitration unit 205 determines whether the write transaction continues in the next cycle of the clock signal CK. If the arbitration unit 205 determines that the write transaction continues, the process proceeds to step S1011 (YES in S1009). If the arbitration unit 205 determines that the write transaction has been completed, the process proceeds to step S1012 (NO in S1009).

[0120] In step S1010, the arbitration unit 205 determines whether the read transaction will continue in the next cycle of the clock signal CK. If the arbitration unit 205 determines that the read transaction will continue, the process proceeds to step S1013 (YES in S1010). If the arbitration unit 205 determines that the read transaction has been completed, the process proceeds to step S1014 (NO in S1010).

[0121] In step S1011, the arbitration unit 205 sets the priority flag to 1, and the flowchart in FIG. 10 ends.

[0122] In step S1012, the arbitration unit 205 sets the priority flag to 0, and the flowchart in FIG. 10 ends.

[0123] In step S1013, the arbitration unit 205 sets the priority flag to 0, and the flowchart in FIG. 10 ends.

[0124] In step S1014, the arbitration unit 205 sets the priority flag to 1, and the flowchart in FIG. 10 ends.

[0125] 11 is a timing chart for explaining a control method of the memory control unit 105 when a write transaction and a read transaction conflict with each other. The memory control unit 105 inputs the write transaction issued by the image processing unit 102 and the read transaction issued by the image processing unit 103, and performs control based on the flowchart of FIG.

[0126] At time T1101, when the ready signal WAr and the valid signal WAv are 1, the write address interface unit 201 inputs the write address WA and the write burst transfer length WL from the image processing unit 102. For example, the write burst transfer length WL is 4. The write data interface unit 202 maintains the ready signal WDr at 1 and starts inputting the write data WD. Since the memory control unit 105 is processing a write transaction and not a read transaction, the process proceeds to step S1007 (NO in S1003).

[0127] At time T1102, the arbitration unit 205 performs the process of step S1007. In step S1007, the arbitration unit 205 sets the chip enable signal CE to 1 and sets the write enable signal WE to 1. Then, the arbitration unit 205 controls the process of writing the write data MWD to the memory address MA of the memory 106. In step S1009, the arbitration unit 205 determines that the write transaction continues, and proceeds to step S1011. In step S1011, the arbitration unit 205 sets the priority flag to 1 and ends the process for the cycle of the clock signal CK. The arbitration unit 205 repeats the same process, writing four pieces of write data WD to the memory 106 in four cycles.

[0128] At time T1103, the arbitration unit 205 performs the process of step S1007 (NO in S1003). In step S1007, the arbitration unit 205 controls the process of writing the write data MWD to memory address MA in the memory 106. In step S1009, the arbitration unit 205 determines that the write transaction is completed, and proceeds to step S1012. In step S1012, the arbitration unit 205 sets the priority flag to 0, and ends the process for the cycle of the clock signal CK.

[0129] At time T1104, when the ready signal WAr and the valid signal WAv are 1, the write address interface unit 201 inputs the write address WA and the write burst transfer length WL from the image processing unit 102. For example, the write burst transfer length WL is 4. The write data interface unit 202 maintains the ready signal WDr at 1 and starts inputting the write data WD. Since the memory control unit 105 is processing a write transaction and not a read transaction, the process proceeds to step S1007 (NO in S1003).

[0130] At time T1105, the arbitration unit 205 performs the processing of step S1007. In step S1007, the arbitration unit 205 sets the chip enable signal CE to 1 and sets the write enable signal WE to 1. The arbitration unit 205 then controls the processing of writing the write data MWD to the memory address MA of the memory 106. In step S1009, the arbitration unit 205 determines that the write transaction continues, and proceeds to step S1011. In step S1011, the arbitration unit 205 sets the priority flag to 1 and ends the processing of the cycle of the clock signal CK.

[0131] Time T1106 is a time during the write process by burst transfer. At time T1106, when the ready signal RAr and the valid signal RAv are 1, the read address interface unit 203 inputs the read address RA and the read burst transfer length RL from the image processing unit 103 and sets the ready signal RAr to 0. For example, the read burst transfer length RL is 4. The read address interface unit 203 outputs the read address RA and the read burst transfer length RL to the arbitration unit 205. Since the memory control unit 105 is processing a write transaction and a read transaction, the process proceeds to step S1004 (YES in S1003). Since the priority flag is 1 in step S1004, the arbitration unit 205 proceeds to step S1005 (NO in S1004).

[0132] In step S1005, the write data interface unit 202 inputs the write data WD by setting the ready signal WDr to 1. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. The arbitration unit 205 then controls the process of writing the write data MWD to the memory 106. In step S1009, the arbitration unit 205 determines that the write transaction continues, and proceeds to step S1011. In step S1011, the arbitration unit 205 sets the priority flag to 1 and ends the process for the cycle of the clock signal CK. The arbitration unit 205 repeats the same process, writing four pieces of write data WD to the memory 106 in four cycles.

[0133] At time T1107, the memory control unit 105 is not processing a write transaction but is processing a read transaction, so the process proceeds to step S1008 (NO in S1002). In step S1008, the arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. The arbitration unit 205 then controls the process of reading read data MRD from the memory 106. In step S1010, the arbitration unit 205 determines that the read transaction continues, and the process proceeds to step S1013. In step S1013, the arbitration unit 205 sets the priority flag to 0 and ends the process for the cycle of the clock signal CK. The arbitration unit 205 repeats the same process, reading four pieces of read data MRD from the memory 106 in four cycles.

[0134] At time T1108, the memory control unit 105 is not processing a write transaction but is processing a read transaction, so the process proceeds to step S1008 (NO in S1002). In step S1008, the arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. The arbitration unit 205 then controls the process of reading the read data MRD from the memory 106. In step S1010, the arbitration unit 205 determines that the read transaction is complete, and the process proceeds to step S1014. In step S1014, the arbitration unit 205 sets the priority flag to 1 and ends the process for that cycle of the clock signal CK.

[0135] At time T1109, the arbitration unit 205 completes the read transaction and sets the ready signal RAr to 1.

[0136] At time T1110, when the ready signal RAr and the valid signal RAv are 1, the read address interface unit 203 inputs the read address RA and the read burst transfer length RL from the image processing unit 103 and sets the ready signal RAr to 0. For example, the read burst transfer length RL is 4. The read address interface unit 203 outputs the read address RA and the read burst transfer length RL to the arbitration unit 205. Since the memory control unit 105 is not processing a write transaction but is processing a read transaction, the process proceeds to step S1008 (NO in S1002).

[0137] At time T1111, the arbitration unit 205 performs the process of step S1008. In step S1008, the arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. Then, the arbitration unit 205 controls the process of reading the read data MRD from the memory 106. In step S1010, the arbitration unit 205 determines that the read transaction continues, and proceeds to step S1013. In step S1013, the arbitration unit 205 sets the priority flag to 0 and ends the process for the cycle of the clock signal CK.

[0138] Time T1112 is a time during the read process by burst transfer. At time T1112, when the ready signal WAr and valid signal WAv are 1, the write address interface unit 201 inputs the write address WA and write burst transfer length WL from the image processing unit 102. For example, the write burst transfer length WL is 4. The write data interface unit 202 maintains the ready signal WDr at 1 and starts inputting the write data WD. Since the write transaction and read transaction are being processed, the memory control unit 105 proceeds to step S1004 (YES in S1003). Since the priority flag is 0 in step S1004, the arbitration unit 205 proceeds to step S1006 (NO in S1004).

[0139] In step S1006, the write data interface unit 202 sets the ready signal WDr to 0, thereby stopping the input of the write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 0. The arbitration unit 205 then controls the process of reading the read data MRD from the memory 106. In step S1010, the arbitration unit 205 determines that the read transaction continues, and proceeds to step S1013. In step S1013, the arbitration unit 205 sets the priority flag to 0, and ends the processing of the cycle of the clock signal CK.

[0140] The arbitration unit 205 repeats the same process, reading four pieces of read data MRD from the memory 106 in four cycles. In step S1010, the arbitration unit 205 determines that the read transaction is completed, and proceeds to step S1014. In step S1014, the arbitration unit 205 sets the priority flag to 1. Since the memory control unit 105 is processing a write transaction and not a read transaction, it proceeds to step S1007 (NO in S1003).

[0141] At time T1113, the arbitration unit 205 performs the process of step S1007. In step S1007, the write data interface unit 202 sets the ready signal WDr to 1, thereby restarting the input of the write data WD. The arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. The arbitration unit 205 then controls the process of writing the write data MWD to the memory address MA of the memory 106. In step S1009, the arbitration unit 205 determines that the write transaction continues, and proceeds to step S1011. In step S1011, the arbitration unit 205 sets the priority flag to 1 and ends the process for the cycle of the clock signal CK. The arbitration unit 205 repeats the same process, writing four pieces of write data WD to the memory 106 in four cycles.

[0142] At time T1114, the write data interface unit 202 completes input of the write data WD. The memory control unit 105 sets the ready signal WAr to 1 and waits to input a write transaction. In step S1007, the arbitration unit 205 sets the chip enable signal CE to 1 and the write enable signal WE to 1. The arbitration unit 205 then controls the process of writing the write data MWD to memory address MA in the memory 106. In step S1009, the arbitration unit 205 determines that the write transaction is complete, and the process proceeds to step S1012. In step S1012, the arbitration unit 205 sets the priority flag to 0 and ends processing for that cycle of the clock signal CK.

[0143] If there is a conflict between the write transaction issued by the image processing unit 102 and the read transaction issued by the image processing unit 103, the memory control unit 105 proceeds to step S1004 (YES in S1003).

[0144] Times T1104 to T1109 correspond to the case where the memory control unit 105 inputs a write transaction before a read transaction in the case of the above conflict. In this case, the arbitration unit 205 performs control so that reading based on the read transaction is performed after completing control of writing based on the write transaction.

[0145] Times T1110 to T1114 correspond to the case where the memory control unit 105 inputs a read transaction before a write transaction in the case of the above conflict. In this case, the arbitration unit 205 performs control so that writing based on the write transaction is performed after completing control of reading based on the read transaction.

[0146] As described above, according to the third embodiment, the arbitration unit 205 sets the priority flag to 1 when a write transaction continues, and sets the priority flag to 1 when a read transaction continues. This allows the arbitration unit 205 to efficiently process the read process even when there is a conflict between the write process and the read process. Note that the memory control unit 105 can selectively perform the control method based on the flowchart in FIG. 4 or the control method based on the flowchart in FIG. 10 depending on the operating status of the electronic device 100. [Explanation of symbols]

[0147] 100 Electronic device, 101 CPU, 102 Image processing unit, 103 Image processing unit, 104 Data bus, 105 Memory control unit, 106 Memory, 201 Write address interface unit, 202 Write data interface unit, 203 Read address interface unit, 204 Read data interface unit, 205 Arbitration unit

Claims

1. Memory and a first bus master that issues a write transaction including a write burst transfer length to the memory; a second bus master that issues a read transaction including a read burst transfer length to the memory; performing a write process in which, in response to the write transaction issued by the first bus master, write data having a length corresponding to the write burst transfer length is written to the memory by burst transfer when there is no conflict between the write transaction issued by the first bus master and the read transaction issued by the second bus master; an arbitration unit that, when there is no conflict between the write transaction issued by the first bus master and the read transaction issued by the second bus master, performs a read process of reading read data of a length corresponding to the read burst transfer length from the memory by burst transfer in response to the read transaction from the second bus master; the arbitration unit controls the write transaction to write data to the memory based on the write transaction and the read transaction to read data from the memory based on the read transaction so that, when there is a conflict between a write process of data with a write burst transfer length of a first length by a write transaction issued by the first bus master and a read process of data with a read burst transfer length of a second length different from the first length by a read transaction issued by the second bus master, the write process of data to the memory based on the write transaction and the read process of data from the memory based on the read transaction are alternately repeated for each clock cycle.

2. 2. The electronic device according to claim 1, wherein, when a write transaction issued by the first bus master and a read transaction issued by the second bus master conflict with each other, the arbitration unit controls the buses to perform a read process if the previous process was a write process, and controls the buses to perform a write process if the previous process was a read process.

3. 3. The electronic device according to claim 1, wherein the arbitration unit controls the execution of a write process or a read process depending on a flag when a conflict occurs between a write transaction issued by the first bus master and a read transaction issued by the second bus master.

4. 4. The electronic device according to claim 1, wherein the memory is a single-port SRAM.

5. the arbitration unit operates in synchronization with a clock signal; 5. The electronic device according to claim 1, wherein the clock cycle is a clock cycle of the clock signal.

6. the first bus master is a first image processing unit that performs image processing, and the second bus master is a second image processing unit that performs image processing; 6. The electronic device according to claim 1, wherein the first image processing unit writes and reads data via the arbitration unit, and the second image processing unit writes and reads data via the arbitration unit.

7. the memory has a plurality of memory banks; 3. The electronic device according to claim 1, wherein, when a write transaction issued by the first bus master and a read transaction issued by the second bus master conflict, if the memory bank that is the target of the write transaction issued by the first bus master and the memory bank that is the target of the read transaction issued by the second bus master are the same, the arbitration unit controls the write process of writing data to the memory bank and the read process of reading data from the memory bank to be alternately repeated every clock cycle.

8. 8. The electronic device according to claim 7, wherein, when a write transaction issued by the first bus master and a read transaction issued by the second bus master conflict with each other, if a memory bank that is a target of the write transaction issued by the first bus master is different from a memory bank that is a target of the read transaction issued by the second bus master, the arbitration unit controls the writing and reading to be performed in parallel on the different memory banks.

9. 9. The electronic device according to claim 7, wherein each of the plurality of memory banks is a single-port SRAM.

10. the arbitration unit performs a first control to perform control such that, when a conflict occurs between a write transaction issued by the first bus master and a read transaction issued by the second bus master, a write process of writing data to the memory and a read process of reading data from the memory are alternately repeated for each clock cycle; 7. The electronic device according to claim 1, wherein the electronic device is configured to perform one of two types of control: when a write transaction issued by the first bus master and a read transaction issued by the second bus master conflict, if the write transaction is input before the read transaction, control is performed so that reading based on the read transaction is performed after writing based on the write transaction is completed, and if the read transaction is input before the write transaction, control is performed so that writing based on the write transaction is performed after reading based on the read transaction is completed.

11. An electronic device as described in any one of claims 1 to 10, characterized in that the arbitration unit controls so that when either the conflicting write transaction or the read transaction is completed first, the write process of data corresponding to the write burst transfer length or the read process of data corresponding to the read burst transfer length is performed by the conflicting write transaction or the read transaction that has not been completed.

12. 1. A method for controlling an electronic device having a memory, a first bus master that issues a write transaction including a write burst transfer length to the memory, and a second bus master that issues a read transaction including a read burst transfer length to the memory, comprising: performing a write process in which, in response to the write transaction issued by the first bus master, write data having a length corresponding to the write burst transfer length is written to the memory by burst transfer when there is no conflict between the write transaction issued by the first bus master and the read transaction issued by the second bus master; an arbitration step of performing a read process in which, when there is no conflict between the write transaction issued by the first bus master and the read transaction issued by the second bus master, read data of a length corresponding to the read burst transfer length is read from the memory by burst transfer in response to the read transaction from the second bus master; a control method characterized in that, when a conflict occurs between a write process of data having a write burst transfer length of a first length by a write transaction issued by the first bus master and a read process of data having a read burst transfer length of a second length different from the first length by a read transaction issued by the second bus master, the arbitration step controls so that the write process of data to the memory based on the write transaction and the read process of data from the memory based on the read transaction are alternately repeated for each clock cycle.

Images