Memory System

Abstract

To provide a memory system that suppresses deterioration in memory access performance to a semiconductor memory device.SOLUTION: A memory system 100 includes: a semiconductor memory device 120 that includes a plurality of bank groups BG0 to BG15; and a memory controller 110 that issues a command in response to a request for access to the semiconductor memory device from an arithmetic unit 200 that accesses the semiconductor memory device. The memory controller sets, according to a data length of the data when the access is requested, an access burst length BLa, which is a burst length when accessing such data, and performs parallel access to access destination bank groups, which are a plurality of bank groups that are different from each other among a plurality of bank groups whose number depends on the access burst length.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to memory systems. [Background technology]

[0002] For example, in SoCs (System on Chip) that perform image processing, technologies are being developed to reduce the amount of data required for calculations. Meanwhile, dynamic random access memories (DRAMs) used as semiconductor memory devices have a minimum access unit, the size of which significantly exceeds the amount of data requested by the SoC. Generally, data is read and written to semiconductor memory devices in units of minimum access units. Therefore, access to data that does not need to be accessed occurs in addition to requested data, potentially reducing the memory access performance of the memory system. The memory system described in Patent Document 1 prevents degradation of memory access performance by alternately accessing two bank groups in the semiconductor memory device for data lengths half the burst length of the minimum access unit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2009 / 130888 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in recent years, semiconductor memory devices have emerged that have a larger minimum access unit of 64 bytes. For such semiconductor memory devices, even if access is made in burst lengths that are half the minimum access unit, the amount of data requested by the SoC is still significantly greater than the amount of data that needs to be accessed, resulting in access to unnecessary data and a decrease in memory access performance, which cannot be fully resolved. [Means for solving the problem]

[0005] The present disclosure can be realized in the following forms.

[0006] According to one embodiment of the present disclosure, there is provided a memory system (100) comprising: a semiconductor memory device (120) having a plurality of bank groups (BG0 to BG15); and a memory controller (110) that issues a command in response to an access request to the semiconductor memory device from an arithmetic unit (200) that accesses the semiconductor memory device, wherein the memory controller sets an access burst length (BLa) that is a burst length when accessing data in accordance with the data length of the access request data, and accesses in parallel a plurality of access destination bank groups that are different from one another among the plurality of bank groups, the number of which corresponds to the access burst length.

[0007] According to this type of memory system, the access burst length is set according to the data length of the data requested for access, and parallel access is performed to a number of different bank groups according to the access burst length. This allows parallel access to an appropriate number of bank groups with an appropriate burst length for each data, thereby suppressing access to unnecessary data and preventing a decrease in memory access performance of the memory system. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an explanatory diagram showing a schematic configuration of a memory system according to an embodiment of the present invention; [Figure 2] 10 is a flowchart illustrating a procedure for memory access processing according to the present embodiment. [Figure 3] 10 is a flowchart showing the procedure of an access burst length determination process according to the present embodiment. [Figure 4] 10 is a timing chart showing the first half of an example of the operation of the memory system of the present embodiment. [Figure 5] 10 is a timing chart showing the second half of an example of the operation of the memory system of the present embodiment. [Figure 6] 10 is a timing chart illustrating an example of an operation of a memory system of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0009] A. Implementation: A-1. System Configuration: As shown in FIG. 1, the memory system 100 of this embodiment includes a memory controller 110 and a semiconductor memory device 120. The memory system 100 reads and writes data in response to an access request issued by a computing device 200. The computing device 200 corresponds to, for example, a CPU or a GPU (Graphics Processing Unit). In this embodiment, the computing device 200 and the memory controller 110 are implemented on the same chip as part of an SoC. Furthermore, the semiconductor memory device 120 is implemented on a chip different from the chip on which the computing device 200 and the memory controller 110 are implemented. Note that the memory system 100 may receive access requests not only from the computing device 200 but also from multiple computing devices 200.

[0010] The memory controller 110 is connected to the arithmetic device 200 via a bus 10, and receives an access request to the semiconductor memory device 120 issued by the arithmetic device 200. The memory controller 110 is also connected to the semiconductor memory device 120 via a bus 20, and issues a command to the semiconductor memory device 120 in response to the access request. The memory controller 110 issues the above-mentioned commands in accordance with a clock cycle that is the basis for the operation of the memory system 100.

[0011] The memory controller 110 sets the access burst length BLa according to the data length of the data to be accessed included in the access request. The access burst length BLa means the burst length when accessing the data to be accessed. A method for setting the access burst length BLa will be explained in the access burst length determination process described later. In this embodiment, whether the access burst length BLa is set according to the data length of the data to be accessed or a fixed burst length is set in advance can be set when the memory system 100 is started up.

[0012] The memory controller 110 converts the logical address of the data to be accessed into a physical address that indicates the storage area in which the data is stored on the semiconductor memory device 120. The method of converting from a logical address to a physical address will be explained in the memory access process described later.

[0013] If the access request is a write access request requesting writing of data to the semiconductor memory device 120, the memory controller 110 issues a write command to the semiconductor memory device 120 to instruct it to write data to an address specified in the access request (hereinafter also referred to as the "access target address"). If the access request is a read access request requesting reading of data from the semiconductor memory device 120, the memory controller 110 issues a read command to the semiconductor memory device 120 to instruct it to read data from the access target address. Hereinafter, write commands and read commands are collectively referred to as "access commands." The memory controller 110 issues multiple access commands sequentially, with at least a clock interval of tCCD_S between them. The interval tCCD_S is defined by the standard of the semiconductor memory device 120 and refers to the shortest clock interval at which two read commands or two write commands can be issued consecutively to two banks belonging to different bank groups.

[0014] The semiconductor memory device 120 receives a write command and stores and holds data at the access target address. Furthermore, the semiconductor memory device 120 receives a read command and reads out the data held at the access target address. Furthermore, when a burst length is specified along with an address by an access command, the semiconductor memory device 120 can continuously input and output data within the range of the specified burst length, starting from the specified address. The semiconductor memory device 120 includes a data storage unit 121, data buses DB0 to DB15, and a parallel-serial conversion unit 122 (hereinafter also referred to as the "PS conversion unit 122"). The semiconductor memory device 120 of this embodiment is an LPDDR5 memory, and the minimum access unit of the semiconductor memory device 120 is 64 bytes.

[0015] The data storage unit 121 includes bank groups BG0 to BG15. The number of bank groups included in the data storage unit 121 is preferably a power of 2. Each of the bank groups BG0 to BG15 is made up of a plurality of banks, and each bank is formed by arranging memory cells, which are storage elements, in a matrix. Each memory cell is configured to be able to write and read data in response to an access command issued by the memory controller 110.

[0016] When writing data from the memory controller 110 to the semiconductor memory device 120, the PS conversion unit 122 receives serially data included in multiple write commands issued by the memory controller 110 via the bus 20. The PS conversion unit 122 can output the received data in parallel to multiple different bank groups via multiple different data buses.

[0017] On the other hand, when reading data from the semiconductor memory device 120 to the memory controller 110, the PS conversion unit 122 can receive data in parallel, via a plurality of different data buses, read from a plurality of bank groups instructed by a read command to read data. The PS conversion unit 122 serially outputs the received data to the memory controller 110 via the bus 20. In this way, in this embodiment, accesses to a plurality of different bank groups can be performed in parallel using a plurality of different data buses, with multiple accesses of the same type, either data writing or data reading.

[0018] A-2.Memory access processing: The memory system 100 receives an access request from the arithmetic device 200 and executes memory access processing to either read or write data. As shown in step S5 of Fig. 2, if the access request received from the arithmetic device 200 is a write access request, the memory system 100 executes data write processing shown in steps S10, S20, S30, S40, and S50. On the other hand, if the access request received from the arithmetic device 200 is a read access request, the memory system 100 executes data read processing shown in steps S12, S22, S32, S42, and S52.

[0019] In the data write process, the memory controller 110 acquires the requested data length RL of the data to be accessed in response to the write access request, and a logical address indicating the write destination of the data to be accessed (step S10).

[0020] In step S20, the memory controller 110 executes the access burst length determination process shown in Fig. 3. In this process, the memory controller 110 sets the access burst length BLa to 1 / m (m is an integer that is a power of 2 and satisfies m≦n) of the burst length of the minimum access unit of the semiconductor memory device 120 (hereinafter also referred to as "basic burst length BL"). n means the number of bank groups included in the data storage unit 121. The access burst length BLa set in this process is stored in the memory controller 110 in association with the logical address of the data to be accessed, and the access burst length BLa set when the data to be accessed was written is also used in the data read process described later.

[0021] If the requested data length RL is equal to or greater than half the basic burst length BL (step S210: Yes), the memory controller 110 sets the access burst length BLa to the length of the basic burst length BL (step S212).

[0022] If the requested data length RL is less than half the basic burst length BL (step S210: No) and if the requested data length RL is equal to or greater than 1 / 4 of the basic burst length BL (step S220: Yes), the memory controller 110 sets the access burst length BLa to half the basic burst length BL (step S222).

[0023] If the requested data length RL is less than 1 / 4 of the basic burst length BL (step S220: No) and if the requested data length RL is 1 / 8 or more of the basic burst length BL (step S230: Yes), the memory controller 110 sets the access burst length BLa to 1 / 4 of the basic burst length BL (step S232).

[0024] If the requested data length RL is less than 1 / 8 of the basic burst length BL (step S230: No) and the requested data length RL is 1 / 16 or more of the basic burst length BL (step S240: Yes), the memory controller 110 sets the access burst length BLa to 1 / 8 of the basic burst length BL (step S242).

[0025] If the requested data length RL is less than 1 / 16 of the basic burst length BL (step S240: No), the memory controller 110 sets the access burst length BLa to 1 / 16 of the basic burst length BL (step S250). After setting the access burst length BLa, the memory controller 110 ends the access burst length determination process.

[0026] In step S30 of FIG. 2, the memory controller 110 converts the acquired logical address into a physical address according to the set access burst length BLa. The physical address obtained after conversion corresponds to the above-mentioned access target address. In this embodiment, the memory controller 110 converts the logical address into a physical address according to a preset conversion rule. The conversion rule differs depending on the access burst length BLa. For example, the access burst length BLa of each data is half the basic burst length BL, and physical addresses are determined so that multiple data items with consecutive logical addresses assigned to each data item are stored alternately in bank group BG0 and bank group BG1. Furthermore, the access burst length BLa of each data item is 1 / 16 of the basic burst length BL, and physical addresses are determined so that multiple data items with consecutive logical addresses assigned to each data item are stored sequentially in bank groups BG0 to BG15. Thus, in this embodiment, when the access burst length BLa is 1 / p (p is an integer that is a power of 2) of the basic burst length BL, the memory controller 110 converts the logical address to a physical address so that data is stored in order in p different bank groups (hereinafter also referred to as "access destination bank groups").

[0027] In step S40, the memory controller 110 generates a write command and issues the write command to the semiconductor memory device 120. The write command includes at least the data to be accessed, the address to be accessed, and the access burst length BLa.

[0028] In step S50, the semiconductor memory device 120 receives the write command and writes the data to be accessed into the memory cell corresponding to the address to be accessed. With this, the memory system 100 ends the data write process and ends the memory access process.

[0029] In the data read process, the memory controller 110 acquires a logical address indicating the read source of the data to be accessed in response to the read access request (step S12). As described above, the access burst length BLa of the data to be accessed is stored in association with the logical address of the data to be accessed, and in the following process, the access burst length BLa set when the data to be accessed was written is used.

[0030] In step S32, the memory controller 110 converts the acquired logical address into a physical address according to the access burst length BLa. Similar to the process in step S30 described above, the memory controller 110 converts the logical address into a physical address according to a preset conversion rule.

[0031] In step S42, the memory controller 110 generates a read command and issues the read command to the semiconductor memory device 120. The read command includes at least an access target address and an access burst length BLa.

[0032] In step S52, the semiconductor memory device 120 receives the read command and reads the data to be accessed from the memory cell corresponding to the address to be accessed. With this, the memory system 100 ends the data read process and ends the memory access process.

[0033] Generally, when the arithmetic device 200 accesses the memory system 100, the same type of access, either data write or data read, is performed consecutively to consecutive logical addresses. In this embodiment, as described above, physical addresses are determined so that data corresponding to consecutive logical addresses are stored in different bank groups. Also, as described above, the semiconductor memory device 120 is configured to be able to access each bank group in parallel using multiple different data buses when accessing multiple different bank groups. Therefore, the memory system 100 can execute memory access processes in parallel corresponding to multiple access requests issued consecutively from the arithmetic device 200, thereby efficiently executing memory accesses.

[0034] The parallel processing of multiple accesses will be described in more detail with reference to FIGS. 4 and 5. FIGS. 4 and 5 show an example of the operation when the semiconductor memory device 120 configured as LPDDR5 as described above executes data read with a basic burst length BL of 32. In the example shown in FIGS. 4 and 5, read commands R0 to R3 are commands instructing the reading of data D0 to D3, respectively. The access burst length BLa of the data D0 to D3 is ¼ the basic burst length BL. The data D0 to D3 are stored in bank groups BG0 to BG3, respectively. The semiconductor memory device 120 receives the read commands R0 to R3 and prepares data output in parallel in each of the bank groups BG0 to BG3. After the data output preparation is completed in each of the bank groups BG0 to BG3, the data D0 to D3 are output to the arithmetic unit 200 continuously without a clock interval.

[0035] On the other hand, when multiple data belonging to different pages of the same bank or the same bank group are read consecutively, preparations for data output for each page must be completed before preparations for data output for other pages can begin. Therefore, as shown in Figure 6, when consecutively accessing data D4 and data D5, both of which belong to bank group BG0, these accesses cannot be executed in parallel, and a clock interval occurs between the two data outputs.

[0036] As described above, the memory system 100 can access the bank groups BG0 to BG3 in parallel, thereby reading out the data D0 to D3 continuously without clock intervals, thereby preventing a decrease in memory access performance.

[0037] According to the memory system 100 of the embodiment described above, the access burst length BLa is set according to the data length of the data to be accessed, and parallel access is performed to the number of access destination bank groups corresponding to the access burst length BLa. Therefore, parallel access can be performed with an appropriate burst length for each data to be accessed, and access to unnecessary data can be suppressed, thereby suppressing a decrease in the memory access performance of the memory system 100.

[0038] In addition, the memory controller 110 converts logical addresses to physical addresses so that data corresponding to consecutive logical addresses are stored in different bank groups among the accessed bank groups, thereby increasing the probability that access requests to data corresponding to consecutive logical addresses can be processed in parallel, and further suppressing deterioration in the memory access performance of the memory system 100.

[0039] B. Other Embodiments: (B1) In the above embodiment, the semiconductor memory device 120 is implemented on a chip different from the chip on which the arithmetic device 200 and the memory controller 110 are implemented, but the present disclosure is not limited to this. The memory controller 110 and the semiconductor memory device 120 may be implemented on the same chip, and the arithmetic device 200 may be implemented on a chip different from the chip on which the memory controller 110 and the semiconductor memory device 120 are implemented. Furthermore, the memory controller 110, the semiconductor memory device 120, and the arithmetic device 200 may be implemented on the same chip.

[0040] (B2) In the above embodiment, the semiconductor memory device 120 has the same number of data buses as the number of bank groups, but the present disclosure is not limited to this. Depending on the data processing speed of the semiconductor memory device 120, it may not be possible to access all of the bank groups included in the semiconductor memory device 120 in parallel. In such a case, the number of data buses may be two or more and may be less than the number of bank groups, depending on the data processing speed of the semiconductor memory device 120. Even in this configuration, the memory system 100 achieves the same effects as the above embodiment.

[0041] (B3) In the above embodiment, the memory controller 110 determines the physical addresses so that, for example, consecutive logical addresses are assigned and a plurality of data items, each of which has an access burst length BLa that is 1 / 16 of the basic burst length BL, are stored in the bank groups BG0 to BG15 in order, but the present disclosure is not limited to this. The memory controller 110 may also determine the physical addresses so that consecutive logical addresses are assigned and a plurality of data items, each of which has an access burst length BLa that is 1 / 16 of the basic burst length BL, are stored in the bank groups BG0 to BG7 in order. Even when the physical addresses are determined in this manner, the memory system 100 achieves the same effects as the above embodiment.

[0042] The present disclosure is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit thereof. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention section can be appropriately replaced or combined to solve some or all of the above-described problems or achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be appropriately deleted. [Explanation of symbols]

[0043] 100... memory system, 110... memory controller, 120... semiconductor memory device, 200... arithmetic unit, BG0 to BG15... bank group, BLa... access burst length, DB0~DB15...Data bus

Claims

1. A memory system (100), comprising: A semiconductor memory device (120) having a plurality of bank groups (BG0 to BG15); a memory controller (110) that issues a command in response to a request to access the semiconductor memory device from an arithmetic unit (200) that accesses the semiconductor memory device; Equipped with The memory controller setting an access burst length (BLa) which is a burst length when accessing the data in accordance with the data length of the access request; accessing in parallel a plurality of access destination bank groups, the plurality of bank groups being different from one another and the number of which corresponds to the access burst length; Memory system.

2. 2. The memory system of claim 1, The semiconductor memory device includes n bank groups (n is an integer that is a power of 2) and n data buses (DB0 to DB15), the memory controller sets the access burst length to 1 / m (m is an integer that is a power of 2 and satisfies m≦n) of the burst length of the minimum access unit of the semiconductor memory device; Memory system.

3. 3. The memory system according to claim 1, the memory controller converts logical addresses into physical addresses so that data corresponding to consecutive logical addresses are stored in mutually different bank groups among the access destination bank groups; Memory system.

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