Power amplification system with an internal optical communication link

Abstract

To provide a system, an amplifier, and a method for implementing an internal optical communication link in a power amplifier system.SOLUTION: A power amplifier system includes a front panel 202, a rear panel 204, optical links 222 and 224, and a controller 206. The front panel 202 includes a plurality of signal endpoints 211, 213a, and 214a, and a first optical interface 232, the first optical interface being coupled to each of the plurality of signal endpoints. The optical link 222 is coupled to the first optical interface. The controller is configured to manage operation of the power amplifier system and is coupled to the optical link 222 via a second optical interface 236. The controller communicates with each of the plurality of signal endpoints over the optical link.SELECTED DRAWING: Figure 2A

Description

Related Applications

[0001] This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 62 / 847,751, entitled "Power Amplifier System With An Optical Communication Link," filed May 14, 2019, and U.S. Provisional Patent Application No. 62 / 856,532, entitled "Power Amplifier System With An Internal Optical Communication Link," filed June 3, 2019, each of which is incorporated herein by reference in its entirety. [Technical Field]

[0002] The present disclosure relates generally to power amplifiers, and more particularly to techniques for implementing an internal optical communication link in a power amplifier system. [Background technology]

[0003] Power amplifiers may be used in a wide range of applications, from communications to electronic warfare systems. The suitability of a given power amplifier for a particular application may be affected by various physical and performance characteristics of the power amplifier, such as reliability, performance, availability, size, weight, etc. For example, these characteristics may dictate whether a given power amplifier system can be deployed in the field.

[0004] It can therefore be seen that there may be a need for a power amplification system with improved physical and performance characteristics. [Brief explanation of the drawings]

[0005] In order to facilitate a more complete understanding of this disclosure, reference is now made to the accompanying drawings, in which like elements are designated with like numerals, and in which the drawings should not be construed as limiting the disclosure, but are intended to be illustrative only.

[0006] [Figure 1A]1 is a simplified diagram of a power amplification system according to some embodiments. [Figure 1B] 1 is a simplified diagram of a power amplification system according to some embodiments. [Figure 1C] 1 is a simplified diagram of a power amplification system according to some embodiments. [Figure 2A] 1 is a simplified diagram of a power amplification system with an internal optical communication link according to some embodiments. [Figure 2B-1] 1 is a simplified diagram of a power amplification system with an internal optical communication link according to some embodiments. [Figure 2B-2] 1 is a simplified diagram of a power amplification system with an internal optical communication link according to some embodiments. [Figure 2B-3] 1 is a simplified diagram of a power amplification system with an internal optical communication link according to some embodiments. [Figure 3A-1] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3A-2] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3A-3] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3A-4] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3A-5] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3A-6] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3B-1] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3B-2] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3B-3] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3B-4] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3B-5] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3B-6] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 3C] 1 is a simplified diagram of an optical communication system according to some embodiments. [Figure 4] 1 is a simplified diagram of a method for communicating over an optical link in a power amplification system. DETAILED DESCRIPTION OF THE INVENTION

[0007] 1A-1C are simplified diagrams of a power amplifier system 100 according to some embodiments. Fig. 1A is a perspective view of the power amplifier system 100, Fig. 1B is a front plan view of the power amplifier system 100, and Fig. 1C is a rear plan view of the power amplifier system 100.

[0008] 1A, the power amplifier system 100 includes a housing 110 that houses various components of the power amplifier system 100. The housing 110 may be of various form factors. For example, the housing 110 may be sized to allow the power amplifier system 100 to be mounted in a standard rack.

[0009] A front panel 112 of the housing 110 may include various interfaces, indicators, connectors, electronic modules, etc. As shown in FIG. 1B , the front panel 112 includes a display panel 120 and various indicators (e.g., LED indicators) 122. Other electronic components 124 are mounted on the front panel 112. In some embodiments, one or more cooling fans 130 may be mounted on the front panel 112.

[0010] 1C , the rear panel 114 of the housing 110 may include a power connector 140 and a circuit breaker 142, as well as various indicators (e.g., LED indicators) 144. The rear panel 114 may further include an input connector 150, an output connector 152, and a blanking signal connector 154. The input connector 150 may be used to receive an input signal or a stimulus signal, the output connector 152 may be used to output an amplified signal, and the blanking signal connector 154 may be used to receive a signal used to disable or mute the power amplifier system 100. The rear panel 114 may further include one or more input / output (I / O) interfaces 160. Examples of the I / O interface 160 may include, but are not limited to, an Ethernet connection, a USB connection, a serial interface, a parallel interface, etc. In some embodiments, one or more fans 130 may be mounted on the rear panel 114.

[0011] Other panels of the housing 110 (for example, side panels, top panel, and bottom panel, not shown) may include additional interfaces, indicators, connectors, fans, switches, buttons, electronic components, and the like.

[0012] As these features suggest, during operation, various information is physically transmitted throughout the power amplifier system 100. For example, control signals may be received from and / or transmitted to the power amplifier system 100 via the I / O interface 160. Information is displayed via the display panel 120. There are also data signals associated with the indicators 122 and 144, the electronic component 124, and the fan 130. Additional information may circulate within the housing 110.

[0013] Given the wide range of information that is transmitted and processed throughout power amplifier system 100 during operation, it is desirable that the information be transmitted reliably. For example, it is desirable to transmit the information in a manner that is robust against electromagnetic interference (EMI) and other noise sources that can adversely affect the reliability of electronic signal communications. Furthermore, it is desirable to transmit the information with low latency.

[0014] One approach to carrying information throughout the power amplifier system 100 is to use electrical cabling. However, using electrical cabling can present several challenges. For example, electrical cabling is generally susceptible to EMI. Therefore, implementing electrical cabling in an EMI-robust manner can add additional complexity to the design of the power amplifier system 100. This additional complexity can increase the likelihood of problems due to human error (e.g., lack of skill) and make the operation, maintenance, and repair of the power amplifier system 100 more difficult. Furthermore, electrical cables can introduce undesirable delays and limit the performance of the power amplifier 100. Furthermore, electrical cables can be heavy overall, especially when each cable carries a different signal (as opposed to multiple signals transmitted over a shared link).

[0015] It is therefore desirable to provide an improved mechanism for communicating information within the power amplifier system 100.

[0016] 2A and 2B are simplified diagrams of a power amplifier system 200 having an internal optical communication link according to some embodiments. FIG. 2A shows a block diagram of the power amplifier system 200, and FIG. 2B shows a schematic diagram of the power amplifier system 200. In some embodiments, components of the power amplifier system 200 may generally correspond to components of the power amplifier system 100. For example, the power amplifier system 200 includes a front panel 202 that generally corresponds to the front panel 112 and a rear panel 204 that generally corresponds to the rear panel 114. The power amplifier system 200 further includes a controller (e.g., a motherboard) 206. In some embodiments, the controller 206 may be configured to manage the operation of the power amplifier system 200 and its various subcomponents. For example, the controller 206 may include an amplifier circuit (e.g., an RF section) 208a and one or more processors (e.g., a system-on-module (SOM)) 208b. The controller 206 may perform various management tasks related to managing the operation of the power amplifier system 200. These management tasks include, but are not limited to, receiving and storing user parameters, selecting an operating mode for the power amplifier system 200, implementing a feedback loop to control the output level of the amplifier circuit (e.g., automatic gain control or automatic power control), blanking or muting the output of the amplifier circuit, collecting data related to the power amplifier system 200, providing instructions to components of the power amplifier system 200, etc.

[0017] In some embodiments, the front panel 202 and the rear panel 204 may each include multiple signal endpoints 211-219. The signal endpoints 211-219 generally correspond to devices, modules, or other components of the power amplifier system 200 that transmit and / or receive information. Examples of the signal endpoints 211-219 include, but are not limited to, input / output (I / O) interfaces, Ethernet interfaces, serial interfaces, devices that receive command and / or control signals, devices that generate status information, display ports, status indicators (e.g., LED indicators), etc. As shown in FIGS. 2A and 2B , the signal endpoints 211-219 may include a touchscreen display (signal endpoint 211), audio and / or visual indicators (signal endpoint 212), peripheral interface controllers (PICs) (signal endpoints 213a and 213b), fans (signal endpoints 214a and 214b), and a communication interface (signal endpoint 219). More generally, the signal endpoints 211-219 can include virtually any component that communicates with other components of the power amplifier system 200 during operation.

[0018] Power amplifier system 200 further includes optical link 222 and optical link 224. As shown in Figures 2A and 2B, optical link 222 connects front panel 202 to controller 206, and optical link 224 connects rear panel 204 to controller 206. In this manner, optical links 222 and 224 enable controller 206 to communicate with signal endpoints 211-219.

[0019] In some embodiments, optical links 222 and 224 may connect to front panel 202, rear panel 204, and controller 206 via optical interfaces 232-238. For example, as shown in FIGS. 2A and 2B , front panel 202 includes optical interface 232, rear panel 204 includes optical interface 234, and controller 206 includes optical interfaces 236 and 238. Optical link 222 is coupled between optical interfaces 232 and 236, and optical link 224 is coupled between optical interfaces 234 and 238. In some embodiments, one or more of optical interfaces 232-238 may be a serializer / deserializer (SerDes) interface. A SerDes interface converts parallel data to serial data for transmission over an optical link (e.g., optical link 222 or 224) and converts serial data received over an optical link to parallel data. In some embodiments, the SerDes interface may be configured to synchronize transmitted and received data, for example, by extracting an embedded clock signal from the transmitted data. In this manner, controller 206 may communicate with multiple endpoints on front panel 202 via a single optical link 222, and similarly, controller 206 may communicate with multiple endpoints on rear panel 204 via a single optical link 224.

[0020] Various communication protocols, standards, and interfaces may be used for communication over optical links 222 and 224. Examples of such protocols include, but are not limited to, Ethernet (e.g., Gigabit Ethernet (GbE) and interfaces used to connect to Ethernet, such as Serial Gigabit Media Independent Interface (SGMII), Management Data Input / Output (MDIO), etc.), DisplayPort (e.g., DP 1.2 interface, auxiliary transmission line, etc.), and general communication buses (e.g., UART, SPI, etc.). Control signals (e.g., pulse width modulation (PWM) control signals, general I / O, etc.) may also be sent and received over optical links 222 and 224. In some embodiments, signals may be encoded for transmission over optical links 222 and 224 using various encoding techniques (e.g., 8b / 10b encoding).

[0021] Generally, the optical links 222 and 224 have limited susceptibility to EMI, improving the robustness of communications between the controller 206 and the signal endpoints 211-219 compared to electrical cabling. Furthermore, because optical signals generally have lower latency than electrical signals, the optical links 222 and 224 can improve the performance of communications between the controller 206 and the signal endpoints 211-219 compared to electrical cabling. Furthermore, the ability to communicate with multiple endpoints over each of the optical links 222 and 224 reduces the amount of wiring in the power amplifier system 200, thereby simplifying assembly and maintenance and reducing the likelihood of workmanship errors.

[0022] In some embodiments, the power amplifier system 200 may include electrical wiring in addition to the optical links 222 and 224. To facilitate the distribution of electrical wiring, the power amplifier system 200 may include an interconnect board (e.g., a side interconnect PCB) 240 connected between the front panel 202, the rear panel 204, and the controller 206. For example, the interconnect board 240 may provide wired connections between the power supply 250, the front panel 202, the rear panel 204, and / or the controller 206. The interconnect board 240 may also provide a backup or contingency route for the controller 206 to communicate with the signal endpoints 211-219. The backup or contingency route may be used, for example, if the optical links 222 and / or 224 are unavailable.

[0023] 3A-3C are simplified diagrams of optical communication systems 300a and 300b according to some embodiments: Figure 3A shows a schematic diagram of optical communication system 300a, Figure 3B shows a schematic diagram of optical communication system 300b, and Figure 3C shows a corresponding block diagram of optical communication system 300b.

[0024] In some embodiments, optical communication systems 300a and 300b may be used to implement optical links 222 and 224 and their corresponding optical interfaces 232-238. With reference to FIG. 3A, optical communication system 300a connects controller 306 (e.g., controller 206) to front panel 302 (e.g., front panel 202) via optical link 322 (e.g., optical link 222). With reference to FIGS. 3B and 3C, optical communication system 300b connects controller 306 to rear panel 304 (e.g., rear panel 204) via optical link 324 (e.g., optical link 224). In some embodiments, optical links 322 and 324 can communicate with components of front panel 302, rear panel 304, and controller 306 via optical interfaces 332-338 (e.g., optical interfaces 232-238).

[0025] 3A, optical link 322 includes optical fiber 342 extending between controller 306 and front panel 302. Similarly, with reference to Figures 3B and 3C, optical link 324 includes optical fiber 344 extending between controller 306 and rear panel 304. In some embodiments, optical fiber 342 and 344 may be multimode fiber (e.g., 850 nm multimode fiber).

[0026] Referring to FIG. 3A , optical link 322 further includes a pair of optical engines 352 and 354 disposed at each end of optical fiber 342. Similarly, referring to FIGS. 3B and 3C , optical link 324 includes a pair of optical engines 356 and 358 disposed at each end of optical fiber 344. In some embodiments, optical engines 352-358 may perform electrical-to-optical and optical-to-electrical conversions during transmission of signals over optical fibers 342 and 344. Optical engines 352-358 may also perform multiplexing techniques (e.g., time division multiplexing (TDM), wavelength division multiplexing (WDM), etc.) to provide one or more communication lanes 360. For example, communication lanes 360 may include a transmit (TX) lane, a receive (RX) lane, a bidirectional lane, etc. In some embodiments, each of communication lanes 360 may include a positive (P) and a negative (N) signal. As shown in Figures 3A and 3B, each of the optical engines 352-358 provides four RX communication lanes and four TX communication lanes.

[0027] In some embodiments, optical interfaces 332-368 may include a pair of serializers 362a-362d and deserializers 364a-364d to enable communication from multiple components over a single optical fiber. For example, referring to FIG. 3A, serializer 362a and deserializer 364a may enable multiple signals 366a to be transmitted from controller 306 over optical link 322 to front panel 302. As shown in FIG. 3A , the plurality of signals 366a include a fan control signal (FAN_CNTRL), a fan on / off signal (FAN_ON_OFF), a transmit LED signal (TX_LED), an alert LED signal (ALERT_LED), a logo LED signal (LOGO_LED), a power LED signal (POWER_LED), and an audio alert signal (AUDIO_ALERT), display port auxiliary transmission line signals (DP_AUX_OE and DP_AUX_OUT), a UART transmit signal (UARTS_TX), and touch display interface signals (TOUCH_SPI_CLK, TOUCH_SPI_MOSI_CLK, and TOUCH_CS).

[0028] 3A, serializer 362b and deserializer 364b may enable a plurality of signals 366b to be transmitted from front panel 302 to controller 306 over optical link 322. As shown in FIG. 3A, signals 366b include a set of fan sense signals (FAN_SENSE1, FAN_SENSE2, FAN_SENSE3, and FAN_SENSE4), display port auxiliary channel signals (DP_AUX_IN and DP_AUX_HPD), UART receive signals (UARTS_RX), and touch display interface signals (TOUCH_PIRQ and TOUCH_SPI_MISQ_DOUT).

[0029] 3B, serializer 362c and deserializer 364c may enable multiple signals 366c to be transmitted from controller 306 to rear panel 304 over optical link 324. Similarly, serializer 362d and deserializer 364d may enable multiple signals 366d to be transmitted from rear panel 304 to controller 306 over optical link 324.

[0030] In some embodiments, one or more signals may be transmitted directly over optical links 322 and 324, bypassing optical interfaces 332-338. Such signals may be transmitted over dedicated communication lanes on optical links 322 and 324. For example, as shown in FIG. 3A , one or more signals 372 (e.g., DisplayPort signals) are transmitted directly over optical link 322 over a dedicated lane of communication lanes 360. Similarly, in FIGS. 3B and 3C , one or more signals 374 (e.g., SGMII signals) are transmitted directly over optical link 324 over a dedicated lane of communication lanes 360.

[0031] 3C, the SGMII signal 374 bypasses the optical interface 338 and connects directly between the optical engine 352 and the processor 382 (e.g., processor 208b). Similarly, the SGMII signal 374 bypasses the optical interface 334 and connects directly between the optical engine 356 and the Ethernet transceiver 384. FIG. 4 is a simplified diagram of a method 400 for communicating over an optical link in a power amplification system. In some embodiments, the method 400 may be performed by the controller 206.

[0032] In step 410, first information is communicated via an optical interface (e.g., optical interface 236) over an optical link (e.g., optical link 222) to a first signal endpoint (e.g., signal endpoint 211) of the power amplification system. The first information may be transmitted by the controller and received by the first signal endpoint, or transmitted by the first signal endpoint and received by the controller, or both (e.g., bidirectional communication). In some embodiments, the optical interface may be a SerDes interface. The SerDes interface may enable the first information to be communicated over a single fiber optic line, even though analog transmission over an electrical cable would use multiple parallel interconnects to communicate the first information. For example, for the embodiment of FIGS. 2A and 2B, step 410 may be performed by controller 206. Similarly, for the embodiment of FIGS. 3A-3C, step 410 may be performed by controller 306.

[0033] At step 420, second information is communicated between the controller and a second signal endpoint (e.g., signal endpoint 212) of the power amplification system over an optical link via an optical interface. Here, the use of an optical interface (e.g., a SerDes interface) may allow the second information to be communicated over the same fiber optic line used to transmit the first information, even though analog transmission over electrical cables would use different cables to communicate the first and second information. For example, for the embodiment of FIG. 2, step 420 may be performed by controller 206. Similarly, for the embodiment of FIGS. 3A-3C, step 420 may be performed by controller 306.

[0034] The present disclosure is not limited in scope by the specific embodiments described herein. Indeed, various other embodiments and modifications of the present disclosure, in addition to the embodiments described herein, will be apparent to those skilled in the art from the foregoing description and the accompanying drawings. Accordingly, such other embodiments and modifications are intended to be within the scope of the present disclosure. Moreover, while the present disclosure has been described herein in the context of at least one particular implementation in at least one particular environment for at least one particular purpose, those skilled in the art will recognize that its utility is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in light of the full breadth and spirit of the present disclosure as set forth herein.

Claims

1. a plurality of electronic components each coupled to the first optical interface; an optical link coupled to the first optical interface; a controller coupled to the optical link via a second optical interface; the controller communicates with each of the plurality of electronic components over the optical link; Power amplification system.

2. 2. The power amplifier system of claim 1, wherein the first optical interface and the second optical interface are serializer / deserializer (SerDes) interfaces.

3. The power amplifier system of claim 1 , further comprising a radio frequency (RF) circuit that generates electromagnetic interference (EMI) within the power amplifier system.

4. 2. The power amplifier system of claim 1, wherein the plurality of electronic components include at least one of an input / output interface, an Ethernet interface, a device configured to receive commands, a device configured to receive control signals, a device that generates status information, a display port, a status indicator, a touchscreen display, a peripheral interface controller, or a fan.

5. The power amplifier system of claim 1 , wherein the plurality of electronic components are mounted on a housing of the power amplifier system.

6. 10. The power amplifier system of claim 1, wherein the controller communicates over the optical link using pulse width modulated (PWM) control signals.

7. The power amplifier system of claim 1 , further comprising an electrical interconnect providing a communication link between each of the plurality of electronic components and the controller.

8. 8. The power amplifier system of claim 7, wherein the electrical interconnect provides a temporary route for the controller to communicate with each of the plurality of electronic components, the temporary route being used when the optical link is determined to be unavailable.

9. The power amplifier system of claim 1 , wherein the controller comprises a motherboard of the power amplifier system.

10. The power amplification system of claim 1 , wherein the optical link comprises a multimode fiber.

11. the controller further includes an electrical-to-optical conversion engine and an optical-to-electrical conversion engine; 10. The power amplification system of claim 1, wherein the electrical-to-optical conversion engine and the optical-to-electrical conversion engine each perform multiplexing to provide one or more communication lanes on the optical link.

12. The power amplifier system of claim 11 , wherein the one or more communication lanes include at least one of a transmit lane, a receive lane, or a bidirectional lane.

13. The power amplifier system of claim 11 , wherein the one or more communication lanes include at least one dedicated communication lane that bypasses the second optical interface.

14. 1. A method of communicating in a power amplification system, comprising: communicating, by a controller of the power amplifier system, via an optical interface over an optical link, first information to and from a first electronic component of the power amplifier system; communicating, by the controller, second information via the optical interface over the optical link to a second electronic component of the power amplifier system; A method comprising:

15. The method of claim 14 , wherein the optical interface is a serializer / deserializer (SerDes) interface.

16. 15. The method of claim 14, further comprising, in response to determining that the optical link is unavailable, communicating, by the controller, third information to at least one of the first electronic component or the second electronic component over a spare electrical interconnect.

17. 15. The method of claim 14, comprising multiplexing the first information and the second information to provide one or more communication lanes over the optical link.

18. the one or more communication lanes include at least one dedicated communication lane that bypasses the second optical interface; at least one of the first information and the second information is communicated over the dedicated communication lane; 18. The method of claim 17.

19. a housing including a plurality of electronic components and a first optical interface coupled to each of the plurality of electronic components; an electromagnetic interference (EMI) source disposed within the enclosure; a motherboard disposed within the housing and including a second optical interface; an optical link coupled between the first optical interface and the second optical interface; the motherboard communicates with each of the plurality of electronic components through the optical link; system.

20. further comprising an interconnection substrate disposed within the housing; the interconnection substrate provides a backup communication path between the motherboard and the plurality of electronic components; 20. The system of claim 19.

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