Liquid dispensing device

Abstract

To provide a liquid ejection device in which heat radiation measures of a driving signal output circuit is improved.SOLUTION: The liquid ejection device comprises: an ejection unit which is supplied with a driving signal to eject liquid; a driving signal output unit which outputs the driving signal; a cooling unit which cools the driving signal output unit; and an electric power supply unit which supplies the cooling unit with electric power, the driving signal output unit has a first mode in which the driving signal output unit outputs, as the driving signal, a first driving signal of a first frequency to the ejection unit and a second mode in which the driving signal output unit outputs, as the driving signal, a second driving signal of a second frequency lower than the first frequency to the ejection unit, wherein electric energy supplied by the electric power supply unit to the cooling unit in the first mode is more than electric energy supplied by the electric power supply unit to the cooling unit in the second mode.SELECTED DRAWING: Figure 22

Description

[Technical Field]

[0001] The present invention relates to a liquid ejection device. [Background technology]

[0002] Liquid ejection devices that form images on a medium by ejecting liquid onto the medium are known to use piezoelectric elements, such as piezo elements, as drive elements, which are driven to eject liquid onto the medium. Electrically, piezoelectric elements serving as drive elements are capacitive loads, similar to capacitors, and a sufficient current must be supplied to operate the piezoelectric elements corresponding to each nozzle. Therefore, liquid ejection devices are equipped with a drive signal output circuit that includes an amplifier circuit and other components that output drive signals to drive the piezoelectric elements. Generally, drive signal output circuits generate heat due to the large currents they output to operate the piezoelectric elements corresponding to the nozzles that eject liquid. Patent Document 1 discloses a liquid ejection device equipped with a drive signal output circuit (drive signal generation circuit) equipped with a heat dissipation mechanism, such as a thermally conductive sheet, as a technology for reducing heat generated by such drive signal output circuits. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-059061 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in recent years, there has been an increasing demand for further improvement in image quality in liquid ejection devices and for faster image formation speeds on media, and the heat dissipation measures for the drive signal output circuit described in Patent Document 1 alone were not sufficient to meet these demands, leaving room for improvement. [Means for solving the problem]

[0005] One aspect of the liquid ejection device according to the present invention is a discharge unit that discharges liquid when a drive signal is supplied; a drive signal output unit that outputs the drive signal; a cooling unit that cools the drive signal output unit; a power supply unit that supplies power to the cooling unit; Equipped with a first mode in which the drive signal output unit outputs a first drive signal of a first frequency to the ejection unit as the drive signal; a second mode in which the drive signal output unit outputs a second drive signal having a second frequency lower than the first frequency to the ejection unit as the drive signal; and The amount of electric power supplied from the power supply unit to the cooling unit in the first mode is greater than the amount of electric power supplied from the power supply unit to the cooling unit in the second mode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating a schematic structure of a liquid ejection device. [Figure 2] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Figure 3] FIG. 2 is a diagram illustrating a schematic configuration of a discharge unit. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of a drive signal selection circuit. [Figure 5] 3A to 3C are diagrams for explaining specific examples of a latch signal, a change signal, a clock signal, and a head control signal. [Figure 6] FIG. 4 is a diagram showing an example of the data configuration of a head control signal. [Figure 7] FIG. 2 is a diagram illustrating an example of a functional configuration of a selection control circuit. [Figure 8] 10 is a diagram showing an example of the decoded content of a decoder included in a selection signal output unit. FIG. [Figure 9] FIG. 4 is a diagram showing an example of the configuration of a selection circuit corresponding to the ejection unit. [Figure 10] 10 is a diagram showing an example of the signal waveform of a drive signal COM output by a drive signal output circuit in the multi-tone mode. FIG. [Figure 11] FIG. 10 is a diagram showing an example of a head control signal in a multi-tone mode. [Figure 12] 12 is a diagram showing the decoded contents of a decoder based on the head control signal shown in FIG. 11. FIG. [Figure 13] 10A and 10B are diagrams for explaining the operation of the drive signal selection circuit in a multi-tone mode. [Figure 14] 10 is a diagram showing an example of the signal waveform of a drive signal COM output by a drive signal output circuit in the binary mode. FIG. [Figure 15] FIG. 10 is a diagram showing an example of a head control signal in a binary mode. [Figure 16] 16 is a diagram showing the decoded contents of a decoder based on the head control signal shown in FIG. 15. FIG. [Figure 17] FIG. 10 is a diagram for explaining the operation of the drive signal selection circuit in a binary mode. [Figure 18] FIG. 10 is a diagram showing an example of the data configuration of a head control signal for realizing even faster image formation on a medium in a binary mode. [Figure 19] 10A and 10B are diagrams for explaining the operation of the liquid ejection device when the temperature of the drive signal output circuit is normal. [Figure 20] 10A and 10B are diagrams for explaining the operation of the liquid ejection device when the temperature of the drive signal output circuit is not normal. [Figure 21] 10 is a diagram schematically illustrating a comparison between the temperature rise value of the drive signal output circuit in the binary mode and the temperature rise value of the drive signal output circuit in the multi-tone mode. FIG. [Figure 22] 10 is a diagram showing a schematic diagram of the relationship between the cooling power supplied to the cooling mechanism by the power supply circuit and the temperature rise value of the drive signal output circuit in the binary mode and the multi-tone mode. FIG. [Figure 23] 10A and 10B are diagrams illustrating an example of threshold temperatures suitable for a binary mode and a multi-tone mode. DETAILED DESCRIPTION OF THE INVENTION

[0007] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for the convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0008] Furthermore, the liquid ejection device according to the present invention is a printing device that ejects ink as a liquid, and will be described using an inkjet printer as an example, but the liquid ejection device is not limited to inkjet printers, and may be, for example, a color material ejection device used in the manufacture of color filters for liquid crystal displays and the like, an electrode material ejection device used in the formation of electrodes for organic electroluminescent displays, surface-emitting displays and the like, a bioorganic material ejection device used in the manufacture of biochips, etc.

[0009] 1. Overview of the liquid ejection device FIG. 1 is a diagram illustrating a schematic structure of a liquid ejection device 1. In this embodiment, the liquid ejection device 1 transports a medium P along a transport direction, and a carriage 20 moves back and forth along a main scanning direction that intersects with the transport direction. In response to the transport of the medium P and the reciprocating movement of the carriage 20, an ejection head 21 mounted on the carriage 20 ejects ink, an example of a liquid. This causes the ink to land at desired positions on the medium P, forming a desired image on the medium P. In other words, the liquid ejection device 1 in this embodiment is a so-called serial printing inkjet printer. This liquid ejection device 1 can use any printing target, such as printing paper, resin film, or fabric, as the medium P. The liquid ejection device 1 may also be a so-called line printing inkjet printer in which one or more ejection heads 21 are arranged side by side to form a nozzle row that is equal to or greater than the width of the medium P along the main scanning direction, and each of the one or more ejection heads 21 ejects ink onto the transported medium P to form a desired image on the medium P.

[0010] As shown in FIG. 1, the liquid ejection device 1 includes an ink container 2, a control mechanism 10, a carriage 20, a moving mechanism 30, and a transport mechanism 40.

[0011] The ink container 2 stores ink of a plurality of colors to be ejected onto the medium P. Examples of colors of ink stored in the ink container 2 include black, cyan, magenta, yellow, red, and gray. The ink container 2 may be an ink cartridge, a bag-shaped ink pack made of flexible film, or an ink tank that can be refilled with ink. Although FIG. 1 illustrates the ink container 2 as being provided at a position different from the carriage 20, the ink container 2 may also be mounted on the carriage 20.

[0012] The control mechanism 10 includes a processing circuit such as a CPU (Central Processing Unit) or FPGA (Field Programmable Gate Array), and a storage circuit such as a semiconductor memory, and controls each element of the liquid ejection device 1 including the ejection head 21.

[0013] The carriage 20 is mounted with a discharge head 21. The carriage 20 is fixed to an endless belt 32 included in the movement mechanism 30.

[0014] The control signal Ctrl-H and the drive signal COM output by the control mechanism 10 are input to the ejection head 21. Ink stored in the ink container 2 is supplied to the ejection head 21 via a tube or the like (not shown). The ejection head 21 then ejects the ink supplied from the ink container 2 based on the input control signal Ctrl-H and drive signal COM.

[0015] The movement mechanism 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 is driven to rotate based on a control signal Ctrl-C input from the control mechanism 10. The endless belt 32 extends along the main scanning direction and rotates in accordance with the rotational drive of the carriage motor 31. As a result, the carriage 20 fixed to the endless belt 32 moves along the main scanning direction. In other words, the control mechanism 10 controls the rotation direction of the carriage motor 31 based on the control signal Ctrl-C, thereby controlling the reciprocating movement of the carriage 20 fixed to the endless belt 32 along the main scanning direction.

[0016] The transport mechanism 40 includes a transport motor 41 and a transport roller 42. The transport motor 41 is driven to rotate based on a control signal Ctrl-T input from the control mechanism 10. The transport roller 42 rotates in accordance with the rotational drive of the transport motor 41. As the transport roller 42 rotates, the medium P is transported along the transport direction. In other words, the control mechanism 10 controls the rotation speed of the transport motor 41 based on the control signal Ctrl-T, thereby controlling the transport of the medium P along the transport direction.

[0017] As described above, in the liquid ejection device 1 of this embodiment, the control mechanism 10 controls the transport of the medium P and the reciprocating movement of the carriage 20. Furthermore, the control mechanism 10 outputs a control signal Ctrl-H and a drive signal COM to the ejection head 21 in conjunction with the transport of the medium P by the transport mechanism 40 and the reciprocating movement of the carriage 20 by the movement mechanism 30. That is, the ejection head 21 ejects ink onto the medium P in conjunction with the transport of the medium P by the transport mechanism 40 and the reciprocating movement of the carriage 20 by the movement mechanism 30. As a result, the ink ejected by the ejection head 21 lands at a desired position on the medium P, forming a desired image on the medium P.

[0018] 2. Functional configuration of the liquid ejection device Next, we will explain the functional configuration of the liquid ejection device 1. Figure 2 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in Figure 2, the liquid ejection device 1 includes a control mechanism 10, an ejection head 21, a carriage motor 31, a transport motor 41, and a linear encoder 90.

[0019] The control mechanism 10 includes a drive circuit 50 , a comparison circuit 70 , a temperature detection circuit 72 , a power supply circuit 80 , a cooling mechanism 82 , and a control circuit 100 .

[0020] The control circuit 100 includes a processor such as a microcontroller, and is communicatively connected to an external device such as a host computer (not shown) that is provided outside the liquid ejection device 1. Various signals such as image data including information about an image to be formed on the medium P are input to the control circuit 100 from the external device. Based on the various signals such as the input image data, the control circuit 100 generates various data for controlling the liquid ejection device 1 and various signals based on the data, and outputs them to corresponding components.

[0021] A specific example of the operation of the control circuit 100 will now be described.

[0022] The control circuit 100 receives an input position information signal Cp indicating the scanning position of the carriage 20 detected by the linear encoder 90. The control circuit 100 determines the scanning position of the ejection head 21 mounted on the carriage 20 based on the input position information signal Cp. The control circuit 100 then generates various signals including control signals Ctrl-C, Ctrl-T, and Ctrl-H in accordance with the image data input from an external device and the position information signal Cp input from the linear encoder 90, and outputs these signals to the corresponding components.

[0023] In detail, the control circuit 100 generates a control signal Ctrl-C for controlling the reciprocating movement of the ejection head 21 based on the position information signal Cp, and outputs the control signal to the carriage motor 31. This controls the scanning position of the ejection head 21 in the main scanning direction. The control circuit 100 also generates a control signal Ctrl-T for controlling the transport of the medium P, and outputs the control signal Ctrl-T to the transport motor 41. This controls the transport position of the medium P. Here, the control signal Ctrl-C output by the control circuit 100 may be converted into a signal in a driver circuit (not shown) and then input to the carriage motor 31. Similarly, the control signal Ctrl-T output by the control circuit 100 may be converted into a signal in a driver circuit (not shown) and then input to the transport motor 41.

[0024] Furthermore, the control circuit 100 generates a latch signal LAT, a change signal CH, a clock signal SCK, and a head control signal DI as a control signal Ctrl-H for controlling the ejection head 21 based on the input image data and position information signal Cp, and outputs these to the ejection head 21. The latch signal LAT, change signal CH, clock signal SCK, and head control signal DI will be described in detail later.

[0025] The control circuit 100 also outputs a basic drive signal dA, which is a digital signal, to the drive circuit 50. The drive circuit 50 includes a drive signal output circuit 52 and a reference voltage signal output circuit 54. The basic drive signal dA is input to the drive signal output circuit 52. The drive signal output circuit 52 then digital-to-analog converts the input digital signal of the basic drive signal dA, and generates the drive signal COM by performing class D amplification on the converted analog signal. The drive signal output circuit 52 then outputs the generated drive signal COM to the ejection head 21. In other words, the basic drive signal dA is a digital signal that defines the signal waveform of the drive signal COM, and the drive signal output circuit 52 generates the drive signal COM by performing class D amplification on the signal waveform defined by the basic drive signal dA.

[0026] Here, the basic drive signal dA may be an analog signal as long as it can define the signal waveform of the drive signal COM. Furthermore, the drive signal output circuit 52 may amplify the signal waveform defined by the basic drive signal dA and output the drive signal COM. Therefore, the drive signal output circuit 52 may generate the drive signal COM by amplifying the signal waveform defined by the basic drive signal dA using class A amplification, class B amplification, or class AB amplification.

[0027] The reference voltage signal output circuit 54 generates a reference voltage signal VBS that serves as a reference potential for driving a piezoelectric element 60 (described later) that the ejection head 21 has. The reference voltage signal output circuit 54 then outputs the generated reference voltage signal VBS to the ejection head 21. Such a reference voltage signal VBS is a signal of constant potential, and may be, for example, a signal of ground potential with a voltage value of 0 V, or a DC voltage signal with a voltage value of 5.5 V, 6 V, or the like.

[0028] The temperature detection circuit 72 detects the temperatures of various parts of the liquid ejector 1, including the drive circuit 50. The temperature detection circuit 72 outputs a temperature information signal Stmp, including the detected temperature Tmp, to the comparison circuit 70. A thermistor element, whose resistance value changes with temperature, may be used as the temperature detection circuit 72. In the liquid ejector 1 of this embodiment, the temperature detection circuit 72 is described as detecting the temperature of the drive signal output circuit 52 included in the drive circuit 50. However, the temperature detection circuit 72 may also detect the temperatures of various parts of the liquid ejector 1, such as the temperature of the control circuit 100, the temperature of various parts of the movement mechanism 30, and the temperature of various parts of the transport mechanism 40, in addition to the drive signal output circuit 52. In this case, the liquid ejector 1 may have multiple temperature detection circuits 72.

[0029] The comparison circuit 70 receives the temperature information signal Stmp output by the temperature detection circuit 72 and the temperature threshold signal Sth output by the control circuit 100. The comparison circuit 70 compares the threshold temperature Tth included in the temperature threshold signal Sth with the detection temperature Tmp included in the temperature information signal Stmp, and outputs a temperature determination signal Res indicating the comparison result to the control circuit 100. For example, a comparator can be used as this comparison circuit 70. The comparison circuit 70 may be configured to include a processor such as a microcontroller. Alternatively, part or all of the configuration of the comparison circuit 70 may be integrated with the control circuit 100.

[0030] The comparator circuit 70 also receives an enable signal EN output by the control circuit 100. When the input enable signal EN indicates a valid state, the comparator circuit 70 compares the threshold temperature Tth with the detection temperature Tmp. When the input enable signal EN indicates a invalid state, the comparator circuit 70 does not compare the threshold temperature Tth with the detection temperature Tmp. Here, the comparator circuit 70 of this embodiment compares the threshold temperature Tth with the detection temperature Tmp when a high-level enable signal EN is input, and does not compare the threshold temperature Tth with the detection temperature Tmp when a low-level enable signal EN is input. That is, in this embodiment, the high-level enable signal EN is a signal indicating a valid state, and the low-level enable signal EN is a signal indicating an invalid state. Alternatively, the low-level enable signal EN may be a signal indicating a valid state, and the high-level enable signal EN may be a signal indicating an invalid state. In the following description, the logic level of various signals may be referred to as a high level as an H level, and a low level as an L level.

[0031] The power supply circuit 80 receives a power control signal Spsy output by the control circuit 100. The power supply circuit 80 generates cooling power Pcl according to the input power control signal Spsy and supplies it to the cooling mechanism 82. Specifically, the power supply circuit 80 changes at least one of the voltage value and current value of the cooling power Pcl supplied to the cooling mechanism 82 based on the input power control signal Spsy. In this way, the power supply circuit 80 adjusts the amount of power supplied to the cooling mechanism 82. In the following description, the power supply circuit 80 will be described as controlling the amount of cooling power Pcl supplied to the cooling mechanism 82 by controlling the voltage value of the cooling power Pcl.

[0032] The cooling mechanism 82 operates using the supplied cooling power Pcl. As a result, the cooling mechanism 82 cools each part of the liquid ejection device 1, including the drive signal output circuit 52. As such a cooling mechanism 82, a fan or a Peltier element, etc., whose cooling capacity can be controlled according to the amount of cooling power Pcl supplied, can be used. Note that the cooling mechanism 82 may cool the control circuit 100, the temperatures of each part of the movement mechanism 30, and each part of the transport mechanism 40, in addition to the drive signal output circuit 52. In this case, the liquid ejection device 1 may have multiple cooling mechanisms 82.

[0033] The ejection head 21 includes a drive signal selection circuit 200 and ejection sections 600[1] to 600[n].

[0034] The drive signal selection circuit 200 is configured to include one or more integrated circuit devices. The drive signal selection circuit 200 receives as input a latch signal LAT, a change signal CH, a clock signal SCK, a head control signal DI, and a drive signal COM. The drive signal selection circuit 200 selects or deselects the signal waveform of the drive signal COM based on the input latch signal LAT, change signal CH, clock signal SCK, and head control signal DI, thereby generating and outputting drive signals VOUT[1] to VOUT[n] that individually correspond to the ejection sections 600[1] to 600[n]. The configuration and operation of the drive signal selection circuit 200 will be described in detail below.

[0035] Here, the ejection units 600[1] to 600[n] of the ejection head 21 all have the same configuration, and when there is no need to distinguish between them, they may be simply referred to as the ejection unit 600. Furthermore, the following description will be given assuming that the ejection unit 600 is supplied with the drive signal VOUT of the drive signals VOUT[1] to VOUT[n].

[0036] Next, a description will be given of the configuration of the discharge unit 600 to which the drive signal VOUT is supplied. Fig. 3 is a diagram for explaining the schematic configuration of the discharge unit 600. In addition to the discharge unit 600, Fig. 3 also illustrates a nozzle plate 632, a reservoir 641, and a supply port 661.

[0037] As shown in FIG. 3 , the ejection unit 600 includes a piezoelectric element 60, a vibration plate 621, a cavity 631, and a nozzle 651. The piezoelectric element 60 includes a piezoelectric body 601 and electrodes 611 and 612. The electrodes 611 and 612 are positioned to sandwich the piezoelectric body 601, thereby forming the piezoelectric element 60. The piezoelectric element 60 is driven so that a central portion thereof is displaced vertically in response to a potential difference between a voltage supplied to the electrode 611 and a voltage supplied to the electrode 612. Specifically, a drive signal VOUT based on a drive signal COM is supplied to the electrode 611, and a reference voltage signal VBS is supplied to the electrode 612. When the voltage value of the drive signal VOUT supplied to the electrode 611 changes, the potential difference between the drive signal VOUT supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612 changes, and as a result, the piezoelectric element 60 is driven so that a central portion thereof is displaced vertically.

[0038] The diaphragm 621 is located below the piezoelectric element 60 in Fig. 3. In other words, the piezoelectric element 60 is formed on the upper surface of the diaphragm 621 in Fig. 3. Such a diaphragm 621 is displaced in the vertical direction as the piezoelectric element 60 is driven in the vertical direction.

[0039] A cavity 631 is located below the diaphragm 621 in FIG. 3. Ink is supplied to the cavity 631 from a reservoir 641. Furthermore, ink stored in the ink container 2 is introduced into the reservoir 641 via a supply port 661. That is, the interior of the cavity 631 is filled with ink stored in the ink container 2. The internal volume of such cavity 631 expands or contracts in accordance with the vertical displacement of the diaphragm 621. That is, the diaphragm 621 functions as a diaphragm that changes the internal volume of the cavity 631, and the cavity 631 functions as a pressure chamber whose pressure changes in accordance with the vertical displacement of the diaphragm 621.

[0040] The nozzle 651 is an opening provided in the nozzle plate 632 and communicates with the cavity 631. When the internal volume of the cavity 631 changes, ink filled inside the cavity 631 is ejected from the nozzle 651 in accordance with the change in the internal volume.

[0041] In the ejection section 600 configured as described above, when the piezoelectric element 60 is driven to bend upward, the vibration plate 621 is displaced upward. This causes the internal volume of the cavity 631 to expand, and as a result, ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven to bend downward, the vibration plate 621 is displaced downward. This causes the internal volume of the cavity 631 to contract, and as a result, an amount of ink corresponding to the degree of contraction of the internal volume of the cavity 631 is ejected from the nozzle 651.

[0042] The piezoelectric element 60 is not limited to the structure shown in FIG. 3 as long as it is driven by the supply of a drive signal VOUT corresponding to the drive signal COM and is capable of ejecting ink from the nozzle 651 when driven.

[0043] As described above, the liquid ejection device 1 in this embodiment includes the ejection unit 600 that ejects ink in response to being supplied with a drive signal VOUT based on the drive signal COM, the drive signal output circuit 52 that outputs the drive signal COM on which the drive signal VOUT is based, the cooling mechanism 82 that cools the drive signal output circuit 52, the power supply circuit 80 that supplies power to the cooling mechanism 82, the temperature detection circuit 72 that detects the temperature of the drive signal output circuit 52, and the comparison circuit 70 that compares the detected temperature Tmp indicating the detection result of the temperature detection circuit 72 with the threshold temperature Tth. The drive signal VOUT based on the drive signal COM output by the drive signal output circuit 52 is supplied to the ejection unit 600, causing the ejection unit 600 to eject ink, and the ink ejected from the ejection unit 600 lands on the medium P, forming an image on the medium P.

[0044] 3. Drive signal selection circuit configuration Next, we will explain the configuration of the drive signal selection circuit 200. Figure 4 is a diagram showing an example of the configuration of the drive signal selection circuit 200. As shown in Figure 4, the drive signal selection circuit 200 has a selection control circuit 210 and selection circuits 230[1] to 230[n].

[0045] A clock signal SCK, a latch signal LAT, a change signal CH, and a head control signal DI are input to the selection control circuit 210. Then, the selection control circuit 210 generates selection signals S[1] to S[n] based on the clock signal SCK, the latch signal LAT, the change signal CH, and the head control signal DI, and outputs them to the corresponding selection circuits 230[1] to 230[n].

[0046] The selection circuits 230[1] to 230[n] are provided corresponding to the respective discharge units 600[1] to 600[n]. A drive signal COM and a corresponding selection signal S[1] to S[n] are input to each of the selection circuits 230[1] to 230[n]. Based on the selection signal S[1] to S[n] input to each of the selection circuits 230[1] to 230[n], the selection circuits 230[1] to 230[n] select or deselect the drive signal COM, thereby generating the corresponding drive signal VOUT[1] to VOUT[n] and outputting it to the corresponding discharge unit 600[1] to 600[n].

[0047] Specifically, the selection circuit 230[i] (i is any value from 1 to n) receives the selection signal S[i] output by the selection control circuit 210 and the drive signal COM. The selection circuit 230[i] then selects or deselects the drive signal COM based on the selection signal S[i] to generate VOUT[i] and output it to the discharge section 600[i].

[0048] Here, the selection circuits 230[1] to 230[n] all have the same configuration, and when there is no need to distinguish between them, they may be simply referred to as selection circuits 230. The selection circuits 230 are provided corresponding to the discharge units 600 among the discharge units 600[1] to 600[n], and the following description will be given assuming that the selection circuit 230 receives as input a selection signal S among the selection signals S[1] to S[n].

[0049] The following describes the details of the configuration of the drive signal selection circuit 200 configured as above. First, the following describes the details of the configuration of the selection control circuit 210 that the drive signal selection circuit 200 has. Before describing the detailed configuration of the selection control circuit 210, specific examples of the latch signal LAT, change signal CH, clock signal SCK, and head control signal DI that are input to the selection control circuit 210 will be described.

[0050] FIG. 5 is a diagram for explaining specific examples of the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI.

[0051] 5, the latch signal LAT is a pulse signal that is output by the control circuit 100 for each latch period Plat. The control circuit 100 generates this latch signal LAT based on a position information signal Cp that indicates the scanning position of the carriage 20 and is input from the linear encoder 90, and outputs the latch signal LAT to the drive signal selection circuit 200.

[0052] The change signal CH is a pulse signal that divides the latch cycle Plat into m periods p1 to pm. The control circuit 100 determines the number of divisions of the latch cycle Plat in accordance with the operation mode of the liquid ejection device 1, which will be described later, and the signal waveform of the drive signal COM, and outputs the change signal CH to the drive signal selection circuit 200. Here, in the liquid ejection device 1 of this embodiment, the control circuit 100 will be described as outputting a maximum of three change signals CH in the latch cycle Plat. That is, in this embodiment, the control circuit 100 divides the latch cycle Plat into a maximum of four periods p1 to p4. Note that the maximum number of divisions of the latch cycle Plat is not limited to four, and may be five or more, or may be three or less, in accordance with the operation mode of the liquid ejection device 1, which will be described later, and the signal waveform of the drive signal COM.

[0053] The head control signal DI is a signal synchronized with the clock signal SCK and includes a discharge control signal SI and a setting information signal SP in serial. The discharge control signal SI determines the amount of ink discharged from the nozzles 651 of each of the discharge units 600[1] to 600[n]. The setting information signal SP also determines the relationship between the amount of ink discharged and the discharge control signal SI during periods p1 to pm determined by the latch signal LAT and the change signal CH. The head control signal DI is generated by the control circuit 100 based on image data input from an external device and is output for each latch period Plat.

[0054] That is, in the liquid ejection device 1 of this embodiment, a latch period Plat is defined by a latch signal LAT based on the scanning position of the carriage 20 carrying the ejection head 21, and the latch period Plat is divided into a plurality of periods p1 to pm using a change signal CH, and the head control signal DI defines the amount of ink ejected in each of the periods p1 to pm defined by the latch signal LAT and the change signal CH. As a result, dots of a size defined by the head control signal DI are formed on the medium P for each latch period Plat. In other words, the latch period Plat for forming dots of a size defined by the head control signal DI on the medium P corresponds to the dot formation period in the liquid ejection device 1.

[0055] Here, a specific example of a head control signal DI including an ejection control signal SI and a setting information signal SP will be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of the data configuration of the head control signal DI. As shown in Fig. 6, the head control signal DI includes the ejection control signal SI and the setting information signal SP in serial.

[0056] The ejection control signal SI includes, in series, upper order ejection data SIH1 to SIHn and lower order ejection data SIL1 to SILn for individually defining the amount of ink ejected from the nozzles 651 of each of the ejection sections 600[1] to 600[n].

[0057] Specifically, the discharge control signal SI includes upper order discharge data SIH1 corresponding to the discharge unit 600[1], upper order discharge data SIH2 corresponding to the discharge unit 600[2], ..., upper order discharge data SIHn-1 corresponding to the discharge unit 600[n-1], and upper order discharge data SIHn corresponding to the discharge unit 600[n], in the order of upper order discharge data SIHn, SIHn-1, ..., SIH2, SIH1. The discharge control signal SI also includes lower order discharge data SIL1 corresponding to the discharge unit 600[1], lower order discharge data SIL2 corresponding to the discharge unit 600[2], ..., lower order discharge data SILn-1 corresponding to the discharge unit 600[n-1], and lower order discharge data SILn corresponding to the discharge unit 600[n], in the order of lower order discharge data SILn, SILn-1, ..., SIL2, SIL1.

[0058] In this case, the upper order ejection data SIHn, SIHn-1, ..., SIH2, SIH1 and the lower order ejection data SILn, SILn-1, ..., SIL2, SIL1 are included in the ejection control signal SI serially in the order of upper order ejection data SIHn, SIHn-1, ..., SIH2, SIH1, and lower order ejection data SILn, SILn-1, ..., SIL2, SIL1. In other words, the ejection control signal SI includes a maximum of 2n bits of data.

[0059] In this case, the amount of ink ejected from the nozzle 651 corresponding to the ejection unit 600[i] is defined by two bits: the upper-order ejection data SIHi and the lower-order ejection data SILi. In this case, the upper-order ejection data SIHi and the lower-order ejection data SILi may be collectively referred to as the ejection data [SIHi, SILi].

[0060] In the following description, the ejection unit 600 corresponds to the upper-order ejection data SIH and the lower-order ejection data SIL. That is, the amount of ink ejected from the ejection unit 600 is determined by two bits, the upper-order ejection data SIH and the lower-order ejection data SIL. In this case, the upper-order ejection data SIH and the lower-order ejection data SIL may be collectively referred to as the ejection data [SIH, SIL].

[0061] The setting information signal SP includes information that defines the relationship between the ejection control signal SI during each of the periods p1 to pm and the amount of ink ejected from the nozzle 651. Specifically, the setting information signal SP defines the relationship between the combination of logical levels of the ejection data [SIH, SIL] included in the ejection control signal SI and the logical level of the selection signal S input to the corresponding selection circuit 230.

[0062] In detail, the setting information signal SP includes setting data PA00 to PA03 which are drive patterns of the piezoelectric elements 60 of the ejection section 600 in the period p1 and define the relationship between the logical level of the selection signal S in the period p1 and the combination of the logical levels of the ejection data [SIH, SIL], and setting data PA10 to PA15 which are drive patterns of the piezoelectric elements 60 of the ejection section 600 in the period p2 and define the relationship between the logical level of the selection signal S in the period p2 and the combination of the logical levels of the ejection data [SIH, SIL]. The set data includes PA13, setting data PA20 to PA23 which are the drive pattern of the piezoelectric element 60 of the ejection section 600 during period p3 and which specify the relationship between the logical level of the selection signal S during period p3 and the combination of the logical levels of the ejection data [SIH, SIL], and setting data PA30 to PA33 which are the drive pattern of the piezoelectric element 60 of the ejection section 600 during period p4 and which specify the relationship between the logical level of the selection signal S during period p4 and the combination of the logical levels of the ejection data [SIH, SIL].

[0063] Such setting data PA00 to PA03, PA10 to PA13, PA20 to PA23, and PA30 to PA33 are serially included in the setting information signal SP in the following order: setting data PA33, PA32, PA31, PA30, PA23, PA22, PA21, PA20, PA13, PA12, PA11, PA10, PA03, PA02, PA01, and PA00. Here, the setting information signal SP in this embodiment will be described as including 16-bit data of setting data PA00 to PA03, PA10 to PA13, PA20 to PA23, and PA30 to PA33, but the amount of data included in the setting information signal SP is not limited to 16 bits.

[0064] As described above, the selection control circuit 210 receives as input the latch signal LAT that defines the latch period Plat, which corresponds to the dot formation period, the change signal CH that divides the latch period Plat into periods p1 to pm, the ejection control signal SI that individually defines the amount of ink ejected onto the medium P from each of the n nozzles 651 during each of the periods p1 to pm, the head control signal DI that serially includes the setting information signal SP that defines the relationship between the ejection control signal SI and the drive pattern of the piezoelectric element 60, and the clock signal SCK that propagates the head control signal DI. The selection control circuit 210 then generates selection signals S[1] to S[n] that correspond to the ejection units 600[1] to 600[n], respectively, based on the input latch signal LAT, change signal CH, clock signal SCK, and head control signal DI, and outputs them to the corresponding selection circuits 230[1] to 230[n].

[0065] Next, a specific example of the configuration of the selection control circuit 210 will be described. Fig. 7 is a diagram showing an example of the functional configuration of the selection control circuit 210. As shown in Fig. 7, the selection control circuit 210 has a control logic circuit 260 and selection signal output units 270[1] to 270[n] provided corresponding to the ejection units 600[1] to 600[n]. The selection control circuit 210 generates and outputs selection signals S[1] to S[n] corresponding to the ejection units 600[1] to 600[n], respectively, based on the head control signal DI during periods p1 to p4 defined by the latch signal LAT and the change signal CH.

[0066] The control logic circuit 260 includes a group of SP registers 262 and a selection control signal generation unit 264 .

[0067] The SP register group 262 includes a plurality of registers connected in series. The head control signal DI is input to the SP register group 262 in synchronization with the clock signal SCK. The SP register group 262 propagates the head control signal DI to subsequent registers in synchronization with the clock signal SCK. In other words, the SP register group 262 includes a so-called shift register.

[0068] Then, when the supply of the clock signal SCK stops, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 included in the setting information signal SP of the head control signal DI are held in the SP register group 262. The selection control signal generator 264 simultaneously latches the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 held in the SP register group 262 at the rising edge of the latch signal LAT, and generates and outputs setting signals Q1 to Q4 based on the latched setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00.

[0069] Specifically, the selection control signal generation unit 264 generates a setting signal Q1 including setting data PA00 to PA03, a setting signal Q2 including setting data PA10 to PA13, a setting signal Q3 including setting data PA20 to PA23, and a setting signal Q4 including setting data PA30 to PA33. and outputs it to the decoder 226 included in each of the selection signal output units 270[1] to 270[n].

[0070] The setting signal Q1 defines the relationship between the combination of logic levels of the ejection data [SIH, SIL] during period p1 and the logic level of the selection signal S based on the setting data PA00 to PA03. The setting signal Q2 defines the relationship between the combination of logic levels of the ejection data [SIH, SIL] during period p2 and the logic level of the selection signal S based on the setting data PA10 to PA13. The setting signal Q3 defines the relationship between the combination of logic levels of the ejection data [SIH, SIL] during period p3 and the logic level of the selection signal S based on the setting data PA20 to PA23. The setting signal Q4 defines the relationship between the combination of logic levels of the ejection data [SIH, SIL] during period p4 and the logic level of the selection signal S based on the setting data PA30 to PA33.

[0071] In the following description, setting signal Q1 including setting data PA00 to PA03 may be referred to as setting signal Q1 [PA00, PA01, PA02, PA03], setting signal Q2 including setting data PA10 to PA13 may be referred to as setting signal Q2 [PA10, PA11, PA12, PA13], setting signal Q3 including setting data PA20 to PA23 may be referred to as setting signal Q3 [PA20, PA21, PA22, PA23], and setting signal Q4 including setting data PA30 to PA33 may be referred to as setting signal Q4 [PA30, PA31, PA32, PA33].

[0072] The selection signal output units 270[1] to 270[n] each have a first register 222a, a second register 222b, a first latch circuit 224a, a second latch circuit 224b, and a decoder 226. In the following description, when there is no need to distinguish between the selection signal output units 270[1] to 270[n], they may be simply referred to as selection signal output units 270. In this case, the description will be given assuming that the selection signal output units 270 are provided corresponding to the discharge units 600.

[0073] The second register 222b included in the selection signal output unit 270[1] is connected to the rear stage of the SP register group 262. The second register 222b included in the selection signal output unit 270[2] is connected to the rear stage of the second register 222b included in the selection signal output unit 270[1]. The second register 222b included in the selection signal output unit 270[i] is connected to the rear stage of the second register 222b included in the selection signal output unit 270[i-1].

[0074] Furthermore, the first register 222a included in the selection signal output unit 270[1] is connected to the rear stage of the second register 222b included in the selection signal output unit 270[n]. The first register 222a included in the selection signal output unit 270[2] is connected to the rear stage of the first register 222a included in the selection signal output unit 270[1]. The first register 222a included in the selection signal output unit 270[i] is connected to the rear stage of the first register 222a included in the selection signal output unit 270[i-1]. And the first register 222a included in the selection signal output unit 270[n] is connected to the rear stage of the first register 222a included in the selection signal output unit 270[n-1].

[0075] That is, the second registers 222b possessed by each of the selection signal output units 270[1] to 270[n] are connected in series in the order of the second register 222b possessed by the selection signal output unit 270[1], the second register 222b possessed by the selection signal output unit 270[2], ..., the second register 222b possessed by the selection signal output unit 270[n], and the first registers 222a possessed by each of the selection signal output units 270[1] to 270[n] are connected in series in the order of the first register 222a possessed by the selection signal output unit 270[1], the first register 222a possessed by the selection signal output unit 270[2], ..., the first register 222a possessed by the selection signal output unit 270[n]. In the selection control circuit 210, the plurality of serially connected registers included in the SP register group 262, the second register 222b of each of the serially connected selection signal output units 270[1] to 270[n], and the first register 222a of each of the serially connected selection signal output units 270[1] to 270[n] are connected in series in the following order: the plurality of serially connected registers included in the SP register group 262, the second register 222b of each of the serially connected selection signal output units 270[1] to 270[n], and the first register 222a of each of the serially connected selection signal output units 270[1] to 270[n]. That is, the multiple registers included in the SP register group 262, the second registers 222b included in each of the selection signal output units 270[1] to 270[n], and the first registers 222a included in each of the selection signal output units 270[1] to 270[n] configure a shift register. As a result, the head control signal DI input to the selection control circuit 210 is propagated in synchronization with the clock signal SCK through the SP register group 262, the n second registers 222b included in each of the selection signal output units 270[1] to 270[n], and the n first registers 222a included in each of the selection signal output units 270[1] to 270[n] in that order.

[0076] Thereafter, the supply of the clock signal SCK stops, and the second register 222b included in the selection signal output unit 270 holds the lower ejection data SIL corresponding to the ejection unit 600, and the first register 222a included in the selection signal output unit 270 holds the upper ejection data SIH corresponding to the ejection unit 600.

[0077] Then, at the rising edge of the latch signal LAT, the upper-order ejection data SIH held in the first register 222a of the selection signal output unit 270 is latched by the first latch circuit 224a of the selection signal output unit 270, and the lower-order ejection data SIL held in the second register 222b of the selection signal output unit 270 is latched by the second latch circuit 224b of the selection signal output unit 270. The first latch circuit 224a of the selection signal output unit 270 outputs the latched upper-order ejection data SIH as latch data LTa to the decoder 226 of the selection signal output unit 270, and the second latch circuit 224b of the selection signal output unit 270 outputs the latched lower-order ejection data SIL as latch data LTb to the decoder 226 of the selection signal output unit 270.

[0078] Here, in the following description, the latch data LTai and latch data LTbi input to the decoder 226 of the selection signal output unit 270[i] may be collectively referred to as latch data [LTai, LTbi], and the latch data LTa and latch data LTb input to the decoder 226 of the selection signal output unit 270 may be collectively referred to as latch data [LTa, LTb].

[0079] The decoder 226 included in the selection signal output unit 270 receives the setting signals Q1 [PA00, PA01, PA02, PA03], Q2 [PA10, PA11, PA12, PA13], Q3 [PA20, PA21, PA22, PA23], and Q4 [PA30, PA31, PA32, PA33] output by the selection control signal generation unit 264, as well as latch data [LTa, LTb] corresponding to the ejection data [SIH, SIL]. The decoder 226 included in the selection signal output unit 270 decodes the latch data [LTa, LTb] based on the setting signals Q1 to Q4 to generate a selection signal S and output it to the selection circuit 230.

[0080] 8 is a diagram showing an example of the decoded contents of the decoder 226 included in the selection signal output unit 270. As shown in Fig. 8, the decoder 226 included in the selection signal output unit 270 outputs a selection signal S obtained by decoding input latch data [LTa, LTb] based on a setting signal Q1 [PA00, PA01, PA02, PA03] during a period p1, outputs a selection signal S obtained by decoded based on a setting signal Q2 [PA10, PA11, PA12, PA13] during a period p2, outputs a selection signal S obtained by decoded based on a setting signal Q3 [PA20, PA21, PA22, PA23] during a period p3, and outputs a selection signal S obtained by decoded based on a setting signal Q4 [PA30, PA31, PA32, PA33] during a period p4.

[0081] Specifically, for example, when latch data [LTa,LTb]=[0,1] corresponding to ejection data [SIH,SIL]=[0,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 decodes the latch data [LTa,LTb]=[0,1] to output a selection signal S of a logic level defined by the setting data PA01 in period p1, output a selection signal S of a logic level defined by the setting data PA11 in period p2, output a selection signal S of a logic level defined by the setting data PA21 in period p3, and output a selection signal S of a logic level defined by the setting data PA31 in period p4. That is, the decoded contents of the decoder 226 of the selection signal output unit 270 are defined by the setting signals Q1 to Q4 output by the selection control signal generation unit 264.

[0082] Next, a description will be given of the configuration of the selection circuits 230[1] to 230[n] to which the selection signals S[1] to S[n] are respectively input. Fig. 9 is a diagram showing an example of the configuration of the selection circuit 230 corresponding to the discharge unit 600. As shown in Fig. 9, the selection circuit 230 has an inverter INV, which is a NOT circuit, and a transfer gate TG.

[0083] The selection signal S output by the selection control circuit 210 is input to the positive control terminal (not circled) of the transfer gate TG, and after its logical level is inverted by an inverter INV, is also input to the negative control terminal (circled) of the transfer gate TG. A drive signal COM is also supplied to the input terminal of the transfer gate TG.

[0084] When an H-level selection signal S is input to such a selection circuit 230, the transfer gate TG establishes conduction between its input terminal and its output terminal, and when an L-level selection signal S is input, the transfer gate TG establishes non-conduction between its input terminal and its output terminal. That is, when an H-level selection signal S is input to the selection circuit 230, the selection circuit 230 outputs the drive signal COM supplied to the input terminal of the transfer gate TG as the drive signal VOUT from the output terminal, and when an L-level selection signal S is input, the selection circuit 230 does not output the drive signal COM supplied to the input terminal of the transfer gate TG as the drive signal VOUT from the output terminal. That is, the selection circuit 230 switches whether or not to output the drive signal COM as the drive signal VOUT depending on the logic level of the input selection signal S.

[0085] In the drive signal selection circuit 200 configured as described above, the selection control circuit 210 generates selection signals S[1] to S[n] corresponding to each of the selection circuits 230[1] to 230[n] individually based on the head control signal DI during each of periods p1 to p4 defined by the latch signal LAT and change signal CH, and outputs these signals to the corresponding selection circuits 230[1] to 230[n]. The selection circuits 230[1] to 230[n] switch whether to output the drive signal COM as the drive signals VOUT[1] to VOUT[n] depending on the logic level of the input selection signals S[1] to S[n]. This individually controls the amount of ink ejected from each of the ejection units 600[1] to 600[n].

[0086] That is, the drive signal selection circuit 200 includes a selection circuit 230 which receives as input a setting information signal SP which includes setting signals Q1 and Q2 and sets the selection rules for the signal waveform included in the drive signal COM, a head control signal DI which includes an ejection control signal SI which controls the gradation of the dots formed by the ink being ejected from the ejection section 600 by specifying the amount of ink ejected from the ejection section 600, and which switches whether or not to supply the signal waveform of the drive signal COM to the ejection section 600 based on the setting information signal SP and the ejection control signal SI. In other words, the liquid ejection device 1 includes a wiring A shown in Figure 4 that transmits to the drive signal selection circuit 200 a setting information signal SP that sets the selection rules for the signal waveform included in the drive signal COM, and a head control signal DI that includes an ejection control signal SI that controls the gradation of dots formed by ink being ejected from the ejection section 600 by specifying the amount of ink ejected from the ejection section 600, a wiring B shown in Figure 4 that transmits the drive signal COM to the drive signal selection circuit 200, and a selection circuit 230 that switches whether or not to supply the signal waveform of the drive signal COM to the ejection section 600 based on the setting information signal SP and the ejection control signal SI.

[0087] 4. Operation mode of the liquid ejection device The liquid ejection device 1 of this embodiment configured as described above has two operation modes for forming an image on the medium P: a multi-tone mode and a binary mode.

[0088] The multi-tone mode is an operating mode that aims to form a high-resolution image on the medium P, and specifically, this is achieved by increasing the number of gradations of dots formed on the medium P by having the ejection head 21 eject ink onto the medium P in multiple batches during the latch period Plat. On the other hand, the binary mode is an operating mode that aims to form an image on the medium P at high speed, and specifically, this is achieved by reducing the number of times ink is ejected onto the medium P during the latch period Plat, thereby shortening the ejection frequency at which ink is ejected onto the medium P.

[0089] In this embodiment, when the liquid ejection device 1 is operating in multi-tone mode, the gradation of the dots formed on the medium P is controlled in four gradations: large dot, medium dot, small dot, and no ejection, thereby realizing high-resolution image formation on the medium P, and when the liquid ejection device 1 is operating in binary mode, the gradation of the dots formed on the medium P is controlled in two gradations: whether or not dots are formed, thereby realizing high-speed image formation on the medium P. In other words, the gradation of the dots formed on the medium P in binary mode is lower than the gradation of the dots formed on the medium P in multi-tone mode, and the dot formation speed at which dots are formed on the medium P in binary mode is faster than the dot formation speed at which dots are formed on the medium P in multi-tone mode.

[0090] Depending on the application, type of medium, and the like, the liquid ejector 1 may be required to form a high-resolution image in some cases, or to form an image at high speed in other cases. The liquid ejector 1 of this embodiment has a multi-tone mode and a binary mode as operation modes for forming an image on the medium P, allowing the user to select an operation mode suited to the application, thereby improving convenience for the user and increasing the versatility of the liquid ejector 1. Specific examples of the multi-tone mode and binary mode that the liquid ejector 1 has will be described.

[0091] In the following description, when explaining the logical levels of various data, the bit data of an H-level signal may be referred to as "1" and the bit data of an L-level signal may be referred to as "0."

[0092] 4.1 Multi-tone mode First, an example of the operation of the liquid ejection device 1 when the operating mode of the liquid ejection device 1 is the multi-tone mode will be described.

[0093] Fig. 10 is a diagram showing an example of the signal waveform of the drive signal COM output by the drive signal output circuit 52 in the multi-gradation mode. As shown in Fig. 10, the drive signal COM in the multi-gradation mode includes a signal waveform in which a trapezoidal waveform Dp11 arranged in a period p1, a trapezoidal waveform Dp21 arranged in a period p2, a trapezoidal waveform Dp31 arranged in a period p3, and a trapezoidal waveform Dp41 arranged in a period p4 are successively arranged.

[0094] The trapezoidal waveform Dp11 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes a predetermined amount of ink to be ejected from the nozzle 651 corresponding to that piezoelectric element 60. The trapezoidal waveform Dp21 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes a smaller amount of ink than the predetermined amount to be ejected from the nozzle 651 corresponding to that piezoelectric element 60. The trapezoidal waveform Dp31 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes an even smaller amount of ink to be ejected from the nozzle 651 corresponding to that piezoelectric element 60. The trapezoidal waveform Dp41 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, does not cause ink to be ejected from the nozzle 651 corresponding to that piezoelectric element 60, but instead vibrates the ink near the opening of the nozzle 651, thereby reducing the risk of an increase in the viscosity of the ink near the nozzle 651.

[0095] In the drive signal COM, each of the trapezoidal waveforms Dp11, Dp21, Dp31, and Dp41 starts and ends at voltage Vc. That is, the trapezoidal waveforms Dp11, Dp21, Dp31, and Dp41 are signal waveforms that all have a common voltage Vc at the start and end timings.

[0096] In the following description, the amount of ink ejected from the nozzle 651 when the trapezoidal waveform Dp11 is supplied to the electrode 611 may be referred to as a large amount, the amount of ink ejected from the nozzle 651 when the trapezoidal waveform Dp21 is supplied to the electrode 611 may be referred to as a medium amount, and the amount of ink ejected from the nozzle 651 when the trapezoidal waveform Dp31 is supplied to the electrode 611 may be referred to as a small amount. Also, the operation of vibrating the ink near the opening of the corresponding nozzle 651 by supplying the trapezoidal waveform Dp41 to the electrode 611 may be referred to as micro-vibration, and the trapezoidal waveform Dp41 that executes this micro-vibration may be referred to as a micro-vibration waveform.

[0097] As described above, the drive signal COM in the multi-tone mode includes trapezoidal waveforms Dp11, Dp21, Dp31, and Dp41 arranged in periods p1 to p4. Therefore, the control circuit 100 outputs a change signal CH that divides the latch period Plat into four so that each of the trapezoidal waveforms Dp11, Dp21, Dp31, and Dp41 arranged in periods p1 to p4 can be selected.

[0098] In the multi-tone mode, the drive signal selection circuit 200 generates drive signals VOUT[1] to VOUT[n] by selecting or deselecting each of the trapezoidal waveforms Dp11, Dp21, Dp31, and Dp41 included in the drive signal COM based on the head control signal DI during each of the periods p1 to p4 defined by the latch signal LAT and the change signal CH, and outputs them to the corresponding ejection sections 600[1] to 600[n].

[0099] FIG. 11 is a diagram showing an example of the head control signal DI in the multi-tone mode.

[0100] As described above, the ejection control signal SI included in the head control signal DI defines the amount of ink ejected from the nozzles 651 of each of the ejection units 600[1] to 600[n]. Therefore, the logical level of the ejection control signal SI in the multi-tone mode changes appropriately depending on the amount of ink ejected from the corresponding nozzle 651 during the period in which the liquid ejection device 1 is performing so-called printing control to eject ink onto the medium P.

[0101] On the other hand, the setting information signal SP included in the head control signal DI in the multi-tone mode serially includes, as shown in Figure 11, "0" as setting data PA33, "0" as setting data PA32, "0" as setting data PA31, "1" as setting data PA30, "1" as setting data PA23, "1" as setting data PA22, "0" as setting data PA21, "0" as setting data PA20, "1" as setting data PA13, "0" as setting data PA12, "1" as setting data PA11, "0" as setting data PA10, "1" as setting data PA03, "1" as setting data PA02, "0" as setting data PA01, and "0" as setting data PA00.

[0102] That is, in this embodiment, when the operating mode of the liquid ejection device 1 is the multi-tone mode, a head control signal DI including a 16-bit setting information signal SP whose logic level is “0001 1100 1010 1100” is input to the drive signal selection circuit 200.

[0103] The setting information signals SP input to the drive signal selection circuit 200 are held in the SP register group 262 and then latched all at once by the selection control signal generation unit 264 at the rising edge of the latch signal LAT. Then, the selection control signal generation unit 264 generates a setting signal Q1 [PA00, PA01, PA02, PA03] = [0,0,1,1], a setting signal Q2 [PA10, PA11, PA12, PA13] = [0,1,0,1], a setting signal Q3 [PA20, PA21, PA22, PA23] = [0,0,1,1], and a setting signal Q4 [PA30, PA31, PA32, PA33] = [1,0,0,0] from the latched setting information signals SP, and outputs them to the decoders 226 included in each of the selection signal output units 270[1] to 270[n].

[0104] As described above, the decoded content of the decoder 226 included in the selection signal output unit 270 is defined by the setting signals Q1 to Q4 output by the selection control signal generation unit 264. Fig. 12 is a diagram showing the decoded content of the decoder 226 based on the head control signal DI shown in Fig. 11. The decoder 226 included in the selection signal output unit 270 decodes the latch data [LTa, LTb] corresponding to the input ejection data [SIH, SIL] according to the content shown in Fig. 12, thereby outputting a selection signal S of a predetermined logic level.

[0105] For example, when latch data [LTa,LTb]=[1,0] corresponding to ejection data [SIH,SIL]=[1,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a high-level selection signal S in period p1, a low-level selection signal S in period p2, a high-level selection signal S in period p3, and a low-level selection signal S in period p4.

[0106] 13 is a diagram for explaining the operation of the drive signal selection circuit 200 in multi-tone mode. The head control signal DI input to the drive signal selection circuit 200 is synchronized with the clock signal SCK and propagates sequentially through multiple registers included in the SP register group 262, the second registers 222b in each of the selection signal output units 270[1] to 270[n], and the first registers 222a in each of the selection signal output units 270[1] to 270[n].

[0107] Then, when the supply of the clock signal SCK stops, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, PA03 to PA00 contained in the setting information signal SP are held in multiple registers included in the SP register group 262, the lower-order ejection data SIL1 to SILn contained in the ejection control signal SI are held in the second register 222b possessed by each of the selection signal output units 270[1] to 270[n], and the upper-order ejection data SIH1 to SIHn contained in the ejection control signal SI are held in the first register 222a possessed by each of the selection signal output units 270[1] to 270[n].

[0108] Thereafter, when the latch signal LAT rises, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, PA03 to PA00 held in the multiple registers included in the SP register group 262 are latched all at once by the selection control signal generation unit 264, the lower-order ejection data SIL1 to SILn held in the second register 222b of each of the selection signal output units 270[1] to 270[n] are latched all at once by the second latch circuit 224b of each of the selection signal output units 270[1] to 270[n], and the upper-order ejection data SIH1 to SIHn held in the first register 222a of each of the selection signal output units 270[1] to 270[n] are latched all at once by the first latch circuit 224a of each of the selection signal output units 270[1] to 270[n].

[0109] The selection control signal generation unit 264 generates setting signals Q1 to Q4 from the latched setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00, and outputs them to the decoders 226 of each of the selection signal output units 270[1] to 270[n]. In addition, the second latch circuits 224b of each of the selection signal output units 270[1] to 270[n] output the lower order ejection data SIL1 to SILn latched therein as latch data LTb1 to LTbn to the corresponding decoders 226, and the first latch circuits 224a of each of the selection signal output units 270[1] to 270[n] output the upper order ejection data SIH1 to SIHn latched therein as latch data LTa1 to LTan to the corresponding decoders 226.

[0110] That is, the decoder 226 of the selection signal output unit 270 receives the setting signal Q1 [PA00, PA01, PA02, PA03] = [0,0,1,1], setting signal Q2 [PA10, PA11, PA12, PA13] = [0,1,0,1], setting signal Q3 [PA20, PA21, PA22, PA23] = [0,0,1,1], and setting signal Q4 [PA30, PA31, PA32, PA33] = [1,0,0,0] output by the selection control signal generation unit 264, as well as the latch data [LTa, LTb] output by the first latch circuit 224a and the second latch circuit 224b of the selection signal output unit 270.

[0111] The decoder 226 included in the selection signal output unit 270 decodes the input latch data [LTa, LTb] as shown in Fig. 12. As a result, the decoder 226 included in the selection signal output unit 270 outputs a selection signal S of a predetermined logic level according to the logic level of the input latch data [LTa, LTb] and the setting signals Q1 to Q4.

[0112] Specifically, when the ejection data [SIH,SIL]=[0,0], i.e., when the latch data [LTa,LTb]=[0,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a low-level selection signal S during period p1, a low-level selection signal S during period p2, a low-level selection signal S during period p3, and a high-level selection signal S during period p4. Accordingly, the input and output terminals of the corresponding selection circuit 230 are controlled to be non-conductive during period p1, non-conductive during period p2, non-conductive during period p3, and conductive during period p4. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that is constant at voltage Vc during period p1, constant at voltage Vc during period p2, constant at voltage Vc during period p3, and has a trapezoidal waveform Dp41 during period p4. In this case, only the ink in the vicinity of the nozzle 651 of the corresponding ejection unit 600 vibrates, and no ink is ejected from the nozzle 651.

[0113] When the ejection data [SIH,SIL]=[0,1], i.e., when the latch data [LTa,LTb]=[0,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a low-level selection signal S during period p1, a high-level selection signal S during period p2, a low-level selection signal S during period p3, and a low-level selection signal S during period p4. Therefore, the input and output terminals of the corresponding selection circuit 230 are controlled to be non-conductive during period p1, conductive during period p2, non-conductive during period p3, and non-conductive during period p4. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that is constant at voltage Vc during period p1, has a trapezoidal waveform Dp21 during period p2, is constant at voltage Vc during period p3, and is constant at voltage Vc during period p4. In this case, a medium amount of ink is ejected from the nozzle 651 of the ejection unit 600.

[0114] When the ejection data [SIH,SIL]=[1,0], i.e., when the latch data [LTa,LTb]=[1,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a high-level selection signal S during period p1, a low-level selection signal S during period p2, a high-level selection signal S during period p3, and a low-level selection signal S during period p4. Therefore, the input and output terminals of the corresponding selection circuit 230 are controlled to be conductive during period p1, non-conductive during period p2, conductive during period p3, and non-conductive during period p4. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that has a trapezoidal waveform Dp11 during period p1, a constant voltage Vc during period p2, a trapezoidal waveform Dp31 during period p3, and a constant voltage Vc during period p4. In this case, a large amount of ink and a small amount of ink are ejected from the nozzles 651 of the ejection unit 600.

[0115] When the ejection data [SIH,SIL]=[1,1], i.e., when the latch data [LTa,LTb]=[1,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a high-level selection signal S during period p1, a high-level selection signal S during period p2, a high-level selection signal S during period p3, and a low-level selection signal S during period p4. Therefore, the input and output terminals of the corresponding selection circuit 230 are controlled to be conductive during period p1, conductive during period p2, conductive during period p3, and non-conductive during period p4. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that has a trapezoidal waveform Dp11 during period p1, a trapezoidal waveform Dp21 during period p2, a trapezoidal waveform Dp31 during period p3, and a constant voltage Vc during period p4. In this case, a large amount of ink, a medium amount of ink, and a small amount of ink are ejected from the nozzles 651 of the ejection unit 600.

[0116] As described above, in the liquid ejection device 1 of this embodiment, when the operating mode is the multi-tone mode, the ejection unit 600 does not eject ink when the corresponding ejection data [SIH,SIL]=[0,0], ejects a medium amount of ink when the corresponding ejection data [SIH,SIL]=[0,1], ejects a large amount of ink and a small amount of ink when the corresponding ejection data [SIH,SIL]=[1,0], and ejects a large amount of ink, a medium amount of ink, and a small amount of ink when the corresponding ejection data [SIH,SIL]=[1,1]. Therefore, when the ejection data [SIH,SIL] = [0,0], no dots are formed on the medium P, when the ejection data [SIH,SIL] = [0,1], dots of a size corresponding to a medium amount of ink are formed on the medium P, when the ejection data [SIH,SIL] = [1,0], dots of a size resulting from a combination of a large amount of ink and a small amount of ink are formed on the medium P, and when the ejection data [SIH,SIL] = [1,1], dots of a size resulting from a combination of a large amount of ink, a medium amount of ink, and a small amount of ink are formed on the medium P.

[0117] That is, when the operating mode of the liquid ejection device 1 of this embodiment is the multi-tone mode, dots of four gradations corresponding to the logical levels of the ejection data [SIH, SIL] are formed on the medium P. This allows the liquid ejection device 1 to form high-resolution images.

[0118] It should be noted that in the multi-tone mode, the number of signal waveforms per latch cycle Plat included in the drive signal COM and the number of times that the drive signal selection circuit 200 controls the ejection of ink from the ejection head 21 per latch cycle Plat are not limited to "4." In other words, the number of gradations of dots formed on the medium P in the multi-tone mode is not limited to "4," and may be changed as appropriate depending on the user's requirements and the application of the liquid ejection device 1.

[0119] 4.2 Binary Mode Next, an example of the operation of the liquid ejection device 1 when the operating mode of the liquid ejection device 1 is the binary mode will be described.

[0120] Fig. 14 is a diagram showing an example of the signal waveform of the drive signal COM output in the binary mode by the drive signal output circuit 52. As shown in Fig. 14, the drive signal COM in the binary mode is a signal waveform formed by successively connecting a trapezoidal waveform Dp12 arranged in a period p1 and a trapezoidal waveform Dp42 arranged in a period p2.

[0121] The trapezoidal waveform Dp12 is a signal waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes a predetermined amount of ink to be ejected from the nozzle 651 corresponding to the piezoelectric element 60. The trapezoidal waveform Dp42 is a micro-vibration waveform that, when supplied to the electrode 611 of the piezoelectric element 60, causes the ink near the opening of the nozzle 651 to vibrate slightly, without causing the ink to be ejected from the nozzle 651 corresponding to the piezoelectric element 60.

[0122] In the drive signal COM, the trapezoidal waveforms Dp12 and Dp42 each start and end at voltage Vc, similar to the trapezoidal waveforms Dp11, Dp21, Dp31, and Dp41. That is, the trapezoidal waveforms Dp12 and Dp42 are signal waveforms in which the voltage values ​​at the start and end timings are both voltage Vc.

[0123] Here, the drive signal COM in the multi-tone mode includes four signal waveforms, namely, trapezoidal waveforms Dp11, Dp21, Dp31, and Dp42, which are respectively arranged in periods p1 to p4 defined by the latch signal LAT and the change signal CH, as shown in FIG. 10 , whereas the drive signal COM in the binary mode includes two signal waveforms, namely, trapezoidal waveforms Dp12 and Dp42, which are respectively arranged in periods p1 to p2 defined by the latch signal LAT and the change signal CH, as shown in FIG. 14 . Therefore, the latch period Plat in the binary mode can be made shorter than the latch period Plat in the multi-tone mode, thereby increasing the scanning speed of the carriage 20 carrying the ejection head 21. In other words, the frequency of the drive signal COM output by the drive signal output circuit 52 in the binary mode can be made higher than the frequency of the drive signal COM output by the drive signal output circuit 52 in the multi-tone mode. As a result, the image forming speed at which an image is formed on the medium P in the binary mode can be made faster than the image forming speed at which an image is formed on the medium P in the multi-tone mode.

[0124] In other words, the liquid ejection device 1 of this embodiment includes a binary mode in which the drive signal output circuit 52 outputs to the ejection section 600 a drive signal COM having a frequency based on a latch cycle Plat including two periods p1 to p2, and a multi-tone mode in which the drive signal output circuit 52 outputs to the ejection section 600 a drive signal COM having a frequency based on a latch cycle Plat including four periods p1 to p4, which is lower than the frequency of the drive signal COM in the binary mode. This makes it possible to form a high-resolution image on the medium P in the multi-tone mode, and to form an image on the medium P at high speed in the binary mode.

[0125] In binary mode, the drive signal selection circuit 200 generates drive signals VOUT[1] to VOUT[n] by selecting or deselecting each of the trapezoidal waveforms Dp12, Dp42 included in the drive signal COM based on the head control signal DI during each of the periods p1 to p2 defined by the latch signal LAT and the change signal CH, and outputs them to the corresponding ejection sections 600[1] to 600[n].

[0126] FIG. 15 is a diagram showing an example of the head control signal DI in the binary mode.

[0127] As described above, the ejection control signal SI included in the head control signal DI determines the amount of ink ejected from the nozzles 651 of each of the ejection units 600[1] to 600[n], just as in the multi-tone mode. Therefore, the logical level of the ejection control signal SI in the binary mode also changes appropriately depending on the amount of ink ejected from the corresponding nozzle 651 during the period when the liquid ejection device 1 is executing print control for ejecting ink onto the medium P.

[0128] On the other hand, the setting information signal SP included in the head control signal DI in the binary mode is different from the setting information signal SP included in the head control signal DI in the multi-tone mode. Specifically, the setting information signal SP included in the head control signal DI in the binary mode serially includes "0" as setting data PA33, "0" as setting data PA32, "0" as setting data PA31, "0" as setting data PA30, "0" as setting data PA23, "0" as setting data PA22, "0" as setting data PA21, "0" as setting data PA20, "0" as setting data PA13, "1" as setting data PA12, "0" as setting data PA11, "1" as setting data PA10, "1" as setting data PA03, "0" as setting data PA02, "1" as setting data PA01, and "0" as setting data PA00.

[0129] That is, in this embodiment, when the operating mode of the liquid ejection device 1 is the binary mode, the head control signal DI including the 16-bit setting information signal SP whose logic level is “0000 0000 0101 1010” is input to the drive signal selection circuit 200.

[0130] The setting information signals SP input to the drive signal selection circuit 200 are held in the SP register group 262 and then latched all at once by the selection control signal generation unit 264 at the rising edge of the latch signal LAT. Then, the selection control signal generation unit 264 generates a setting signal Q1 [PA00, PA01, PA02, PA03] = [0,1,0,1], a setting signal Q2 [PA10, PA11, PA12, PA13] = [1,0,1,0], a setting signal Q3 [PA20, PA21, PA22, PA23] = [0,0,0,0], and a setting signal Q4 [PA30, PA31, PA32, PA33] = [0,0,0,0] from the latched setting information signals SP, and outputs them to the decoders 226 included in each of the selection signal output units 270[1] to 270[n].

[0131] That is, the binary mode setting information signal SP includes setting data PA00, PA01, PA02, and PA03 corresponding to the setting signal Q1, and setting data PA10, PA11, PA12, and PA13 corresponding to the setting signal Q2, which is the inverted bit data of the setting signal Q1.

[0132] As described above, in the binary mode as well as the multi-tone mode, the decoded content of the decoder 226 in the selection signal output unit 270 is determined by the setting signals Q1 to Q4 output by the selection control signal generation unit 264. Figure 16 is a diagram showing the decoded content of the decoder 226 based on the head control signal DI shown in Figure 15. The decoder 226 in the selection signal output unit 270 outputs a selection signal S of a predetermined logic level by decoding the latch data [LTa, LTb] corresponding to the input ejection data [SIH, SIL] according to the content shown in Figure 16.

[0133] For example, when latch data [LTa,LTb]=[1,0] corresponding to ejection data [SIH,SIL]=[1,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a low-level selection signal S in period p1, a high-level selection signal S in period p2, a low-level selection signal S in period p3, and a low-level selection signal S in period p4.

[0134] 17 is a diagram illustrating the operation of the drive signal selection circuit 200 in binary mode. As in the multi-tone mode, the head control signal DI input to the drive signal selection circuit 200 is synchronized with the clock signal SCK and propagates sequentially through multiple registers included in the SP register group 262, the second registers 222b in each of the selection signal output units 270[1] to 270[n], and the first registers 222a in each of the selection signal output units 270[1] to 270[n].

[0135] Then, when the supply of the clock signal SCK stops, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, PA03 to PA00 contained in the setting information signal SP are held in multiple registers included in the SP register group 262, the lower-order ejection data SIL1 to SILn contained in the ejection control signal SI are held in the second register 222b possessed by each of the selection signal output units 270[1] to 270[n], and the upper-order ejection data SIH1 to SIHn contained in the ejection control signal SI are held in the first register 222a possessed by each of the selection signal output units 270[1] to 270[n].

[0136] Thereafter, when the latch signal LAT rises, the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, PA03 to PA00 held in the multiple registers included in the SP register group 262 are latched all at once by the selection control signal generation unit 264, the lower ejection data SIL1 to SILn held in the second register 222b of each of the selection signal output units 270[1] to 270[n] are latched all at once by the second latch circuit 224b of each of the selection signal output units 270[1] to 270[n], and the upper ejection data SIH1 to SIHn held in the first register 222a of each of the selection signal output units 270[1] to 270[n] are latched all at once by the first latch circuit 224a of each of the selection signal output units 270[1] to 270[n].

[0137] The selection control signal generation unit 264 generates setting signals Q1 to Q4 from the latched setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00, and outputs them to the decoders 226 of each of the selection signal output units 270[1] to 270[n]. In addition, the second latch circuits 224b of each of the selection signal output units 270[1] to 270[n] output the lower order ejection data SIL1 to SILn latched therein as latch data LTb1 to LTbn to the corresponding decoders 226, and the first latch circuits 224a of each of the selection signal output units 270[1] to 270[n] output the upper order ejection data SIH1 to SIHn latched therein as latch data LTa1 to LTan to the corresponding decoders 226.

[0138] That is, the decoder 226 of the selection signal output unit 270 receives the setting signal Q1 [PA00, PA01, PA02, PA03] = [0,1,0,1], setting signal Q2 [PA10, PA11, PA12, PA13] = [1,0,1,0], setting signal Q3 [PA20, PA21, PA22, PA23] = [0,0,0,0], and setting signal Q4 [PA30, PA31, PA32, PA33] = [0,0,0,0] output by the selection control signal generation unit 264, as well as the latch data [LTa, LTb] output by the first latch circuit 224a and the second latch circuit 224b of the selection signal output unit 270.

[0139] The decoder 226 included in the selection signal output unit 270 decodes the input latch data [LTa, LTb] as shown in Fig. 16. As a result, the decoder 226 included in the selection signal output unit 270 outputs a selection signal S of a predetermined logic level according to the logic level of the input latch data [LTa, LTb] and the setting signals Q1 to Q4.

[0140] Specifically, when the ejection data [SIH,SIL]=[0,0], i.e., when the latch data [LTa,LTb]=[0,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a low-level selection signal S during period p1 and a low-level selection signal S during period p2. Therefore, the input and output terminals of the corresponding selection circuit 230 are controlled to be non-conductive during period p1 and conductive during period p2. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that is constant at voltage Vc during period p1 and has a trapezoidal waveform Dp42 during period p2. In this case, only the ink near the nozzle 651 of the ejection unit 600 vibrates, and no ink is ejected from the nozzle 651.

[0141] When the ejection data [SIH,SIL]=[0,1], i.e., when the latch data [LTa,LTb]=[0,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a high-level selection signal S during period p1 and a low-level selection signal S during period p2. Therefore, the input and output terminals of the corresponding selection circuit 230 are controlled to be conductive during period p1 and non-conductive during period p2. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that has a trapezoidal waveform Dp12 during period p1 and is constant at a voltage Vc during period p2. In this case, a predetermined amount of ink is ejected from the nozzle 651 of the ejection unit 600.

[0142] When the ejection data [SIH,SIL]=[1,0], i.e., when the latch data [LTa,LTb]=[1,0] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a low-level selection signal S during period p1 and a high-level selection signal S during period p2. Therefore, the input and output terminals of the corresponding selection circuit 230 are controlled to be non-conductive during period p1 and conductive during period p2. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that is constant at voltage Vc during period p1 and has a trapezoidal waveform Dp42 during period p2. In this case, only the ink near the nozzle 651 of the ejection unit 600 vibrates, and no ink is ejected from the nozzle 651.

[0143] When the ejection data [SIH,SIL]=[1,1], i.e., when the latch data [LTa,LTb]=[1,1] is input to the decoder 226 of the selection signal output unit 270, the decoder 226 of the selection signal output unit 270 outputs a high-level selection signal S during period p1 and a low-level selection signal S during period p2. Therefore, the input and output terminals of the corresponding selection circuit 230 are controlled to be conductive during period p1 and non-conductive during period p2. As a result, the drive signal selection circuit 200 outputs a drive signal VOUT that has a trapezoidal waveform Dp12 during period p1 and is constant at a voltage Vc during period p2. In this case, a predetermined amount of ink is ejected from the nozzle 651 of the ejection unit 600.

[0144] As described above, in the liquid ejection device 1 of this embodiment, when the operating mode is binary mode, the ejection unit 600 does not eject ink when the corresponding ejection data [SIH,SIL]=[0,0], ejects a predetermined amount of ink when the corresponding ejection data [SIH,SIL]=[0,1], does not eject ink when the corresponding ejection data [SIH,SIL]=[1,0], and ejects a predetermined amount of ink when the corresponding ejection data [SIH,SIL]=[1,1]. Therefore, when the ejection data [SIH,SIL]=[0,0], When the ejection data [SIH,SIL]=[1,0], no dots are formed on the medium P, and when the ejection data [SIH,SIL]=[0,1] and when the ejection data [SIH,SIL]=[1,1], dots of a size corresponding to a specified amount of ink are formed on the medium P.

[0145] As described above, when the operating mode of the liquid ejection device 1 of this embodiment is the binary mode, the latch period Plat can be made shorter than in the multi-tone mode, thereby realizing high-speed image formation on the medium P in the binary mode.

[0146] Here, in the above-described binary mode, it is conceivable to further shorten the latch period Plat from the viewpoint of further increasing the speed of image formation on the medium P. However, if the latch period Plat is further shortened, the data length of the head control signal DI may become a rate-limiting factor for the speed of image formation on the medium P, which may result in making it difficult to further increase the speed of image formation on the medium P. In particular, since the ejection control signal SI included in the head control signal DI is a signal that individually defines the amount of ink ejected from the nozzles 651 of each of the ejection units 600[1] to 600[n], as the number of nozzles in the liquid ejection device 1 increases, the data length of the ejection control signal SI also becomes longer, which may result in an increased risk that the data length of the head control signal DI may become a rate-limiting factor for the speed of image formation on the medium P.

[0147] To address this problem, in the liquid ejection device 1 of this embodiment, the setting information signal SP in binary mode includes setting data PA00, PA01, PA02, PA03 corresponding to setting signal Q1, and setting data PA10, PA11, PA12, PA13 corresponding to setting signal Q2, which is the inverted bit data of setting signal Q1, thereby reducing the risk that the data length of the head control signal DI will become a rate limiting factor, and making it possible to further increase the speed of image formation on medium P.

[0148] Specifically, in the liquid ejection device 1 of this embodiment, the setting information signal SP in the binary mode includes setting data PA00, PA01, PA02, PA03 corresponding to the setting signal Q1, and setting data PA10, PA11, PA12, PA13 corresponding to the setting signal Q2 in which the bit data of the setting signal Q1 is inverted. As a result, the decoder 226 outputs a selection signal S of the same logical level in both periods p1 and p2 when latch data [LTa,LTb]=[0,0] is input and when latch data [LTa,LTb]=[1,0] is input, as shown in FIG. 16, and outputs a selection signal S of the same logical level in both periods p1 and p2 when latch data [LTa,LTb]=[0,1] is input and when latch data [LTa,LTb]=[1,1] is input. That is, when the liquid ejection device 1 of this embodiment is in binary mode, the decoder 226 outputs a selection signal S of a predetermined logic level based only on the logic level of the lower-order ejection data SIL.

[0149] In other words, the logical level of the upper ejection data SIH does not contribute to the logical level of the selection signal S output by the decoder 226, and therefore the head control signal DI in the binary mode does not need to include the upper ejection data SIH1 to SIHn. Figure 18 is a diagram showing an example of the data configuration of the head control signal DI for achieving even faster image formation on the medium P in the binary mode.

[0150] As shown in Figure 18, the ejection control signal SI included in the head control signal DI for achieving further increases in image formation speed in binary mode is an n-bit signal that includes lower order ejection data SIL1 corresponding to ejection section 600[1], lower order ejection data SIL2 corresponding to ejection section 600[2], ..., lower order ejection data SILn-1 corresponding to ejection section 600[n-1], and lower order ejection data SILn corresponding to ejection section 600[n], in the order of lower order ejection data SILn, SILn-1, ..., SIL2, SIL1.

[0151] When such a head control signal DI is input to the drive signal selection circuit 200, the head control signal DI is propagated in synchronization with the clock signal SCK through the SP register group 262 and the n second registers 222b included in each of the selection signal output units 270[1] to 270[n] in that order. As a result, when the supply of the clock signal SCK stops, the SP register group 262 holds the setting data PA33 to PA30, PA23 to PA20, PA13 to PA10, and PA03 to PA00 included in the setting information signal SP of the head control signal DI, the second register 222b included in the selection signal output unit 270 holds the lower-order ejection data SIL corresponding to the ejection unit 600, and the first register 222a included in the selection signal output unit 270 holds an indefinite value.

[0152] Thereafter, when the latch signal LAT rises, the decoder 226 of the selection signal output unit 270 receives the setting signals Q1 to Q4 output by the selection control signal generation unit 264, the latch data LTa whose logical level is indefinite, and LTb corresponding to the lower ejection data SIL.

[0153] In this case, in the liquid ejection device 1 of this embodiment, in binary mode, the decoder 226 of the selection signal output unit 270 can output a selection signal S of a predetermined logic level based only on the logic level of the lower-order ejection data SIL. Therefore, even when latch data LTa with an indefinite logic level is input to the decoder 226 of the selection signal output unit 270, the decoder 226 can output a selection signal S of the same logic level as when the head control signal DI shown in FIG. 15 is input. That is, in both cases when the head control signal DI shown in FIG. 15 is input to the drive signal selection circuit 200 and when the head control signal DI shown in FIG. 18 is input to the drive signal selection circuit 200, the selection control circuit 210 outputs a selection signal S of the same logic level to each of the selection circuits 230[1] to 230[n]. As a result, each of the selection circuits 230[1] to 230[n] outputs the same drive signal VOUT[1] to VOUT[n] to the corresponding ejection units 600[1] to 600[n]. This reduces the risk that the data length of the head control signal DI will become a rate limiting factor, and as a result, it becomes possible to further increase the speed at which images are formed on the medium P in the binary mode.

[0154] In other words, the data size of the setting information signal SP in the binary mode is equal to the data size of the setting information signal SP in the multi-tone mode, and by making the data size of the ejection control signal SI in the binary mode smaller than the data size of the ejection control signal SI in the multi-tone mode, the risk of the data length of the head control signal DI becoming rate-limiting is reduced, making it possible to further increase the speed of image formation on the medium P.

[0155] 5 Operation of the temperature detection circuit and comparison circuit and timing for determining abnormal temperature Next, the detection of the temperature of the drive signal output circuit 52 by the temperature detection circuit 72 and the operation of the comparison circuit 70 based on the temperature detection result by the temperature detection circuit 72 will be described. In the following description, one end of the liquid ejection device 1 along the main scanning direction will sometimes be referred to as one end, and the other end of the liquid ejection device 1 along the main scanning direction will sometimes be referred to as the other end. The direction from one end of the liquid ejection device 1 to the other end will sometimes be referred to as the forward direction, and the direction from the other end of the liquid ejection device 1 to one end will sometimes be referred to as the reverse direction.

[0156] First, the operation of the liquid ejector 1 when the temperature of the drive signal output circuit 52 is normal will be described with reference to Fig. 19. Fig. 19 is a diagram for explaining the operation of the liquid ejector 1 when the temperature of the drive signal output circuit 52 is normal.

[0157] 19, at time t0, image data and the like are input to a control circuit 100 of the liquid ejection device 1. The control circuit 100 executes image conversion processing to generate various signals from the input image data for forming an image corresponding to the image data on a medium P.

[0158] Thereafter, at time t1, the control circuit 100 outputs a forward control signal Fw as a control signal Ctrl-C for moving the carriage 20 forward in the main scanning direction. This causes the carriage 20 to move forward in the main scanning direction. As the carriage 20 moves, the linear encoder 90 generates a position information signal Cp and outputs it to the control circuit 100. Then, based on the input position information signal Cp, the control circuit 100 generates a latch signal LAT, a change signal CH, a clock signal SCK, and a head control signal DI and outputs them to the ejection head 21.

[0159] Also, at time t1, the control circuit 100 outputs a basic drive signal dA to the drive signal output circuit 52. The drive signal output circuit 52 generates a drive signal COM including a signal waveform corresponding to the input basic drive signal dA and outputs it to the ejection head 21. At this time, the drive signal output circuit 52 generates the drive signal COM and outputs it to the ejection head 21, causing the temperature of the drive signal output circuit 52 to rise. The temperature detection circuit 72 detects the temperature of the drive signal output circuit 52 as a detected temperature Tmp, generates a temperature information signal Stmp including the detected temperature Tmp, and outputs it to the comparison circuit 70.

[0160] At this time, the temperature threshold signal Sth including the threshold temperature Tth and the enable signal EN of L level indicating invalidity are input to the comparator circuit 70. Therefore, the comparator circuit 70 does not compare the threshold temperature Tth with the detected temperature Tmp, and outputs the temperature determination signal Res of L level indicating that the temperature of the drive signal output circuit 52 is normal.

[0161] Furthermore, from the viewpoint of reducing the temperature rise of the drive signal output circuit 52, the power supply circuit 80 outputs the cooling power Pcl of the voltage signal Vcl1 to the cooling mechanism 82. The cooling mechanism 82 starts cooling the drive signal output circuit 52 with a cooling capacity that corresponds to the amount of cooling power Pcl supplied and the voltage value of the voltage signal Vcl1.

[0162] Then, at time t2 when the carriage 20 reaches the other end of the liquid ejection device 1, the control circuit 100 outputs a stop control signal St as a control signal Ctrl-C for stopping the movement of the carriage 20 in the main scanning direction. This causes the carriage 20 to stop at the other end of the liquid ejection device 1. As the carriage 20 stops, the linear encoder 90 stops generating the position information signal Cp, and the control circuit 100 stops generating the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI.

[0163] Furthermore, at time t2, the control circuit 100 outputs a basic drive signal dA that causes the drive signal output circuit 52 to output a drive signal COM having a constant voltage value of Vc. This causes the drive signal output circuit 52 to generate a drive signal COM having a constant voltage value of Vc and output it to the ejection head 21.

[0164] In this case, since the control circuit 100 stops generating the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI, the transfer gate TG included in the selection circuit 230 of the drive signal selection circuit 200 is controlled to be non-conductive. Therefore, the drive signal COM is not supplied to the electrode 611 of the piezoelectric element 60 of the ejection section 600. This reduces the power consumption of the drive signal output circuit 52, and as a result, the temperature of the drive signal output circuit 52 drops. The temperature detection circuit 72 detects the temperature of the drive signal output circuit 52 as a detected temperature Tmp, generates a temperature information signal Stmp including the detected temperature Tmp, and The drive signal output circuit 52 outputs a temperature determination signal Res at an L level indicating that the temperature of the drive signal output circuit 52 is normal. At this time, the comparator circuit 70 receives a temperature threshold signal Sth including the threshold temperature Tth and an enable signal EN at an H level indicating that the temperature is valid. Therefore, the comparator circuit 70 compares the threshold temperature Tth with the detected temperature Tmp, and if the detected temperature Tmp is lower than the threshold temperature Tth, the comparator circuit 70 outputs a temperature determination signal Res at an L level indicating that the temperature of the drive signal output circuit 52 is normal.

[0165] At time t3, a predetermined period of time after the carriage 20 has stopped at the other end of the liquid ejection device 1, the control circuit 100 outputs a reverse direction control signal Rv as a control signal Ctrl-C for moving the carriage 20 in the reverse direction along the main scanning direction. This causes the carriage 20 to move in the reverse direction along the main scanning direction. As the carriage 20 moves, the linear encoder 90 generates a position information signal Cp and outputs it to the control circuit 100. Then, based on the input position information signal Cp, the control circuit 100 generates a latch signal LAT, a change signal CH, a clock signal SCK, and a head control signal DI and outputs them to the ejection head 21.

[0166] Also, at time t3, the control circuit 100 outputs a basic drive signal dA to the drive signal output circuit 52. The drive signal output circuit 52 generates a drive signal COM including a signal waveform corresponding to the input basic drive signal dA and outputs it to the ejection head 21. At this time, because the drive signal output circuit 52 generates the drive signal COM and outputs it to the ejection head 21, the temperature of the drive signal output circuit 52 rises again. The temperature detection circuit 72 detects the temperature of the drive signal output circuit 52 as a detected temperature Tmp, generates a temperature information signal Stmp including the detected temperature Tmp, and outputs it to the comparison circuit 70. At this time, the comparison circuit 70 receives a temperature threshold signal Sth including the threshold temperature Tth and an enable signal EN at an L level indicating invalidity. Therefore, the comparison circuit 70 does not compare the threshold temperature Tth with the detected temperature Tmp, and outputs a temperature determination signal Res at an L level indicating that the temperature of the drive signal output circuit 52 is normal.

[0167] Then, at time t4 when the carriage 20 reaches one end of the liquid ejection device 1, the control circuit 100 outputs a stop control signal St as a control signal Ctrl-C for stopping the movement of the carriage 20 in the main scanning direction. In other words, the carriage 20 stops at one end of the liquid ejection device 1. As the carriage 20 stops, the linear encoder 90 stops generating the position information signal Cp, and the control circuit 100 stops generating the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI.

[0168] Furthermore, at time t4, the control circuit 100 outputs a basic drive signal dA that causes the drive signal output circuit 52 to output a drive signal COM having a constant voltage value of Vc. This causes the drive signal output circuit 52 to generate a drive signal COM having a constant voltage value of Vc and output it to the ejection head 21.

[0169] In this case, because the control circuit 100 stops generating the latch signal LAT, change signal CH, clock signal SCK, and head control signal DI, the transfer gate TG included in the selection circuit 230 of the drive signal selection circuit 200 is controlled to be non-conductive. Therefore, the drive signal COM is not supplied to the electrode 611 of the piezoelectric element 60 of the ejection portion 600. This reduces the power consumption of the drive signal output circuit 52, resulting in a drop in the temperature of the drive signal output circuit 52. The temperature detection circuit 72 detects the temperature of the drive signal output circuit 52 as a detected temperature Tmp, generates a temperature information signal Stmp including the detected temperature Tmp, and outputs it to the comparison circuit 70. At this time, the comparison circuit 70 receives a temperature threshold signal Sth including a threshold temperature Tth and an enable signal EN at an H level indicating validity. Therefore, the comparison circuit 70 compares the threshold temperature Tth with the detected temperature Tmp, and if the detected temperature Tmp is lower than the threshold temperature Tth, it outputs an L-level temperature determination signal Res indicating that the temperature of the drive signal output circuit 52 is normal.

[0170] At time t5, a predetermined period after the carriage 20 has stopped at one end of the liquid ejection device 1, the control circuit 100 outputs a forward direction control signal Fw as a control signal Ctrl-C for moving the carriage 20 forward along the main scanning direction. The control circuit 100 then executes the same operation as at time t1 described above. That is, time t5 corresponds to the time t1 described above, and from time t5 onwards, the liquid ejection device 1 repeatedly executes the same operations as from time t1 to time t4 described above. This makes it possible to eject ink onto the entire area of ​​the medium P being transported along the transport direction, forming a desired image on the medium P.

[0171] That is, from time t1 to time t2 and from time t3 to time t4, the liquid ejection device 1 moves the carriage 20 in the main scanning direction, and the ejection head 21 ejects ink onto the medium P. As a result, from time t1 to time t2 and from time t3 to time t4, the liquid ejection device 1 forms an image on the medium P. The periods from time t1 to time t2 and from time t3 to time t4, during which the liquid ejection device 1 forms an image on the medium P, may be referred to as an image formation period Pimg.

[0172] Furthermore, the liquid ejection device 1 switches the movement direction of the carriage 20 from forward to reverse between times t2 and t3, and switches the movement direction of the carriage 20 from reverse to forward between times t4 and t5. At this time, the carriage 20 stops and the ejection head 21 does not eject ink onto the medium P. In other words, the liquid ejection device 1 does not form an image on the medium P between times t2 and t3 and between times t4 and t5. The periods between times t2 and t3 and between times t4 and t1 during which the liquid ejection device 1 does not form an image on the medium P may be referred to as stop periods Ps.

[0173] The control circuit 100 outputs an H-level enable signal EN to the comparison circuit 70 during the image formation period Pimg, and outputs an H-level enable signal EN to the comparison circuit 70 during the stop period Ps. That is, the comparison circuit 70 compares the threshold temperature Tth with the detection temperature Tmp during the stop period Ps, but does not compare the threshold temperature Tth with the detection temperature Tmp during the image formation period Pimg. In other words, the comparison circuit 70 determines whether the temperature of the drive signal output circuit 52 is normal during the stop period Ps, but does not determine whether the temperature of the drive signal output circuit 52 is normal during the image formation period Pimg. This reduces the risk that noise that may be generated by the operation of the comparison circuit 70 will contribute to the printing process while the liquid ejection device 1 is performing the printing process, improving the quality of the image formed on the medium P and reducing the power consumption of the liquid ejection device 1 during the printing process.

[0174] Next, the operation of the liquid ejection device 1 when the temperature of the drive signal output circuit 52 is not normal will be described with reference to Fig. 20. Fig. 20 is a diagram for explaining the operation of the liquid ejection device 1 when the temperature of the drive signal output circuit 52 is not normal.

[0175] 20, at time t11, the control circuit 100 outputs a forward control signal Fw as a control signal Ctrl-C for moving the carriage 20 forward in the main scanning direction. This causes the carriage 20 to move forward in the main scanning direction, and the linear encoder 90 outputs a position information signal Cp. Then, based on the position information signal Cp, the control circuit 100 generates a latch signal LAT, a change signal CH, a clock signal SCK, and a head control signal DI, and outputs them to the ejection head 21.

[0176] Furthermore, at time t11, the control circuit 100 outputs the basic drive signal dA to the drive signal output circuit 52. This causes the drive signal output circuit 52 to generate a drive signal COM according to the input basic drive signal dA and output it to the ejection head 21. The drive signal output circuit 52 generates the drive signal COM and outputs it to the ejection head 21, causing the temperature of the drive signal output circuit 52 to rise. At this time, the temperature of the drive signal output circuit 52 becomes higher than when it is normal.

[0177] The temperature detection circuit 72 detects the temperature of the drive signal output circuit 52 as a detected temperature Tmp, generates a temperature information signal Stmp including the detected temperature Tmp, and outputs it to the comparison circuit 70. At this time, the comparison circuit 70 receives a temperature threshold signal Sth including the threshold temperature Tth and an enable signal EN at an L level indicating invalidity. Therefore, the comparison circuit 70 does not compare the threshold temperature Tth with the detected temperature Tmp, and outputs a temperature determination signal Res at an L level indicating that the temperature of the drive signal output circuit 52 is normal. Furthermore, because the enable signal EN at an L level indicating invalidity is received by the comparison circuit 70, the comparison circuit 70 continues to output a temperature determination signal Res at an L level indicating that the temperature of the drive signal output circuit 52 is normal, even if the detected temperature Tmp input to the comparison circuit 70 exceeds the threshold temperature Tth, as shown at time t12.

[0178] Then, at time t13 when the carriage 20 reaches the other end of the liquid ejection device 1, the control circuit 100 outputs a stop control signal St as a control signal Ctrl-C for stopping the movement of the carriage 20 in the main scanning direction. This causes the carriage 20 to stop at the other end of the liquid ejection device 1. As the carriage 20 stops, the linear encoder 90 stops generating the position information signal Cp, and the control circuit 100 stops generating the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI.

[0179] Also, at time t13, the control circuit 100 outputs a basic drive signal dA that causes the drive signal output circuit 52 to output a drive signal COM with a constant voltage value of Vc. This causes the drive signal output circuit 52 to generate a drive signal COM with a constant voltage value of Vc and output it to the ejection head 21. In this case, the control circuit 100 stops generating the latch signal LAT, change signal CH, clock signal SCK, and head control signal DI. Therefore, the transfer gate TG included in the selection circuit 230 of the drive signal selection circuit 200 is controlled to be non-conductive. Therefore, the drive signal COM is not supplied to the electrode 611 of the piezoelectric element 60 of the ejection section 600.

[0180] At this time, the comparator circuit 70 receives a temperature threshold signal Sth including the threshold temperature Tth and an enable signal EN at an H level indicating validity. Therefore, the comparator circuit 70 compares the threshold temperature Tth with the detected temperature Tmp. Because the detected temperature Tmp is greater than the threshold temperature Tth, the comparator circuit 70 outputs an H-level temperature determination signal Res indicating that the temperature of the drive signal output circuit 52 is abnormal. At this time, the power supply circuit 80 outputs cooling power Pcl to the cooling mechanism 82, the voltage signal Vcl2 having a greater voltage value than the voltage signal Vcl1. That is, the cooling mechanism 82 cools the drive signal output circuit 52 with a higher cooling capacity. In other words, if the detected temperature Tmp, which indicates the temperature of the drive signal output circuit 52 detected by the temperature detection circuit 72, is greater than the threshold temperature Tth, the power supply circuit 80 increases the amount of cooling power Pcl supplied to the cooling mechanism 82. This increases the cooling efficiency of the drive signal output circuit 52 experiencing a temperature abnormality.

[0181] Here, at time t13, the control circuit 100 stops generating the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI, so the transfer gate TG included in the selection circuit 230 of the drive signal selection circuit 200 is controlled to be non-conductive. Therefore, the drive signal COM is not supplied to the electrode 611 of the piezoelectric element 60 of the ejection portion 600. This reduces the power consumption of the drive signal output circuit 52, and as a result, the temperature of the drive signal output circuit 52 drops.

[0182] When the threshold temperature Tth included in the input temperature information signal Stmp falls below the threshold temperature Tth as the temperature of the drive signal output circuit 52 decreases, the comparison circuit 70 outputs an L-level temperature determination signal Res indicating that the temperature of the drive signal output circuit 52 is normal.

[0183] At this time, the power supply circuit 80 outputs the cooling power Pcl of the voltage signal Vcl1 to the cooling mechanism 82. This reduces the power consumption by the cooling mechanism 82.

[0184] At time t14, a predetermined period after the carriage 20 stops at the other end of the liquid ejection device 1, if the comparison circuit 70 outputs a low-level temperature determination signal Res, indicating that the temperature of the drive signal output circuit 52 is normal, the control circuit 100 outputs a reverse direction control signal Rv as the control signal Ctrl-C for moving the carriage 20 in the reverse direction along the main scanning direction. This causes the carriage 20 to move in the reverse direction along the main scanning direction. As the carriage 20 moves, the linear encoder 90 generates a position information signal Cp and outputs it to the control circuit 100. Based on the input position information signal Cp, the control circuit 100 generates a latch signal LAT, a change signal CH, a clock signal SCK, and a head control signal DI and outputs them to the ejection head 21.

[0185] Also, at time t14, the control circuit 100 outputs a basic drive signal dA to the drive signal output circuit 52. The drive signal output circuit 52 generates a drive signal COM including a signal waveform corresponding to the input basic drive signal dA and outputs it to the ejection head 21. At this time, because the drive signal output circuit 52 generates the drive signal COM and outputs it to the ejection head 21, the temperature of the drive signal output circuit 52 rises again. The temperature detection circuit 72 detects the temperature of the drive signal output circuit 52 as a detected temperature Tmp, generates a temperature information signal Stmp including the detected temperature Tmp, and outputs it to the comparison circuit 70. At this time, the comparison circuit 70 receives a temperature threshold signal Sth including the threshold temperature Tth and an enable signal EN at an L level indicating invalidity. Therefore, the comparison circuit 70 does not compare the threshold temperature Tth with the detected temperature Tmp, and outputs a temperature determination signal Res at an L level indicating that the temperature of the drive signal output circuit 52 is normal, regardless of the detected temperature Tmp.

[0186] Then, at time t15 when the carriage 20 reaches one end of the liquid ejection device 1, the control circuit 100 outputs a stop control signal St as a control signal Ctrl-C for stopping the movement of the carriage 20 in the main scanning direction. In other words, the carriage 20 stops at the other end of the liquid ejection device 1. As the carriage 20 stops, the linear encoder 90 stops generating the position information signal Cp, and the control circuit 100 stops generating the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI.

[0187] Also, at time t15, the control circuit 100 outputs a basic drive signal dA that causes the drive signal output circuit 52 to output a drive signal COM with a constant voltage value of Vc. This causes the drive signal output circuit 52 to generate a drive signal COM with a constant voltage value of Vc and output it to the ejection head 21. In this case, the control circuit 100 stops generating the latch signal LAT, change signal CH, clock signal SCK, and head control signal DI. Therefore, the transfer gate TG included in the selection circuit 230 of the drive signal selection circuit 200 is controlled to be non-conductive. Therefore, the drive signal COM is not supplied to the electrode 611 of the piezoelectric element 60 of the ejection section 600.

[0188] At this time, the comparator circuit 70 receives a temperature threshold signal Sth including the threshold temperature Tth and an enable signal EN at an H level indicating validity. Therefore, the comparator circuit 70 compares the threshold temperature Tth with the detected temperature Tmp. Because the detected temperature Tmp is greater than the threshold temperature Tth, the comparator circuit 70 outputs an H-level temperature determination signal Res indicating that the temperature of the drive signal output circuit 52 is abnormal. At this time, the power supply circuit 80 outputs cooling power Pcl to the cooling mechanism 82, the voltage signal Vcl2 having a greater voltage value than the voltage signal Vcl1. That is, the cooling mechanism 82 cools the drive signal output circuit 52 with a higher cooling capacity. In other words, if the detected temperature Tmp, which indicates the temperature of the drive signal output circuit 52 detected by the temperature detection circuit 72, is greater than the threshold temperature Tth, the power supply circuit 80 increases the amount of cooling power Pcl supplied to the cooling mechanism 82. This increases the cooling efficiency of the drive signal output circuit 52 experiencing a temperature abnormality.

[0189] Furthermore, at time t15, the control circuit 100 stops generating the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI, so the transfer gate TG included in the selection circuit 230 of the drive signal selection circuit 200 is controlled to be non-conductive. Therefore, the drive signal COM is not supplied to the electrode 611 of the piezoelectric element 60 of the ejection section 600. This reduces the power consumption of the drive signal output circuit 52, and as a result, the temperature of the drive signal output circuit 52 drops.

[0190] At time t16, a predetermined period after the carriage 20 has stopped at one end of the liquid ejection device 1, if the comparison circuit 70 outputs an H-level temperature determination signal Res indicating that the temperature of the drive signal output circuit 52 is not normal, the control circuit 100 stops the output of the drive signal output circuit 52. Here, stopping the output of the drive signal output circuit 52 may mean, for example, that the control circuit 100 generates a basic drive signal dA corresponding to the drive signal COM at ground potential and supplies it to the drive signal output circuit 52, or that the control circuit 100 stops outputting the basic drive signal dA to the drive signal output circuit 52. In other words, if the detected temperature Tmp, which indicates the detection result of the temperature of the drive signal output circuit 52 detected by the temperature detection circuit 72, is greater than the threshold temperature Tth, the drive signal output circuit 52 stops outputting the drive signal COM.

[0191] Furthermore, at time t16, if the comparison circuit 70 outputs an H-level temperature determination signal Res indicating that the temperature of the drive signal output circuit 52 is not normal, the control circuit 100 may continue to output the stop control signal St as the control signal Ctrl-C for stopping the movement of the carriage 20 in the main scanning direction, and may continue to stop the generation of the latch signal LAT, the change signal CH, the clock signal SCK, and the head control signal DI. In other words, if the detected temperature Tmp indicating the detection result of the temperature of the drive signal output circuit 52 detected by the temperature detection circuit 72 is higher than the threshold temperature Tth, the liquid ejection device 1 may stop image formation on the medium P.

[0192] Then, at a subsequent time t17, the temperature of the drive signal output circuit 52 drops, and the comparison circuit 70 outputs an L-level temperature determination signal Res, indicating that the temperature of the drive signal output circuit 52 is normal. At this time, the control circuit 100 may continue to stop the operation of each part of the liquid ejection device 1, including the drive signal output circuit 52, or may start the operation of each part of the liquid ejection device 1, including the drive signal output circuit 52, a predetermined time after time t17. Furthermore, the control circuit 100 may start the operation of each part of the liquid ejection device 1, including the drive signal output circuit 52, a predetermined time after the L-level temperature determination signal Res is input, and then, when an H-level temperature determination signal Res is input again, continue to stop the operation of each part of the liquid ejection device 1, including the drive signal output circuit 52.

[0193] As described above, in the liquid ejection device 1 of this embodiment, the comparison circuit 70 does not compare the threshold temperature Tth with the detected temperature Tmp during the image formation period Pimg, but instead compares the threshold temperature Tth with the detected temperature Tmp during the halt period Ps, thereby reducing the power consumption of the liquid ejection device 1. Therefore, when comparing the threshold temperature Tth with the detected temperature Tmp during the halt period Ps, the liquid ejection device 1 estimates the temperature rise of the drive signal output circuit 52 during the image formation period Pimg and determines whether the temperature of the drive signal output circuit 52 is normal. Therefore, the threshold temperature Tth for determining whether the temperature of the drive signal output circuit 52 is normal is set so that it does not reach the maximum threshold temperature Tch, at which the risk of the drive signal output circuit 52 malfunctioning increases, even if the temperature of the drive signal output circuit 52 rises during the image formation period Pimg.

[0194] However, the driving state of the liquid ejector 1 as shown in this embodiment differs between the multi-tone mode, which is intended to form a high-quality image on the medium P, and the binary mode, which is intended to form an image on the medium P at high speed. Therefore, the temperature rise value of the drive signal output circuit 52 during the image formation period Pimg also differs between the multi-tone mode and the binary mode. Therefore, if the threshold temperature Tth is set based on the temperature rise value of the drive signal output circuit 52 that occurs in an operation mode with a small temperature rise during the image formation period Pimg, the temperature of the drive signal output circuit 52 may reach the maximum threshold temperature Tch when the liquid ejector 1 operates in an operation mode with a large temperature rise. On the other hand, if the threshold temperature Tth is set based on the temperature rise value of the drive signal output circuit 52 that occurs in an operation mode with a large temperature rise during the image formation period Pimg, the temperature of the drive signal output circuit 52 may be excessively low relative to the maximum threshold temperature Tch when the liquid ejector 1 operates in an operation mode with a small temperature rise, resulting in an over-specified liquid ejector 1.

[0195] The liquid ejection device 1 of this embodiment has a characteristic configuration that reduces the risk of such problems occurring. In explaining this characteristic configuration, we will first explain the difference in temperature rise of the drive signal output circuit 52 in multi-tone mode and binary mode. Figure 21 is a diagram that schematically shows a comparison between the temperature rise value of the drive signal output circuit 52 in binary mode and the temperature rise value of the drive signal output circuit 52 in multi-tone mode. Note that Figure 21(1) illustrates the "temperature rise value of the drive signal output circuit 52 in binary mode," and Figure 21(2) illustrates the "temperature rise value of the drive signal output circuit 52 in multi-tone mode."

[0196] 21(1), when the liquid ejector 1 is driven in binary mode, the temperature rise value of the drive signal output circuit 52 during the image formation period Pimg is a rise temperature Tbin, while when the liquid ejector 1 is driven in multi-tone mode, the temperature rise value of the drive signal output circuit 52 during the image formation period Pimg is a rise temperature Tmg which is smaller than the rise temperature Tbin. In other words, the temperature rise value during the image formation period Pimg when the liquid ejector 1 is driven in binary mode is greater than the temperature rise value during the image formation period Pimg when the liquid ejector 1 is driven in multi-tone mode.

[0197] In binary mode, the latch period Plat is shorter than in multi-tone mode, from the perspective of increasing the speed at which dots are formed on the medium P. Therefore, the frequency of the drive signal COM is also shorter, and the amount of current per unit time generated in conjunction with the propagation of the drive signal COM output by the drive signal output circuit 52 in binary mode is greater than the amount of current per unit time generated in conjunction with the propagation of the drive signal COM output by the drive signal output circuit 52 in multi-tone mode. As a result, as shown in FIG. 21 , the rise in temperature Tbin, which is the temperature rise during the image formation period Pimg when the liquid ejector 1 is operating in binary mode, is greater than the rise in temperature Tmg, which is the temperature rise during the image formation period Pimg when the liquid ejector 1 is operating in multi-tone mode.

[0198] Therefore, in the liquid ejection device 1 of this embodiment, the control circuit 100 uses the power control signal Spsy to perform control so that the amount of cooling power Pcl supplied by the power supply circuit 80 to the cooling mechanism 82 in the binary mode is greater than the amount of cooling power Pcl supplied by the power supply circuit 80 to the cooling mechanism 82 in the multi-gradation mode. In other words, the liquid ejection device 1 of this embodiment has a configuration in which the amount of power supplied by the power supply circuit 80 to the cooling mechanism 82 in the binary mode is greater than the amount of power supplied by the power supply circuit 80 to the cooling mechanism 82 in the multi-gradation mode.

[0199] 22 is a diagram schematically illustrating the relationship between the cooling power Pcl supplied to the cooling mechanism 82 by the power supply circuit 80, and the temperature rise value of the drive signal output circuit 52 in the binary mode and the temperature rise value of the drive signal output circuit 52 in the multi-gradation mode. Note that Fig. 22(1) illustrates the "relationship between the cooling power Pcl and the temperature rise value of the drive signal output circuit 52 in the binary mode," and Fig. 22(2) illustrates the "relationship between the cooling power Pcl and the temperature rise value of the drive signal output circuit 52 in the multi-gradation mode."

[0200] As shown in Figure 22, when the liquid ejection device 1 is operating in binary mode, the control circuit 100 outputs a power control signal Spsy to the power supply circuit 80, which sets the voltage value of the voltage signal Vcl1 of the cooling power Pcl output by the power supply circuit 80 to voltage Vcl1-1, and when the liquid ejection device 1 is operating in multi-tone mode, the control circuit 100 outputs a power control signal Spsy to the power supply circuit 80, which sets the voltage value of the voltage signal Vcl1 of the cooling power Pcl output by the power supply circuit 80 to voltage Vcl1-2, which is smaller than voltage Vcl1-1.

[0201] This makes the cooling capacity of the cooling mechanism 82 for the drive signal output circuit 52 in the binary mode higher than the cooling capacity of the cooling mechanism 82 for the drive signal output circuit 52 in the multi-gradation mode, and as a result, the temperature rise value of the drive signal output circuit 52 can be reduced in the binary mode.

[0202] Specifically, the rise temperature Tbin, which is the temperature rise value during the image formation period Pimg when the liquid ejector 1 is driven in binary mode, drops from rise temperature Tbin1 to rise temperature Tbin2. This makes it possible to reduce the temperature difference between the rise temperature Tbin, which is the temperature rise value during the image formation period Pimg when the liquid ejector 1 is driven in binary mode, and the rise temperature Tmg, which is the temperature rise value during the image formation period Pimg when the liquid ejector 1 is driven in multi-tone mode.

[0203] As a result, when the liquid ejection device 1 is operating in a multi-tone mode with a small temperature rise, if the threshold temperature Tth is set based on the temperature rise Tmg of the drive signal output circuit 52 during the image formation period Pimg, even when the liquid ejection device 1 is operating in a binary mode with a large temperature rise, the risk of the temperature of the drive signal output circuit 52 reaching the maximum threshold temperature Tch is reduced because the temperature difference between the temperature rise Tbin and the temperature rise Tmg is small.

[0204] Furthermore, when the liquid ejection device 1 is operating in a binary mode with a large temperature rise, if the threshold temperature Tth is set based on the temperature rise Tbin of the drive signal output circuit 52 during the image formation period Pimg, even when the liquid ejection device 1 is operating in a multi-tone mode with a small temperature rise, the temperature difference between the temperature rise Tbin and the temperature rise Tmg is small, which reduces the risk that the temperature of the drive signal output circuit 52 will become excessively low compared to the maximum threshold temperature Tch.

[0205] Here, when the liquid ejection device 1 is operating in binary mode, the control circuit 100 outputs a power control signal Spsy to the power supply circuit 80, which sets the voltage value of the voltage signal Vcl2 of the cooling power Pcl output by the power supply circuit 80 to voltage Vcl2-1, and when the liquid ejection device 1 is operating in multi-tone mode, the control circuit 100 may output a power control signal Spsy to the power supply circuit 80, which sets the voltage value of the voltage signal Vcl2 of the cooling power Pcl output by the power supply circuit 80 to voltage Vcl2-2, which is smaller than voltage Vcl2-1.

[0206] Furthermore, in the liquid ejection device 1 of this embodiment, the control circuit 100 is configured so that the threshold temperature Tth included in the temperature threshold signal Sth input to the comparison circuit 70 in the binary mode is lower than the threshold temperature Tth included in the temperature threshold signal Sth input to the comparison circuit 70 in the multi-tone mode. In other words, the liquid ejection device 1 of this embodiment is configured so that the threshold temperature Tth1 in the binary mode is lower than the threshold temperature Tth2 in the multi-tone mode.

[0207] Fig. 23 is a diagram showing an example of a threshold temperature Tth1 suitable for the binary mode and a threshold temperature Tth2 suitable for the multi-tone mode. In Fig. 23, Fig. 23(1) shows the "threshold temperature Tth1 suitable for the binary mode" and Fig. 23(2) shows the "threshold temperature Tth2 suitable for the multi-tone mode."

[0208] As shown in Figure 23, among the threshold temperatures Tth, the threshold temperature Tth1 suitable for binary mode can be determined by subtracting the increased temperature Tbin2, which is the temperature increase value of the drive signal output circuit 52 that occurs during the image formation period Pimg when the liquid ejection device 1 is operating in binary mode, from the maximum set temperature Tlim, which is the maximum threshold temperature Tch at which the risk of failure in the drive signal output circuit 52 increases with a certain margin added.

[0209] Furthermore, among the threshold temperatures Tth, the threshold temperature Tth2 suitable for the multi-tone mode can be determined by subtracting the increased temperature Tmg, which is the temperature increase value of the drive signal output circuit 52 that occurs during the image formation period Pimg when the liquid ejection device 1 is operating in the multi-tone mode, from the maximum set temperature Tlim, which is the maximum threshold temperature Tch at which the risk of failure in the drive signal output circuit 52 increases with a certain margin added.

[0210] At this time, as described above, the rising temperature Tbin2 is greater than the rising temperature Tmg. Therefore, the threshold temperature Tth1 suitable for the binary mode is lower than the threshold temperature Tth2 suitable for the multi-tone mode. In other words, it is preferable that the threshold temperature Tth1 in the binary mode is lower than the threshold temperature Tth2 in the multi-tone mode.

[0211] Specifically, when the liquid ejection device 1 is operating in binary mode, the control circuit 100 outputs a temperature threshold signal Sth including a threshold temperature Tth1 as the threshold temperature Tth to the comparison circuit 70, and when the liquid ejection device 1 is operating in multi-tone mode, the control circuit 100 outputs a temperature threshold signal Sth including a threshold temperature Tth2 as the threshold temperature Tth to the comparison circuit 70.

[0212] That is, the control circuit 100 switches the threshold temperature Tth included in the temperature threshold signal Sth depending on the operating mode of the liquid ejector 1. As a result, even if there is a temperature difference between the increased temperature Tbin2, which is the temperature increase value during the image formation period Pimg when the liquid ejector 1 is operating in binary mode, and the increased temperature Tmg, which is the temperature increase value during the image formation period Pimg when the liquid ejector 1 is operating in multi-tone mode, the maximum temperatures of the drive signal output circuit 52 that can occur during the image formation period Pimg can both be set to the maximum set temperature Tlim. As a result, the risk of the temperature of the drive signal output circuit 52 reaching the maximum threshold temperature Tch is reduced, and the risk of the liquid ejector 1 exceeding its specifications is also reduced.

[0213] Here, the drive signal output circuit 52 is an example of a drive signal output section, and the drive signal COM output by the drive signal output circuit 52 and the drive signal VOUT based on the drive signal COM are examples of drive signals. The cooling mechanism 82 is an example of a cooling section, and the power supply circuit 80 that supplies cooling power Pcl to the cooling mechanism 82 is an example of a power supply section. The temperature detection circuit 72 is an example of a temperature detection section, and the comparison circuit 70 that compares the detected temperature Tmp output by the temperature detection circuit 72 with the threshold temperature Tth is an example of a comparison section, and the threshold temperature Tth is an example of an abnormal temperature threshold. The wiring A that propagates the head control signal DI, which includes the setting information signal SP and the ejection control signal SI, to the drive signal selection circuit 200 is an example of a first wiring, and the wiring B that propagates the drive signal COM is an example of a second wiring.

[0214] Furthermore, the binary mode is an example of a first mode, the drive signal COM in the binary mode is an example of a first drive signal, and the frequency of the drive signal COM in the binary mode, which corresponds to a latch period Plat consisting of periods p1 and p2, is an example of a first frequency. Furthermore, the multi-tone mode is an example of a second mode, the drive signal COM in the multi-tone mode is an example of a second drive signal, and the frequency of the drive signal COM in the multi-tone mode, which corresponds to a latch period Plat consisting of periods p1 to p4, is an example of a second frequency. Furthermore, the setting information signal SP included in the head control signal DI is an example of a setting information signal group, the ejection control signal SI included in the head control signal DI is an example of an ejection control signal group, at least one of the trapezoidal waveforms Dp11, Dp21, Dp31, Dp41, Dp12, and Dp42 included in the drive signal COM is an example of a drive waveform, the setting signal Q1 included in the setting information signal SP is an example of first setting information, and the setting signal Q2 is an example of second setting information.

[0215] 6. Action and Effects As described above, the liquid ejection device 1 in this embodiment includes a binary mode in which the drive signal output circuit 52 outputs to the ejection section 600 a drive signal COM having a frequency based on the latch cycle Plat including two periods p1 to p2, and a multi-tone mode in which the drive signal output circuit 52 outputs to the ejection section 600 a drive signal COM having a frequency based on the latch cycle Plat including four periods p1 to p4, which is lower than the frequency of the drive signal COM in the binary mode, and the binary mode enables high-speed image formation on the medium P, while the multi-tone mode enables high-resolution image formation on the medium P. In this liquid ejection device 1, because the operating modes are different, the temperature rise value generated in the drive signal output circuit 52 differs between the binary mode and the multi-tone mode. Therefore, if the threshold temperature Tth is set based on the temperature rise value of the drive signal output circuit 52 that occurs in an operating mode with a small temperature rise during the image formation period Pimg, there is a risk that the temperature of the drive signal output circuit 52 will reach the maximum threshold temperature Tch when operating in an operating mode with a large temperature rise.On the other hand, if the threshold temperature Tth is set based on the temperature rise value of the drive signal output circuit 52 that occurs in an operating mode with a large temperature rise during the image formation period Pimg, there is a risk that the temperature of the drive signal output circuit 52 will be excessively low compared to the maximum threshold temperature Tch when operating in an operating mode with a small temperature rise, resulting in a problem of the liquid ejection device 1 being over-specified.

[0216] To address this problem, the liquid ejection device 1 of this embodiment is configured so that the amount of power supplied by the power supply circuit 80 to the cooling mechanism 82 in binary mode is greater than the amount of power supplied by the power supply circuit 80 to the cooling mechanism 82 in multi-tone mode, thereby reducing the temperature difference between the elevated temperature Tbin, which is the temperature rise value during the image formation period Pimg when the liquid ejection device 1 is operating in binary mode, and the elevated temperature Tmg, which is the temperature rise value during the image formation period Pimg when the liquid ejection device 1 is operating in multi-tone mode.

[0217] As a result, when the liquid ejection device 1 is operating in a multi-tone mode with a small temperature rise, if the threshold temperature Tth is set based on the temperature rise Tmg of the drive signal output circuit 52 during the image formation period Pimg, the risk of the temperature of the drive signal output circuit 52 reaching the maximum threshold temperature Tch is reduced, even when the liquid ejection device 1 is operating in a binary mode with a large temperature rise.Furthermore, when the liquid ejection device 1 is operating in a binary mode with a large temperature rise, if the threshold temperature Tth is set based on the temperature rise Tbin of the drive signal output circuit 52 during the image formation period Pimg, the risk of the temperature of the drive signal output circuit 52 becoming excessively low compared to the maximum threshold temperature Tch is reduced, even when the liquid ejection device 1 is operating in a multi-tone mode with a small temperature rise, because the temperature difference between the temperature rise Tbin and the temperature rise Tmg is small.

[0218] In other words, the liquid ejection device 1 of this embodiment can further improve the image quality of the liquid ejection device 1 and meet the demand for faster image formation speed on the medium P, while solving the problem of heat generation in the drive signal output circuit 52 that occurs due to different operating modes of the liquid ejection device 1.

[0219] 7. Variations In the liquid ejection device 1 of this embodiment described above, the number of gradations of dots formed on the medium P in the multi-tone mode is four, but the number of gradations of dots formed on the medium P in the multi-tone mode is not limited to four, and may be five or more. In this case, the head control signal DI includes, as the ejection control signal SI, in addition to the upper-order ejection data SIH1 to SIHn and the lower-order ejection data SIL1 to SILn that define the ejection amount of ink ejected from the nozzles 651 of each of the ejection units 600[1] to 600[n], The medium ejection data SIM1 to SIMn may be included. That is, the ejection amount of ink ejected from the nozzles 651 of each of the ejection sections 600[1] to 600[n] may be defined by data of 3 bits or more.

[0220] Furthermore, in the liquid ejection device 1 of this embodiment, the drive signal selection circuit 200 generates the drive signal VOUT by selecting or deselecting the signal waveform included in one drive signal COM based on the latch signal LAT, change signal CH, clock signal SCK, and head control signal DI, but the drive signal output circuit 52 may output the drive signal COMA and drive signal COMB as the drive signal COM, and the drive signal selection circuit 200 may select or deselect the signal waveform included in the drive signal COMA and select or deselect the signal waveform included in the drive signal COMB during each of periods p1 to pm based on the latch signal LAT, change signal CH, clock signal SCK, and head control signal DI, thereby generating the drive signal VOUT and outputting it to the ejection section 600.

[0221] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be combined as appropriate.

[0222] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0223] The following can be derived from the above-described embodiment and modifications.

[0224] One aspect of the liquid ejection device is a discharge unit that discharges liquid when a drive signal is supplied; a drive signal output unit that outputs the drive signal; a cooling unit that cools the drive signal output unit; a power supply unit that supplies power to the cooling unit; Equipped with a first mode in which the drive signal output unit outputs a first drive signal of a first frequency to the ejection unit as the drive signal; a second mode in which the drive signal output unit outputs a second drive signal having a second frequency lower than the first frequency to the ejection unit as the drive signal; and The amount of electric power supplied from the power supply unit to the cooling unit in the first mode is greater than the amount of electric power supplied from the power supply unit to the cooling unit in the second mode.

[0225] This liquid ejection device has a first mode in which the drive signal output unit outputs a first drive signal of a first frequency to the ejection unit as a drive signal, and a second mode in which the drive signal output unit outputs a second drive signal of a second frequency lower than the first frequency to the ejection unit as a drive signal. In this case, because the first frequency of the first drive signal output by the drive signal output unit in the first mode is higher than the second frequency of the second drive signal output by the drive signal output unit in the second mode, the temperature rise occurring in the drive signal output unit in the first mode is higher than the temperature rise occurring in the drive signal output unit in the second mode. Even when the liquid ejection device has two operating modes with different temperature rise values, the power supply unit can increase the amount of power supplied to the cooling unit for the drive signal output unit in the first mode, thereby reducing the difference between the temperature rise value of the drive signal output unit in the first mode and the temperature rise value of the drive signal output unit in the second mode. As a result, even if the liquid ejection device has two operating modes of temperature rise, in each operating mode, the risk of abnormalities occurring in the drive signal output unit due to excessive temperature rise in the drive signal output unit is reduced, and the risk of the liquid ejection device having excessive specifications is reduced due to excessive suppression of the temperature of the drive signal output unit.

[0226] That is, this liquid ejection device can solve the problem of heat generation in the drive signal output section that occurs because the liquid ejection device has a plurality of operation modes.

[0227] In one aspect of the liquid ejection device, a temperature detection unit that detects a temperature; a comparison unit that compares the detection result of the temperature detection unit with an abnormal temperature threshold; Equipped with The abnormal temperature threshold in the first mode may be lower than the abnormal temperature threshold in the second mode.

[0228] According to this liquid ejection device, the comparison unit that compares the temperature of the drive signal output unit with the abnormal temperature threshold sets the abnormal temperature threshold in the first mode, which has a large temperature rise value, lower than the abnormal temperature threshold in the second mode, which has a small temperature rise value, thereby reducing the difference between the temperature that the drive signal output unit can reach in the first mode and the temperature that the drive signal output unit can reach in the second mode. This reduces the risk of an abnormality occurring in the drive signal output unit due to an excessive rise in temperature in each operating mode, even if the temperature rise value in the first mode and the temperature rise value in the second mode occur, and also reduces the risk of the liquid ejection device exceeding its specifications due to excessive suppression of the temperature of the drive signal output unit.

[0229] In one aspect of the liquid ejection device, When the detection result is greater than the abnormal temperature threshold, the drive signal output unit may stop outputting the drive signal.

[0230] According to this liquid ejection device, if a temperature abnormality occurs in the drive signal output section, the drive signal output section stops operating, thereby reducing the risk of the temperature abnormality spreading throughout the liquid ejection device, and as a result, improving the reliability of the liquid ejection device.

[0231] In one aspect of the liquid ejection device, When the detection result is greater than the abnormal temperature threshold, the power supply unit may increase the amount of power supplied to the cooling unit.

[0232] According to this liquid ejection device, when a temperature abnormality occurs in the drive signal output section, the power supply section increases the amount of power supplied to the cooling section, thereby improving the cooling capacity of the cooling section for the drive signal output section, thereby reducing the temperature rise in the drive signal output section.

[0233] In one aspect of the liquid ejection device, a first wiring that propagates a group of setting information signals, including first setting information and second setting information, that set a selection rule for a drive waveform included in the drive signal, and a group of ejection control signals that control the gradation of dots formed on a medium by ejecting liquid from the ejection units; a second wiring for transmitting the drive signal; a selection circuit that switches whether or not the drive waveform is supplied to the ejection unit based on the setting information signal group and the ejection control signal group; Equipped with the gradation of the dots formed on the medium in the first mode is lower than the gradation of the dots formed on the medium in the second mode; The group of setting information signals in the first mode may include the second setting information in which bit data of the first setting information is inverted.

[0234] This liquid ejection device can achieve two operating modes with different dot gradations without changing the hardware configuration, thereby increasing the versatility of the liquid ejection device.

[0235] In one aspect of the liquid ejection device, a data size of the setting information signal group in the first mode is equal to a data size of the setting information signal group in the second mode; The data size of the group of ejection control signals in the first mode may be smaller than the data size of the group of ejection control signals in the second mode.

[0236] According to this liquid ejection device, the setting information signal group in the first mode includes second setting information in which the bit data of the first setting information is inverted, so that even if the data size of the ejection control signal group in the first mode is reduced, two operating modes with different dot gradations can be realized without changing the hardware configuration, and because the data size of the ejection control signal group in the first mode is reduced, the risk that the data size of the ejection control signal group in the first mode will become a limiting factor for the ejection speed of ink onto the medium is reduced, and as a result, the ejection speed of ink onto the medium in the first mode can be improved.

[0237] In one aspect of the liquid ejection device, The first mode may be a binary mode, and the second mode may be a multi-tone mode. [Explanation of symbols]

[0238] 1...liquid ejection device, 2...ink container, 10...control mechanism, 20...carriage, 21...ejection head, 30...movement mechanism, 31...carriage motor, 32...endless belt, 40...transport mechanism, 41...transport motor, 42...transport roller, 50...drive circuit, 52...drive signal output circuit, 54...reference voltage signal output circuit, 60...piezoelectric element, 70...comparison circuit, 72...temperature detection circuit, 80...power supply circuit, 82...cooling mechanism, 90...linear encoder, 100...control circuit, 200...drive signal selection circuit, 210...selection control circuit, 222a...first register Star, 222b...second register, 224a...first latch circuit, 224b...second latch circuit, 226...decoder, 230...selection circuit, 260...control logic circuit, 262...SP register group, 264...selection control signal generation unit, 270...selection signal output unit, 600...ejection unit, 601...piezoelectric body, 611, 612...electrodes, 621...vibration plate, 631...cavity, 632...nozzle plate, 641...reservoir, 651...nozzle, 661...supply port, A, B...wiring, INV...inverter, P...medium, TG...transfer gate

Claims

1. a discharge unit that discharges liquid when a drive signal is supplied; a drive signal output unit that outputs the drive signal; a cooling unit that cools the drive signal output unit; a power supply unit that supplies power to the cooling unit; Equipped with The drive signal output unit outputs a first drive signal of a first frequency to the ejection unit as the drive signal. a first mode of applying a force; the drive signal output unit outputs a second drive signal having a second frequency lower than the first frequency to the drive circuit; a second mode in which the signal is output to the discharge unit; and The amount of power supplied from the power supply unit to the cooling unit in the first mode is the amount of power supplied by the power supply unit to the cooling unit in the The first mode is a binary mode, and the second mode is a multi-tone mode. A liquid ejection device characterized by:

2. a temperature detection unit that detects a temperature; a comparison unit that compares the detection result of the temperature detection unit with an abnormal temperature threshold; Equipped with The abnormal temperature threshold in the first mode is equal to the abnormal temperature threshold in the second mode. lower than The liquid ejection device according to claim 1 .

3. When the detection result is greater than the abnormal temperature threshold, the drive signal output unit Stop the output of the signal.

3. The liquid ejection device according to claim 2.

4. When the detection result is greater than the abnormal temperature threshold, the power supply unit supplies the power to the cooling unit. Increase the amount of power supplied, 4. The liquid ejection device according to claim 2 or 3.

5. The driving signal includes first setting information and second setting information, and a selection rule for a driving waveform included in the driving signal is set. and a set of setting information signals for determining the pattern formed on the medium by ejecting the liquid from the ejection unit. a first wiring for transmitting a group of ejection control signals for controlling the gradation of the dots; a second wiring for transmitting the drive signal; Based on the set information signal group and the ejection control signal group, the drive waveform is supplied to the ejection unit. a selection circuit for switching whether or not to supply the Equipped with The gradation of the dots formed on the medium in the first mode is the gradation of the dots formed on the medium is lower than that of the dots formed on the medium, In the first mode, the setting information signal group has the bit data of the first setting information inverted. The second setting information includes 5. The liquid ejection device according to claim 1, wherein the ejection head is a nozzle.

6. The data size of the setting information signal group in the first mode is The data size of the setting information signal group is equal to the data size of the setting information signal group, The data size of the ejection control signal group in the first mode is The data size of the ejection control signal group is smaller than the data size of the ejection control signal group.

6. The liquid ejection device according to claim 5.

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