Semiconductor Devices

Abstract

The purpose of the present invention is to suppress an increase in the size of a device. This semiconductor device comprises: a P electrode provided extending outward from a first side surface of a substrate; an AC electrode provided extending outward from a second side surface on the side opposite the first side surface; and first and second connection electrodes provided extending outward from at least one of a third side surface that intersects the first side surface and a fourth side surface on the side opposite the third side surface, where above the substrate, the first connection electrode overlaps neither the P electrode nor the AC electrode, and above the substrate, the second connection electrode overlaps neither the P electrode nor the AC electrode.

Description

[Technical Field]

[0001] The technology disclosed herein relates to semiconductor technology for power applications. [Background technology]

[0002] A conventional power device module includes a P electrode, an N electrode, and an AC electrode, each of which is provided on a first side surface on the outside of the frame of the power device module or a second side surface opposite to the first side surface.

[0003] When multiple power device modules are connected in parallel, the oscillation phenomenon can be suppressed by connecting the AC electrodes and N electrodes of the parallel-connected power device modules together.

[0004] Generally, when multiple power device modules are connected in parallel for use, other power device modules are arranged facing the third side surface, which is a side surface perpendicular to the first side surface and the second side surface, and the fourth side surface, which is a side surface opposite the third side surface.

[0005] Therefore, by providing AC electrodes or N electrodes on the opposing third and fourth side surfaces, it becomes easy to connect the AC electrodes or N electrodes of the power device modules connected in parallel.

[0006] For example, as shown in Patent Document 1, power device modules each having an AC electrode and an N electrode on a side perpendicular to a side on which a P electrode and an N electrode are provided are arranged so that the sides on which the AC electrode and the N electrode are provided face each other. This makes it easy to connect the AC electrodes and N electrodes of adjacent power device modules, thereby suppressing oscillation. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2019-169609 Summary of the Invention [Problem to be solved by the invention]

[0008] In the structure shown in Patent Document 1, electrodes are wired so as to overlap each other in a plan view within the sealing resin of the power device module. The electrodes that are wired so as to overlap each other in a plan view must be spaced apart to maintain insulation. This results in a problem of an increase in the size of the device.

[0009] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology that facilitates wiring when used in parallel connection while suppressing an increase in the size of the device. [Means for solving the problem]

[0010] A semiconductor device according to a first aspect of the technology disclosed in the present specification includes a substrate, at least one semiconductor element provided on an upper surface of the substrate, a P-electrode electrically connected to the semiconductor element and extending outward in a planar view from a first side surface of the substrate, an AC electrode electrically connected to the semiconductor element and extending outward in a planar view from a second side surface opposite to the first side surface, a third side surface electrically connected to the semiconductor element and the AC electrode and intersecting the first side surface, and a P-electrode electrically connected to the third side surface of the substrate. a first connection electrode provided to extend outward in a plan view from at least one of the third side face and the fourth side face opposite to the first side face, and a second connection electrode electrically connected to the semiconductor element and provided to extend outward in a plan view from at least one of the third side face and the fourth side face, wherein the first connection electrode does not overlap with either the P electrode or the AC electrode above the substrate in a plan view, and the second connection electrode does not overlap with either the P electrode or the AC electrode above the substrate in a plan view. The semiconductor device further includes a resin portion provided on the upper surface of the substrate to cover the semiconductor element, a portion of the P electrode, a portion of the AC electrode, a portion of the first connection electrode, and a portion of the second connection electrode, wherein in the resin portion, the first connection electrode does not overlap with either the P electrode or the AC electrode in a planar view, and in the resin portion, the second connection electrode does not overlap with either the P electrode or the AC electrode in a planar view, and further includes an N electrode electrically connected to the semiconductor element and extending outward from the first side surface in a planar view, and the second connection electrode is electrically connected to the N electrode. [Effects of the Invention]

[0011] According to at least the first aspect of the technology disclosed herein, the connection electrode is provided on a side surface that intersects with the side surface on which the P electrode and the AC electrode are provided, which facilitates wiring while suppressing oscillation when the configuration is connected in parallel. Furthermore, the connection electrode is provided above the substrate so as not to overlap with either the P electrode or the AC electrode in a plan view, which enables the device to be made more compact.

[0012] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a plan view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 2] 1 is a plan view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 3] 1 is a plan view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 4] 1 is a perspective view showing an example of the configuration of a semiconductor device according to an embodiment; [Figure 5] 1 is a perspective view showing an example of the configuration of a semiconductor device according to an embodiment; [Figure 6] FIG. 2 is a side view of the configuration shown in the figure. [Figure 7] 1 is a perspective view showing an example of the configuration of a semiconductor device according to an embodiment; [Figure 8] 1 is a side view showing an example of the configuration of a semiconductor device according to an embodiment; [Figure 9] 1 is a side view showing an example of the configuration of a semiconductor device according to an embodiment; [Figure 10] 1 is a plan view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 11] FIG. 1 is a plan view showing an example of the configuration of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0015] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0016] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0017] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0018] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0019] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0020] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude another component "C" from being interposed between A and B.

[0021] First Embodiment A semiconductor device according to this embodiment will be described below. For convenience of explanation, the configuration of a semiconductor device known to the inventor will be described first.

[0022] In the following description, the expression "A and B are electrically connected" means that current can flow between the configuration A and the configuration B in both directions.

[0023] Fig. 11 is a plan view showing an example of the configuration of a semiconductor device. In the semiconductor device shown in Fig. 11, N electrode 161, P electrode 131, and AC electrode 151 are provided so as to protrude outside the frame of substrate 100, with the electrodes being partially covered with resin part 80.

[0024] Here, N electrode 161 and P electrode 131 are provided outside the frame of a first side surface of substrate 100. On the other hand, AC electrode 151 is provided outside the frame of a second side surface that is the side surface opposite to the first side surface.

[0025] <Configuration of semiconductor device> Fig. 1 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in Fig. 1, the semiconductor device has metal layers 11, 12, and 13 formed on the upper surface of a substrate 100 while being spaced apart from one another.

[0026] A P-electrode 31 is bonded to the upper surface of metal layer 11 via bonding portion 21. A semiconductor element 41 is also bonded to the upper surface of metal layer 11. That is, P-electrode 31 is electrically connected to semiconductor element 41 via metal layer 11. An AC electrode 53 is also bonded to the upper surface of semiconductor element 41. AC electrode 53 is also wired (connected) to AC electrode 52. AC electrode 53 is also bonded to metal layer 12 via bonding portion 22.

[0027] An AC electrode 51 is joined to the upper surface of metal layer 12 via joint 23. That is, AC electrode 53 is electrically connected to AC electrode 51 via metal layer 12. A semiconductor element 42 is joined to the upper surface of metal layer 12. That is, AC electrode 51 is electrically connected to semiconductor element 42 via metal layer 12. An N-electrode 63 is joined to the upper surface of semiconductor element 42. N-electrode 63 is joined to metal layer 13 via joint 24.

[0028] An N-electrode 62 is joined to the upper surface of metal layer 13 via bonding portion 25. In addition, an N-electrode 61 is joined to the upper surface of metal layer 13 via bonding portion 26. N-electrode 61 is electrically connected to semiconductor element 42 via metal layer 13 and N-electrode 63.

[0029] Here, the P electrode, N electrode, and AC electrode (output terminal) are, for example, lead terminals used in semiconductor devices. Lead terminals are generally supplied as lead frames made by punching a thin, strip-shaped metal plate in a predetermined pattern, and are cut off from the frame after the necessary processing.

[0030] The P electrode 31 and the N electrode 61 are provided outside the frame of a first side surface of the substrate 100. The AC electrode 51 is provided outside the frame of a second side surface opposite the first side surface.

[0031] The AC electrode 52 and the N electrode 62 are provided outside the frame of the third side surface, which is perpendicular to the first side surface, and the AC electrode 53 and the N electrode 63 are provided outside the frame of the fourth side surface, which is the side surface opposite to the third side surface.

[0032] According to this configuration, AC electrode 52 and AC electrode 53 are electrically connected to AC electrode 51 via metal layer 12. Furthermore, N electrode 62 and N electrode 63 are electrically connected to N electrode 61 via metal layer 13.

[0033] More specifically, above substrate 100 overlapping with substrate 100 in a planar view, AC electrodes 52 and 53 are arranged without overlapping with any of P electrode 31, AC electrode 51, and N electrode 61 in a planar view. Similarly, above substrate 100 overlapping with substrate 100 in a planar view, N electrodes 62 and 63 are arranged without overlapping with any of P electrode 31, AC electrode 51, and N electrode 61 in a planar view.

[0034] Therefore, within the frame of the substrate 100, the electrodes do not cross over each other (i.e., do not overlap in a planar view), and the AC electrode 52 and the N electrode 62 can be provided outside the frame of the third side, and the AC electrode 53 and the N electrode 63 can be provided outside the frame of the fourth side.

[0035] In other words, above the substrate 100 that overlaps with the substrate 100 in a planar view, none of the AC electrodes 52, 53, N-electrode 62, and N-electrode 63 are provided at positions that do not overlap with the P-electrode 31 in a planar view. Moreover, above the substrate 100 that overlaps with the substrate 100 in a planar view, none of the AC electrodes 52, 53, N-electrode 62, and N-electrode 63 are provided at positions that do not overlap with the AC electrode 51 in a planar view. Moreover, above the substrate 100 that overlaps with the substrate 100 in a planar view, none of the AC electrodes 52, 53, N-electrode 62, and N-electrode 63 are provided at positions that do not overlap with the N-electrode 61 in a planar view.

[0036] It is sufficient that the semiconductor device includes at least one semiconductor element.

[0037] <Second embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0038] <Configuration of semiconductor device> 2 is a plan view showing an example of the configuration of a semiconductor device according to the present embodiment. As shown in the example of FIG. 2, the semiconductor device has a metal layer 11 and a metal layer 12 formed on the upper surface of a substrate 100A while being spaced apart from each other.

[0039] A P-electrode 31 is bonded to the upper surface of the metal layer 11 via a bonding portion 21. A semiconductor element 41 is bonded to the upper surface of the metal layer 11. An AC electrode 53A is bonded to the upper surface of the semiconductor element 41. The AC electrode 53A is wired (connected) to an AC electrode 52A. The AC electrode 53A is bonded to the metal layer 12 via a bonding portion 22.

[0040] An AC electrode 51 is bonded to the upper surface of metal layer 12 via bonding portion 23. A semiconductor element 42 is also bonded to the upper surface of metal layer 12. An N-electrode 63A is also bonded to the upper surface of semiconductor element 42. N-electrode 63A is also wired (connected) to N-electrode 62A.

[0041] The P electrode 31 is provided outside the frame of a first side surface of the substrate 100A, and the AC electrode 51 is provided outside the frame of a second side surface opposite the first side surface.

[0042] Additionally, AC electrode 52A and N electrode 62A are provided outside the frame of a third side surface that is perpendicular to the first side surface, and AC electrode 53A and N electrode 63A are provided outside the frame of a fourth side surface that is the side surface opposite the third side surface.

[0043] According to this configuration, AC electrode 52A and AC electrode 53A are electrically connected to AC electrode 51 via metal layer 12.

[0044] Therefore, AC electrode 52A and N electrode 62A can be provided outside the frame of the third side surface, and AC electrode 53A and N electrode 63A can be provided outside the frame of the fourth side surface, without the electrodes crossing each other in three dimensions (i.e., without overlapping in a plan view) within the frame of substrate 100. Furthermore, since no N electrode is provided on the first side surface, the device can be made smaller.

[0045] <Third embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0046] <Configuration of semiconductor device> 1 is partially covered with resin part 80 on the upper surface of substrate 100, specifically, semiconductor elements 41, 42, parts of P-electrode 31, parts of N-electrode 61, parts of AC electrode 52, parts of AC electrode 53, parts of N-electrode 62, parts of N-electrode 63, and parts of AC electrode 51 corresponding to each substrate 100 are covered with resin part 80, and a plurality of semiconductor elements are arranged adjacent to each other with the third side surface and the fourth side surface facing each other.

[0047] 3, inside the resin part 80, none of the AC electrodes 52, 53, N-electrode 62, and N-electrode 63 are provided at positions that do not overlap with the P-electrode 31 in a planar view. Furthermore, inside the resin part 80, none of the AC electrodes 52, 53, N-electrode 62, and N-electrode 63 are provided at positions that do not overlap with the AC electrode 51 in a planar view. Furthermore, inside the resin part 80, none of the AC electrodes 52, 53, N-electrode 62, and N-electrode 63 are provided at positions that do not overlap with the N-electrode 61 in a planar view.

[0048] 3, the AC electrode 52 on the third side surface and the AC electrode 53 on the fourth side surface of the substrates 100 arranged adjacent to each other (facing each other) are joined (i.e., the AC electrodes on the opposing side surfaces are connected to each other), and the N electrode 62 on the third side surface and the N electrode 63 on the fourth side surface are joined (i.e., the N electrodes on the opposing side surfaces are connected to each other). These electrodes can be joined by, for example, welding, bolting, or soldering.

[0049] With this configuration, it is possible to suppress oscillation of the semiconductor elements in the plurality of power device modules connected in parallel.

[0050] <Fourth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0051] <Configuration of semiconductor device> Fig. 4 is a perspective view showing an example of the configuration of a semiconductor device according to this embodiment. The structure shown in Fig. 4 is a structure in which a resin part 80 is formed above the structure shown in Fig. 2, and an N bus bar 70 is further provided on the upper surface of the resin part 80.

[0052] 4, N bus bar 70 is joined to N electrode 62 and N electrode 63. N bus bar 70 is also formed to extend to a position adjacent to P electrode 31 outside the frame of the first side surface of substrate 100A.

[0053] With this configuration, the N bus bar 70 is located at the top of the semiconductor device, so that the N bus bar 70 on the top surface of the resin part 80 forms a parallel plate with the wiring inside the resin part 80. This makes it possible to suppress inductance.

[0054] <Fifth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0055] <Configuration of semiconductor device> Fig. 5 is a perspective view showing an example of the configuration of a semiconductor device according to this embodiment. The structure shown in Fig. 5 is a structure in which a resin part 80 is formed above the structure shown in Fig. 2 (however, the shape of P electrode 31A is deformed), and an N bus bar 72 is further provided on the upper surface of resin part 80. Fig. 6 is a side view of the configuration shown in Fig. 5.

[0056] 5 and 6, N bus bar 72 is joined to N electrode 62 and N electrode 63, respectively. N bus bar 72 is formed outside the frame of the first side surface of substrate 100A, extending to form a parallel plate with P electrode 31A. In other words, outside the frame of the first side surface, N bus bar 72 is arranged to overlap P electrode 31A in a plan view.

[0057] With this configuration, the inductance can be effectively suppressed. Note that N-electrode 61 and P-electrode 31 in Fig. 1 may be arranged to overlap each other in plan view outside the frame of the first side surface.

[0058] Sixth Embodiment A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0059] <Configuration of semiconductor device> Fig. 7 is a perspective view showing an example of the configuration of a semiconductor device according to this embodiment. The structure shown in Fig. 7 is a structure in which a resin part 80A is formed above the structure shown in Fig. 2, and an N bus bar 70A is further provided on the upper surface of the resin part 80.

[0060] 7, N bus bar 70A is joined to N electrode 62 and N electrode 63. N bus bar 70A is also formed to extend to a position adjacent to P electrode 31 outside the frame of the first side surface of substrate 100A.

[0061] Furthermore, multiple holes 70B are formed in N bus bar 70A. The relative positions of N bus bar 70A and resin part 80A are determined so that multiple protrusions 82 formed on the upper surface of resin part 80A fit into holes 70B (i.e., so that protrusions 82 overlap holes 70B in plan view). Note that there may be only one protrusion 82 and one hole 70B.

[0062] According to this configuration, the relative positions of N bus bar 70A and resin portion 80A are determined by hole 70B and protrusion 82, so that misalignment during assembly of the semiconductor device can be suppressed.

[0063] Seventh Embodiment A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0064] <Configuration of semiconductor device> Fig. 8 is a side view showing an example of the configuration of a semiconductor device according to this embodiment. The structure shown in Fig. 8 is a structure in which the shape of the resin portion in the structure shown in Fig. 4 is deformed.

[0065] As shown in FIG. 8, a guide portion 84 is formed on the upper surface of the resin portion 80B. The guide portion 84 is a convex portion on the upper surface of the resin portion 80B. The N bus bar 74 is joined to the N electrode 62 and the N electrode 63, respectively. The N bus bar 74 is disposed adjacent to the guide portions 84 on the upper surface of the resin portion 80B at a position where it is sandwiched between the guide portions 84 in a plan view. Specifically, the N bus bar 74 is disposed on the upper surface of the resin portion 80B while being fixed between two guide portions 84. The N bus bar 74 may be surrounded on all sides by guide portions 84 that are provided continuously in the circumferential direction. Both the convex portion 82 and the guide portions 84 shown in FIG. 7 may be provided.

[0066] With this configuration, the N bus bar 74 is positioned by fitting between the guide portions 84, thereby preventing misalignment during assembly of the semiconductor device. Furthermore, the formation of the guide portions 84 can maintain a long creepage distance between the N bus bar 74 and the AC electrodes, thereby improving insulation strength.

[0067] <Eighth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0068] <Configuration of semiconductor device> Fig. 9 is a side view showing an example of the configuration of a semiconductor device according to this embodiment. The structure shown in Fig. 9 is a structure in which the shape of at least one of the AC electrodes and the N electrodes in the structure shown in Fig. 1 is modified.

[0069] 9, N-electrode 63A has a curved portion 63B, which can reduce the height of the end portion connected to N-electrode 62 in an adjacent power device module. Bending portion 63B, for example, bends (moves) the end portion of N-electrode 63A toward the upper surface of substrate 100 by the thickness of N-electrode 63A.

[0070] With this configuration, a sufficient insulation distance is ensured, thereby maintaining good insulation between the components placed on the semiconductor device and N-electrode 63A. The components placed on the semiconductor device may be, for example, a bus bar or a control board.

[0071] In the above description, N electrode 63A has curved portion 63B, but the electrode having a curved portion may be N electrode 62, AC electrode 52, AC electrode 53, etc. Also, both the electrode provided outside the frame of the third side surface and the electrode provided outside the frame of the fourth side surface may have a curved portion.

[0072] <Ninth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0073] <Configuration of semiconductor device> Fig. 10 is a plan view showing an example of the configuration of a semiconductor device according to this embodiment. In the structure shown in Fig. 10, the electrodes of the adjacent power device modules in the structure shown in Fig. 3 that are not connected to their counterparts, i.e., the unbonded AC electrode 52 on the third side surface, the unbonded AC electrode 53 on the fourth side surface, the unbonded N electrode 62 on the third side surface, and the unbonded N electrode 63 on the fourth side surface in Fig. 3, are not arranged outside the frame of the corresponding side surface. Note that it is sufficient that at least one of the electrodes not connected to their counterparts in the adjacent power device modules is not bonded, and this is not limited to the case where all of the electrodes not connected to their counterparts in the adjacent power device modules are not bonded, as shown in Fig. 10.

[0074] This configuration maintains good insulation on the surface where the N-electrode and AC-electrodes are not provided, and therefore, even if another device is placed opposite the surface where the N-electrode and AC-electrodes are not provided, there is no need to consider the insulation distance separately, which prevents the device size from increasing.

[0075] <Tenth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0076] <Configuration of semiconductor device> In any of the above embodiments, the semiconductor element may be made of SiC.

[0077] <Effects of the above-described embodiments> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the corresponding specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another corresponding specific configuration.

[0078] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0079] According to the embodiment described above, the semiconductor device includes substrate 100 (or substrate 100A), at least one semiconductor element 41 (or semiconductor element 42), P electrode 31 (or P electrode 31A), AC electrode 51, a first connection electrode, and a second connection electrode. Here, the first connection electrode corresponds to at least one of AC electrode 52, AC electrode 52A, AC electrode 53, AC electrode 53A, etc., for example. The second connection electrode corresponds to at least one of N electrode 62, N electrode 62A, N electrode 63, N electrode 63A, etc. Semiconductor element 41 is provided on the upper surface of substrate 100. P electrode 31 is electrically connected to semiconductor element 41. P electrode 31 is provided to extend outward from a first side surface of substrate 100 in a plan view. AC electrode 51 is electrically connected to semiconductor element 41. The AC electrode 51 is provided to extend outward in a planar view from a second side surface opposite the first side surface. The AC electrode 52 is electrically connected to the semiconductor element 41 and the AC electrode 51. The AC electrode 52 is provided to extend outward in a planar view from at least one of a third side surface intersecting the first side surface and a fourth side surface opposite the third side surface. The N electrode 62 is electrically connected to the semiconductor element 41. The N electrode 62 is provided to extend outward in a planar view from at least one of the third side surface and the fourth side surface. Above the substrate 100, the AC electrode 52 does not overlap with either the P electrode 31 or the AC electrode 51 in a planar view. Above the substrate 100, the N electrode 62 does not overlap with either the P electrode 31 or the AC electrode 51 in a planar view.

[0080] According to this configuration, the AC electrodes 52, 53, N electrodes 62, and 63, which are connection electrodes, are provided on side surfaces that intersect with the side surfaces on which the P electrodes 31 and AC electrodes 51 are provided. This makes it possible to easily perform wiring while suppressing oscillation when the configuration is connected in parallel. Furthermore, the AC electrodes 52, 53, N electrodes 62, and N electrodes 63, which are connection electrodes, are provided above the substrate 100 so as not to overlap with either the P electrodes 31 or the AC electrodes 51 in a plan view. This allows for the device to be made more compact.

[0081] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0082] Furthermore, according to the embodiment described above, the semiconductor device includes resin part 80 (or resin part 80A or resin part 80B). Resin part 80 is provided on the upper surface of substrate 100, covering semiconductor element 41, part of P-electrode 31, part of AC electrode 51, part of AC electrode 52, and part of N-electrode 62. In resin part 80, AC electrode 52 does not overlap with either P-electrode 31 or AC electrode 51 in a planar view. In resin part 80, N-electrode 62 does not overlap with either P-electrode 31 or AC electrode 51 in a planar view. With this configuration, within resin part 80, AC electrode 52, AC electrode 53, N-electrode 62, and N-electrode 63 are provided so as not to overlap with either P-electrode 31 or AC electrode 51 in a planar view. This enables the device to be miniaturized.

[0083] Furthermore, according to the embodiment described above, the semiconductor device includes N-electrode 61 (or N-bus bar 70, N-bus bar 70A, N-bus bar 72, N-bus bar 74) that is electrically connected to semiconductor element 41 and that is provided extending outward from the first side surface in a planar view. N-electrode 62 is electrically connected to N-electrode 61. With this configuration, above substrate 100, AC electrode 52, AC electrode 53, N-electrode 62, and N-electrode 63 are provided so as not to overlap any of P-electrode 31, AC electrode 51, and N-electrode 61 in a planar view. This enables the device to be miniaturized.

[0084] Furthermore, according to the embodiment described above, resin part 80 is provided so as to cover a portion of N-electrode 61. Within resin part 80, AC electrode 52 does not overlap N-electrode 61 in a planar view. Within resin part 80, N-electrode 62 does not overlap N-electrode 61 in a planar view. According to this configuration, within resin part 80, AC electrode 52, AC electrode 53, N-electrode 62, and N-electrode 63 are provided so as not to overlap P-electrode 31, AC electrode 51, or N-electrode 61 in a planar view. This enables the device to be made more compact.

[0085] Furthermore, according to the embodiment described above, the N bus bar 70 is disposed on the upper surface of the resin part 80. With this configuration, the N bus bar 70 is located at the top of the semiconductor device, and therefore the N bus bar 70 on the upper surface of the resin part 80 becomes a parallel plate with the wiring inside the resin part 80. This makes it possible to suppress inductance.

[0086] Furthermore, according to the embodiment described above, at least one protrusion 82 is formed on the top surface of resin part 80A. At least one hole 70B into which protrusion 82 fits is formed in N bus bar 70A at a position that overlaps with protrusion 82 in a plan view. With this configuration, the relative positions of N bus bar 70A and resin part 80A can be easily determined by hole 70B and protrusion 82, and misalignment during assembly of the semiconductor device can be suppressed.

[0087] Furthermore, according to the embodiment described above, at least one guide portion 84 is formed on the upper surface of the resin portion 80B. The N bus bar 74 on the upper surface of the resin portion 80B is disposed adjacent to the guide portion 84 in a plan view. With this configuration, the N bus bar 74 is easily positioned by fitting between the guide portions 84, and misalignment during assembly of the semiconductor device can be suppressed. Furthermore, if the formation of the guide portion 84 maintains a long creepage distance between the N bus bar 74 and the AC electrode, the insulation strength can be improved.

[0088] Furthermore, according to the embodiment described above, the N bus bar 70 extending from the first side surface is adjacent to the P electrode 31 extending from the first side surface in a plan view. With this configuration, the N bus bar 70 is located at the top of the semiconductor device, and the N bus bar 70 on the top surface of the resin part 80 becomes a parallel plate with the wiring inside the resin part 80. This makes it possible to suppress inductance.

[0089] Furthermore, according to the embodiment described above, N bus bar 72 extending from the first side surface overlaps with P electrode 31A extending from the first side surface in a plan view. This configuration effectively reduces inductance. Furthermore, because P electrode 31A and N bus bar 72 are positioned to overlap outside the frame of the first side surface, the semiconductor device can be made smaller.

[0090] According to the embodiment described above, the semiconductor device includes a plurality of substrates 100. A semiconductor element 41, a P-electrode 31, an AC electrode 51, an AC electrode 52, and an N-electrode 62 are provided on each substrate 100. The adjacent substrates 100 are referred to as a first substrate and a second substrate, respectively. The fourth side surface of the first substrate faces the third side surface of the second substrate. The AC electrode 52 extending outward from the fourth side surface of the first substrate in a planar view is connected to the AC electrode 52 extending outward from the third side surface of the second substrate in a planar view. The N-electrode 62 extending outward from the fourth side surface of the first substrate in a planar view is connected to the N-electrode 62 extending outward from the third side surface of the second substrate in a planar view. According to this configuration, by connecting the AC electrodes 52 and 53 of adjacent power device modules and also connecting the N electrodes 62 and 63 of adjacent power device modules, the potential difference between the semiconductor elements in the multiple power device modules connected in parallel can be reduced, thereby suppressing oscillation of the semiconductor elements.

[0091] Furthermore, according to the embodiment described above, at least one of the AC electrode 52 and the N electrode 62 does not extend from at least one of the third side surface of the first substrate and the fourth side surface of the second substrate. With this configuration, the N electrode and the AC electrode are not provided on the surface that does not face the adjacent power device module, so good insulation can be maintained on that surface. Therefore, even if another device is placed opposite the surface on which the N electrode and the AC electrode are not provided, there is no need to consider the insulation distance, and therefore an increase in the device size can be suppressed.

[0092] Furthermore, according to the embodiment described above, at least one of AC electrode 52 and N-electrode 63A, which extend outward in plan view from the fourth side surface, includes curved portion 63B outside resin portion 80. Bent portion 63B bends the end portion extending outward in plan view from the fourth side surface toward the upper surface of substrate 100. This configuration allows the height of the joint between the electrodes of adjacent semiconductor devices to be lowered when semiconductor devices are arranged adjacent to each other. Therefore, by ensuring a sufficient insulation distance, good insulation can be maintained between N-electrode 63A and components installed above the semiconductor device.

[0093] Furthermore, according to the embodiment described above, the semiconductor of the semiconductor element 41 is made of SiC. With this configuration, by using SiC for the semiconductor of the semiconductor element, the element size can be made smaller than when a Si element is used. Therefore, the size of the semiconductor device can be made smaller. When the size of the semiconductor device is made smaller, the connection distance between the semiconductor elements used in parallel connection becomes shorter, and the potential difference between the semiconductor elements can be made smaller.

[0094] <Modifications of the above-described embodiments> In the embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0095] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0096] Furthermore, in the embodiments described above, when a material name is mentioned without any particular specification, it is assumed that the material may contain other additives, such as an alloy, unless a contradiction arises.

[0097] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, it is also understood that "one or more" of that component may be provided.

[0098] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0099] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0100] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art. [Explanation of symbols]

[0101] 31 P electrode, 31A P electrode, 41 semiconductor element, 42 semiconductor element, 51 AC electrode, 52 AC electrode, 52A AC electrode, 53 AC electrode, 53A AC electrode, 61 N electrode, 62 N electrode, 62A N electrode, 63 N electrode, 63A N electrode, 70B hole, 80 resin part, 80A resin part, 80B resin part, 82 convex part, 84 guide part, 100 substrate, 100A substrate, 131 P electrode, 151 AC electrode, 161 N electrode.

Claims

1. A substrate, at least one semiconductor element provided on an upper surface of the substrate; a P-electrode electrically connected to the semiconductor element and extending outward from a first side surface of the substrate in a plan view; an AC electrode electrically connected to the semiconductor element and extending outward in a plan view from a second side surface opposite to the first side surface; a first connection electrode electrically connected to the semiconductor element and the AC electrode, and extending outward in a plan view from at least one of a third side surface intersecting the first side surface and a fourth side surface opposite to the third side surface; a second connection electrode electrically connected to the semiconductor element and extending outward in a plan view from at least one of the third side surface and the fourth side surface; above the substrate, the first connection electrode does not overlap with either the P electrode or the AC electrode in a plan view; above the substrate, the second connection electrode does not overlap with either the P electrode or the AC electrode in a plan view; a resin portion provided on the upper surface of the substrate to cover the semiconductor element, a portion of the P electrode, a portion of the AC electrode, a portion of the first connection electrode, and a portion of the second connection electrode; In the resin portion, the first connection electrode does not overlap with either the P electrode or the AC electrode in a plan view, In the resin portion, the second connection electrode does not overlap with either the P electrode or the AC electrode in a plan view, an N-electrode electrically connected to the semiconductor element and extending outward from the first side surface in a plan view; the second connection electrode is electrically connected to the N electrode; Semiconductor device.

2. 2. The semiconductor device according to claim 1, the resin portion is provided so as to cover a portion of the N-electrode; In the resin portion, the first connection electrode does not overlap the N-electrode in a plan view, In the resin portion, the second connection electrode does not overlap with the N-electrode in a plan view. Semiconductor device.

3. 2. The semiconductor device according to claim 1, The N-electrode is disposed on the upper surface of the resin portion. Semiconductor device.

4. 4. The semiconductor device according to claim 3, At least one protrusion is formed on the upper surface of the resin portion, At least one hole into which the protrusion fits is formed in the N-electrode at a position overlapping the protrusion in a plan view. Semiconductor device.

5. 5. The semiconductor device according to claim 3, At least one guide portion is formed on the upper surface of the resin portion, the N-electrode on the upper surface of the resin portion is disposed adjacent to the guide portion in a plan view; Semiconductor device.

6. 5. The semiconductor device according to claim 1, the N-electrode extending from the first side surface is adjacent to the P-electrode extending from the first side surface in a plan view; Semiconductor device.

7. 5. The semiconductor device according to claim 1, the N-electrode extending from the first side surface overlaps with the P-electrode extending from the first side surface in a plan view; Semiconductor device.

8. A substrate; at least one semiconductor element provided on an upper surface of the substrate; a P-electrode electrically connected to the semiconductor element and extending outward from a first side surface of the substrate in a plan view; an AC electrode electrically connected to the semiconductor element and extending outward in a plan view from a second side surface opposite to the first side surface; a first connection electrode electrically connected to the semiconductor element and the AC electrode, and extending outward in a plan view from at least one of a third side surface intersecting the first side surface and a fourth side surface opposite to the third side surface; a second connection electrode electrically connected to the semiconductor element and extending outward in a plan view from at least one of the third side surface and the fourth side surface; above the substrate, the first connection electrode does not overlap with either the P electrode or the AC electrode in a plan view; above the substrate, the second connection electrode does not overlap with either the P electrode or the AC electrode in a plan view; A plurality of the substrates are provided, the semiconductor element, the P electrode, the AC electrode, the first connection electrode, and the second connection electrode are provided on the respective substrates; The plurality of substrates arranged adjacent to each other are defined as a first substrate and a second substrate, the fourth side surface of the first substrate and the third side surface of the second substrate are disposed opposite to each other, the first connection electrode provided to extend outward from the fourth side surface of the first substrate in a plan view is connected to the first connection electrode provided to extend outward from the third side surface of the second substrate in a plan view; the second connection electrode provided to extend outward from the fourth side surface of the first substrate in a plan view is connected to the second connection electrode provided to extend outward from the third side surface of the second substrate in a plan view; Semiconductor device.

9. 9. The semiconductor device according to claim 8, At least one of the first connection electrode and the second connection electrode does not extend from at least one of the third side surface of the first substrate and the fourth side surface of the second substrate. Semiconductor device.

10. 5. The semiconductor device according to claim 1, at least one of the first connection electrode and the second connection electrode, which are provided so as to extend outward from the fourth side surface in a plan view, includes a curved portion outside the resin portion; the bending portion bends an end portion extending outward from the fourth side surface in a plan view toward the upper surface of the substrate; Semiconductor device.

11. 5. The semiconductor device according to claim 1, The semiconductor of the semiconductor element is made of SiC. Semiconductor device.

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