Semiconductor Devices

Abstract

To provide a semiconductor device with an excellent semiconductor characteristic useful for a power device, and a semiconductor system having the semiconductor device.SOLUTION: The semiconductor device is a junction barrier Schottky diode (JBS) provided with at least one p-type semiconductor 1 such as a p-type-doped crystalline oxide semiconductor between an n-type semiconductor layer 3 such as an n-type semiconductor layer mainly containing an oxide semiconductor with an ohmic electrode 4 deposited thereon, and a barrier electrode 2 provided on the n-type semiconductor layer 3, where a Schottky barrier can be formed between the n-type semiconductor layer 3 and the barrier electrode. The p-type semiconductor 1 is buried in the n-type semiconductor layer 3 and protrudes into the barrier electrode 2 from the n-type semiconductor layer 3.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device useful as a power device or the like, and a semiconductor system including the same. [Background technology]

[0002] Conventionally, semiconductor devices having a Schottky barrier electrode provided on a semiconductor substrate have been known, and various studies have been conducted on the Schottky barrier electrode with the aim of increasing the reverse breakdown voltage and further reducing the forward rise voltage. Patent Document 1 describes a technique in which a metal with a small barrier height is placed in the center of a semiconductor, and a Schottky contact is formed between the metal with a large barrier height and the semiconductor in the peripheral part of the semiconductor, thereby increasing the reverse breakdown voltage and further reducing the forward rise voltage.

[0003] Combinations of Schottky electrodes and ohmic electrodes have also been studied. For example, Patent Document 2 describes a wide bandgap semiconductor device in which a Schottky electrode and an ohmic electrode made of the same metal are formed on a substrate. It is described that this configuration can improve thermal breakdown resistance when a high current, such as a surge current, flows in the forward direction. However, these have not been entirely satisfactory, due to issues such as the adhesion at the interfaces between the Schottky junction and the ohmic junction and between the junctions themselves, the need for limitations on electrode materials, and problems such as temperature-dependent changes in barrier height. Therefore, a semiconductor device with low contact resistance, low turn-on voltage, and excellent temperature stability has been eagerly awaited.

[0004] Patent Document 3 describes a semiconductor device in which a conductive guard ring is connected to a main junction joined to a Schottky electrode via a short circuit, and states that such a semiconductor device alleviates electric field concentration and contributes to improving breakdown voltage. However, even if multiple guard rings are installed, there is a problem that the breakdown voltage actually deteriorates because they are short-circuited to the main junction. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 52-101970 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-78660 [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-107408 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device with excellent semiconductor characteristics. [Means for solving the problem]

[0007] As a result of intensive research to achieve the above-mentioned object, the inventors have found that in a semiconductor device in which one or more p-type semiconductors are provided between an n-type semiconductor layer and an electrode, by configuring a part or all of the p-type semiconductors to protrude into the electrode, it is possible to reduce contact resistance, suppress electric field concentration, and improve breakdown voltage, and have found that such a semiconductor device can solve the above-mentioned conventional problems in one fell swoop. Furthermore, after obtaining the above findings, the present inventors conducted further studies and completed the present invention.

[0008] That is, the present invention relates to the following inventions. [1] A semiconductor device in which one or more p-type semiconductors are provided between an n-type semiconductor layer and an electrode, and a part or all of the p-type semiconductors protrude into the electrode. [2] The semiconductor device according to [1], wherein the p-type semiconductor is embedded in the electrode. [3] The semiconductor device according to [1] or [2], wherein three or more of the p-type semiconductors are provided. [4] The semiconductor device according to any one of [1] to [3], wherein the n-type semiconductor layer contains an oxide semiconductor as a main component. [5] The semiconductor device according to any one of [1] to [4], wherein the n-type semiconductor layer contains a gallium compound as a main component. [6] The semiconductor device according to any one of [1] to [5], wherein the n-type semiconductor layer contains, as a main component, a crystalline oxide semiconductor having a corundum structure or a hexagonal structure. [7] The semiconductor device according to any one of [1] to [6] above, wherein the p-type semiconductor is an oxide semiconductor containing one or more metals selected from Groups 13 and 9 of the periodic table. [8] The semiconductor device according to any one of [1] to [7], wherein the p-type semiconductor is an oxide semiconductor containing gallium. [9] The semiconductor device according to any one of [1] to [8], wherein the p-type semiconductor is a crystalline oxide semiconductor having a corundum structure or a hexagonal structure.

[10] The semiconductor device according to any one of [1] to [9], wherein ten or more of the p-type semiconductors are provided.

[11] The semiconductor device according to any one of [1] to

[10] , wherein the p-type semiconductor is epitaxially grown on the n-type semiconductor layer.

[12] The semiconductor device according to any one of [1] to

[11] , wherein the p-type semiconductor includes a laterally grown region.

[13] The semiconductor device according to any one of [1] to

[12] above, which is a diode.

[14] The semiconductor device according to any one of [1] to

[13] above, which is a junction barrier Schottky barrier diode.

[15] The semiconductor device according to any one of [1] to

[14] above, which is a power device.

[16] A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [1] to

[15] above. [Effects of the Invention]

[0009] The semiconductor device of the present invention has excellent semiconductor properties. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram schematically illustrating a preferred embodiment of a junction barrier Schottky diode (JBS) of the present invention. [Figure 2] 2A to 2C are diagrams illustrating a preferred method for manufacturing the junction barrier Schottky diode (JBS) of FIG. 1. [Figure 3] 1 is a diagram schematically illustrating a preferred embodiment of a junction barrier Schottky diode (JBS) of the present invention. [Figure 4] 4A to 4C are diagrams illustrating a preferred method for manufacturing the junction barrier Schottky diode (JBS) of FIG. 3. [Figure 5] 1 is a diagram schematically illustrating a preferred embodiment of a junction barrier Schottky diode (JBS) of the present invention. [Figure 6] 1 is a diagram schematically illustrating a preferred embodiment of a junction barrier Schottky diode (JBS) of the present invention. [Figure 7] 1 is a diagram schematically illustrating a preferred embodiment of a junction barrier Schottky diode (JBS) of the present invention. [Figure 8] 1 is a diagram schematically illustrating a preferred embodiment of a junction barrier Schottky diode (JBS) of the present invention. [Figure 9] FIG. 1 is a diagram schematically illustrating a preferred example of a power supply system. [Figure 10] FIG. 1 is a diagram schematically illustrating a preferred example of a system device. [Figure 11]FIG. 1 is a diagram schematically illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 12] FIG. 1 is a schematic diagram of a film forming apparatus (mist CVD apparatus) used in a reference example. [Figure 13] 8A to 8C are diagrams illustrating a preferred method for manufacturing the junction barrier Schottky diode (JBS) of FIG. 7. [Figure 14] 8A to 8C are diagrams illustrating a preferred method for manufacturing the junction barrier Schottky diode (JBS) of FIG. 7. [Figure 15] FIG. 10 is a diagram showing the results of IV measurement in a reference example. [Figure 16] FIG. 1 is a schematic diagram of a film forming apparatus (mist CVD apparatus) used in the examples. [Figure 17] FIG. 1 is a diagram showing the results of IV measurement in Examples and Comparative Examples. [Figure 18] FIG. 1 shows the results of TEM observation in an example. [Figure 19] FIG. 1 is a schematic diagram illustrating an example of a film formation apparatus used to form a p-type semiconductor. [Figure 20] 1 is a diagram schematically illustrating a preferred embodiment of a junction barrier Schottky diode (JBS) of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] The semiconductor device of the present invention is a semiconductor device in which one or more p-type semiconductors are provided between an n-type semiconductor layer and an electrode, and a part or all of the p-type semiconductors protrude into the electrode. In the present invention, it is preferable that a part of the p-type semiconductor is buried in the n-type semiconductor layer. The p-type semiconductor can be buried in the n-type semiconductor layer by a conventional method, by burying a part of the p-type semiconductor in the n-type semiconductor layer. According to such a preferred embodiment, electric field concentration can be further suppressed and contact resistance can be further reduced.

[0012] The electrode is not particularly limited and may be a known electrode. The constituent material of the electrode is not particularly limited as long as it can be used as an electrode, and may be a conductive inorganic material or a conductive organic material. In the present invention, the electrode material is preferably a metal. The metal is not particularly limited, but preferably includes at least one metal selected from Groups 4 to 11 of the periodic table. Examples of metals in Group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf), with Ti being preferred. Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals in Group 6 of the periodic table include one or more metals selected from chromium (Cr), molybdenum (Mo), and tungsten (W). In the present invention, Cr is preferred because it provides better semiconductor properties such as switching characteristics. Examples of metals in Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt), with Pt being preferred. Examples of metals in Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). Examples of methods for forming the electrodes include known methods, such as dry methods and wet methods. Examples of dry methods include known methods such as sputtering, vacuum deposition, and CVD. Examples of wet methods include screen printing and die coating. In the present invention, the electrode is preferably a barrier electrode (Schottky electrode) that forms a Schottky barrier having a predetermined barrier height at the interface with the n-type semiconductor layer.

[0013] The n-type semiconductor layer is not particularly limited as long as it is primarily composed of a semiconductor. However, in the present invention, the n-type semiconductor layer preferably contains an oxide semiconductor as its primary component, and more preferably a crystalline oxide semiconductor as its primary component. The crystalline oxide semiconductor preferably has a β-gallium structure, a corundum structure, or a hexagonal structure, more preferably a corundum structure or a hexagonal structure, and most preferably a corundum structure. The n-type semiconductor layer also preferably contains a gallium compound as its primary component, more preferably an InAlGaO-based semiconductor, and most preferably α-Ga2O3 or a mixed crystal thereof as its primary component. Note that the "primary component" refers to, for example, when the crystalline oxide semiconductor is α-Ga2O3, the atomic ratio of gallium among the metal elements in the n-type semiconductor layer is 0.5 or more. In the present invention, the atomic ratio of gallium among the metal elements in the n-type semiconductor layer is preferably 0.7 or more, and more preferably 0.8 or more. The thickness of the semiconductor layer is not particularly limited and may be 1 μm or less or 1 μm or more, but in the present invention, it is preferably 1 μm to 40 μm, more preferably 1 μm to 25 μm. The surface area of ​​the n-type semiconductor layer is not particularly limited, but it is preferably 1 μm to 40 μm, more preferably 1 μm to 25 μm. 2 May be more than 1 mm 2or less. The crystalline oxide semiconductor is usually single crystal, but may be polycrystalline. The n-type semiconductor layer may be a single layer film or a multilayer film. When the n-type semiconductor layer is a multilayer film, the multilayer film preferably has a thickness of 40 μm or less. Furthermore, when the n-type semiconductor layer is a multilayer film including at least a first semiconductor layer and a second semiconductor layer and a Schottky electrode is provided on the first semiconductor layer, the multilayer film is also preferably a multilayer film in which the carrier concentration of the first semiconductor layer is lower than the carrier concentration of the second semiconductor layer. In this case, the second semiconductor layer usually contains a dopant, and the carrier concentration of the semiconductor layer can be appropriately set by adjusting the doping amount. The plane orientation of the main surface of the n-type semiconductor layer is also not particularly limited. Examples of the plane orientation of the main surface of the n-type semiconductor layer include the c-plane, m-plane, a-plane, and r-plane. In the present invention, the m-plane is preferred.

[0014] The n-type semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known dopant. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, and niobium. In the present invention, the dopant is preferably Sn, Ge, or Si. The content of the dopant in the composition of the semiconductor film is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. In the present invention, when the n-type semiconductor layer is a multilayer film including a first semiconductor layer and a second semiconductor layer, it is preferable that the dopant used in the first semiconductor layer is germanium, silicon, titanium, zirconium, vanadium, or niobium, and the dopant used in the second semiconductor layer is tin, since this further improves the semiconductor properties without impairing adhesion.

[0015] The n-type semiconductor layer is preferably formed by, for example, a mist CVD method or the like, and more specifically, for example, by atomizing or forming droplets from a raw material solution (atomization / dropletization step), transporting the resulting mist or droplets onto a substrate with a carrier gas (transport step), and then causing a thermal reaction of the mist or droplets in a film formation chamber to deposit a semiconductor film containing a crystalline oxide semiconductor as a main component on the substrate (film formation step).

[0016] (Atomization / dropletization process) In the atomization / dropletization step, the raw material solution is atomized or converted into droplets. The atomization or dropletization means for the raw material solution is not particularly limited as long as it can atomize or dropletize the raw material solution, and any known means may be used. However, in the present invention, an atomization or dropletization means using ultrasonic waves is preferred. The mist or droplets obtained using ultrasonic waves are preferable because they have an initial velocity of zero and float in the air. For example, rather than being sprayed like a spray, the mist floats in space and can be transported as a gas, which is highly suitable because it is not damaged by collision energy. The droplet size is not particularly limited and can be on the order of a few millimeters, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0017] (Raw material solution) The raw material solution is not particularly limited as long as it can be atomized or formed into droplets and contains a raw material capable of forming an n-type semiconductor layer, and may be an inorganic material or an organic material. However, in the present invention, the raw material is preferably a metal or a metal compound, and more preferably contains one or more metals selected from gallium, iron, indium, aluminum, vanadium, titanium, chromium, rhodium, nickel, cobalt, zinc, magnesium, calcium, silicon, yttrium, strontium, and barium.

[0018] In the present invention, the raw material solution can be suitably prepared by dissolving or dispersing the metal in the form of a complex or salt in an organic solvent or water. Examples of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of the salt include organic metal salts (e.g., metal acetates, metal oxalates, and metal citrates), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, and metal iodides).

[0019] It is also preferable to mix additives such as hydrohalic acid and oxidizing agents into the raw material solution. Examples of hydrohalic acids include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among these, hydrobromic acid and hydroiodic acid are preferred because they produce higher-quality films. Examples of oxidizing agents include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, as well as hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

[0020] The raw material solution may contain a dopant. By including a dopant in the raw material solution, doping can be performed well. The dopant is not particularly limited as long as it does not impede the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, and p-type dopants. The concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the dopant concentration may be, for example, about 1×10 17 / cm 3 Furthermore, according to the present invention, the dopant may be present in a concentration as low as about 1×10 20 / cm 3 In the present invention, the concentration may be as high as 1×10 17 / cm3 It is preferable that the carrier concentration be equal to or higher than this.

[0021] The solvent for the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the solvent preferably contains water, and more preferably is water or a mixed solvent of water and alcohol.

[0022] (Transportation process) In the transport step, the mist or droplets are transported into the film formation chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not impede the objectives of the present invention. Suitable examples include oxygen, ozone, inert gases such as nitrogen and argon, and reducing gases such as hydrogen gas and forming gas. The carrier gas may be one type, or two or more types. A dilution gas with a reduced flow rate (e.g., a 10-fold dilution gas) may also be used as a second carrier gas. The number of carrier gas supply locations may be one or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, more preferably 0.1 to 1 L / min.

[0023] (Film forming process) In the film-forming process, the mist or droplets are thermally reacted in a film-forming chamber to form the semiconductor film on the substrate. The thermal reaction may be carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but not too high (e.g., 1000°C), preferably 650°C or lower, and most preferably 300°C to 650°C. The thermal reaction may be carried out under vacuum, a non-oxygen atmosphere, a reducing gas atmosphere, or an oxygen atmosphere, as long as it does not impede the objectives of the present invention. However, the non-oxygen or oxygen atmosphere is preferred. The thermal reaction may be carried out under atmospheric pressure, elevated pressure, or reduced pressure, but atmospheric pressure is preferred in the present invention. The film thickness can be controlled by adjusting the film-forming time.

[0024] (Base) The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is also not particularly limited as long as it does not impede the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound. The substrate may have any shape, and is effective for all shapes, such as a plate-like shape (e.g., a flat plate or a disk), a fiber-like shape, a rod-like shape, a column-like shape, a rectangular column-like shape, a cylindrical shape, a spiral shape, a spherical shape, a ring-like shape, etc., but in the present invention, a substrate is preferred. The thickness of the substrate is not particularly limited in the present invention.

[0025] The substrate is not particularly limited as long as it is plate-shaped and serves as a support for the semiconductor film. It may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate. However, the substrate is preferably an insulating substrate, and also preferably a substrate having a metal film on its surface. Examples of the substrate include a base substrate containing as its main component a substrate material having a corundum structure, a base substrate containing as its main component a substrate material having a β-gallia structure, or a base substrate containing as its main component a substrate material having a hexagonal crystal structure. Here, "main component" means that the substrate material having the specific crystal structure preferably accounts for 50% or more, more preferably 70% or more, and even more preferably 90% or more, in atomic ratio, of the total components of the substrate material; it may be 100%.

[0026] The substrate material is not particularly limited, and may be any known material, as long as it does not impede the objectives of the present invention. Suitable examples of substrate materials having a corundum structure include α-Al2O3 (sapphire substrate) and α-Ga2O3. More preferred examples include a-plane sapphire substrates, m-plane sapphire substrates, r-plane sapphire substrates, c-plane sapphire substrates, and α-type gallium oxide substrates (a-plane, m-plane, or r-plane). Examples of base substrates primarily composed of substrate materials having a β-gallium structure include β-Ga2O3 substrates and mixed crystal substrates containing Ga2O3 and Al2O3, with Al2O3 being greater than 0 wt% and less than 60 wt%. Examples of base substrates primarily composed of substrate materials having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates. In the present invention, the sapphire substrate is preferably an m-plane sapphire substrate.

[0027] In the present invention, an annealing treatment may be carried out after the film formation step. The annealing temperature is not particularly limited as long as it does not impede the object of the present invention, and is usually 300°C to 650°C, and preferably 350°C to 550°C. The annealing time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. The annealing may be carried out in any atmosphere as long as it does not impede the object of the present invention, but is preferably carried out in an oxygen-free atmosphere, and more preferably in a nitrogen atmosphere.

[0028] In the present invention, the semiconductor film may be provided directly on the substrate, or may be provided via another layer such as a buffer layer or a stress relaxation layer. The means for forming each layer is not particularly limited and may be any known means, but in the present invention, a mist CVD method is preferred.

[0029] In the present invention, the semiconductor film may be used as the n-type semiconductor layer in a semiconductor device after being peeled off from the base or the like by a known means, or may be used as the n-type semiconductor layer in a semiconductor device as it is.

[0030] The p-type semiconductor is not particularly limited as long as it does not impede the objectives of the present invention. Examples of the p-type semiconductor include crystalline oxide semiconductors p-doped with a p-type dopant (preferably Mg, Zn, or Ca). In addition to Mg, Zn, and Ca, examples of the p-type dopant include H, Li, Na, K, Rb, Cs, Fr, Be, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Cd, Hg, Tl, Pb, N, and P, as well as two or more elements thereof. The p-type semiconductor is preferably a crystalline oxide semiconductor having a corundum structure or a hexagonal structure, more preferably a crystalline oxide semiconductor having a corundum structure. In the present invention, the p-type semiconductor is preferably an oxide semiconductor containing one or more metals selected from Groups 9 and 13 of the periodic table. Examples of Group 9 metals in the periodic table include cobalt, rhodium, and iridium, with iridium being preferred in the present invention. Examples of Group 13 metals in the periodic table include aluminum, gallium, and indium. Furthermore, in the present invention, the p-type semiconductor is preferably an oxide semiconductor containing gallium, more preferably an InAlGaO-based semiconductor as the main component, and most preferably α-Ga2O3 or a mixed crystal thereof as the main component. Examples of the α-Ga2O3 mixed crystal include a mixed crystal of the α-Ga2O3 with one or more metal oxides, and suitable examples of the metal oxide include aluminum oxide, indium oxide, iridium oxide, rhodium oxide, and iron oxide. In the present invention, the α-Ga2O3 mixed crystal is preferably a mixed crystal of the α-Ga2O3 and α-Ir2O3. The p-type semiconductor can be obtained, for example, by adding a p-type dopant and hydrobromic acid to a raw material solution containing a metal and subjecting it to a mist CVD method. Note that the steps, means, and conditions of the mist CVD method may be the same as those of the atomization / dropletization step, transport step, and film formation step, as well as the means and conditions described above.The number of p-type semiconductors is not particularly limited as long as it does not impede the object of the present invention, but in the present invention, 3 or more is preferable because it can more effectively suppress electric field concentration and improve the electrical characteristics of the semiconductor device, 4 or more is more preferable, 10 or more is even more preferable, and 40 or more is most preferable. According to such a preferred embodiment, it is possible to further reduce the turn-on voltage of the semiconductor device, improve the temperature stability, and further improve the breakdown voltage, which is preferable. Preferably, there are multiple p-type semiconductors protruding into the electrode, and more preferably, three or more p-type semiconductors. In such cases, the distance between the p-type semiconductors is not particularly limited as long as it does not impede the objectives of the present invention, but in the present invention, it is preferably 0.125 μm to 4 μm. The p-type semiconductor layer is also preferably buried in the n-type semiconductor layer. In such cases, the depth of the p-type semiconductor buried in the n-type semiconductor layer is not particularly limited as long as it does not impede the objectives of the present invention, but in the present invention, it is preferably 0.125 μm to 4 μm. In the present invention, it is also preferable that the p-type semiconductor is epitaxially grown on the n-type semiconductor layer, and it is also preferable that the p-type semiconductor includes a laterally grown region. By using such a preferable p-type semiconductor, the performance of the JBS diode can be better exhibited, for example, even when the crystalline oxide semiconductor has a corundum structure.

[0031] Furthermore, when the p-type semiconductor is an oxide semiconductor containing iridium, the p-type semiconductor can be suitably formed, for example, by using a film formation apparatus shown in FIG. 19 to sublimate a solid (e.g., powder) of a metal oxide gas (sublimation step), and then using the obtained metal oxide gas to grow crystals on the substrate (crystal growth step).

[0032] (sublimation process) In the sublimation process, a solid (e.g., powder) of the metal oxide gas is sublimated to obtain a gaseous metal oxide gas. Examples of the metal oxide gas include metal oxides of metals contained in gaseous p-type oxide semiconductors. The valence of the metal oxide is not particularly limited as long as it does not impede the objectives of the present invention. The metal oxide may be monovalent, divalent, trivalent, or tetravalent. In the present invention, the metal oxide preferably contains a metal of Group 9 of the periodic table, more preferably iridium. When the p-type oxide semiconductor contains a mixed crystal, the metal oxide preferably contains iridium and a metal of Group 9 or Group 13 other than iridium. By using such a preferred metal oxide, a p-type semiconductor having a band gap of 2.4 eV or more can be obtained, thereby enabling the p-type semiconductor to exhibit a wider band gap and better electrical properties.

[0033] In the present invention, when the p-type semiconductor is an oxide semiconductor containing iridium, it is preferable to use IrO2 gas as the metal oxide gas. Examples of sublimation means include heating means. The heating temperature is not particularly limited, but is preferably 600°C to 1200°C, more preferably 800°C to 1000°C. In the present invention, it is preferable that the metal oxide gas obtained by sublimation is transported to the substrate by a carrier gas. The type of carrier gas is not particularly limited as long as it does not impede the object of the present invention, and examples include oxygen, ozone, inert gases such as nitrogen and argon, and reducing gases such as hydrogen gas and forming gas. However, in the present invention, it is preferable to use oxygen as the carrier gas. Examples of carrier gases using oxygen include air, oxygen gas, and ozone gas, with oxygen gas and / or ozone gas being particularly preferable. In addition, the type of carrier gas may be one type, or two or more types. A dilution gas with a different carrier gas concentration (e.g., a 10-fold dilution gas) may also be used as a second carrier gas. The number of carrier gas supply points may be two or more, and the flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 0.1 to 10 L / min.

[0034] (Crystal growth process) In the crystal growth step, the metal oxide gas is used to grow crystals near the substrate surface, forming a film on part or all of the substrate surface. The crystal growth temperature is preferably lower than the heating temperature in the sublimation step, more preferably 900°C or lower, and most preferably 500°C to 900°C. Furthermore, crystal growth may be performed under any atmosphere, including vacuum, oxygen-free, reducing gas, or oxidizing atmospheres, as long as it does not impede the objectives of the present invention. It may also be performed under atmospheric pressure, elevated pressure, or reduced pressure. In the present invention, however, it is preferably performed under an oxidizing atmosphere, and more preferably under atmospheric pressure. The "oxidizing atmosphere" is not particularly limited as long as it allows the formation of metal oxide crystals or mixed crystals. It may be any atmosphere in the presence of oxygen or an oxygen-containing compound. For example, an oxidizing atmosphere may be formed using an oxygen-containing carrier gas or an oxidizing agent. The film thickness can be controlled by adjusting the film formation time. In the present invention, a p-type dopant may be included in the metal oxide gas and subjected to this step to perform p-type doping. Examples of the p-type dopant include Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, Pb, N, P, and combinations of two or more of these elements. In the present invention, the p-type dopant is preferably a Group 1 or 2 metal of the periodic table, more preferably a Group 2 metal, and most preferably magnesium (Mg). In the present invention, the p-type semiconductor obtained in this step may be annealed.

[0035] The semiconductor device of the present invention typically includes an ohmic electrode. Known electrode materials may be used for the ohmic electrode, and are not particularly limited as long as they do not impede the object of the present invention. However, the ohmic electrode preferably contains a metal of Group 4 or 11 of the periodic table. The metal of Group 4 or 11 of the periodic table suitable for use in the ohmic electrode may be the same as the metal contained in the Schottky electrode. The ohmic electrode may be a single metal layer or may contain two or more metal layers. The method for forming the ohmic electrode is not particularly limited, and examples include known methods such as vacuum deposition and sputtering. The metal constituting the ohmic electrode may also be an alloy. In the present invention, the ohmic electrode preferably contains Ti and / or Au.

[0036] Preferred embodiments of the present invention will be described in more detail below with reference to the drawings, but the present invention is not limited to these embodiments.

[0037] FIG. 1 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present invention. The semiconductor device shown in FIG. 1 includes an n-type semiconductor layer 3, an electrode (barrier electrode) 2 disposed on the n-type semiconductor layer and capable of forming a Schottky barrier between the electrode (barrier electrode) 2 and the n-type semiconductor layer 3, and a p-type semiconductor disposed between the electrode (barrier electrode) 2 and the n-type semiconductor layer 3 and capable of forming a Schottky barrier between the electrode (barrier electrode) 2 and the n-type semiconductor layer 3. The p-type semiconductor 1 is stacked on the n-type semiconductor layer 3 and protrudes into the electrode (barrier electrode) 2. In the present invention, the p-type semiconductors are preferably disposed at regular intervals, and more preferably, the p-type semiconductors are disposed between both ends of the electrode (barrier electrode) and the n-type semiconductor layer. This preferred embodiment of the JBS provides excellent thermal stability and adhesion, reduces leakage current, suppresses electric field concentration, and exhibits superior semiconductor properties, such as reduced contact resistance. The semiconductor device of FIG. 1 includes an ohmic electrode 4 on the n-type semiconductor layer 3 on the side opposite to the electrode (barrier electrode) 2 side.

[0038] 1, the layers other than the p-type semiconductor may be formed by any known means without particular limitation as long as the object of the present invention is not impaired. For example, a film may be formed by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or by direct patterning using printing techniques.

[0039] A preferred manufacturing process for the semiconductor device of FIG. 1 will be described below with reference to FIG. 2. FIG. 2(a) shows a semiconductor substrate serving as an n-type semiconductor layer 3. A p-type oxide semiconductor containing gallium is then formed as a p-type semiconductor 1 on the semiconductor substrate of FIG. 1(a) by mist CVD, yielding the stack shown in FIG. 2(b). The resulting stack is then etched using photolithography to remove unnecessary portions, yielding the stack shown in FIG. 2(c). After obtaining the stack shown in FIG. 2(c), an electrode (barrier electrode) 2 is formed on the p-type semiconductor 1 and the n-type semiconductor layer 3 by the dry method (preferably vacuum deposition or sputtering) or the wet method, yielding the stack shown in FIG. 2(d). The stack shown in FIG. 2(d) has a structure in which the p-type semiconductor 1 is embedded in the n-type semiconductor layer 3 and protrudes into the electrode (barrier electrode) 2. This structure suppresses electric field concentration and reduces contact resistance, making it particularly useful for semiconductor devices with excellent voltage resistance.

[0040] FIG. 3 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present invention. The semiconductor device shown in FIG. 3 includes an n-type semiconductor layer 3, an electrode (barrier electrode) 2 disposed on the n-type semiconductor layer and capable of forming a Schottky barrier between the electrode (barrier electrode) 2 and the n-type semiconductor layer 3, and a p-type semiconductor disposed between the electrode (barrier electrode) 2 and the n-type semiconductor layer 3 and capable of forming a Schottky barrier between the electrode (barrier electrode) 2 and the n-type semiconductor layer 3. The p-type semiconductor 1 is embedded in the n-type semiconductor layer 3 and protrudes from the n-type semiconductor layer 3 into the electrode (barrier electrode) 2. In the present invention, the p-type semiconductors are preferably disposed at regular intervals, and more preferably, the p-type semiconductors are disposed between both ends of the electrode (barrier electrode) and the n-type semiconductor layer. This preferred embodiment of the JBS provides excellent thermal stability and adhesion, reduces leakage current, suppresses electric field concentration, and exhibits superior semiconductor properties such as reduced contact resistance. The semiconductor device of FIG. 3 includes an ohmic electrode 4 on the n-type semiconductor layer 3 on the side opposite to the electrode (barrier electrode) 2 side.

[0041] The means for forming each layer of the semiconductor device in FIG. 3 may include the means for forming each layer described above.

[0042] A preferred manufacturing process for the semiconductor device of FIG. 3 will be described below with reference to FIG. 4. FIG. 4(a) shows a semiconductor substrate serving as an n-type semiconductor layer 3 having multiple trenches formed on its surface. A p-type oxide semiconductor containing gallium is then deposited as a p-type semiconductor 1 on the semiconductor substrate of FIG. 4(a) by mist CVD, yielding the stack shown in FIG. 4(b). The resulting stack is then etched using photolithography to remove unnecessary portions, yielding the stack shown in FIG. 4(c). After obtaining the stack shown in FIG. 4(c), an electrode (barrier electrode) 2 is formed on the p-type semiconductor 1 and the n-type semiconductor layer 3 by the dry method (preferably vacuum deposition or sputtering) or the wet method, yielding the stack shown in FIG. 4(d). The stack shown in FIG. 4(d) has a structure in which the p-type semiconductor 1 is embedded in the n-type semiconductor layer 3 and protrudes into the electrode (barrier electrode) 2. This further suppresses electric field concentration and reduces contact resistance, making it useful for semiconductor devices with excellent breakdown voltage.

[0043] Figure 20 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present invention. The semiconductor device of Figure 20 differs from the semiconductor device of Figure 3 in that 10 or more p-type semiconductors 1 are provided. In the present invention, it is preferable that 40 or more p-type semiconductors are provided. This configuration can improve the breakdown voltage of the semiconductor device.

[0044] FIG. 5 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present invention. The semiconductor device of FIG. 5 differs from the semiconductor device of FIG. 3 in that a guard ring 5 is provided around the outer periphery of the electrode (barrier electrode). This configuration allows for a semiconductor device with superior semiconductor characteristics, such as breakdown voltage. In the present invention, as shown in FIG. 7, by burying a portion of the guard ring 5 in the surface of the n-type semiconductor layer 3, the breakdown voltage can be improved more effectively. Furthermore, by using a metal with a high barrier height for the guard ring, the guard ring can be provided industrially advantageously together with the electrode (barrier electrode), and can be formed without significantly affecting the n-type semiconductor layer or increasing the on-resistance.

[0045] The guard ring is typically made of a material with a high barrier height. Examples of materials used for the guard ring include conductive materials with a barrier height of 1 eV or more, and these materials may be the same as the electrode material. In the present invention, the material used for the guard ring is preferably a metal, as this provides high design freedom for the voltage-resistant structure, allows for the provision of multiple guard rings, and flexibly improves the voltage resistance. The shape of the guard ring is not particularly limited, and examples include a square shape, a circle, a U-shape, an L-shape, and a strip shape. In the present invention, a square shape or a circle is preferred. The number of guard rings is also not particularly limited, but is preferably three or more, more preferably six or more. In the semiconductor device of FIG. 5, the guard rings are provided on the outer periphery of the barrier electrode. However, in the present invention, the guard rings may be provided between both ends of the Schottky electrode and the n-type semiconductor layer.

[0046] A preferred manufacturing process for the semiconductor device of FIG. 7 will be described below with reference to FIGS. 13 and 14. FIG. 13(a) shows a stacked body in which an ohmic electrode 4 is stacked on a semiconductor substrate serving as an n-type semiconductor layer 3, and multiple trenches are formed on the opposite surface. Then, for the stacked body of FIG. 13(a), a p-type semiconductor 1 is formed on the n-type semiconductor layer 3 by photolithography, as shown in FIG. 13(b), and then the surface of the n-type semiconductor layer 3 is exposed, as shown in FIG. 4(c). The stacked bodies of FIGS. 13(b) and (c) have a p-type semiconductor 1, an n-type semiconductor layer 3, and an ohmic electrode 4 stacked. After obtaining the stacked body of FIG. 13(c), an electrode (barrier electrode) 2 is formed on the p-type semiconductor 1 and the n-type semiconductor layer 3 by the dry method (preferably vacuum deposition or sputtering) or the wet method, etc., to obtain the stacked body of FIG. 13(d).

[0047] The stack shown in FIG. 13(d) is then etched using photolithography to remove a portion of the electrode (barrier electrode) 2 and a portion of the n-type semiconductor layer 3, as shown in FIG. 14(e). After obtaining the stack shown in FIG. 14(e), a guard ring 5 is formed on the exposed n-type semiconductor layer 3 by the dry method (preferably vacuum deposition or sputtering) or the wet method, resulting in the stack shown in FIG. 14(f). The stack shown in FIG. 14(f) includes a guard ring 5, an electrode (barrier electrode) 2, a p-type semiconductor 1, an n-type semiconductor layer 3, and an ohmic electrode 4. After obtaining the stack shown in FIG. 14(f), etching is performed using photolithography to remove unnecessary portions, resulting in the stack shown in FIG. 14(g). The stack shown in FIG. 14(g) has a p-type semiconductor 1 embedded in the n-type semiconductor layer 3 and a guard ring 5 embedded in the periphery of the n-type semiconductor layer 3, resulting in superior breakdown voltage and other characteristics. In the above description, the guard ring 5 is formed last, but in the present invention, it is also preferable to form the guard ring 5 before forming the electrode (barrier electrode) 2. By forming it in this manner, the influence of the metal during electrode formation can be suppressed.

[0048] FIG. 6 shows a junction barrier Schottky diode (JBS) according to a preferred embodiment of the present invention. The semiconductor device of FIG. 6 differs from the semiconductor device of FIG. 1 in that a guard ring 5 is provided around the outer periphery of the electrode (barrier electrode). This configuration allows for a semiconductor device with superior semiconductor characteristics, such as breakdown voltage. In the present invention, as shown in FIG. 8, by burying a portion of the guard ring 5 in the surface of the n-type semiconductor layer 3, the breakdown voltage can be improved more effectively. Furthermore, by using a metal with a high barrier height for the guard ring, the guard ring can be provided industrially advantageously together with the electrode (barrier electrode), and can be formed without significantly affecting the n-type semiconductor layer or increasing the on-resistance.

[0049] The semiconductor device is particularly useful as a power device. Examples of the semiconductor device include diodes and transistors (e.g., MESFETs), among which diodes are preferred, and junction barrier Schottky diodes (JBSs) are more preferred.

[0050] In addition to the above features, the semiconductor device of the present invention can be suitably used as a power module, inverter, or converter using known means, and further suitably used in, for example, a semiconductor system using a power supply device. The power supply device can be fabricated from or as the semiconductor device by connecting it to a wiring pattern using known means. FIG. 9 shows an example of a power supply system. In FIG. 9, a power supply system 170 is configured using multiple power supply devices 171 and 172 and a control circuit 173. As shown in FIG. 10, the power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182. FIG. 11 shows an example of a power supply circuit diagram for a power supply device. FIG. 11 shows the power supply circuit of the power supply device, which is composed of a power circuit and a control circuit. DC voltage is switched at high frequency by an inverter 192 (comprising MOSFETs A to D) to convert it to AC, which is then insulated and transformed by a transformer 193. The rectified voltage is then rectified by rectifier MOSFETs 194 (A to B'), smoothed by a DCL 195 (smoothing coils L1 and L2) and a capacitor, and output as a DC voltage. At this time, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and rectifying MOSFET 194 so as to obtain a desired output voltage. [Example]

[0051] (Reference Example 1: Formation of p-type semiconductor and adjustment of barrier height by p-type semiconductor) In Reference Example 1, the formation of a p-type semiconductor on an n-type semiconductor layer and the adjustment of the barrier height by the p-type semiconductor were evaluated. 1-1. Formation of p-type semiconductor layer 1-1-1. Film deposition equipment 9, the mist CVD apparatus 19 used in the reference example will be described. The mist CVD apparatus 19 includes a susceptor 21 on which a substrate 20 is placed, a carrier gas supply means 22a for supplying a carrier gas, a flow rate control valve 23a for adjusting the flow rate of the carrier gas delivered from the carrier gas supply means 22a, a carrier gas (dilution) supply means 22b for supplying a carrier gas (dilution), a flow rate control valve 23b for adjusting the flow rate of the carrier gas delivered from the carrier gas (dilution) supply means 22b, a mist generating source 24 containing a raw material solution 24a, a container 25 for containing water 25a, an ultrasonic vibrator 26 attached to the bottom of the container 25, a supply pipe 27 made of a quartz tube with an inner diameter of 40 mm, and a heater 28 installed around the supply pipe 27. The susceptor 21 is made of quartz, and the surface on which the substrate 20 is placed is inclined relative to the horizontal. By fabricating both the supply pipe 27 and the susceptor 21, which form the film formation chamber, from quartz, impurities originating from the apparatus are prevented from being mixed into the film formed on the substrate 20.

[0052] 1-1-2. Preparation of raw material solution Gallium bromide and magnesium bromide were mixed with ultrapure water to prepare an aqueous solution with an atomic ratio of magnesium to gallium of 1:0.01 and gallium bromide of 0.1 mol / L. At this time, the aqueous solution contained 20% hydrohalic acid by volume, and this was used as the raw material solution.

[0053] 1-1-3. Preparation for film formation The raw material solution 24a obtained in 1-1-2 above was placed in the mist generating source 24. Next, a sapphire substrate having an n+ type semiconductor layer (α-Ga2O3) formed on its surface by mist CVD was placed on the susceptor 21 as the substrate 20, and the heater 28 was operated to raise the temperature in the film formation chamber 27 to 520°C. Next, the flow rate control valves 23a and 23b were opened to supply carrier gas from the carrier gas supply means 22a and 22b, which are carrier gas sources, into the film formation chamber 27. After the atmosphere in the film formation chamber 27 was sufficiently replaced with the carrier gas, the flow rate of the carrier gas and the flow rate of the carrier gas (diluted) were adjusted to 1 L / min, respectively. Nitrogen was used as the carrier gas.

[0054] 1-1-4. Semiconductor film formation Next, ultrasonic vibrator 26 was vibrated at 2.4 MHz, and the vibrations were propagated to raw material solution 24a through water 25a, thereby atomizing raw material solution 24a and generating mist. This mist was introduced into film formation chamber 27 by a carrier gas, and reacted in film formation chamber 27 at atmospheric pressure and 520°C to form a semiconductor film on substrate 20. The film formation time was 60 minutes.

[0055] 1-1-5.Evaluation The phase of the film obtained in 1-1-4 above was identified using an XRD diffractometer, and it was found that the film obtained using hydrobromic acid as the hydrohalic acid was α-Ga2O3.

[0056] 1-2.Evaluation To confirm whether magnesium functions normally as a p-type dopant in the p-type semiconductor layer, IV measurements were performed on the α-Ga2O3 film obtained in 1-1 above. The results of the IV measurements are shown in Figure 15. As is clear from Figure 15, excellent rectification was observed, and a good PN junction was formed between the n+ type semiconductor layer and the p-type semiconductor layer. Furthermore, since magnesium functions normally as a p-type dopant, it can be seen that the barrier height can be adjusted by forming a p-type semiconductor.

[0057] (Reference Example 2: Formation of p-type semiconductor (α-Ir2O3) and adjustment of barrier height by p-type semiconductor) In Reference Example 2, the formation of α-Ir2O3 as a p-type semiconductor on an n-type semiconductor layer and the adjustment of the barrier height by the p-type semiconductor were evaluated.

[0058] 2-1. Formation of p-type semiconductor layer 2-1-1. Film deposition equipment The film formation apparatus used in the reference example will be described with reference to Figure 19. The film formation apparatus 51 in Figure 19 includes a quartz cylinder 52 connected to a carrier gas supply source, and a quartz raw material setting table 54 inside the quartz cylinder 52, with raw material 55 placed on the raw material setting table 54. A cylindrical heater 3 is provided outside the quartz cylinder 52 around the raw material setting table, so that the raw material 55 can be heated. A quartz substrate stand is installed as a susceptor 57 at the back of the quartz cylinder 52, and the installation position of the susceptor 57 is adjusted so that the temperature is within the crystal growth temperature range.

[0059] 2-1-2. Preparation for film formation IrO2 powder was placed on a raw material setting table 54 as raw material 55, and a sapphire substrate was placed on a susceptor 57 as a substrate 56. Next, the temperature of heater 53 was raised to 850°C to heat the IrO2 powder placed on the raw material setting table 54, thereby sublimating the IrO2 powder and generating gaseous iridium oxide.

[0060] 2-1-3. Film formation Next, while maintaining the temperature of heater 53 at 850°C, carrier gas was supplied from the carrier gas supply source into quartz tube 52, and the metal oxide gas (gaseous iridium oxide) generated in 2-1-2 above was supplied to substrate 56 through quartz tube 52. The flow rate of the carrier gas was 1.0 L / min, and oxygen was used as the carrier gas. This metal oxide gas reacted near the surface of substrate 56 under atmospheric pressure, forming a film on the substrate. The film formation time was 120 minutes.

[0061] 2-2.Evaluation The film obtained in 2-1 above was identified using an X-ray diffraction device, and was found to be an α-Ir2O3 film. Furthermore, an n-type semiconductor layer and an n+-type semiconductor layer made of α-Ga2O3 film were formed on the p-type semiconductor layer obtained in 2-1 above using the mist CVD method, and then IV measurements were performed. The results showed excellent rectification, and a good PN junction was formed between the n-type and p-type semiconductor layers. It was also found that the barrier height could be adjusted by forming a p-type semiconductor.

[0062] (Example 1) Fabrication of a JBS diode 1. Formation of n+ type semiconductor layer 1-1. Film deposition equipment The mist CVD apparatus 109 used in this example will be described with reference to Figure 16. The mist CVD apparatus 109 includes a carrier gas source 22a for supplying a carrier gas, a flow rate control valve 23a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 22a, a carrier gas (diluted) source 22b for supplying a carrier gas (diluted), a flow rate control valve 23b for adjusting the flow rate of the carrier gas (diluted) delivered from the carrier gas (diluted) source 22b, a mist source 24 for containing a raw material solution 24a, a container 25 for containing water 25a, an ultrasonic vibrator 26 attached to the bottom of the container 25, a film formation chamber 30, a quartz supply pipe 27 connecting the mist source 24 to the film formation chamber 30, and a hot plate (heater) 28 installed in the film formation chamber 30. A substrate 20 is placed on the hot plate 28.

[0063] 1-2. Preparation of raw material solution Tin bromide was dissolved in a 0.1 mol / L aqueous solution of gallium bromide so that the molar ratio of gallium to tin was 1:0.12, and hydrobromic acid was added at a volume ratio of 15% to prepare a raw material solution.

[0064] 1-3. Preparation for film deposition The raw material solution 24a obtained in 1-2 above was placed in the mist generating source 24. Next, an m-plane sapphire substrate with an undoped α-GaO layer formed on its surface as a buffer layer was used as the substrate 20, and it was placed on the hot plate 28. The hot plate 28 was operated to raise the substrate temperature to 600°C. Next, the flow rate control valves 23a and 23b were opened to supply carrier gas from the carrier gas supply devices 22a and 22b, which serve as carrier gas sources, into the film formation chamber 30. After the atmosphere in the film formation chamber 30 was sufficiently replaced with the carrier gas, the flow rates of the carrier gas and the carrier gas (dilution) were adjusted to 1.0 L / min and 1.0 L / min, respectively. Nitrogen was used as the carrier gas.

[0065] 1-4. Film formation Next, ultrasonic vibrator 26 was vibrated at 2.4 MHz, and the vibrations were propagated to raw material solution 24a through water 25a, atomizing raw material solution 24a to generate mist (atomized droplets) 24b. This mist 24b was introduced into film formation chamber 30 via supply pipe 27 by a carrier gas, and the mist thermally reacted on substrate 20 at 600°C under atmospheric pressure to form a film on substrate 20. The film formation time was 1 hour. The obtained film was identified using an X-ray diffraction apparatus to be an α-Ga2O3 single crystal film.

[0066] 2. Formation of n-type semiconductor layer Gallium bromide was mixed with ultrapure water to prepare a 0.1 mol / L aqueous solution of gallium bromide as the raw material solution. A 10% volumetric hydrobromic acid solution was added, and the deposition time was 50 minutes. An n-type semiconductor layer was deposited on the n+ type semiconductor layer obtained in 1. in the same manner as in 1. above. The resulting film was identified using an X-ray diffraction apparatus and found to be an α-Ga2O3 single crystal film. The n-type semiconductor layer was patterned using a mask so that a portion of the n+ type semiconductor layer was exposed.

[0067] 3. Formation of SiO2 mask pattern An SiO2 film was formed on the n-type semiconductor layer obtained in 2 above, and then photolithography and wet etching were performed to form a mask pattern for forming a p-type buried layer.

[0068] 4.P-type semiconductor burying formation A p-type semiconductor was formed on the mask pattern obtained in 3. above in the same manner as in 1. above, except that the source solution used was a 0.1 mol / L gallium bromide aqueous solution to which magnesium bromide was dissolved, with a gallium to magnesium molar ratio of 1:0.1, with 20% hydrohalic acid added by volume, the film formation temperature was 540°C, and the film formation time was 30 minutes. The p-type semiconductor located between both ends of the Schottky electrode and the n-type semiconductor layer was formed as a guard ring. The obtained p-type semiconductor was identified using an X-ray diffraction apparatus and was found to be α-Ga2O3 single crystal.

[0069] 5. Regrowth of n-type semiconductor layer After removing the SiO2 mask pattern formed in step 3 above by etching, an n-type semiconductor layer was regrown so that part of the p-type semiconductor obtained in step 4 above was embedded in the n-type semiconductor layer. The growth of the n-type semiconductor layer was carried out in the same manner as in step 2 above, except that the film formation time was changed to 25 minutes. The number of embedded p-type semiconductors was 40.

[0070] 6. Formation of Schottky electrodes On the n-type semiconductor layer with the p-type semiconductor buried therein obtained in step 5 above, a Co film was formed as a Schottky electrode. The Co film was formed by EB evaporation. The film thickness was 200 nm.

[0071] 7. Ohmic Electrode Formation On the n+ type semiconductor layer exposed in the above step 2, a Ti film was formed as an ohmic electrode. The Ti film was formed by EB evaporation. The film thickness was 200 nm.

[0072] 8. Cross-section observation A cross section of the resulting JBS diode was observed using a TEM, and it was found that the p-type semiconductor was embedded in the n-type semiconductor layer and protruded into the Schottky electrode, as shown in Figure 18. Furthermore, it was found that the p-type semiconductor contained a good lateral growth region.

[0073] (Example 2) Fabrication of JBS diode 1. Formation of n+ type semiconductor layer The raw material solution used was a 0.1 mol / L aqueous gallium bromide solution to which tin bromide was dissolved so that the gallium to tin molar ratio was 1:1:0.04, with 15% hydrobromic acid added by volume, and the film formation time was 10 minutes. The film was formed in the same manner as in Example 1. 1. Formation of n+ type semiconductor layer. The obtained film was identified using an X-ray diffractometer and was found to be an α-Ga2O3 single crystal film.

[0074] 2. Formation of n-type semiconductor layer Except for changing the film formation time to 20 minutes, the film was formed in the same manner as in 2. Formation of n-type semiconductor layer in Example 1. The obtained film was identified using an X-ray diffractometer and was found to be an α-Ga2O3 single crystal film.

[0075] 3. Formation of trenches for burying p-type semiconductors Using photolithography and dry etching, a groove for burying a p-type semiconductor was formed in the n-type semiconductor layer obtained in 2 above.

[0076] 4.P-type semiconductor burying formation Except for the film formation time being 14 minutes, the p-type semiconductor film formed in the above 3. was formed in the same manner as in 4. Formation of embedded p-type semiconductor in Example 1. The number of embedded p-type semiconductors was 75.

[0077] 5. Formation of Schottky electrodes A Schottky electrode was formed on the n-type semiconductor layer with the p-type semiconductor buried therein, obtained in 4. above, in the same manner as in 6. Formation of Schottky electrode in Example 1.

[0078] 6. Ohmic Electrode Formation An ohmic electrode was formed on the n+ type semiconductor layer whose surface had been partially exposed by etching, in the same manner as in 7. Formation of ohmic electrode in Example 1.

[0079] 7. Cross-section observation A cross section of the resulting JBS diode was observed in the same manner as in Example 1, and it was found that the p-type semiconductor was embedded in the n-type semiconductor layer and protruded into the Schottky electrode. Furthermore, it was found that the p-type semiconductor contained a good lateral growth region.

[0080] (Comparative Example 1) Fabrication of Schottky Barrier Diode (SBD) An SBD was fabricated in the same manner as in Example 1, except that the p-type semiconductor was not formed.

[0081] (Comparative Example 2) Fabrication of JBS diode A JBS diode was fabricated in the same manner as in Example 1, except that the p-type semiconductor was formed so that it did not protrude into the electrode, and two p-type semiconductors were provided.

[0082] (evaluation) IV measurements were performed on the JBS diodes obtained in Example 2 and Comparative Example 1. The results are shown in FIG. 17. As is clear from FIG. 17, the JBS diode of Example 2 exhibits better suppression of electric field concentration and superior breakdown voltage compared to the SBD of Comparative Example 1. Furthermore, the results of the forward IV measurements indicated that the JBS diode of Example 2 had a lower contact resistance compared to the SBD of Comparative Example 1. Similar IV measurements were performed on the JBS diode of Example 1, and it was found to have electrical characteristics equivalent to those of the JBS diode of Example 2. Furthermore, it was found that the JBS diode of Comparative Example 2 had electrical characteristics equivalent to those of the SBD of Comparative Example 1. [Industrial Applicability]

[0083] The semiconductor device of the present invention can be used in a wide range of fields, including semiconductors (for example, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful as a power device. [Explanation of symbols]

[0084] 1 p-type semiconductor 2 Electrode (barrier electrode) 3 n-type semiconductor layer 4 Ohmic electrodes 5 Guard Ring 19 Mist CVD equipment 20 Substrate 21 Susceptor 22a Carrier gas supply means 22b Carrier gas (dilution) supply means 23a Flow control valve 23b Flow control valve 24 Mist source 24a Raw material solution 25 Container 25a water 26 Ultrasonic vibrator 27 Supply pipe 28 Heater 29 Exhaust port 51 Film deposition equipment 52 Quartz tube 53 Heater 54 Raw material installation table 55 Raw materials 56 Circuit Board 57 Susceptor 109 Mist CVD equipment 170 Power System 171 Power supply 172 Power supply 173 Control Circuit 180 System Unit 181 Electronic circuit 182 Power System 192 inverter 193 Trans 194 Rectifier MOSFET 195 DCL 196 PWM control circuit 197 Voltage Comparator

Claims

1. A semiconductor device in which one or more p-type semiconductors are provided between an n-type semiconductor layer and an electrode, the n-type semiconductor layer containing an oxide semiconductor as a main component, the p-type semiconductor being an oxide semiconductor, a portion of the p-type semiconductor protruding into the electrode, and another portion of the p-type semiconductor being embedded in the n-type semiconductor layer, and ten or more of the p-type semiconductors being provided.

2. A semiconductor device in which one or more p-type semiconductors are provided between an n-type semiconductor layer and an electrode, the n-type semiconductor layer containing an oxide semiconductor as a main component, the p-type semiconductor being an oxide semiconductor, a part or all of the p-type semiconductor protruding into the electrode, the electrode being a Schottky electrode in contact with an upper surface of the p-type semiconductor, and ten or more of the p-type semiconductors being provided.

3. 1. A semiconductor device comprising one or more p-type semiconductors between an n-type semiconductor layer and an electrode, wherein the n-type semiconductor layer contains an oxide semiconductor as a main component, the p-type semiconductor is an oxide semiconductor, the p-type semiconductor contains a p-type dopant, the p-type dopant containing one or more elements selected from Mg, Zn, Ca, H, Li, Na, K, Rb, Cs, Fr, Be, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Cd, Hg, Tl, Pb, N, and P, a part or all of the p-type semiconductor protrudes into the electrode, and 10 or more of the p-type semiconductors are provided.

4. 1. A semiconductor device including one or more p-type semiconductors between an n-type semiconductor layer and an electrode, wherein the n-type semiconductor layer contains an oxide semiconductor as a main component, the p-type semiconductor is an oxide semiconductor, and the p-type semiconductor contains one or more elements selected from Mg, Zn, Ca, H, Li, Na, K, Rb, Cs, Fr, Be, Sr, Ba, Ra, Mn, Pd, Cu, Ag, Au, Cd, Hg, Tl, Pb, N, and P, a part or all of the p-type semiconductor protrudes into the electrode, and 10 or more of the p-type semiconductors are provided.

5. 5. The semiconductor device according to claim 1, wherein the p-type semiconductor is an oxide semiconductor containing one or more metals selected from Groups 13 and 9 of the periodic table.

6. 1. A semiconductor device having one or more p-type semiconductors provided between an n-type semiconductor layer and an electrode, wherein the n-type semiconductor layer contains an oxide semiconductor as a main component, a part or all of the p-type semiconductor protrudes into the electrode, the p-type semiconductor is an oxide semiconductor, the p-type semiconductor contains a mixed crystal of two or more metal oxides as a main component, the metal oxides contain metals belonging to different element groups selected from Groups 8, 9, and 13 of the periodic table, and the semiconductor device has 10 or more p-type semiconductors provided.

7. 7. The semiconductor device according to claim 6, wherein the mixed crystal is an oxide semiconductor containing one or more metals selected from Groups 13 and 9 of the periodic table.

8. 8. The semiconductor device according to claim 2, wherein the p-type semiconductor is buried in the n-type semiconductor layer.

9. 9. The semiconductor device according to claim 1, wherein the n-type semiconductor layer contains a gallium compound as a main component.

10. 10. The semiconductor device according to claim 1, wherein the n-type semiconductor layer contains, as a main component, a crystalline oxide semiconductor having a corundum structure or a hexagonal structure.

11. 11. The semiconductor device according to claim 1, wherein the p-type semiconductor is an oxide semiconductor containing gallium.

12. 12. The semiconductor device according to claim 1, wherein the p-type semiconductor is a crystalline oxide semiconductor having a corundum structure or a hexagonal structure.

13. 13. The semiconductor device according to claim 1, wherein the p-type semiconductor is epitaxially grown on the n-type semiconductor layer.

14. 14. The semiconductor device according to claim 1, wherein the p-type semiconductor includes a laterally grown region.

15. 15. The semiconductor device according to claim 1, wherein the p-type semiconductor is a single crystal.

16. 16. The semiconductor device according to claim 1, wherein the n-type semiconductor layer and the p-type semiconductor layer have the same crystal structure.

17. 17. The semiconductor device according to claim 1, wherein the band gap of the p-type semiconductor is 2.4 eV or more.

18. The dopant concentration of the p-type semiconductor is 1×10 １６ / cm ３ ~1 x 10 ２２ / cm ３ The semiconductor device according to any one of claims 1 to 17, wherein

19. The semiconductor device according to any one of claims 1 to 18, which is a diode.

20. 20. The semiconductor device according to claim 1, which is a junction barrier Schottky diode.

21. The semiconductor device according to any one of claims 1 to 20, which is a power device.

22. A semiconductor system comprising a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of claims 1 to 21.

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