Image sensor including pixels containing internal capacitors

Abstract

To provide an image sensor that includes a pixel including an internal capacitor.SOLUTION: An image sensor of the present invention includes a plurality of pixels. Each of the plurality of pixels includes: a photodetection circuit which includes a photodiode and generates a detection signal; and an analog-to-digital converter which converts the detection signal using a ramp signal. The photodetection circuit includes: a floating diffusion node which accumulates photocharges generated by the photodiode and has a parasitic capacitor; and an overflow transistor which electrically connects the floating diffusion node to a first internal capacitor of the analog-to-digital converter.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to image sensors, and more particularly to image sensors including pixels that include internal capacitors. [Background technology]

[0002] An image sensor is a device that captures two-dimensional or three-dimensional images of an object. Image sensors generate images of an object using photoelectric conversion elements that react to the intensity of light reflected from the object. Recently, with the development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in a variety of electronic devices, such as digital cameras, camcorders, PCS (Personal Communication Systems), game consoles, security cameras, medical microcameras, and mobile phones.

[0003] Image sensors can increase their resolution by arranging more pixels. As the size of each pixel decreases, a pixel structure is required to efficiently increase the capacitance of the floating diffusion node. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-129795 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide an image sensor including a pixel that increases the capacitance of a floating diffusion node using an internal capacitor. [Means for solving the problem]

[0006] According to one aspect of the present invention, an image sensor is provided that includes a plurality of pixels, each of which includes a photodetection circuit including a photodiode that generates a detection signal, and an analog-to-digital converter that converts the detection signal using a ramp signal. The photodetection circuit includes a floating diffusion node that accumulates photocharges generated in the photodiode and has a parasitic capacitor, and an overflow transistor that electrically connects the floating diffusion node to a first internal capacitor of the analog-to-digital converter.

[0007] In order to achieve the above object, another aspect of the present invention provides an image sensor that operates in a plurality of modes depending on illuminance, and includes: a pixel array including a plurality of pixels, each including a photodetection circuit and an analog-to-digital converter that converts a detection signal detected by the photodetection circuit; and a pixel driver that provides an overflow control signal to the pixel array, wherein photocharges generated in the photodetection circuit in response to the overflow control signal are stored in an internal capacitor included in the analog-to-digital converter.

[0008] According to yet another aspect of the present invention, which has been made to achieve the above-mentioned object, there is provided an image sensor having a plurality of pixels, each of which includes: a photodetection circuit including a photodiode for generating a detection signal; and a pixel signal generation circuit including at least one capacitor in which a charge corresponding to the detection signal is stored, for generating a pixel signal corresponding to the detection signal, wherein the photodetection circuit includes a floating diffusion node for accumulating photocharges generated in the photodiode; and an overflow transistor electrically connecting the floating diffusion node to the at least one capacitor of the pixel signal generation circuit.

[0009] According to one aspect of the present invention, there is provided an image sensor having a plurality of pixels, each of which includes a photodetection circuit that detects an optical signal and outputs a detection signal, and a pixel signal generation circuit that outputs a pixel signal based on the detection signal. The photodetection circuit includes a photodiode that generates photocharges based on the optical signal, a floating diffusion node that accumulates the photocharges and has a parasitic capacitor, a reset transistor that resets the floating diffusion node, and an overflow transistor that electrically connects a source follower that generates a detection signal based on a voltage of the floating diffusion node, the floating diffusion node, and an output node to which the detection signal is output. [Effects of the Invention]

[0010] According to the image sensor of the present invention, by turning on / off the overflow transistor, the equivalent capacitance of the floating diffusion node FD is increased at high illumination, thereby ensuring a high dynamic range (HDR) without increasing the area of ​​the pixel PX, and by decreasing the equivalent capacitance of the floating diffusion node FD at low illumination, a high conversion gain can be obtained and a wide dynamic range (WDR) can be ensured. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating an example of an image sensor according to an embodiment of the present invention. [Figure 2] 1 is a block diagram of a first example of a portion of a pixel included in an image sensor according to an embodiment of the present invention; [Figure 3] 4 is a timing diagram illustrating control signals and ramp signals provided to pixels included in an image sensor according to an embodiment of the present invention. [Figure 4]FIG. 10 is a diagram showing the potential levels of pixels in a sampling period during an overflow operation. [Figure 5] FIG. 2 is a block diagram of a second example of a portion of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 6] FIG. 10 is a block diagram of a third example of a portion of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 7] FIG. 2 is a block diagram illustrating another example of an image sensor according to an embodiment of the present invention. [Figure 8] FIG. 10 is a block diagram of a fourth example of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 9] FIG. 10 is a block diagram of a fifth example of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram of a sixth example of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 11] FIG. 10 is a circuit diagram of a seventh example of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 12] FIG. 1 is a block diagram of an electronic device including a multi-camera module. [Figure 13] FIG. 13 is a detailed block diagram of the camera module of FIG. 12. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0013] 1 is a block diagram showing an example of an image sensor according to an embodiment of the present invention. The pixel PX shown in FIG. 1 is a digital pixel, and is used to explain an example of a pixel including a capacitor therein.

[0014] The image sensor 10 is mounted in an electronic device having an image or light sensing function. For example, the image sensor 10 is mounted in electronic devices such as a camera, a smartphone, a wearable device, an Internet of Things (IoT), a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), and a navigation device. The image sensor 10 is also mounted in electronic devices provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0015] The image sensor 10 includes a pixel array 100, a pixel driver 200, a ramp signal generator 300, a controller 400, a digital signal processing unit 500, and an interface circuit 600. The pixel array 100 includes a plurality of pixels PX, each of which is configured to sense an external optical signal and output a digital output signal DOUT corresponding to the sensed optical signal.

[0016] The pixels PX sense light signals using light-sensing elements and convert them into electrical digital output signals DOUT. Each of the pixels PX senses light in a specific spectral region. For example, the pixels PX include a red pixel that converts light in the red spectral region into an electrical signal, a green pixel that converts light in the green spectral region into an electrical signal, and a blue pixel that converts light in the blue spectral region into an electrical signal. A color filter that transmits light in the specific spectral region and a microlens for focusing the light are arranged above each of the pixels PX.

[0017] The pixel PX includes a photodetection circuit 110, an analog-to-digital converter (ADC) 120, and a memory 130. The photodetection circuit 110 includes a light-sensing element and converts an externally sensed light signal into an electrical signal, i.e., an analog signal, a detection signal. For example, the light-sensing element includes a photodiode, a phototransistor, a photogate, or a PIN photodiode (pinned photo diode). The detection signal includes a detection signal resulting from a reset operation of the pixel PX and a detection signal resulting from a light-detection operation of the pixel PX.

[0018] The ADC 120 converts the detection signal output from the photodetection circuit 110 into a digital signal, and the memory 130 stores the converted digital signal. The memory 130 outputs a digital output signal DOUT under the control of the pixel driver 200. The ADC 120 converts the detection signal into a digital signal by comparing it with a ramp signal RAMP.

[0019] The image sensor 10 according to the present invention operates in multiple operation modes depending on the illuminance. Each pixel PX has a different equivalent capacitance of a floating diffusion node, where charge corresponding to an optical signal is accumulated, depending on the operation mode. For example, in a high-illuminance environment, the image sensor 10 electrically connects the floating diffusion node of the photodetection circuit 110 to an internal capacitor included in the ADC 120, thereby relatively increasing the equivalent capacitance of the floating diffusion node. In addition, in a low-illuminance environment, the image sensor 10 electrically isolates the floating diffusion node from the internal capacitor included in the ADC 120, thereby relatively decreasing the equivalent capacitance of the floating diffusion node.

[0020] The pixel driver 200 outputs a control signal CTRL for controlling the plurality of pixels PX included in the pixel array 100. In response to the control signal CTRL generated by the pixel driver 200, each of the plurality of pixels PX generates a detection signal, converts the detection signal into a digital signal using a ramp signal RAMP, stores the digital signal, and outputs the stored digital signal as a digital output signal DOUT. In response to the control signal CTRL generated by the pixel driver 200, each of the plurality of pixels PX has a different operation mode and a different equivalent capacitance of the floating diffusion node.

[0021] The ramp signal generator 300 generates and outputs a ramp signal RAMP to the pixel array 100. The ramp signal RAMP is provided to the ADC 120 of the pixel PX and is used as a reference signal to which the detection signal is compared. In one embodiment, the ramp signal RAMP is a steadily decreasing or increasing signal (i.e., an increasing / decreasing signal with a single slope).

[0022] The controller 400 controls the overall operation of the image sensor 10. For example, the controller 400 controls the operation timing of the image sensor 10 based on control information received from an external device (e.g., an image signal processor (ISP), an application processor (AP), etc.) via the interface circuit 600. The pixel driver 200 and the ramp signal generator 300 generate a control signal CTRL and a ramp signal RAMP based on timing signals provided by the controller 400.

[0023] The digital signal processor 500 performs digital signal processing on the digital output signal DOUT received from the pixel array 100 and provides final image data ID to an external device. The digital output signal DOUT includes a reset value resulting from the reset operation of the pixel PX and an image signal value resulting from the light detection operation of the pixel PX. The digital signal processor 500 determines a final digital value corresponding to the light signal sensed by one pixel PX by performing an operation on the reset value and the image signal value. The final image data ID is generated by combining the final digital values ​​determined for each of the multiple pixels PX. That is, a correlated double sampling operation is implemented through the digital output signal DOUT generated by the operation of the ADC 120 included in the pixel PX and the digital signal processing operation of the digital signal processor 500.

[0024] The interface circuit 600 is configured to receive control information from an external device or output a final image data ID. In one embodiment, the interface circuit 600 transmits and receives detailed information to and from an external device based on a pre-defined protocol.

[0025] FIG. 2 is a block diagram of a first example of a portion of a pixel included in an image sensor according to an embodiment of the present invention. Below, the structure and operation of the pixel PX of FIG. 1 will be described based on an exemplary circuit diagram to clearly explain the technical concept of the present invention. However, the scope of the present invention is not limited thereto, and the pixel PX may be modified in various forms. The photodetector circuit 110 described in FIG. 2 is an example of the photodetector circuit 110 of FIG. 1, and the ADC 120 described in FIG. 2 is an example of the ADC 120 of FIG. 1. In addition, the reset control signal RS, the transmission control signal TS, the selection control signal SEL, the overflow control signal OFS, and the switching control signal SS described in FIG. 2 are included in the control signal CTRL of FIG. 1.

[0026] 2, the photodetection circuit 110 includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a source follower SF, and a selection transistor SX. The photodiode PD can be replaced with another photoelectric conversion element.

[0027] The photodiode PD generates photocharges that vary depending on the intensity of incident light. The transfer transistor TX transfers the photocharges to the floating diffusion node FD in response to a transfer control signal TS output from the pixel driver (200 in FIG. 1).

[0028] The floating diffusion node FD accumulates photocharges generated by the photodiode PD. The floating diffusion node FD essentially has a parasitic capacitor CFD, and photocharges are accumulated in the parasitic capacitor CFD. The reset transistor RX resets the floating diffusion node FD to the power supply voltage VDD level in response to a reset control signal RS provided from the pixel driver 200.

[0029] The source follower SF transmits the detection signal DS to the output node N0 due to the potential caused by the photocharges accumulated in the floating diffusion node FD. The source follower SF is connected to the output node N0 and provides a current path through which the current of the source follower SF flows in response to the selection control signal SEL output from the pixel driver 200.

[0030] 2, the photodetection circuit 110 of the pixel PX includes one photodiode PD and is shown as a 4T (4-transistor) structure including a transfer transistor TX, a reset transistor RX, a source follower SF, and a selection transistor SX, but each of the multiple pixels PX included in the image sensor according to the present invention is not limited to the structure shown in FIG. 2. At least one transistor among the transfer transistor TX, reset transistor RX, source follower SF, and selection transistor SX may be omitted.

[0031] The pixel PX according to the present invention includes an overflow transistor SOF connected between a floating diffusion node FD and an output node NO, and electrically connects or disconnects the floating diffusion node FD from the output node NO in response to an overflow control signal OFS output from the pixel driver 200.

[0032] The ADC 120 is, for example, a single-slope ADC. The ADC 120 includes a comparator 121, a first switch SW1, a second switch SW2, a first capacitor C1, and a second capacitor C2. The comparator 121 includes a differential amplifier. A first input terminal of the comparator 121 receives a detection signal DS as a first input signal INN through a first capacitor C1, and a second input terminal of the comparator 121 receives a ramp signal RAMP as a second input signal INP through a second capacitor C2. The comparator 121 compares the detection signal DS received through the capacitor pair (C1, C2) with the ramp signal RAMP and outputs a comparison result signal COUT.

[0033] The first capacitor C1 is a capacitor having a relatively large capacitance and is connected to the output node NO of the photodetection circuit 110. When the overflow transistor SOF is turned on, the floating diffusion node FD is connected to the output node NO, and the parasitic capacitor CFD of the floating diffusion node FD is electrically connected to the first capacitor C1 of the ADC 120. Therefore, when the overflow transistor SOF is turned on, the equivalent capacitance of the floating diffusion node FD increases, and more photocharges generated in the photodiode PD are stored in the parasitic capacitor CFD of the floating diffusion node FD and the first capacitor C1 of the ADC 120. That is, the full well capacity (FWC) of the pixel PX increases. Therefore, the image sensor according to the present invention increases the equivalent capacitance of the floating diffusion node FD under high illumination conditions by turning on / off the overflow transistor SOF, thereby ensuring a high dynamic range (HDR) without increasing the area of ​​the pixel PX. In addition, in low illumination, a high conversion gain can be obtained by reducing the equivalent capacitance of the floating diffusion node FD, thereby ensuring a wide dynamic range (WDR).

[0034] When the first switch SW1 and the second switch SW2 are turned on by the switching control signal SS, the input terminal and the output terminal of the comparator 121 are connected to each other, resetting the comparator 121. For example, the comparator 121 is reset in response to the switching control signal SS in an auto-zero period before the comparison operation of the comparator 121 is performed.

[0035] 3 is a timing diagram illustrating control signals and ramp signals provided to pixels included in an image sensor according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating potential levels of pixels during a sampling period A during an overflow operation.

[0036] 2 and 3, the pixel PX operates in a plurality of operation modes depending on the illuminance, for example, in the high illuminance operation mode, it performs the overflow operation mode and the HCG (high conversion gain) mode, while in the low illuminance operation mode, it performs only the HCG (high conversion gain) mode.

[0037] The overflow operation mode is an operation mode for sensing photocharges generated in the photodiode PD and overflowing. The overflow operation mode includes the following operations. In the overflow operation mode, the selection control signal SEL is held at a low level, and the selection transistor SX is held in an off state. When the overflow operation mode is initiated, the reset control signal RS and the transmission control signal TS are simultaneously held at a high level, thereby resetting both the photodiode PD and the floating diffusion node FD.

[0038] When the transmission control signal TS transitions from a high level to a low level, the overflow control signal OFS transitions from a low level to a high level. In response to the overflow control signal OFS, the overflow transistor SOF is turned on, connecting the floating diffusion node FD and the output node NO. The maximum charge storage capacitance (FWC) of the pixel PX is the sum of the capacitance of the parasitic capacitor CFD of the floating diffusion node FD and the capacitance of the first capacitor C1 of the ADC 120. That is, the charge overflowing from the photodiode PD is stored in the extended FWC without being drained. Increasing the FWC allows for an increase in the charge storage time.

[0039] The switching control signal SS transitions from a low level to a high level and maintains a high level before the comparator 121 performs a comparison operation, i.e., before the comparator 121 performs a sampling operation. Therefore, the input terminal of the comparator 121, to which the first input signal INN is input, and the output terminal of the comparator 121, from which the comparison result signal COUT is output, are connected, thereby stabilizing the voltage of the input terminal.

[0040] The voltage VFD at the floating diffusion node FD gradually decreases when the reset control signal RS transitions from high to low, completing the reset operation of the floating diffusion node FD and causing the charge accumulated in the photodiode PD to overflow. The voltage VFD at the floating diffusion node FD gradually decreases as the overflowed photocharges are accumulated in the floating diffusion node FD and the first capacitor C1 of the ADC 120.

[0041] 2 to 4, the switching control signal SS transitions from a high level to a low level to perform sampling in the sampling period A. At this time, the voltage level of the first input signal INN when the comparator 121 is reset is referred to as an auto-zero voltage AZV.

[0042] The floating diffusion node FD and the first capacitor C1 are charged with charges overflowing from the photodiode PD, and the first input signal INN corresponding to the amount of the charged charges Q2 is sampled as the first image signal S1.

[0043] To convert the first image signal S1, which is an analog signal, into a digital signal, the ramp signal RAMP gradually increases after an offset is added during the sampling period A. When the voltage level of the first image signal S1 becomes lower than the ramp signal RAMP, the polarity of the comparison result signal COUT of the comparator 121 changes. The first image signal S1 is converted into a digital signal based on the time T1 at which the polarity of the comparison result signal COUT changes.

[0044] When the digital conversion of the first image signal S1 is completed, the reset control signal RS transitions from low to high, the charges stored in the floating diffusion node FD and the first capacitor C1 are drained, and the voltage VFD of the floating diffusion node FD is reset to the power supply voltage VDD. The change in the voltage VFD of the floating diffusion node FD increases the voltage level of the first input signal INN, and the first input signal INN is sampled as the first reset signal R1.

[0045] To convert the analog first reset signal R1 into a digital signal, the ramp signal RAMP is gradually increased after an offset is added. When the voltage level of the first reset signal R1 becomes lower than the ramp signal RAMP, the polarity of the comparison result signal COUT of the comparator 121 changes. The first reset signal R1 is converted into a digital signal based on the time T2 when the polarity of the comparison result signal COUT changes.

[0046] 2 and 3, the HCG mode refers to a mode for sensing photocharges generated in the photodiode PD that have not overflowed. The HCG mode includes the following operations. In the HCG mode, the overflow control signal OFS is held at a low level, the overflow transistor SOF is held in an off state, and the floating diffusion node FD and the output node NO of the photodetection circuit 110 are electrically isolated. Also, in the HCG mode, the selection control signal SEL is held at a high level, and the selection transistor SX is held in an on state.

[0047] When the HCG mode is initiated, the reset control signal RS is at a high level, the floating diffusion node FD is reset, and the voltage VFD of the floating diffusion node FD is reset to the power supply voltage VDD. When the reset control signal RS transitions from a high level to a low level and the reset operation of the floating diffusion node FD is completed, the switching control signal SS transitions from a low level to a high level, and the comparator 121 is reset.

[0048] When the switching control signal SS transitions from high to low again, a comparison operation between the first input signal INN and the ramp signal RAMP is performed, and the first input signal INN is sampled as the second reset signal R2.

[0049] To convert the analog second reset signal R2 into a digital signal, the ramp signal RAMP is gradually decreased after an offset is added. When the voltage level of the second reset signal R2 becomes higher than the ramp signal RAMP, the polarity of the comparison result signal COUT of the comparator 121 changes. The second reset signal R2 is converted into a digital signal based on the point in time when the polarity of the comparison result signal COUT changes.

[0050] When the digital conversion of the second reset signal R2 is completed, the transmission control signal TS transitions from low to high, and the charge accumulated in the photodiode PD is transferred to the floating diffusion node FD. The voltage VFD at the floating diffusion node FD decreases depending on the amount of charge (e.g., Q1 in FIG. 4) accumulated in the photodiode PD. The first input signal INN corresponding to the amount of charge Q1 is sampled as the second image signal S2.

[0051] To convert the second image signal S2, which is an analog signal, into a digital signal, the ramp signal RAMP is gradually decreased after an offset is added. When the voltage level of the second image signal S2 becomes higher than the ramp signal RAMP, the polarity of the comparison result signal COUT of the comparator 121 changes. The second image signal S2 is converted into a digital signal based on the point in time when the polarity of the comparison result signal COUT changes.

[0052] The image sensor according to the present invention performs the overflow operation mode and the HCG mode in the high illumination mode, thereby detecting high illumination light without discarding the overflow charge. Also, in the HCG mode, the equivalent capacitance of the floating diffusion node FD is further reduced in the overflow operation mode, thereby increasing the potential change of the floating diffusion node FD and increasing the conversion gain. On the other hand, in the low illumination mode, the image sensor performs only the HCG mode, thereby increasing the conversion gain.

[0053] Figure 5 is a block diagram of a second example of a portion of a pixel included in an image sensor according to an embodiment of the present invention. The photodetection circuit 110a described in Figure 5 is an example of the photodetection circuit 110 in Figure 1, and in the description of Figure 5, duplicated explanations of the same reference numerals as in Figure 2 will be omitted.

[0054] 5, the photodetector circuit 110a includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a source follower SF, a select transistor SX, an overflow transistor SOF, and a conversion gain transistor DCGX. The conversion gain transistor DCGX is turned on / off by a conversion gain control signal DCGS. The control signals (RS, DCGS, TS, OFS, SEL) provided to the photodetector circuit 110a are part of the control signal CTRL generated by the pixel driver (200 in FIG. 1).

[0055] A power supply voltage VDD is applied to a first terminal of the reset transistor RX, and a second terminal thereof is connected to a reset node NR. A first terminal of the conversion gain transistor DCGT is connected to the reset node NR, and a second terminal of the conversion gain transistor DCGT is connected to a floating diffusion node FD.

[0056] The reset node NR essentially has a parasitic capacitor CDCG, and photocharges are accumulated in the parasitic capacitor CDCG. In one embodiment, the image sensor supports a dual conversion gain (DCG) function by operating in a low conversion gain (LCG) mode and an HCG mode. In the LCG mode, the conversion gain control signal DCGS is at a high level when the transmission control signal TS is held at a high level to accumulate photocharges generated in the photodiode PD in the floating diffusion node FD. While photocharges are accumulated in the parasitic capacitor CFD of the floating diffusion node FD, the conversion gain transistor DCGX is turned on, and photocharges are also accumulated in the parasitic capacitor CDCG of the conversion gain transistor DCGX. This effectively increases the equivalent capacitance of the floating diffusion node FD, thereby reducing the conversion gain.

[0057] On the other hand, in the HCG mode, when the transmission control signal TS is held at a high level, the conversion gain control signal DCGS is held at a low level, and the equivalent capacitance of the floating diffusion node FD becomes relatively small, but the conversion efficiency increases. Therefore, the image sensor according to the present invention can perform all of the overflow mode, LCG mode, and HCG mode within one frame, thereby expanding the dynamic range.

[0058] In this embodiment, an additional capacitor is further connected to the reset node NR, so that when the conversion gain transistor DCGT is turned on, the additional capacitor is electrically connected to the floating diffusion node FD, thereby further increasing the equivalent capacitance of the floating diffusion node FD.

[0059] Figure 6 is a block diagram of a third example of a portion of a pixel included in an image sensor according to an embodiment of the present invention. The photodetection circuit 110b described in Figure 6 is an example of the photodetection circuit 110 in Figure 1, and in the description of Figure 6, duplicated explanations of the same reference numerals as in Figures 2 and 5 will be omitted.

[0060] 6, the photodetector circuit 110b includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a source follower SF, a select transistor SX, and a conversion gain transistor DCGX. The control signals (RS, DCGS, TS, OFS, SEL) provided to the photodetector circuit 110b are part of the control signal CTRL generated by the pixel driver (200 in FIG. 1).

[0061] The photodetection circuit 110b further includes an overflow transistor SOFa connected between the floating diffusion node FD and the reset node NR, and electrically connects or disconnects the floating diffusion node FD and the reset node NR in response to an overflow control signal OFS output from the pixel driver (200 in FIG. 1).

[0062] In an overflow operation mode, the image sensor according to the present invention simultaneously turns on the overflow transistor SOFa and the conversion gain transistor DCGT to control the pixel so that photocharges generated in the photodiode PD and overflowing are accumulated in the parasitic capacitor CFD of the floating diffusion node FD, the parasitic capacitor CDCG of the conversion gain transistor DCGX, and the first capacitor C1 of the ADC 120. In an LCG mode, the image sensor turns off the overflow transistor SOFa and turns on the conversion gain transistor DCGT to control the pixel so that photocharges generated in the photodiode PD and overflowing are accumulated in the parasitic capacitor CFD of the floating diffusion node FD and the parasitic capacitor CDCG of the conversion gain transistor DCGX. In an HCG mode, the image sensor turns off both the overflow transistor SOFa and the conversion gain transistor DCGT to control the pixel so that photocharges generated in the photodiode PD and overflowing are accumulated only in the parasitic capacitor CFD of the floating diffusion node FD.

[0063] FIG. 7 is a block diagram illustrating another example of an image sensor according to an embodiment of the present invention. The pixel PX′ illustrated in FIG. 7 is intended to illustrate an example of a pixel including a capacitor therein, and is a pixel capable of global shutter operation. Compared to the image sensor 10 of FIG. 1, the image sensor 10′ of FIG. 7 does not include an ADC 510 within each pixel PX′, but includes an ADC 510 outside the pixel array 100′. In the description of FIG. 7, duplicated descriptions of elements that are the same as those in FIG. 1 will be omitted.

[0064] 7, the image sensor 10′ includes a pixel array 100′, a pixel driver 200′, a ramp signal generator 300′, a controller 400′, a readout circuit 500′, and an interface circuit 600′. The pixel array 100′ includes a plurality of pixels PX′, each of which is configured to sense an external optical signal and output a pixel signal PXS corresponding to the sensed optical signal.

[0065] In the pixel array 100', a plurality of pixels PX' are arranged in a matrix of a plurality of rows and a plurality of columns. The image sensor 10' controls the photocharge accumulation time of the pixels PX' arranged in different rows in a global shutter mode to be the same, thereby eliminating image distortion due to differences in photocharge accumulation time.

[0066] The pixel PX' includes a photodetection circuit 110' and a pixel signal generation circuit 120'. The photodetection circuit 110' includes a light sensing element and converts an externally sensed light signal into an electrical signal, i.e., an analog detection signal. The detection signal includes a detection signal generated by a reset operation of the photodetection circuit 110' and a detection signal generated by a photodetection operation of the photodetection circuit 110'.

[0067] The pixel signal generation circuit 120' receives the detection signal, generates a pixel signal PXS corresponding to the detection signal, and outputs the pixel signal PXS via a column line. The pixel signal generation circuit 120' includes an internal capacitor to store a charge corresponding to the detection signal. For example, the pixel signal generation circuit 120' includes a first capacitor for storing a charge corresponding to a light detection operation and a second capacitor for storing a charge corresponding to a reset operation. Because the pixel PX' includes the first capacitor and the second capacitor, the photocharge accumulation timing of the pixels PX' arranged in different rows can be controlled to be the same.

[0068] The image sensor 10′ according to the present invention operates in multiple operation modes depending on the illuminance. Each pixel PX′ has a different equivalent capacitance of a floating diffusion node, where charge corresponding to an optical signal is accumulated, depending on the operation mode. For example, in a high-illuminance environment, the image sensor 10′ electrically connects the floating diffusion node of the photodetection circuit 110′ to an internal capacitor included in the pixel signal generation circuit 120′, thereby relatively increasing the equivalent capacitance of the floating diffusion node. In addition, in a low-illuminance environment, the image sensor 10′ electrically isolates the floating diffusion node from the internal capacitor included in the pixel signal generation circuit 120′, thereby relatively decreasing the equivalent capacitance of the floating diffusion node.

[0069] The pixel driver 200′ outputs a control signal CTRL′ for controlling a plurality of pixels PX′ included in the pixel array 100′. In response to the control signal CTRL′ generated by the pixel driver 200′, each of the plurality of pixels PX′ operates in a plurality of operation modes according to illumination intensity. In one embodiment, the pixel driver 200′ determines activation and deactivation timings of the control signal CTRL′ for each of the plurality of pixels PX′ to operate in a global shutter mode.

[0070] The ramp signal generator 300′ generates a ramp signal RAMP′ and provides the ramp signal RAMP′ to a readout circuit 500′, for example, an ADC 510. The ramp signal RAMP′ is a signal for converting an analog signal into a digital signal, and is generated to have a triangular wave form.

[0071] The readout circuit 500' includes an ADC 510 and a memory 530. The ADC 510 samples and holds the pixel signal PXS provided from the pixel array 100', and performs correlated double sampling, double-sampling the reset signal and the image signal and outputting a level corresponding to the difference. The ADC 510 receives a ramp signal RAMP', compares the reset signal with the image signal, and outputs a comparison result signal. The ADC 510 converts the comparison result signal into a digital signal. The memory 530 latches the digital signal and sequentially outputs the latched image data ID.

[0072] 8 and 9 are block diagrams showing fourth and fifth examples of pixels included in an image sensor according to an embodiment of the present invention. The pixels (PX', PXa') described in FIGS. 8 and 9 are examples of pixels capable of global shutter operation, and the image sensor according to the present invention is not limited to the circuit configuration of the pixels (PX', PXa'). It is obvious that the circuit configuration of the pixel signal generation circuit 120' included in each of the pixels (PX', PXa') can be modified in various ways.

[0073] The reset control signal RS, the conversion gain control signal DCGS, the transmission control signal TS, the overflow control signal OFS, the precharge control signal PC, the sampling control signals (SAMPS1, SAMPS2), and the selection control signals (SEL1, SEL2) described in Figures 8 and 9 are included in the control signal CTRL' in Figure 7. In the description of Figures 8 and 9, duplicated explanations will be omitted for the same reference numerals as those in Figures 2, 5, and 6.

[0074] 8, the pixel PX' includes a photodetector circuit 110' and a pixel signal generator circuit 120' that outputs a first pixel signal PXS1 and a second pixel signal PXS2 based on a detection signal DS output from the photodetector circuit 110'. The photodetector circuit 110' includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a source follower SF, a precharge transistor PCX, an overflow transistor SOF, and a conversion gain transistor DCGX. The photodetector circuit 110' outputs a detection signal DS corresponding to the optical signal. However, the photodetector circuit 110' shown in FIG. 8 may not include the conversion gain transistor DCGX.

[0075] The overflow transistor SOF is connected between the floating diffusion node FD and the output node NO. The overflow transistor SOF electrically connects or disconnects the floating diffusion node FD and the output node NO in response to an overflow control signal OFS output from the pixel driver 200.

[0076] A first terminal of the precharge transistor PCX is coupled to the output node NO, and a second terminal of the precharge transistor PCX is coupled to the ground voltage. The precharge transistor PCX operates as a current source in response to a precharge control signal PC. In one embodiment, an additional transistor is coupled in series between the source follower SF and the precharge transistor PCX.

[0077] The pixel signal generating circuit 120' includes a first sampling transistor SAMP1, a second sampling transistor SAMP2, a first capacitor C1', a second capacitor C2', a first source follower SF1, a second source follower SF2, a first selection transistor SX1, and a second selection transistor SX2.

[0078] The first sampling transistor SAMP1 is connected between the output node NO and a first node N1 and is turned on / off by a first sampling control signal SAMPS1, and the second sampling transistor SAMP2 is connected between the output node NO and a second node N2 and is turned on / off by a second sampling control signal SAMPS2.

[0079] A first terminal of the first capacitor C1' is connected to the first node N1, and a power supply voltage VDD is applied to a second terminal of the first capacitor C1'. However, the second terminal of the first capacitor C1' may be grounded. When the first sampling transistor SAMP1 is turned on, charges corresponding to the detection signal DS are accumulated in the first capacitor C1'. For example, charges resulting from a photocharge accumulation operation are accumulated in the first capacitor C1'.

[0080] A first terminal of the second capacitor C2' is connected to the second node N2, and a power supply voltage VDD is applied to a second terminal of the second capacitor C2'. However, the second terminal of the second capacitor C2' may be grounded. When the second sampling transistor SAMP2 is turned on, charge corresponding to the detection signal DS is accumulated in the second capacitor C2'. For example, charge corresponding to the reset operation of the floating diffusion node FD is accumulated in the second capacitor C2'.

[0081] A first terminal of the first source follower SF1 is connected to the power supply voltage VDD, and a second terminal of the first source follower SF1 is connected to the first selection transistor SX1. The first source follower SF1 buffers a signal corresponding to the charge stored in the first capacitor C1′ and amplifies a potential change at the first node N1 to output the first pixel signal PXS1.

[0082] A first end of the first selection transistor SX1 is connected to the first source follower SF1, and a second end of the first selection transistor SX1 is connected to the first column line CL1. The first selection transistor SX1 outputs an image signal SIG generated by a photocharge accumulation operation as a first pixel signal PXS1 to the first column line CL1 in response to a first selection control signal SEL1.

[0083] The second source follower SF2 has a first terminal connected to the power supply voltage VDD and a second terminal connected to the second selection transistor SX2, and buffers a signal corresponding to the charge stored in the second capacitor C2′, amplifies a potential change at the second node N2, and outputs a second pixel signal PXS2.

[0084] The second selection transistor SX2 has a first end connected to the second source follower SF2 and a second end connected to the second column line CL2, and outputs a reset signal RST as a second pixel signal PXS2 to the second column line CL2 in response to a second selection control signal SEL2.

[0085] The first capacitor C1' has a relatively large capacitance. When the overflow transistor SOF and the first sampling transistor SAMP1 are turned on and the precharge transistor PCX is turned off, the floating diffusion node FD, the output node NO, and the first node N1 are connected, and the parasitic capacitor CFD of the floating diffusion node FD is electrically connected to the first capacitor C1' of the pixel signal generation circuit 120'. Therefore, when the overflow transistor SOF is turned on, the equivalent capacitance of the floating diffusion node FD increases, and more photocharges generated by the photodiode PD are stored in the parasitic capacitor CFD of the floating diffusion node FD and the first capacitor C1'. The maximum charge storage capacitance (FWC) of the pixel PX' increases.

[0086] In the overflow operation mode, the image sensor according to the present invention controls the pixel by turning on the conversion gain transistor DCGT, the overflow transistor SOF, and the first sampling transistor SAMP1 and turning off the precharge transistor PCX, so that the photocharges generated in the photodiode PD and overflowing are stored in the parasitic capacitor CFD of the floating diffusion node FD, the parasitic capacitor CDCG of the conversion gain transistor DCGX, and the first capacitor C1' of the pixel signal generation circuit 120'. However, without being limited thereto, the conversion gain transistor DCGT may be maintained in an off state in the overflow operation mode.

[0087] In addition, the image sensor controls the pixel in the LCG mode by turning off the overflow transistor SOF and turning on the conversion gain transistor DCGX so that photocharges generated in the photodiode PD and overflowing are accumulated in the parasitic capacitor CFD of the floating diffusion node FD and the parasitic capacitor CDCG of the conversion gain transistor DCGX. In addition, in the HCG mode, the image sensor controls the pixel by turning off both the overflow transistor SOF and the conversion gain transistor DCGT so that photocharges generated in the photodiode PD and overflowing are accumulated only in the parasitic capacitor CFD of the floating diffusion node FD.

[0088] 9, pixel PXa' includes a photodetection circuit 110a' and a pixel signal generation circuit 120' that outputs a first pixel signal PXS1 and a second pixel signal PXS2 based on a detection signal DS output from the photodetection circuit 110a'. The photodetection circuit 110a' includes a photodiode PD, a transfer transistor TX, a reset transistor RX, a source follower SF, a precharge transistor PCX, an overflow transistor SOFa, and a conversion gain transistor DCGX.

[0089] The overflow transistor SOFa electrically connects or disconnects the floating diffusion node FD and the reset node NR in response to an overflow control signal OFS output from the pixel driver (200 in FIG. 1).

[0090] In the overflow operation mode, the image sensor turns on the conversion gain transistor DCGT, the overflow transistor SOFa, and the first sampling transistor SAMP1 and turns off the precharge transistor PCX to control the pixel so that photocharges generated in the photodiode PD and overflowing are accumulated in the parasitic capacitor CFD of the floating diffusion node FD, the parasitic capacitor CDCG of the conversion gain transistor DCGX, and the first capacitor C1' of the pixel signal generation circuit 120'. In the LCG mode, the image sensor turns off the overflow transistor SOFa and turns on the conversion gain transistor DCGT to control the pixel so that photocharges generated in the photodiode PD and overflowing are accumulated in the parasitic capacitor CFD of the floating diffusion node FD and the parasitic capacitor CDCG of the conversion gain transistor DCGX. In the HCG mode, the image sensor turns off both the overflow transistor SOFa and the conversion gain transistor DCGT to control the pixel so that photocharges generated in the photodiode PD and overflowing are accumulated only in the parasitic capacitor CFD of the floating diffusion node FD.

[0091] 8 and 9, the image sensor according to the present invention increases the equivalent capacitance of the floating diffusion node FD at high illumination and decreases the equivalent capacitance of the floating diffusion node FD at low illumination by turning on / off the overflow transistors SOF and SOFa, thereby ensuring a wide dynamic range without increasing the area of ​​the pixel PX. Also, because the pixel PX′ further includes a conversion gain transistor DCGX, the image sensor operates in an overflow operation mode, an LCG mode, and an HCG mode by controlling the on / off of the overflow transistors SOF and SOFa and the conversion gain transistor DCGX.

[0092] 10 and 11 are block diagrams of sixth and seventh examples of pixels included in an image sensor according to an embodiment of the present invention. The pixels (PXb', PXc') described in FIGS. 10 and 11 are examples of pixels capable of global shutter operation, and the image sensor according to the present invention is not limited to the circuit configuration of the pixels (PXb', PXc'). It is obvious that the circuit configuration of the pixel signal generation circuit 120b' included in each of the pixels (PXb', PXc') can be modified in various ways.

[0093] The reset control signal RS, conversion gain control signal DCGS, transmission control signal TS, overflow control signal OFS, precharge control signal PC, precharge selection control signal PSEL, sampling control signals (SAMPS1, SAMPS2), and selection control signal SEL' described in Figures 10 and 11 are included in the control signal CTRL' in Figure 7. In the description of Figures 10 and 11, duplicated explanations will be omitted for the same reference symbols as those in Figures 8 and 9.

[0094] 10, pixel PXb' includes a photodetection circuit 110' and a pixel signal generation circuit 120b' that outputs a pixel signal PXS based on a detection signal DS output from the photodetection circuit 110'. The pixel signal generation circuit 120b' includes a precharge selection transistor PSEL, a first sampling transistor SAMP1, a second sampling transistor SAMP2, a first capacitor C1', a second capacitor C2', a source follower SF', and a selection transistor SX'.

[0095] The precharge selection transistor PSX is connected between the output node NO of the photodetection circuit 110′ and the sensing node NS of the pixel signal generation circuit 120b′, and is turned on or off by a precharge selection control signal PSEL to reset the sensing node NS.

[0096] The first sampling transistor SAMP1 is connected to the sensing node NS. The first sampling transistor SAMP1 is turned on / off by a first sampling control signal SAMPS1 to store charges in the first capacitor C1′ according to the detection signal DS. For example, charges due to photocharge storage are stored in the first capacitor C1′.

[0097] The second sampling transistor SAMP2 is connected to the sensing node NS. The second sampling transistor SAMP2 is turned on / off by a second sampling control signal SAMPS2 to store charges in the second capacitor C2' according to the detection signal DS. For example, charges due to a photocharge accumulation operation are stored in the second capacitor C2'. For example, charges due to a reset operation of the floating diffusion node FD are stored in the second capacitor C2'.

[0098] The source follower SF' amplifies the potential change at the sensing node NS to output a pixel signal PXS, and the selection transistor SX' outputs the pixel signal PXS to the column line CL in response to the selection control signal SEL'. The pixel signal PXS outputs an image signal SIG due to the photocharge accumulation operation and a reset signal RST due to the reset operation for the floating diffusion node FD.

[0099] In the overflow operation mode, the image sensor according to the present invention turns on the conversion gain transistor DCGT, the overflow transistor SOF, the precharge selection transistor PSX, and the first sampling transistor SAMP1, and turns off the precharge transistor PCX, thereby controlling the pixel so that the photocharges generated in the photodiode PD and overflowing are accumulated in the parasitic capacitor CFD of the floating diffusion node FD, the parasitic capacitor CDCG of the conversion gain transistor DCGX, and the first capacitor C1' of the pixel signal generation circuit 120b'. However, without being limited thereto, the conversion gain transistor DCGT may be maintained in an off state in the overflow operation mode.

[0100] In addition, the image sensor controls the pixel in the LCG mode by turning off the overflow transistor SOF and turning on the conversion gain transistor DCGT so that photocharges generated in the photodiode PD and overflowing are accumulated in the parasitic capacitor CFD of the floating diffusion node FD and the parasitic capacitor CDCG of the conversion gain transistor DCGX. In addition, in the HCG mode, the image sensor controls the pixel by turning off both the overflow transistor SOF and the conversion gain transistor DCGT so that photocharges generated in the photodiode PD and overflowing are accumulated only in the parasitic capacitor CFD of the floating diffusion node FD.

[0101] 10 and 11, pixels (PXb', PXc') include photodetection circuits (110', 110a') and a pixel signal generation circuit 120b' that outputs a pixel signal PXS based on a detection signal DS output from the photodetection circuits (110', 110a'). The image sensor according to the present invention can ensure a high dynamic range without increasing the area of ​​pixel PX by turning on / off overflow transistors (SOF, SOFa) to increase the equivalent capacitance of the floating diffusion node FD under high illumination and decrease the equivalent capacitance of the floating diffusion node FD under low illumination. Furthermore, because pixels (PXb', PXc') further include conversion gain transistors DCGX, the image sensor can operate in an overflow operation mode, an LCG mode, or an HCG mode by controlling the on / off of the overflow transistors (SOF, SOFa) and the conversion gain transistor DCGX.

[0102] Figure 12 is a block diagram of an electronic device including a multi-camera module. Figure 13 is a detailed block diagram of the camera module of Figure 12. Figure 13 describes the detailed configuration of camera module 1100b, but the following description also applies to other camera modules (1100a, 1100c) depending on the embodiment.

[0103] 12, an electronic device 1000 includes a camera module group 1100, an application processor 1200, a PMIC (power management integrated circuit) 1300, and an external memory 1400. The camera module group 1100 includes multiple camera modules (1100a, 1100b, 1100c). Although the drawing illustrates an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged, the embodiment is not limited thereto.

[0104] Referring to FIGS. 12 and 13, the camera module 1100b includes a prism 1105, an optical path folding element (hereinafter referred to as “OPFE”) 1110, an actuator 1130, an image sensing device 1140, and a storage 1150.

[0105] Prism 1105 includes a reflective surface 1107 made of a light-reflecting material and deforms the path of light L incident from outside. OPFE 1110 includes optical lenses, for example, consisting of m groups (where m is a natural number). Actuator 1130 moves OPFE 1110 or the optical lenses (hereinafter referred to as optical lenses) to a specific position.

[0106] The image sensing device 1140 includes an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 senses an image of a sensing target using light L provided through an optical lens. The image sensor 1142 is the image sensor 10 described in FIG. 1 or the image sensor 10' described in FIG. 7.

[0107] Control logic 1144 controls the overall operation of camera module 1100b, for example, via control signals provided over control signal line CSLb.

[0108] In one embodiment, one camera module (e.g., 1100b) of the multiple camera modules (1100a, 1100b, 1100c) is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a, 1100c) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the embodiment is not limited thereto.

[0109] In one embodiment, one camera module (e.g., 1100c) of the plurality of camera modules (1100a, 1100b, 1100c) is a vertical depth camera that extracts depth information using, for example, infrared rays (IR). In this case, the application processor 1200 merges image data provided from the vertical depth camera with image data provided from a different camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0110] In one embodiment, at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules (1100a, 1100b, 1100c) have different fields of view (fields of view), for example, but not limited to, at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules (1100a, 1100b, 1100c) have different optical lenses.

[0111] In one embodiment, the viewing angles of the camera modules (1100a, 1100b, 1100c) are different from each other, and in this case, the optical lenses included in the camera modules (1100a, 1100b, 1100c) are also different from each other, but this is not a limitation.

[0112] In one embodiment, each of the multiple camera modules (1100a, 1100b, 1100c) is physically separated from the other. That is, instead of the multiple camera modules (1100a, 1100b, 1100c) sharing the same sensing area of ​​a single image sensor 1142, an independent image sensor 1142 is disposed within each of the multiple camera modules (1100a, 1100b, 1100c).

[0113] 12, the application processor 1200 includes an image processing unit 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 is implemented separately from the camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c are implemented separately on separate semiconductor chips.

[0114] The image processing device 1210 includes a number of sub-image processors (1212a, 1212b, 1212c), an image generator 1214, and a camera module controller 1216.

[0115] The image processing device 1210 includes a plurality of sub-image processors (1212a, 1212b, 1212c) whose number corresponds to the number of the camera modules (1100a, 1100b, 1100c).

[0116] Image data generated from each camera module (1100a, 1100b, 1100c) is provided to the corresponding sub-image processor (1212a, 1212b, 1212c) via separate image signal lines (ISLa, ISLb, ISLc). For example, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such image data transmission is performed using, for example, a camera serial interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiment is not limited thereto.

[0117] The image data provided to each of the sub-image processors (1212a, 1212b, 1212c) is provided to an image generator 1214. The image generator 1214 generates an output image using the image data provided from each of the sub-image processors (1212a, 1212b, 1212c) in accordance with image generation information or a mode signal.

[0118] Specifically, the image generator 1214 generates an output image by merging at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles in response to the image generation information or mode signal. Also, the image generator 1214 selects one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles in response to the image generation information or mode signal to generate an output image.

[0119] The camera module controller 1216 provides control signals to each of the camera modules (1100a, 1100b, 1100c). The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules (1100a, 1100b, 1100c) via separate control signal lines (CSLa, CSLb, CSLc).

[0120] The application processor 1200 stores the received image data, i.e., the encoded data, in an internal memory 1230 provided therein or in an external memory 1400 external to the application processor 1200, and then reads and decodes the encoded data from the internal memory 1230 or the external memory 1400, and displays an image generated based on the decoded image data. For example, a corresponding sub-processor among the multiple sub-processors (1212a, 1212b, 1212c) of the image processing device 1210 performs decoding and image processing on the decoded image data.

[0121] The PMIC 1300 supplies power, e.g., a power supply voltage, to each of the multiple camera modules (1100a, 1100b, and 1100c). For example, under the control of the application processor 1200, the PMIC 1300 supplies a first power to the camera module 1100a via a power signal line PSLa, a second power to the camera module 1100b via a power signal line PSLb, and a third power to the camera module 1100c via a power signal line PSLc.

[0122] Since the resolution of an image sensor increases by arranging a large number of pixels therein, and the size of each pixel decreases accordingly, a pixel structure for efficiently increasing the capacitance of the floating diffusion node is required. The present invention provides an image sensor including a pixel that increases the capacitance of the floating diffusion node using an internal capacitor.

[0123] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0124] 10, 10' image sensor 100, 100' pixel array 110, 110a, 110b, 110', 110a' photodetection circuit 120, 120', 120b', 510 Analog-to-Digital Converter (ADC) 121 (COMP) 130, 530 memory 200, 200' pixel driver 300, 300' Ramp Signal Generator 400, 400' Controller 500 Digital Signal Processing Unit 500' Readout Circuit 600, 600' interface circuit 1000 electronic devices 1100 Camera Module Group 1100a~1100c Camera Module 1105 Prism 1107 Reflective surface 1110 Optical Path Holding Element (OPFE) 1130 Actuator 1140 Image sensing device 1142 Image Sensor 1144 Control Logic 1146 memory 1147 Calibration Data 1150 Storage 1200 Application Processor (AP) 1210 Image Processing Device 1212a~1212C Sub-Image Processor 1214 Image Generator 1216 Camera Module Controller 1220 memory controller 1230 internal memory 1300 PMIC(power management integrated circuit) 1400 external memory C1, C1' First capacitor C2, C2' Second capacitor CL Column Line CL1, CL2 1st and 2nd column lines CDCG DCGX parasitic capacitor Parasitic Capacitors in CFD COUT comparison result signal CSLa~CSLc control signal lines CTRL, CTRL' control signals DCGS Conversion gain control signal DCGX Conversion Gain Transistor DOUT Digital output signal DS detection signal FD Floating Diffusion Node ID Final image data INN, INP 1st and 2nd input signals ISLa~ISLc Image signal lines N1, N2 1st and 2nd nodes NO output node NR Reset Node NS Sensing Node OFS Overflow control signal PC Precharge control signal PCX precharge transistor PD photodiode PSLa~PSLc Power signal line PX, PX', PXa', PXb', PXc pixels PXS Pixel Signal PXS1 First pixel signal (SIG) PXS2 Second pixel signal (RST) Q1, Q2 charge amount R1, R2 First and second reset signals RAMP, RAMP' ramp signal RS Reset control signal RX reset transistor S1, S2 First and second image signals SAMP1, SAMP2 First and second sampling transistors SAMPS1, SAMPS2 First and second sampling control signals SEL, SEL' selection control signal SEL1, SEL2 First and second selection control signals SF, SF' Source Follower SF1, SF2 First and second source followers SOF, SOFa overflow transistor SS Switching control signal SX, SX' select transistors SX1, SX2 First and second select transistors SW1, SW2 1st and 2nd switches TS transmission control signal TX Transistor VDD power supply voltage VFD FD voltage

Claims

1. An image sensor comprising a plurality of pixels, Each of the plurality of pixels is a photodetection circuit including a photodiode for generating a detection signal; an analog-to-digital converter that converts the detection signal using a ramp signal; The photodetection circuit includes: a floating diffusion node that accumulates photocharges generated by the photodiode and has a parasitic capacitor; an overflow transistor electrically connecting the floating diffusion node and a first internal capacitor of the analog-to-digital converter.

2. the photodetection circuit further includes a source follower that amplifies a voltage change at the floating diffusion node and outputs the amplified voltage change to an output node; 2. The image sensor of claim 1, wherein the overflow transistor is connected between the floating diffusion node and the output node.

3. The photodetection circuit includes: a reset transistor that resets the floating diffusion node to a power supply voltage; 3. The image sensor of claim 2, further comprising: a conversion gain transistor connected between a reset node connected to one end of the reset transistor and the floating diffusion node.

4. The photodetection circuit includes: a source follower that amplifies a voltage change at the floating diffusion node and outputs the amplified voltage change to an output node; a reset transistor that resets the floating diffusion node to a power supply voltage; a conversion gain transistor connected between a reset node connected to one end of the reset transistor and the floating diffusion node, 2. The image sensor of claim 1, wherein the overflow transistor is connected between the reset node and the output node.

5. The analog-to-digital converter a second internal capacitor to which the ramp signal is input; 2. The image sensor of claim 1, further comprising: a comparator that compares the detection signal received through the first internal capacitor with the ramp signal received through the second internal capacitor and outputs a comparison result signal.

6. 2. The image sensor of claim 1, wherein the ramp signal is generated to increase at a constant gradient during an interval in which the overflow transistor is on.

7. the photodetection circuit further includes a selection transistor connected to an output node from which the detection signal is output; 2. The image sensor of claim 1, wherein the selection transistor is in an off state during a period in which the overflow transistor is in an on state.

8. An image sensor that operates in a plurality of modes depending on illuminance, a pixel array including a plurality of pixels, each including a photodetection circuit and an analog-to-digital converter for converting a detection signal detected by the photodetection circuit; a pixel driver that provides an overflow control signal to the pixel array; photocharges generated by the photodetection circuit in response to the overflow control signal are stored in an internal capacitor included in the analog-to-digital converter; In an overflow operation mode due to a high-illuminance environment, the pixel driver generates the overflow control signal so that photocharges generated in the photodetection circuit are stored in an internal capacitor included in the analog-to-digital converter; In a high conversion gain (HCG) mode in a low-light environment, the pixel driver generates the overflow control signal to electrically isolate a floating diffusion node of the photodetection circuit, where the photocharge is accumulated, from an internal capacitor included in the analog-to-digital converter.

9. 10. The image sensor of claim 8, wherein the photodetection circuit comprises an overflow transistor connected between a floating diffusion node of the photodetection circuit where the photocharges are accumulated and an output node of the photodetection circuit where the detection signal is output, and controlled by the overflow control signal.

10. The photodetection circuit a floating diffusion node that stores the photocharges and has a parasitic capacitor; a reset transistor that resets the floating diffusion node to a power supply voltage; 9. The image sensor of claim 8, further comprising: a conversion gain transistor connected between a reset node connected to one end of the reset transistor and the floating diffusion node.

11. 11. The image sensor of claim 10, wherein the photodetection circuit further comprises an overflow transistor connected between the reset node and an output node of the photodetection circuit from which the detection signal is output and controlled by the overflow control signal.

12. the analog-to-digital converter converts the detection signal into a digital signal using a ramp signal; 10. The image sensor of claim 8, wherein the analog-to-digital converter converts the detection signal according to the photocharge stored in the internal capacitor into a digital signal, and then converts the detection signal according to a reset state of the photodetection circuit into a digital signal.

13. An image sensor comprising a plurality of pixels, Each of the plurality of pixels is a photodetection circuit including a photodiode for generating a detection signal; a pixel signal generating circuit including at least one capacitor in which a charge corresponding to the detection signal is stored, and generating a pixel signal corresponding to the detection signal; The photodetection circuit includes: a floating diffusion node that accumulates photocharges generated by the photodiode; an overflow transistor electrically connecting the floating diffusion node and the at least one capacitor of the pixel signal generating circuit; a source follower that amplifies a voltage change at the floating diffusion node and outputs the amplified voltage change to an output node; a reset transistor that resets the floating diffusion node to a power supply voltage; and a conversion gain transistor connected between a reset node connected to one end of the reset transistor and the floating diffusion node.

14. The image sensor of claim 13, wherein the overflow transistor is connected between the floating diffusion node and the output node.

15. The image sensor of claim 13, wherein the overflow transistor is connected between the reset node and the output node.

16. The pixel signal generating circuit a first capacitor for storing a charge corresponding to a voltage of the floating diffusion node where the photocharges are accumulated; a second capacitor for storing a charge corresponding to the reset voltage of the floating diffusion node; 14. The image sensor of claim 13, wherein the overflow transistor electrically connects the floating diffusion node and the first capacitor.

17. 17. The image sensor of claim 16, wherein the image sensor operates in a plurality of operation modes depending on illuminance, and in a high-illuminance environment, photocharges generated in the photodetection circuit are stored in the floating diffusion node and the first capacitor.

Images