Imaging device and camera system

Abstract

Provided is an imaging device and the like that can improve reliability and suppress a decrease in conversion gain of at least some pixels. [Solution] The imaging device includes a plurality of pixels 10, including pixel 10A. Each of the plurality of pixels 10 includes a photoelectric conversion unit 12 that converts light into signal charges, a charge storage node FD that stores the signal charges, and a protection transistor 25, one of whose source and drain are electrically connected to the charge storage node FD. The gate of the protection transistor 25 of pixel 10A is electrically connected to the charge storage node FD of pixel 10B and is electrically insulated from the charge storage node FD of pixel 10A.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and a camera system. [Background technology]

[0002] 2. Description of the Related Art Imaging devices using a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor are widely used in digital cameras and the like.

[0003] Furthermore, an imaging device has been proposed that has a structure in which a photoelectric conversion unit having a photoelectric conversion layer is disposed above a semiconductor substrate. An imaging device having such a structure is sometimes called a stacked imaging device. In a stacked imaging device, signal charges generated in the photoelectric conversion unit by photoelectric conversion are accumulated in a charge accumulation region, and a signal corresponding to the amount of charge accumulated in the charge accumulation region is read out.

[0004] In an imaging device in which signal charge is accumulated in such a charge accumulation region, if the signal charge accumulates in the charge accumulation region and the absolute value of the potential of the charge accumulation region rises excessively, there is a risk that circuit elements such as transistors electrically connected to the charge accumulation region may deteriorate or be damaged.In response to this, the solid-state imaging element disclosed in Patent Document 1 has a protection transistor connected to the charge accumulation section to clip the potential of the charge accumulation section, thereby improving the reliability of the solid-state imaging element. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-209342 Summary of the Invention [Problem to be solved by the invention]

[0006] The present disclosure provides an imaging device and the like that can improve reliability and suppress a decrease in the conversion gain of at least some pixels. [Means for solving the problem]

[0007] An imaging device according to one embodiment of the present disclosure includes a plurality of pixels including a first pixel, each of the plurality of pixels including a photoelectric conversion unit that converts light into a signal charge, a charge accumulation region that accumulates the signal charge, and a first transistor having one of a source and a drain electrically connected to the charge accumulation region, and the gate of the first transistor of the first pixel is electrically connected to a node whose potential changes in response to a change in the potential of the charge accumulation region of the first pixel, and is electrically insulated from the charge accumulation region of the first pixel.

[0008] A camera system according to one aspect of the present disclosure includes the imaging device described above. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide an imaging device or the like that can improve reliability and suppress a decrease in the conversion gain of at least some pixels. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating an exemplary configuration of an imaging device according to the first embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating an exemplary circuit configuration of a pixel according to the first embodiment. [Figure 3] FIG. 3 is a schematic diagram illustrating an exemplary circuit configuration of a pixel according to Modification 1 of Embodiment 1. In FIG. [Figure 4] FIG. 4 is a schematic diagram illustrating an exemplary circuit configuration of a pixel according to Modification 2 of Embodiment 1. In FIG. [Figure 5] FIG. 5 is a schematic diagram illustrating an exemplary circuit configuration of a pixel according to Modification 3 of Embodiment 1. In FIG. [Figure 6]FIG. 6 is a schematic diagram illustrating an exemplary circuit configuration of a pixel according to the fourth modification of the first embodiment. [Figure 7] FIG. 7 is a schematic diagram illustrating an exemplary circuit configuration of a pixel according to Modification 5 of Embodiment 1. In FIG. [Figure 8] FIG. 8 is a diagram schematically showing the relationship between the potential of the charge storage node and the potential of the node between the amplification transistor and the selection transistor. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of a camera system according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] (How one aspect of the present disclosure was achieved) Before describing the embodiments of the present disclosure in detail, the process by which one aspect of the present disclosure was achieved will be described.

[0012] In an imaging device, when excessive light is incident on a photoelectric conversion unit, as described above, signal charge accumulates in the charge accumulation region, causing an excessive increase in the absolute value of the potential of the charge accumulation region, which may result in degradation or damage to circuit elements such as transistors electrically connected to the charge accumulation region. Therefore, to improve the reliability of the imaging device, it is necessary to suppress the excessive increase in the absolute value of the potential of the charge accumulation region. Therefore, providing a protection transistor for clipping the potential of the charge accumulation region, as described in Patent Document 1, is effective in improving the reliability of the imaging device. In conventional imaging devices such as the solid-state imaging element described in Patent Document 1, each pixel is provided with a charge accumulation region and a protection transistor, and the gate of the protection transistor is connected to the charge accumulation region of each pixel. In such a configuration, the gate of the protection transistor connected to the charge accumulation region also functions as a capacitance for accumulating signal charge, thereby increasing the capacitance of the charge accumulation region. As a result, even if the amount of signal charge accumulated in the charge accumulation region remains the same, the potential of the charge accumulation region is less likely to change, resulting in a problem of reduced conversion gain for each pixel in conventional imaging devices.

[0013] The present disclosure has been made based on the inventor's point of view, and provides an imaging device etc. that can improve reliability by using a protection transistor and can suppress a decrease in the conversion gain of at least some pixels.

[0014] (Summary of the Disclosure) As an overview of the present disclosure, examples of an imaging device and a camera system according to the present disclosure are shown below.

[0015] For example, an imaging device according to a first aspect of the present disclosure includes a plurality of pixels including a first pixel, each of the plurality of pixels including a photoelectric conversion unit that converts light into a signal charge, a charge accumulation region that accumulates the signal charge, and a first transistor having one of a source and a drain electrically connected to the charge accumulation region, and the gate of the first transistor of the first pixel is electrically connected to a node whose potential changes in response to a change in the potential of the charge accumulation region of the first pixel, and is electrically insulated from the charge accumulation region of the first pixel.

[0016] As a result, the potential of the charge accumulation region of the first pixel connected to one of the source and drain of the first transistor is clipped in accordance with the potential of a node connected to the gate of the first transistor and corresponding to the potential of the charge accumulation region of the first pixel. This prevents an excessive increase in the absolute value of the potential of the charge accumulation region of the first pixel, thereby improving the reliability of the imaging device. Furthermore, because the charge accumulation region of the first pixel is insulated from the gate of the first transistor, the gate of the first transistor does not function as a capacitance for accumulating signal charge in the first pixel, thereby preventing an increase in the capacitance of the charge accumulation region of the first pixel. As a result, a decrease in the conversion gain of the first pixel can be prevented. As a result, the imaging device according to this aspect can improve reliability and prevent a decrease in the conversion gain of the first pixel.

[0017] Also, for example, an imaging device according to a second aspect of the present disclosure is an imaging device according to the first aspect, wherein the plurality of pixels includes a second pixel, the node is the charge storage region of the second pixel, and the gate of the first transistor of the second pixel is electrically connected to the charge storage region of the second pixel.

[0018] This makes it possible to suppress a decrease in the conversion gain of the first pixel by utilizing the second pixel that is different from the first pixel.

[0019] Also, for example, an imaging device according to a third aspect of the present disclosure is the imaging device according to the second aspect, in which the second pixel is a dummy pixel.

[0020] This makes it possible to suppress a decrease in the conversion gain of the first pixel by using dummy pixels that do not affect the generation of an image.

[0021] Also, for example, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to the first aspect, wherein the first pixel includes a second transistor whose gate is connected to the charge storage region and which outputs a signal corresponding to the potential of the charge storage region, and the node is electrically connected to an output terminal of the second transistor.

[0022] This makes it possible to suppress a decrease in the conversion gain of the first pixel by utilizing the second transistor in the first pixel, and also makes it possible to shorten the wiring connecting the gate of the first transistor and the node.

[0023] Also, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to the second or third aspect, in which a first voltage or a ground voltage is applied to the other of the source and drain of the first transistor of the first pixel and the other of the source and drain of the first transistor of the second pixel.

[0024] This allows a fixed voltage to be supplied to the other of the source and drain of the first transistor.

[0025] Also, for example, an imaging device according to a sixth aspect of the present disclosure is an imaging device according to the second, third, or fifth aspect, in which the first pixel includes a color filter that transmits green light, and the second pixel includes a color filter that transmits light of a color different from green.

[0026] As a result, the first pixel, in which the decrease in conversion gain is suppressed, becomes a green pixel that makes a large contribution to the luminance signal, and therefore the sensitivity to the luminance signal can be increased.

[0027] Also, for example, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to the second, third, fifth or sixth aspect, in which the plurality of pixels includes a third pixel, and the gate of the first transistor of the third pixel is electrically connected to the charge storage region of the second pixel.

[0028] This makes it possible to suppress a decrease in conversion gain not only in the first pixel but also in the third pixel by utilizing the second pixel.

[0029] Also, for example, an imaging device according to an eighth aspect of the present disclosure is an imaging device according to the second, third, fifth, sixth or seventh aspect, in which the first pixel and the second pixel are adjacent to each other.

[0030] This allows the wiring connecting the gate of the first transistor of the first pixel and the charge accumulation region of the second pixel to be shortened. Although this wiring functions as a capacitance for accumulating signal charges in the second pixel, the shorter the wiring, the lower the capacitance of this wiring. Therefore, it is possible to suppress a decrease in the conversion gain of the second pixel.

[0031] Also, for example, an imaging device according to a ninth aspect of the present disclosure is the imaging device according to the second aspect, wherein the first pixel and the second pixel are adjacent to each other, the plurality of pixels include a third pixel adjacent to the first pixel and a fourth pixel adjacent to the second pixel and the third pixel, and the gate of the first transistor of the third pixel and the gate of the first transistor of the fourth pixel are electrically connected to the charge storage region of the second pixel.

[0032] This makes it possible to suppress a decrease in conversion gain not only in the first pixel but also in the third and fourth pixels by utilizing the second pixel.

[0033] Also, for example, an imaging device according to a tenth aspect of the present disclosure is an imaging device according to the ninth aspect, wherein each of the first pixel, the second pixel, the third pixel, and the fourth pixel includes a color filter that transmits light in the same wavelength band.

[0034] This makes it possible to suppress a decrease in the conversion gain of the first pixel, the third pixel, and the fourth pixel by utilizing the second pixel that outputs a signal of the same color.

[0035] Also, for example, an imaging device according to an eleventh aspect of the present disclosure is an imaging device according to the second, fifth or eighth aspect, in which when the electrical connection between the gate of the first transistor of the first pixel and the gate of the first transistor of the second pixel and the charge storage region of the second pixel is eliminated, the sensitivity of the second pixel is lower than the sensitivity of the first pixel.

[0036] This allows the second pixel, which is designed for low-sensitivity imaging, to be used to suppress a decrease in the conversion gain of the first pixel. Also, by connecting the gate of the first transistor to the charge storage region of the second pixel, the conversion gain of the second pixel is further reduced, enabling imaging over a wider dynamic range.

[0037] Also, for example, an imaging device according to a twelfth aspect of the present disclosure is an imaging device according to the first aspect, wherein the photoelectric conversion unit includes a photoelectric conversion layer that generates the signal charge, a first electrode, and a second electrode that faces the first electrode via the photoelectric conversion layer and collects the signal charge, and the node is an electrode different from the second electrode of the first pixel and is connected to an electrode that faces the first electrode via the photoelectric conversion layer.

[0038] This makes it possible to suppress a decrease in the conversion gain of the first pixel by utilizing a node connected to an electrode other than the second electrode of the first pixel and facing the first electrode via the photoelectric conversion layer.

[0039] Also, for example, a camera system according to a thirteenth aspect of the present disclosure includes the imaging device according to any one of the first to twelfth aspects.

[0040] As a result, the camera system according to this aspect includes the imaging device described above, and therefore can improve reliability and suppress a decrease in the conversion gain of at least some of the pixels.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in this specification can be combined with each other unless a contradiction arises. Furthermore, among the components in the following embodiments, components not recited in independent claims are described as optional components. In the following description, components having substantially the same functions are denoted by common reference symbols, and their description may be omitted. Furthermore, to avoid overly complicated drawings, some elements may be omitted. Furthermore, each figure is a schematic diagram and is not necessarily a precise illustration.

[0042] Furthermore, in this specification, terms indicating relationships between elements, such as "equal," terms indicating the shapes of elements, such as "square" or "circle," and numerical ranges are not expressions that express only the strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0043] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Note that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" are used not only when two components are spaced apart and another component is present between them, but also when two components are closely arranged and in contact with each other. Furthermore, in this specification, "plan view" refers to a view perpendicular to the main surface of the semiconductor substrate, in other words, when viewed from the thickness direction of the semiconductor substrate.

[0044] Furthermore, in this specification, "connection" means an electrical connection unless otherwise specified. Furthermore, in this specification, the term "node" means an electrical connection between multiple elements in an electric circuit, and is a concept that includes wiring and the like that provides the electrical connection between the multiple elements. Furthermore, in this specification, "an element being connected to a node" is an expression that can also include the case where the element is part of the node.

[0045] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used to avoid confusion between similar components and to distinguish between components.

[0046] (Embodiment 1) The imaging device according to the first embodiment will be described below.

[0047] [Overall configuration] First, the overall configuration of the imaging device according to this embodiment will be described.

[0048] Fig. 1 is a diagram showing an exemplary configuration of an imaging device 100 according to Embodiment 1. As shown in Fig. 1, the imaging device 100 includes a plurality of pixels 10 formed on a semiconductor substrate 60, and peripheral circuits including a vertical scanning circuit 40, an AD conversion circuit 42, a horizontal signal readout circuit 44, and a control circuit 46.

[0049] Each pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 generates positive and negative charges, typically hole-electron pairs, in response to incident light. The charges generated in the photoelectric conversion unit 12 are used as signal charges. That is, the photoelectric conversion unit 12 converts light into signal charges. The photoelectric conversion unit 12 is, for example, a photoelectric conversion structure including a photoelectric conversion layer disposed above a semiconductor substrate 60. The photoelectric conversion unit 12 may be a photodiode formed on the semiconductor substrate 60. Note that, in FIG. 1, the photoelectric conversion units 12 of each pixel 10 are illustrated as being spatially separated from one another; however, this is merely for convenience of explanation; the photoelectric conversion units 12 of multiple pixels 10 may be disposed continuously above the semiconductor substrate 60 without any gaps between them.

[0050] The plurality of pixels 10 are arranged in a plurality of rows and columns in a plan view. The plurality of pixels 10 are arranged, for example, two-dimensionally on the semiconductor substrate 60 to form an imaging region R1. For example, if each pixel 10 has a photoelectric conversion unit 12 arranged above the semiconductor substrate 60, the imaging region R1 can be defined as the region of the semiconductor substrate 60 that is covered by the photoelectric conversion unit 12.

[0051] The number and arrangement of the pixels 10 are not limited to the example shown in the figure. Furthermore, in the example shown in Fig. 1, the center of each pixel 10 is located on a lattice point of a square lattice, but for example, multiple pixels 10 may be arranged so that the center of each pixel 10 is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. Therefore, the column direction and the row direction do not need to be perpendicular to each other as long as they intersect.

[0052] As will be described later, each pixel 10 may have a color filter. The color filter is disposed on the light incident side of the photoelectric conversion section 12.

[0053] In the example shown in FIG. 1, the peripheral circuit includes a vertical scanning circuit 40, an AD conversion circuit 42, and a horizontal signal readout circuit 44. Also, as shown in FIG. 1, the peripheral circuit may additionally include a control circuit 46. The peripheral circuit may further include, for example, a voltage supply circuit that supplies a predetermined voltage to the pixels 10 and the like. The peripheral circuit may further include a signal processing circuit, an output circuit, and the like. The peripheral circuit is disposed, for example, in a peripheral region R2. The peripheral region R2 is a region on the semiconductor substrate 60 surrounding the imaging region R1. At least a portion of the peripheral circuit may be disposed on one or more semiconductor substrates other than the semiconductor substrate 60 on which the pixels 10 are formed. In other words, at least a portion of the peripheral circuit may not be disposed in the peripheral region R2. In this case, the one or more other semiconductor substrates may be stacked on the semiconductor substrate 60. Furthermore, a portion of the components included in the pixels 10 may also be disposed on one or more other semiconductor substrates.

[0054] The vertical scanning circuit 40, also called a row scanning circuit, is connected to row control lines 34 provided corresponding to each row of the plurality of pixels 10. For ease of viewing, only one row control line 34 is shown per row in FIG. 1, but as will be described later, the row control lines 34 may include two or more control lines per row. The vertical scanning circuit 40 applies a predetermined voltage to the row control lines 34 to select the pixels 10 row by row and cause the pixels 10 to output signals, perform reset operations, and the like.

[0055] The AD conversion circuit 42 is connected to vertical signal lines 35 provided corresponding to each column of the plurality of pixels 10. The columns of the plurality of pixels 10 and the vertical signal lines 35 correspond, for example, one-to-one. Analog signals output from the pixels 10 are input to the AD conversion circuit 42. The AD conversion circuit 42 performs noise suppression signal processing, typified by correlated double sampling, analog-to-digital (AD) conversion, and the like.

[0056] The horizontal signal readout circuit 44 is also called a column scanning circuit, and sequentially reads out the digital signals output from the AD conversion circuit 42 to a subsequent circuit (not shown).

[0057] The row control lines 34 and the vertical signal lines 35 are formed in a wiring layer on the semiconductor substrate 60, for example.

[0058] The control circuit 46 receives command data, a clock, and the like provided, for example, from outside the imaging device 100, and controls the entire imaging device 100. The control circuit 46 has, for example, a timing generator and supplies drive signals to the vertical scanning circuit 40, the AD conversion circuit 42, the horizontal signal readout circuit 44, and the like. The control circuit 46 may also control the gain of AD conversion by the AD conversion circuit 42. The control circuit 46 may be realized, for example, by a microcontroller including one or more processors. The functions of the control circuit 46 may be realized by a combination of a general-purpose processing circuit and software, or by hardware specialized for such processing.

[0059] [Circuit configuration] Next, the circuit configuration of the pixel 10 of the imaging device 100 will be described.

[0060] Fig. 2 is a schematic diagram illustrating an exemplary circuit configuration of a pixel 10 according to the present embodiment. Of the multiple pixels 10, Fig. 2 illustrates four pixels 10 arranged in two rows and two columns. For ease of viewing, Fig. 2 illustrates only the wiring and circuits necessary for explanation, and the circuit configuration of the pixel 10 may include wiring, circuits, etc. that are not illustrated in Fig. 2.

[0061] In the example shown in FIG. 2, the plurality of pixels 10 include pixel 10A, pixel 10B, pixel 10C, and pixel 10D. The pixels 10A, pixel 10B, pixel 10C, and pixel 10D are, for example, two rows and two columns of pixels 10 adjacent to one another in the row and column directions. In the example shown in FIG. 2, pixel 10A and pixel 10B are adjacent to one another. Furthermore, pixel 10B and pixel 10C are adjacent to one another. Furthermore, pixel 10C and pixel 10D are adjacent to one another. Furthermore, pixel 10A and pixel 10D are adjacent to one another. The plurality of pixels 10 are, for example, arranged two-dimensionally, with four pixels 10, pixel 10A, pixel 10B, pixel 10C, and pixel 10D, being used as a unit and repeating this unit. In the description of this embodiment, the pixels 10 will be distinguished as pixel 10A, pixel 10B, pixel 10C, and pixel 10D, as necessary. In the present embodiment, the pixel 10A and the pixel 10C are an example of a first pixel, and the pixel 10B and the pixel 10D are an example of a second pixel.

[0062] 2, the pixel 10A, the pixel 10B, the pixel 10C, and the pixel 10D each include a photoelectric conversion unit 12, a reset transistor 22, an amplification transistor 23, a selection transistor 24, a protection transistor 25, a charge storage node FD, and a color filter CF. The pixels 10A, the pixel 10B, the pixel 10C, and the pixel 10D have the same circuit configuration as one another, except for the connection configuration of the protection transistor 25, for example.

[0063] The charge accumulation node FD is connected to the photoelectric conversion unit 12 and accumulates signal charges generated by the photoelectric conversion unit 12. The charge accumulation node FD accumulates signal charges corresponding to light incident on the photoelectric conversion unit 12. The charge accumulation node FD constitutes at least a part of a charge accumulation region that accumulates signal charges. The charge accumulation node FD is also called a "floating diffusion node."

[0064] The photoelectric conversion unit 12 includes a pixel electrode 12a, a counter electrode 12c, and a photoelectric conversion layer 12b disposed between the pixel electrode 12a and the counter electrode 12c. The pixel electrode 12a, the photoelectric conversion layer 12b, and the counter electrode 12c are stacked in this order on a semiconductor substrate 60, for example. The photoelectric conversion unit 12 may further include other elements such as an electron blocking layer and a hole blocking layer. The counter electrode 12c is an example of a first electrode, and the pixel electrode 12a is an example of a second electrode.

[0065] The counter electrode 12c and the photoelectric conversion layer 12b are formed, for example, across a plurality of pixels 10. The pixel electrode 12a is provided for each pixel 10. The pixel electrode 12a is electrically isolated from the pixel electrodes 12a of other pixels 10. At least one of the counter electrode 12c and the photoelectric conversion layer 12b may be provided separately for one or more pixels 10.

[0066] The pixel electrode 12a is electrically connected to the photoelectric conversion layer 12b and serves to collect signal charges generated in the photoelectric conversion layer 12b. The pixel electrode 12a is connected to a charge storage node FD. The pixel electrode 12a is made of a conductive material. The signal charges collected by the pixel electrode 12a are stored in the charge storage node FD.

[0067] The counter electrode 12c is, for example, a transparent electrode made of a transparent conductive material. The counter electrode 12c is disposed on the light-incident side of the photoelectric conversion layer 12b. A bias voltage VITO is supplied to the counter electrode 12c. By controlling the bias voltage VITO, either the holes or the electrons of the hole-electron pairs generated in the photoelectric conversion layer 12b by photoelectric conversion can be collected by the pixel electrode 12a as signal charges. For example, when holes are used as signal charges, a bias voltage VITO that makes the counter electrode 12c higher in potential than the pixel electrode 12a can be applied to the counter electrode 12c, thereby selectively collecting holes by the pixel electrode 12a. Alternatively, by making the counter electrode 12c lower in potential than the pixel electrode 12a, the pixel electrode 12a can selectively collect electrons. The potential difference between the pixel electrode 12a and the counter electrode 12c when the pixel electrode 12a collects signal charges is, for example, 5V or more and 15V or less.

[0068] The photoelectric conversion layer 12b is a layer that absorbs photons and generates photocharges that become signal charges. Specifically, the photoelectric conversion layer 12b receives incident light and generates hole-electron pairs. That is, the signal charges are either holes or electrons. For example, when holes are used as signal charges, the holes are collected by the pixel electrode 12a. Electrons, which are charges of the opposite polarity to the signal charges, are collected by the counter electrode 12c. An example in which the signal charges are holes will be described below. The photoelectric conversion layer 12b is made of a photoelectric conversion material, and is formed, for example, from an organic semiconductor material. The photoelectric conversion layer 12b may also be formed from an inorganic semiconductor material.

[0069] The reset transistor 22, the amplification transistor 23, the selection transistor 24, and the protection transistor 25 are, for example, field effect transistors (FETs) formed on a semiconductor substrate 60 that supports the photoelectric conversion unit 12. For each of the reset transistor 22, the amplification transistor 23, the selection transistor 24, and the protection transistor 25, for example, an N-channel MOSFET (Metal Oxide Semiconductor FET) is used.

[0070] One of the source and drain of the reset transistor 22 is connected to the charge storage node FD. The other of the source and drain of the reset transistor 22 is supplied with, for example, a reset voltage VR. The other of the source and drain of the reset transistor 22 may also be connected to a feedback path that negatively feeds back the output of the pixel 10. The gate of the reset transistor 22 is connected to a reset control signal line (not shown in FIG. 2) included in the row control line 34. A reset signal RST is supplied to the gate of the reset transistor 22 from the vertical scanning circuit 40 via the reset control signal line. The reset transistor 22 is turned on, for example, when the reset signal RST is at a high level. When the reset transistor 22 is turned on, the potential of the charge storage node FD is reset to the reset voltage VR.

[0071] A power supply voltage VDD is supplied to one of the source and drain of the amplification transistor 23. The other of the source and drain of the amplification transistor 23 is connected to one of the source and drain of the selection transistor 24. The gate of the amplification transistor 23 is connected to a charge storage node FD. As a result, when the selection transistor 24 is in an on state, the amplification transistor 23 forms a source follower circuit together with a current source (not shown) connected to the vertical signal line 35. At this time, the other of the source and drain of the amplification transistor 23 outputs an analog signal corresponding to the potential of the charge storage node FD to the vertical signal line 35 via the selection transistor 24. The potential of the charge storage node FD after exposure of the pixel 10 corresponds to the amount of signal charge stored in a charge storage region that at least partially includes the charge storage node FD due to exposure.

[0072] One of the source and drain of the selection transistor 24 is connected to the other of the source and drain of the amplification transistor 23. The other of the source and drain of the selection transistor 24 is connected to a vertical signal line 35. The gate of the selection transistor 24 is connected to a selection control signal line (not shown in FIG. 2) included in the row control line 34. A selection signal SEL is supplied to the gate of the selection transistor 24 from the vertical scanning circuit 40 via the selection control signal line. When the selection signal SEL is at a high level, the selection transistor 24 is rendered conductive and outputs an analog signal from the amplification transistor 23 to the vertical signal line 35. That is, an analog signal from the pixel 10 is input to the AD conversion circuit 42 via the vertical signal line 35.

[0073] One of the source and drain of the protection transistor 25, which is an example of a first transistor, is connected to the charge storage node FD. The other of the source and drain of the protection transistor 25 is connected to ground. That is, a ground voltage is applied to the other of the source and drain of the protection transistor 25. Note that a first voltage having a magnitude different from the ground voltage, such as a power supply voltage VDD, may be applied to the other of the source and drain of the protection transistor 25.

[0074] The gate of the protection transistor 25 of pixel 10A is connected to the charge storage node FD of pixel 10B and is electrically isolated from the charge storage node FD of pixel 10A. The gate of the protection transistor 25 of pixel 10B is connected to the charge storage node FD of pixel 10B. The gate of the protection transistor 25 of pixel 10C is connected to the charge storage node FD of pixel 10D and is electrically isolated from the charge storage node FD of pixel 10C. The gate of the protection transistor 25 of pixel 10D is connected to the charge storage node FD of pixel 10D.

[0075] When the amount of light incident on the photoelectric conversion unit 12 increases, such as when high-intensity light is incident on the photoelectric conversion unit 12, the amount of holes accumulated in the charge storage node FD increases. In this case, the potential of the charge storage node FD may exceed 5 V, for example, which may destroy the gate oxide film of the amplification transistor 23 connected to the charge storage node FD. Therefore, when the potential of the charge storage node FD rises above a predetermined potential, the protection transistor 25 is made conductive. This allows the holes accumulated in the charge storage node FD to be discharged, thereby lowering the potential of the charge storage node FD.

[0076] Specifically, in pixel 10B, the gate of the protection transistor 25 is connected to the charge storage node FD of pixel 10B, so when the potential of the charge storage node FD of pixel 10B rises above a predetermined potential, the protection transistor 25 becomes conductive. As a result, the potential of the charge storage node FD of pixel 10B is clipped at the predetermined potential. This prevents damage to the amplification transistor 23 of pixel 10B. In pixel 10D, the gate of the protection transistor 25 is also connected to the charge storage node FD of pixel 10D, similar to pixel 10B.

[0077] Furthermore, in pixel 10A, the gate of the protection transistor 25 is connected to the charge storage node FD of pixel 10B. Therefore, when the potential of the charge storage node FD of pixel 10B rises above a predetermined potential, the protection transistor 25 becomes conductive. The pixels 10A and 10B are adjacent to each other in the row direction, and the potential of the charge storage node FD of pixel 10B changes in response to changes in the potential of the charge storage node FD of pixel 10A. Therefore, when the potential of the charge storage node FD of pixel 10A rises above a predetermined potential, the potential of the charge storage node FD of pixel 10B also rises above the predetermined potential at approximately the same time. Therefore, when the potential of the charge storage node FD of pixel 10A rises above approximately the predetermined potential, the protection transistor 25 of pixel 10A becomes conductive, and the potential of the charge storage node FD of pixel 10A is clipped at approximately the predetermined potential. This prevents damage to the amplification transistor 23 of pixel 10A. The pixel 10C is similar to the pixel 10A in that the gate of the protection transistor 25 is connected to the charge storage node FD of the adjacent pixel 10D. In this embodiment, the charge storage nodes FD in the pixels 10B and 10D are an example of a node. Also, the pixel electrode 12a connected to the charge storage node FD in the pixels 10B and 10D is an example of an electrode connected to a node.

[0078] Here, in pixels 10B and 10D, the gate of the protection transistor 25 is connected to its own charge storage node FD. Therefore, the gate of the protection transistor 25 also functions as a capacitance for storing signal charge, and the capacitance of the charge storage region increases in pixels 10B and 10D. If the amount of signal charge generated in the photoelectric conversion unit 12 is QPHOTO and the capacitance of the charge storage region is CFD, the amplitude VFD of the potential of the charge storage region (= the potential of the charge storage node FD) is expressed by the following equation:

[0079] VFD=QPHOTO / CFD

[0080] Therefore, when the capacitance (CFD) of the charge storage region increases as in pixels 10B and 10D, the potential of the charge storage region becomes less likely to change even with the same amount of signal charge (QPHOTO). In other words, the photoelectric conversion gain decreases. The photoelectric conversion gain can also be considered the sensitivity of pixel 10.

[0081] On the other hand, in the pixel 10A and the pixel 10C, the gate of the protection transistor 25 is electrically insulated from its own charge storage node FD. Therefore, the gate of its own protection transistor 25 does not function as a capacitance for storing signal charge, and an increase in the capacitance of the charge storage region due to the gate of the protection transistor 25 does not occur. Therefore, in the pixel 10A and the pixel 10C, a decrease in the conversion gain of photoelectric conversion can be suppressed. As described above, the imaging device 100 according to this embodiment can improve reliability by using the protection transistor 25, and can suppress a decrease in the conversion gain of the pixel 10A and the pixel 10C.

[0082] Furthermore, pixel 10A and pixel 10B are adjacent to each other. Therefore, the wiring connecting the gate of the protection transistor 25 of pixel 10A and the charge storage node FD of pixel 10B can be shortened. Although this wiring functions as a capacitance for storing signal charges in pixel 10B, the short length of this wiring can reduce the capacitance of this wiring. Therefore, a decrease in the conversion gain of pixel 10B can be suppressed. Since pixel 10C and pixel 10D are also adjacent to each other, the same can be said for pixel 10D as for pixel 10B.

[0083] In the imaging device 100, the pixels 10A and 10C have different photoelectric conversion gains than the pixels 10B and 10D. Therefore, the difference in conversion gain is adjusted by, for example, changing the AD conversion gain in the AD conversion circuit 42 or the gain for the digital signal after AD conversion for each pixel 10. The gain adjustment for the digital signal is performed by, for example, a camera signal processing circuit 604 (described later). The amount of gain adjustment is set based on the capacitance for accumulating signal charge for each pixel 10, which is determined by, for example, simulation or measurement.

[0084] 2, pixel 10A and pixel 10C are green pixels including green (G) color filters CF that transmit green light. Pixel 10B is a red pixel including red (R) color filters CF that transmit red light. Pixel 10D is a blue pixel including blue (B) color filters CF that transmit blue light. Light transmitted through the color filters CF enters photoelectric conversion unit 12. In the example shown in FIG. 2, the color filters CF are arranged in a Bayer array.

[0085] If the pixel value of a red pixel is R, the pixel value of a green pixel is G, and the pixel value of a blue pixel is B, then the luminance signal Y of the final image is expressed by, for example, the following equation.

[0086] Y=0.30R+0.59G+0.11B

[0087] Therefore, the luminance signal Y is largely contributed by green pixels, and as in the example shown in Figure 2, pixels 10A and 10C, in which the reduction in conversion gain is suppressed, are green pixels, thereby achieving increased sensitivity in the luminance signal Y.

[0088] It should be noted that at least some of the pixels 10 may not include the color filter CF.

[0089] (Modification of the first embodiment) Next, modifications of the first embodiment will be described. In the following description of the modifications, differences between the first embodiment and each modification of the first embodiment will be mainly described, and descriptions of commonalities will be omitted or simplified. The imaging device according to each modification described below differs from the imaging device 100 according to the first embodiment above mainly in that the plurality of pixels 10 include pixels 10 having circuit configurations different from those of the pixels 10A, 10B, 10C, and 10D according to the first embodiment. The imaging device according to each modification described below has a configuration in which, for example, the pixels 10A, 10B, 10C, and 10D are replaced with pixels according to each modification.

[0090] [Variation 1] Fig. 3 is a schematic diagram showing an exemplary circuit configuration of a pixel 10 according to this modification. Of the multiple pixels 10, Fig. 3 shows four pixels 10 arranged in two rows and two columns. For ease of viewing, Fig. 3 shows only the wiring and circuits necessary for explanation, and the circuit configuration of the pixel 10 may include wiring, circuits, etc. not shown in Fig. 3.

[0091] In the imaging device according to this modification, the plurality of pixels 10 include pixel 10A1, pixel 10B1, pixel 10C1, and pixel 10D1. The pixels 10A1, pixel 10B1, pixel 10C1, and pixel 10D1 are, for example, two rows and two columns of pixels 10 adjacent to one another in the row and column directions. In the example shown in FIG. 3, the pixels 10A1 and 10B1 are adjacent to one another. The pixels 10B1 and 10C1 are adjacent to one another. The pixels 10C1 and 10D1 are adjacent to one another. The pixels 10A1 and 10D1 are adjacent to one another. In this modification, the plurality of pixels 10 are, for example, two-dimensionally arranged such that four pixels 10, pixel 10A1, pixel 10B1, pixel 10C1, and pixel 10D1, are repeated as a unit. In the description of this modification, the pixel 10 will be distinguished as pixel 10A1, pixel 10B1, pixel 10C1, and pixel 10D1 as necessary. In this modification, pixel 10C1 is an example of a first pixel, pixel 10D1 is an example of a second pixel, pixel 10B1 is an example of a third pixel, and pixel 10A1 is an example of a fourth pixel.

[0092] As shown in FIG. 3, pixels 10A1, 10B1, 10C1, and 10D1 according to this modification are the same as pixels 10A, 10B, 10C, and 10D according to embodiment 1, except that the connection configuration of protection transistor 25 is different.

[0093] The gate of the protection transistor 25 of the pixel 10A1 is connected to the charge storage node FD of the pixel 10D1 and is electrically insulated from the charge storage node FD of the pixel 10A1. The gate of the protection transistor 25 of the pixel 10B1 is connected to the charge storage node FD of the pixel 10D1 and is electrically insulated from the charge storage node FD of the pixel 10B1. The gate of the protection transistor 25 of the pixel 10C1 is connected to the charge storage node FD of the pixel 10D1 and is electrically insulated from the charge storage node FD of the pixel 10C1. The gate of the protection transistor 25 of the pixel 10D1 is connected to the charge storage node FD of the pixel 10D1. In this modification, the charge storage node FD of the pixel 10D1 is an example of a node. Furthermore, the pixel electrode 12a connected to the charge storage node FD of the pixel 10D1 is an example of an electrode connected to a node.

[0094] In this modification, in the pixel 10A1, the pixel 10B1, and the pixel 10C1, the gate of the protection transistor 25 is electrically insulated from its own charge storage node FD. Therefore, it is possible to suppress a decrease in the conversion gain of photoelectric conversion in three of the four pixels 10 shown in FIG. 3, namely, the pixel 10A1, the pixel 10B1, and the pixel 10C1.

[0095] 3, pixel 10A1 and pixel 10C1 are green pixels including green (G) color filters CF that transmit green light. Pixel 10B1 is a red pixel including red (R) color filters CF that transmit red light. Pixel 10D1 is a blue pixel including blue (B) color filters CF that transmit blue light. Therefore, the reduction in conversion gain is suppressed in green pixels, which have a large contribution to the luminance signal Y, and in red pixels, which have the second largest contribution to the luminance signal Y after green pixels, and thus the sensitivity to the luminance signal Y can be increased.

[0096] [Variation 2] Fig. 4 is a schematic diagram showing an exemplary circuit configuration of a pixel 10 according to this modification. Of the multiple pixels 10, Fig. 4 shows four pixels 10 arranged in two rows and two columns. For ease of viewing, Fig. 4 shows only the wiring and circuits necessary for explanation, and the circuit configuration of the pixel 10 may include wiring, circuits, etc. not shown in Fig. 4.

[0097] In the imaging device according to this modification, the plurality of pixels 10 include pixels 10A2, 10B2, 10C2, and 10D2. The pixels 10A2, 10B2, 10C2, and 10D2 are, for example, two rows and two columns of pixels 10 adjacent to one another in the row and column directions. In the example shown in FIG. 4, the pixels 10A2 and 10B2 are adjacent to one another. The pixels 10B2 and 10C2 are also adjacent to one another. The pixels 10C2 and 10D2 are also adjacent to one another. The pixels 10A2 and 10D2 are also adjacent to one another. In this modification, the plurality of pixels 10 are arranged two-dimensionally, for example, with four pixels 10, i.e., the pixels 10A2, 10B2, 10C2, and 10D2, as a unit, and the wavelength bands transmitted by the color filters CF are repeatedly changed in this unit. In the description of this modification, the pixel 10 will be distinguished as pixel 10A2, pixel 10B2, pixel 10C2, and pixel 10D2 as necessary. In this modification, pixel 10C2 is an example of a first pixel, pixel 10D2 is an example of a second pixel, pixel 10B2 is an example of a third pixel, and pixel 10A2 is an example of a fourth pixel.

[0098] As shown in FIG. 4, pixels 10A2, 10B2, 10C2, and 10D2 according to this modification are the same as pixels 10A1, 10B1, 10C1, and 10D1 according to modification 1 of embodiment 1, except that the wavelength bands transmitted by the color filters CF are different.

[0099] Pixels 10A2, 10B2, 10C2, and 10D2 according to this modification have the same circuit configuration as pixels 10A1, 10B1, 10C1, and 10D1 according to Modification 1 of Embodiment 1. Therefore, a decrease in the conversion gain of photoelectric conversion can be suppressed in three of the four pixels 10 shown in FIG. 4: pixel 10A2, pixel 10B2, and pixel 10C2. In this modification, the charge storage node FD in pixel 10D2 is an example of a node. Furthermore, pixel electrode 12a connected to charge storage node FD in pixel 10D2 is an example of an electrode connected to a node.

[0100] Each of the pixels 10A2, 10B2, 10C2, and 10D2 includes a color filter CF that transmits light of the same wavelength band. In the example shown in FIG. 4, each of the pixels 10A2, 10B2, 10C2, and 10D2 is a green pixel that includes a green (G) color filter CF that transmits green light. When the multiple pixels 10 include the pixels 10A2, 10B2, 10C2, and 10D2 shown in FIG. 4, the color filters CF are arranged in a quad-Bayer array, in which color filters CF of the same color are arranged in four adjacent pixels 10 arranged in two rows and two columns. That is, the multiple pixels 10 include four blue pixels arranged in two rows and two columns (not shown) and four red pixels arranged in two rows and two columns (not shown). In this modified example, the reduction in the photoelectric conversion gain can be suppressed in three of the four pixels 10 having color filters CF of the same color, and the effect of reduced sensitivity due to the protection transistor 25 of the pixels 10 of each color as a whole can be suppressed.

[0101] The gates of the protection transistors 25 of the pixels 10A2, 10B2, and 10C2 are connected to the charge storage node FD of the pixel 10D2 that has a color filter CF of the same color.

[0102] [Variation 3] Fig. 5 is a schematic diagram showing an exemplary circuit configuration of a pixel 10 according to this modification. Note that Fig. 5 shows two pixels 10 out of the multiple pixels 10. For ease of viewing, Fig. 5 shows only the wiring and circuits necessary for explanation, and the circuit configuration of the pixel 10 may include wiring, circuits, etc. that are not shown in Fig. 5.

[0103] In the imaging device according to this modification, the plurality of pixels 10 include a pixel 10A3 and a pixel 10B3. In the example shown in FIG. 5, the pixel 10A3 and the pixel 10B3 are adjacent to each other. In this modification, the plurality of pixels 10 are arranged two-dimensionally, for example, with two pixels 10, the pixel 10A3 and the pixel 10B3, being used as a unit and being repeated in this unit. In the description of this modification, the pixels 10 will be distinguished as the pixel 10A3 and the pixel 10B3 as necessary. In this modification, the pixel 10A3 is an example of a first pixel, and the pixel 10B3 is an example of a second pixel.

[0104] 5, the pixel 10A3 has a circuit configuration similar to that of the pixel 10A according to embodiment 1. The pixel 10B3 has a circuit configuration that further includes a capacitive element 26 in addition to the circuit configuration of the pixel 10B according to embodiment 1.

[0105] One end of the capacitance element 26 is connected to the charge storage node FD. A reference voltage VS is supplied to the other end of the capacitance element 26. The capacitance element 26 is, for example, a metal-oxide-metal (MOM) capacitance, a metal-insulator-metal (MIM) capacitance, a metal-oxide semiconductor (MOS) capacitance, or a trench capacitance.

[0106] The capacitive element 26 functions as an additional capacitance for storing signal charge in the pixel 10B3. In other words, the capacitive element 26 reduces the conversion gain of the photoelectric conversion of the pixel 10B3. Therefore, the pixel 10B3 is a low-sensitivity pixel having lower sensitivity than the pixel 10A3. In the imaging device according to this modification, the multiple pixels 10 include the pixel 10A3, which is a high-sensitivity pixel having a relatively high sensitivity, and the pixel 10B3, which is a low-sensitivity pixel having a relatively low sensitivity, thereby enabling wide dynamic range imaging. Note that the sensitivity of the pixel 10 also changes depending on the connection configuration between the charge storage node FD and the gate of the protection transistor 25. Therefore, this comparison of sensitivity is based on the assumption that the electrical connection between the charge storage node FD and the gate of the protection transistor 25 is eliminated.

[0107] The gate of the protection transistor 25 of the pixel 10A3 is connected to the charge storage node FD of the pixel 10B3 and is electrically insulated from the charge storage node FD of the pixel 10A3. The gate of the protection transistor 25 of the pixel 10B3 is connected to the charge storage node FD of the pixel 10B3. In this modification, the charge storage node FD of the pixel 10B3 is an example of a node. Furthermore, the pixel electrode 12a connected to the charge storage node FD of the pixel 10B3 is an example of an electrode connected to a node.

[0108] In this modification, the gate of the protection transistor 25 in the pixel 10A3 is electrically insulated from its own charge storage node FD. This prevents a decrease in the conversion gain of photoelectric conversion in the pixel 10A3, which is a high-sensitivity pixel. On the other hand, because the gate of the protection transistor 25 in the pixel 10A3 is connected to the charge storage node FD in the pixel 10B3, the conversion gain of photoelectric conversion in the pixel 10B3, which is a low-sensitivity pixel, is reduced, enabling imaging over a wider dynamic range.

[0109] In this modification, even if the same amount of signal charge is generated in the photoelectric conversion unit 12 of the pixel 10A3 and the pixel 10B3, the potential of the charge storage node FD will differ significantly due to the influence of the capacitive element 26. As a result, when the protection transistors 25 of both the pixel 10A3 and the pixel 10B3 are operated based on the potential of the charge storage node FD of the pixel 10B3, the potential of the charge storage node FD of the pixel 10A3 may rise excessively depending on the capacitance of the capacitive element 26. Therefore, the operating voltages of the protection transistors 25 of the pixel 10A3 and the pixel 10B3 may be adjusted to be different, as necessary, for example, by designing the protection transistor 25 of the pixel 10A3 so that its threshold voltage is lower than that of the protection transistor 25 of the pixel 10B3. Furthermore, the operating voltage of the protection transistor 25 may be adjusted by adjusting the voltage applied to the other of the source and drain of the protection transistor 25, in addition to or instead of designing the protection transistor 25. Furthermore, the adjustment of the operating voltage of the protection transistor 25 between the pixels 10 may be performed in the imaging devices according to the modifications other than the first embodiment and the third modification of the first embodiment.

[0110] 5, the sensitivity of pixel 10B3 is reduced by including capacitive element 26, but this is not limiting. For example, the sensitivity of pixel 10B3 may be reduced by reducing the area of ​​pixel electrode 12a of pixel 10B3.

[0111] [Variation 4] Fig. 6 is a schematic diagram showing an exemplary circuit configuration of a pixel 10 according to this modification. Note that Fig. 6 shows five of the multiple pixels 10. For ease of viewing, Fig. 6 shows only the wiring and circuits necessary for explanation, and the circuit configuration of the pixel 10 may include wiring, circuits, etc. that are not shown in Fig. 6.

[0112] In the imaging device according to this modification, the plurality of pixels 10 include pixel 10A4, pixel 10B4, pixel 10C4, pixel 10D4, and pixel 10E4. In the example shown in FIG. 6, pixel 10A4 and pixel 10B4 are adjacent to each other. Furthermore, pixel 10B4 and pixel 10E4 are adjacent to each other. Furthermore, pixel 10E4 and pixel 10C4 are adjacent to each other. Furthermore, pixel 10C4 and pixel 10D4 are adjacent to each other. In this modification, the plurality of pixels 10 are arranged two-dimensionally, for example, with five pixels 10, i.e., pixel 10A4, pixel 10B4, pixel 10C4, pixel 10D4, and pixel 10E4, being repeated in this unit. In the description of this modification, the pixels 10 will be distinguished as pixel 10A4, pixel 10B4, pixel 10C4, pixel 10D4, and pixel 10E4, as necessary. In this modification, pixel 10C4 is an example of a first pixel, and pixel 10E4 is an example of a second pixel.

[0113] As shown in FIG. 6, pixels 10A4, 10B4, 10C4, and 10D4 according to this modification are the same as pixels 10A, 10B, 10C, and 10D according to embodiment 1, except that the connection configuration of the protection transistor 25 is different.

[0114] The pixel 10E4 includes a photoelectric conversion unit 12, a reset transistor 22, a protection transistor 25, and a charge accumulation node FD. The pixel 10E4 is a dummy pixel in which the signal charge generated by the photoelectric conversion unit 12 does not contribute to the generation of an image by the imaging device. The pixel 10E4, which is a dummy pixel, only needs to include at least the photoelectric conversion unit 12 and the charge accumulation node FD. The pixel 10E4 does not output an analog signal corresponding to the potential of the charge accumulation node FD, for example, by not including the amplification transistor 23 or the selection transistor 24. Note that the pixel 10E4 may include at least one of the amplification transistor 23, the selection transistor 24, and the color filter CF, as long as the signal charge generated by the photoelectric conversion unit 12 of the pixel 10E4 does not contribute to the generation of an image by the imaging device.

[0115] The gate of the protection transistor 25 of the pixel 10A4 is connected to the charge storage node FD of the pixel 10E4 and is electrically insulated from the charge storage node FD of the pixel 10A4. The gate of the protection transistor 25 of the pixel 10B4 is connected to the charge storage node FD of the pixel 10E4 and is electrically insulated from the charge storage node FD of the pixel 10B4. The gate of the protection transistor 25 of the pixel 10C4 is connected to the charge storage node FD of the pixel 10E4 and is electrically insulated from the charge storage node FD of the pixel 10C4. The gate of the protection transistor 25 of the pixel 10D4 is connected to the charge storage node FD of the pixel 10E4 and is electrically insulated from the charge storage node FD of the pixel 10D4. The gate of the protection transistor 25 of the pixel 10E4 is connected to the charge storage node FD of the pixel 10E4. In this modification, the charge storage node FD of the pixel 10E4 is an example of a node. Furthermore, the pixel electrode 12a connected to the charge storage node FD in the pixel 10E4 is an example of an electrode connected to a node.

[0116] In this modification, in pixels 10A4, 10B4, 10C4, and 10D4, which are effective pixels that output signals for generating an image, the gates of the protection transistors 25 are electrically insulated from their own charge storage nodes FD. Furthermore, the gates of the protection transistors 25 in pixels 10A4, 10B4, 10C4, and 10D4 are connected to the charge storage node FD of pixel 10E4, which is a dummy pixel. Therefore, in this modification, while the provision of the protection transistor 25 prevents damage to the amplification transistor 23, a decrease in the gain of photoelectric conversion occurs in the dummy pixels, and a decrease in the conversion gain of photoelectric conversion is suppressed in the effective pixels.

[0117] [Variation 5] Fig. 7 is a schematic diagram illustrating an exemplary circuit configuration of a pixel 10 according to this modification. Note that Fig. 7 illustrates one pixel 10 out of multiple pixels 10. For ease of viewing, Fig. 7 illustrates only the wiring and circuits necessary for explanation, and the circuit configuration of the pixel 10 may include wiring, circuits, etc. that are not illustrated in Fig. 7.

[0118] In the imaging device according to this modification, the plurality of pixels 10 includes a pixel 10A5 as the pixel 10. For example, in this modification, each of the plurality of pixels 10 is a pixel 10A5. Also, in this modification, the pixel 10A5 is an example of a first pixel.

[0119] 7, the circuit configuration of the pixel 10A5 according to this modification is the same as that of the pixel 10A according to the first embodiment, except that the gate of the protection transistor 25 is connected to a node N0 between the amplification transistor 23 and the selection transistor 24. The node N0 is connected to the other of the source and drain of the amplification transistor 23 and one of the source and drain of the selection transistor 24.

[0120] The gate of the protection transistor 25 of the pixel 10A5 is connected to a node N0 connected to the other of the source and drain, which is the output terminal of the amplification transistor 23 of the pixel 10A5. In this modification, the amplification transistor 23 of the pixel 10A5 is an example of a second transistor.

[0121] FIG. 8 is a diagram schematically illustrating the relationship between the potential of the charge storage node FD and the potential of node N0. In FIG. 8, the horizontal axis represents the potential of the charge storage node FD, and the vertical axis represents the potential of node N0. The potential of node N0 is the same as the signal output from the output terminal of the amplification transistor 23 depending on the potential of the charge storage node FD. Therefore, as shown in FIG. 8, the potential of node N0 varies linearly with respect to the charge storage node FD until it exceeds the power supply voltage VDD. Therefore, in pixel 10A5, when the potential of node N0 rises above a predetermined potential, protection transistor 25 becomes conductive, and the potential of the charge storage node FD is clipped to a potential corresponding to the predetermined potential of node N0. This prevents damage to the amplification transistor 23 of pixel 10A5.

[0122] As described above, the potential of node N0 does not exceed the power supply voltage VDD. On the other hand, the potential of charge storage node FD can rise up to the bias voltage VITO, and therefore can rise to a voltage higher than the power supply voltage VDD. Therefore, the pixel 10A5 uses, for example, a protection transistor 25 whose threshold voltage is adjusted to be equal to or lower than the power supply voltage VDD by design. Furthermore, the operating voltage of the protection transistor 25 may be adjusted by adjusting the voltage applied to the other of the source and drain of the protection transistor 25, in addition to or instead of the design of the protection transistor 25.

[0123] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, a camera system including an imaging device according to the present disclosure will be described.

[0124] FIG. 9 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

[0125] 9, camera system 400 according to this embodiment includes lens optical system 601, imaging device 602, system controller 603, and camera signal processing circuit 604. Camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0126] The lens optical system 601 focuses light onto an imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The imaging device 602 may be, for example, an imaging device according to any one of the above-described first embodiment and modifications 1 to 5 of the first embodiment.

[0127] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0128] The camera signal processing circuit 604 has a function of processing an output signal from the image capture device 602. The camera signal processing circuit 604 receives output data such as a differential digital signal from the image capture device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 may generate the above-described luminance signal Y based on the output signal from the image capture device 602. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The image capture device 602 and the camera signal processing circuit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 602 as a part thereof.

[0129] (Other embodiments) While the imaging device and camera system according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included within the scope of the present disclosure.

[0130] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents. [Industrial Applicability]

[0131] The imaging device according to the present disclosure is useful, for example, in image sensors, digital cameras, etc. The imaging device according to the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc. [Explanation of symbols]

[0132] 10, 10A, 10B, 10C, 10D, 10A1, 10B1, 10C1, 10D1, 10A2, 10B2, 10C2, 10D2, 10A3, 10B3, 10A4, 10B4, 10C4, 10D4, 10E4, 10A5 pixels 12 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c Counter electrode 22 Reset transistor 23 Amplifying transistor 24 Select transistor 25 Protection transistor 26 Capacitor element 34 Row Control Line 35 Vertical signal line 40 Vertical scanning circuit 42 AD conversion circuit 44 Horizontal signal readout circuit 46 Control circuit 60 Semiconductor substrate 100, 602 Imaging device 400 Camera System 601 Lens Optical System 603 System Controller 604 Camera signal processing circuit CF color filter

Claims

1. a plurality of pixels including a first pixel; Each of the plurality of pixels is a photoelectric conversion unit that converts light into a signal charge; a charge accumulation region for accumulating the signal charges; a first transistor having one of a source and a drain electrically connected to the charge storage region; Including, a gate of the first transistor of the first pixel is electrically connected to a node whose potential changes in response to a change in potential of the charge storage region of the first pixel, and is electrically insulated from the charge storage region of the first pixel; Imaging device.

2. the plurality of pixels includes a second pixel, the node is the charge storage region of the second pixel; a gate of the first transistor of the second pixel electrically connected to the charge storage region of the second pixel; The imaging device according to claim 1 .

3. the second pixel is a dummy pixel; The imaging device according to claim 2 .

4. The first pixel is a second transistor having a gate connected to the charge storage region and outputting a signal corresponding to the potential of the charge storage region; the node is electrically connected to the output terminal of the second transistor; The imaging device according to claim 1 .

5. a first voltage or a ground voltage is applied to the other of the source and the drain of the first transistor of the first pixel and the other of the source and the drain of the first transistor of the second pixel; 4. The imaging device according to claim 2.

6. the first pixel includes a color filter that transmits green light; the second pixel includes a color filter that transmits light of a color different from green; 4. The imaging device according to claim 2.

7. the plurality of pixels includes a third pixel, a gate of the first transistor of the third pixel electrically connected to the charge storage region of the second pixel; 4. The imaging device according to claim 2.

8. the first pixel and the second pixel are adjacent to each other; 4. The imaging device according to claim 2.

9. the first pixel and the second pixel are adjacent to each other, the plurality of pixels include a third pixel adjacent to the first pixel and a fourth pixel adjacent to the second pixel and the third pixel, a gate of the first transistor of the third pixel and a gate of the first transistor of the fourth pixel are electrically connected to the charge storage region of the second pixel; The imaging device according to claim 2 .

10. each of the first pixel, the second pixel, the third pixel, and the fourth pixel includes a color filter that transmits light of the same wavelength band; The imaging device according to claim 9 .

11. a sensitivity of the second pixel when an electrical connection between the gate of the first transistor of the first pixel and the charge storage region of the second pixel is eliminated is lower than a sensitivity of the first pixel; The imaging device according to claim 2 .

12. the photoelectric conversion unit includes a photoelectric conversion layer that generates the signal charges, a first electrode, and a second electrode that faces the first electrode across the photoelectric conversion layer and collects the signal charges; the node is an electrode different from the second electrode of the first pixel and is connected to an electrode facing the first electrode via the photoelectric conversion layer; The imaging device according to claim 1 .

13. An imaging device comprising: an imaging device according to any one of claims 1 to 4 and 9 to 12; Camera system.

Images