Spattering target, spattering target production method, crystal oxide thin film, thin film transistor, and electronic equipment

Abstract

Provided is a spattering target (1) comprising an oxide sintered compact including an In element, a Ga element, and an O element. Said sintered compact includes a crystal structure represented by In2O3, the atomic composition ratio of the Ga element in the oxide sintered compact satisfies expression (1), and the flexural strength of the oxide sintered compact is 140 MPa or greater.　Expression (1): 8 ≤ Ga / (In+Ga) ≤ 20

Description

Sputtering target, sputtering target manufacturing method, crystalline oxide thin film, thin film transistor, and electronic device

[0001] The present invention relates to a sputtering target, a method for manufacturing a sputtering target, a crystalline oxide thin film, a thin film transistor, and an electronic device.

[0002] In recent years, amorphous oxide semiconductors such as InGaZnO have come to be used as channel layers of thin film transistors (hereinafter sometimes referred to as TFTs), in addition to polycrystalline silicon thin films and amorphous silicon thin films. Oxide semiconductors are characterized by their large-area uniformity, similar to that of amorphous silicon. In addition, oxide semiconductors can be used in areas up to 10 cm ２ / Vs or more, and has a mobility higher than that of amorphous silicon.

[0003] However, amorphous oxide thin films have a problem in that the carrier supply source is oxygen vacancy, and the behavior of electrons is not necessarily stable against external factors such as heat, resulting in unstable thin-film transistor operation. Furthermore, continuous application of a negative bias to a thin-film transistor under visible light irradiation causes a negative shift in threshold voltage (negative bias photodegradation). For this reason, research has been conducted in recent years to apply crystalline oxide thin films, rather than amorphous oxide thin films, to the channel layer of thin-film transistors.

[0004] Patent Document 1 describes a gallium-containing alloy having a Ga / (In+Ga) atomic ratio of more than 0.15 and not more than 0.45, and a bixbyite-type crystal phase. ２ O ３Patent Document 1 describes a crystalline oxide thin film composed only of a gallium oxide phase. The oxide thin film described in Patent Document 1 is obtained by depositing the film using a sputtering target containing an oxide sintered body obtained from raw materials consisting of indium oxide and gallium oxide, followed by etching and annealing. Patent Document 1 also describes a TFT using the oxide thin film as a channel material. Furthermore, Patent Document 1 describes that by selecting the composition range described in Patent Document 1, a film that can be etched with a common weak acid such as oxalic acid, rather than a strong acid such as aqua regia, can be obtained without using a special film deposition method.

[0005] Patent Document 2 describes an oxide sintered body containing indium and gallium as oxides. This oxide sintered body is made of In having a bixbyite structure. ２ O ３ The phase becomes the main crystalline phase, and β-Ga ２ O ３ GaInO ３ phase, or GaInO ３ phase and (Ga, In) ２ O ３ The oxide sintered body is finely dispersed as crystal grains having an average grain size of 5 μm or less, and the gallium content is 10 atomic % or more and less than 35 atomic % in terms of the Ga / (In+Ga) atomic ratio.

[0006] Patent Document 3 describes an oxide sintered body made of indium oxide having a crystal structure substantially exhibiting a bixbyite structure. In the oxide sintered body, gallium atoms are dissolved in the indium oxide as a solid solution, and the atomic ratio Ga / (Ga+In) is 0.10 to 0.15. Patent Document 3 also describes a sputtering target obtained from the oxide sintered body described in Patent Document 3.

[0007] Furthermore, Patent Documents 2 and 3 describe that by controlling the sputtering target to have an appropriate crystal phase, it is possible to suppress nodules and prevent abnormal discharge.

[0008] International Publication No. 2015 / 008805 International Publication No. 2009 / 008297 Japanese Patent Application Laid-Open No. 2011-146571

[0009] In the TFT manufacturing process, there is a need for high power (high output) sputtering film deposition to improve productivity and TFT stability. However, sputtering film deposition at high power increases the likelihood of abnormal discharge (so-called arcing) during film deposition. Furthermore, the surface of the sputtering target becomes highly heated when exposed to high-energy plasma. This creates a temperature difference between the front surface of the sputtering target and the cooled back surface, which generates thermal stress. As a result, cracks may occur in the sputtering target.

[0010] In conventional sputtering targets, the generation of cracks that occurs when a film is formed by sputtering at high power has not been sufficiently studied, and there is room for further improvement in sputtering targets.

[0011] An object of the present invention is to provide a sputtering target that allows for sputtering film formation at high power (high output), a method for manufacturing the sputtering target, a crystalline oxide thin film using the sputtering target, a thin film transistor including the crystalline oxide thin film, and an electronic device including the thin film transistor.

[0012] [1] A sputtering target comprising an oxide sintered body containing In, Ga, and O, wherein the oxide sintered body contains In ２ O ３ a sputtering target comprising: a crystal structure represented by the formula: wherein the atomic composition ratio of the Ga element in the oxide sintered body satisfies the following formula (1); and the oxide sintered body has a flexural strength of 140 MPa or more.

[0013] [2] The In ２ O ３ The sputtering target according to [1], wherein the average grain size of the crystal structure represented by the formula (I) is 3 μm or less.

[0014] [3] The density measured by the Archimedes method is 6.3 g / cm ３ The sputtering target according to [1] or [2],

[0015] [4] The oxide sintered body is GaInO ３ The sputtering target according to any one of [1] to [3], comprising a crystal structure represented by the following formula:

[0016] [5] The sputtering target according to any one of [1] to [4], wherein the oxide sintered body further includes a crystal structure A in which diffraction peaks are observed at the following positions (A) to (E) in terms of incident angle (2θ) by X-ray (CuKα ray) diffraction measurement: (A) 28° or more and 29° or less (B) 45° or more and less than 46° (C) 46° or more and less than 47° (D) 47° or more and 48° or less (E) 50° or more and 51° or less

[0017] [6] A method for producing a sputtering target according to any one of [1] to [5], comprising the steps of: preparing raw material powder having a particle size of 0.5 μm or less; mixing the raw material powder to obtain a raw material mixture, and then granulating the raw material mixture to obtain raw material granules; molding the raw material granules to obtain a molded body; and sintering the molded body to obtain the oxide sintered body.

[0018] [7] A crystalline oxide thin film obtained by using the sputtering target according to any one of [1] to [5].

[0019] [8] A thin film transistor comprising the crystalline oxide thin film according to [7].

[0020] [9] An electronic device comprising the thin film transistor according to [8].

[0021] According to one aspect of the present invention, there are provided a sputtering target that allows for high-power (high-output) sputtering film formation, a method for manufacturing the sputtering target, a crystalline oxide thin film using the sputtering target, a thin-film transistor including the crystalline oxide thin film, and an electronic device including the thin-film transistor.

[0022] 1 is a perspective view showing the shape of a target according to one embodiment of the present invention. FIG. 2 is a perspective view showing the shape of a target according to one embodiment of the present invention. FIG. 3 is a perspective view showing the shape of a target according to one embodiment of the present invention. FIG. 4 is a longitudinal sectional view showing a thin film transistor according to one embodiment of the present invention. FIG. 5 is a longitudinal sectional view showing a thin film transistor according to one embodiment of the present invention. FIG. 6 is a longitudinal sectional view showing a quantum tunnel field effect transistor according to one embodiment of the present invention. FIG. 7 is a longitudinal sectional view showing another embodiment of a quantum tunnel field effect transistor. FIG. 8 is a longitudinal sectional view for explaining a manufacturing procedure of a quantum tunnel field effect transistor. FIG. 9 is a longitudinal sectional view for explaining a manufacturing procedure of a quantum tunnel field effect transistor. FIG. 10 is a longitudinal sectional view for explaining a manufacturing procedure of a quantum tunnel field effect transistor. FIG. 11 is a longitudinal sectional view for explaining a manufacturing procedure of a quantum tunnel field effect transistor. FIG. 12 is a longitudinal sectional view for explaining a manufacturing procedure of a quantum tunnel field effect transistor. FIG. 13 is a top view showing a display device using a thin film transistor according to one embodiment of the present invention. FIG. 14 is a diagram showing a circuit of a pixel portion that can be applied to pixels of a VA-type liquid crystal display device. FIG. 15 is a diagram showing a circuit of a pixel portion of a display device using an organic EL element. FIG. 16 is a diagram showing a circuit of a pixel portion of a solid-state imaging element using a thin film transistor according to one embodiment of the present invention. FIG. 17 is an X-ray diffraction pattern of the oxide sintered body produced in Example 1. FIG. 18 is a mapping image of oxygen atoms in the oxide sintered body produced in Example 1.

[0023] Hereinafter, embodiments will be described with reference to the drawings, etc. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0024] In the drawings, sizes, layer thicknesses, regions, etc. may be exaggerated for clarity. Therefore, the present invention is not limited to the illustrated sizes, layer thicknesses, regions, etc. Note that the drawings are schematic illustrations of ideal examples, and the present invention is not limited to the shapes, values, etc. shown in the drawings.

[0025] The ordinal numbers "first," "second," and "third" used in this specification are used to avoid confusion between components, and components that are not specified numerically are not limited in number.

[0026] In this specification and the like, the terms "film" or "thin film" and "layer" can be used interchangeably in some cases.

[0027] In the sintered body and oxide thin film of this specification and the like, the terms "compound" and "crystalline phase" can be interchangeable in some cases.

[0028] In this specification, the “oxide sintered body” may be simply referred to as the “sintered body.” In this specification, the “sputtering target” may be simply referred to as the “target.”

[0029] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes, wiring, switching elements (such as transistors), resistive elements, inductors, capacitors, and other elements with various functions.

[0030] In this specification, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms source and drain may be used interchangeably.

[0031] In this specification, a numerical range expressed using "to" means a range that includes the numerical value before "to" as the lower limit and the numerical value after "to" as the upper limit.

[0032] The present inventors have invented the present invention based on the following findings: Cracks that occur during high-power (high-output) sputtering deposition are thought to be caused by the temperature difference between the surface of the sputtering target, which is exposed to high-energy plasma, and the temperature difference between the surface of the target and the cooled back surface of the target, causing thermal stress. Parameters related to crack occurrence include, for example, (1) flexural strength, (2) thermal conductivity, (3) linear expansion coefficient, and (4) Young's modulus.

[0033] The values ​​of the above-mentioned (2) thermal conductivity, (3) linear expansion coefficient, and (4) Young's modulus can be somewhat changed by, for example, changing the crystal structure and changing the ratio of the constituent crystals. On the other hand, (1) flexural strength can be improved by suppressing voids in the sintered body and reducing the average grain size of the crystalline phase. Therefore, increasing the flexural strength is effective in improving crack resistance (hereinafter, this resistance may be referred to as power resistance) when forming a film by sputtering at high power (high output).

[0034] In view of the above, the present inventors have found that in a sputtering target including an oxide sintered body containing In, Ga, and O, by examining the crystal structure contained in the sintered body and the atomic composition ratio of Ga, high-output sputtering film formation is possible. Furthermore, the present inventors have found that in a sputtering target including an oxide sintered body containing In, Ga, and O, by examining the crystal structure contained in the sintered body and the atomic composition ratio of Ga, and further ２ O ３ By examining the average grain size of the crystal structure represented by the formula (1), it has been found that it is possible to form a film by sputtering at a high output and to improve crack resistance.

[0035] [Sputtering Target] The sputtering target according to this embodiment includes a sintered body. The sintered body is used as a film raw material when forming a film by sputtering. That is, the sputtering target according to this embodiment includes an oxide sintered body containing In, Ga, and O elements. The sintered body contains In, ２ O ３ The oxide sintered body has a crystal structure represented by the following formula (1), in which the atomic composition ratio of the Ga element in the oxide sintered body satisfies the following formula (1), and the flexural strength of the oxide sintered body is 140 MPa or more: 8≦Ga / (In+Ga)≦20 (1)

[0036] In formula (1), In and Ga represent the number of indium atoms and the number of gallium atoms in the sintered body, respectively.

[0037] <Crystal Grain Size of Sintered Body> In the sintered body provided in the target according to this embodiment, the sintered body is ２ O ３ The sintered body includes a crystal structure represented by the formula: ２ O ３ In addition to the crystal structure represented by GaInO ３ It may also include other crystal structures such as

[0038] In the sintered body according to this embodiment ２ O ３ It is preferable that the proportion of the crystal structure represented by the formula (1) is substantially 80% or more in terms of area ratio. ２ O ３ The crystal structure represented by the following formula (1) is preferably the main phase in the sintered body of the target according to this embodiment. ２ O ３ The crystal structure represented by the formula is a bixbyite phase. ２ O ３ The proportion of the crystal structure represented by the formula (1) was determined by X-ray diffraction (XRD) measurement of the sintered body, and was determined from the peak area of ​​the strongest line of each crystal phase and the RIR value (Reference Intensity Ratio).

[0039] In one embodiment of the sintered body, the crystalline phase of the sintered body is ２ O ３The crystal structure represented by (i.e., In ２ O ３ bixbyite phase represented by ３ When the crystal structure is represented by ２ O ３ The proportion of the crystal structure represented by In ２ O ３ and GaInO ３ In for the entire crystal structure of the crystal structure represented by ２ O ３ In one embodiment of the sintered body, the crystalline phase of the sintered body is ２ O ３ The crystal structure represented by GaInO ３ and the crystal structure A described later, ２ O ３ The proportion of the crystal structure represented by In ２ O ３ The crystal structure represented by GaInO ３ and the entire crystal structure of the crystal structure A. ２ O ３ is the proportion of the crystal structure expressed as

[0040] In the sintered body provided in the target according to this embodiment, In contained in the sintered body ２ O ３ The average grain size of the crystal structure represented by the formula (I) is preferably 3 μm or less. ２ O ３ The average grain size of the crystal structure represented by the formula (I) is preferably 3 μm or less. ２ O ３ When the average grain size of the crystal structure represented by In is 3 μm or less, the bending strength of the sintered body is improved, and as a result, the power resistance is further improved. ２ O ３ The average particle size of the crystal structure represented by In is more preferably 2.5 μm or less, and even more preferably 2 μm or less. ２ O ３The lower limit of the average grain size of the crystal structure represented by is not particularly limited, and may be, for example, 1 μm or more. ２ O ３ In addition to the crystal structure represented by, for example, GaInO ３ When the crystal structure represented by ２ O ３ The average grain size of the crystal structure represented by GaInO ３ However, it is also possible to reduce the average grain size of the crystal structure represented by GaInO ３ When the average grain size of the crystal structure expressed by ２ O ３ If the average grain size of the crystal structure represented by the formula (1) is large, it is difficult to obtain excellent bending strength.

[0041] In ２ O ３ The average grain size of the crystal structure represented by the formula (1) can be calculated as follows. First, the polished sintered body is observed using an SEM, and a secondary electron image and a backscattered electron image are observed at a magnification of 2000 times. When observing using the SEM, the atomic ratio of each crystal grain is determined using energy dispersive X-ray spectroscopy (EDS). In addition, the sintered body is subjected to X-ray diffraction (XRD) measurement to confirm the crystal phase. Next, each crystal phase is identified by comparing it with the crystal structure identified by X-ray diffraction (XRD). The crystal grains are measured using the obtained SEM image, and the average grain size is calculated.

[0042] In ２ O ３Specifically, the average grain size of the crystal structure represented by can be measured, for example, as follows. When the planar shape of the sintered body is rectangular, the surface of the sintered body is divided into 16 equal areas, and 1 cm squares are cut out at 16 center points of each rectangle, and mirror polished to obtain measurement samples. The measurement surface of the cut-out sintered body is further divided into 9 equal areas, and secondary electron images and backscattered electron images are observed at 2000x magnification at the 9 center points of each rectangle. During SEM observation, EDS measurement is performed, and each crystal grain is identified by comparing it with the crystal structure identified by XRD. Particle diameters are measured from the obtained SEM images, and the average value of the grain diameters of the particles within the 9 frames is calculated. This operation is performed on the measurement samples cut out from 16 locations, and the average value of the grain diameters obtained from a total of 144 SEM images is used as the average grain size. For particles with an aspect ratio of less than 2, the particle size is measured as the equivalent circle diameter of the crystal grain based on JIS R 1670:2006. Specifically, the procedure for measuring the equivalent circle diameter is to place a circular ruler on the grain to be measured in a microstructure photograph and read the diameter equivalent to the area of ​​the grain to be measured. For particles with an aspect ratio of 2 or more, the average value of the longest diameter and the shortest diameter is taken as the particle size. More specifically, this can be confirmed by the method described in the examples below.

[0043] <Crystalline structure of sintered body> In the sintered body provided in the target according to this embodiment, the crystalline phase of the sintered body is In ２ O ３ In addition to the crystal structure represented by the formula (1), it is preferable that the sintered body further contains a crystal structure A in which diffraction peaks are observed at the following positions (A) to (E) in terms of the angle of incidence (2θ) by X-ray (CuKα ray) diffraction measurement. ２ O ３ and GaInO ３ In addition to the crystal structure represented by the formula (A), it is also preferable that the crystal structure further includes the crystal structure A. (A) 28° or more and 29° or less (B) 45° or more and less than 46° (C) 46° or more and less than 47° (D) 47° or more and 48° or less (E) 50° or more and 51° or less

[0044] The observation of X-ray diffraction peaks at each of the positions (A) to (E) means that, when measured by X-ray (CuKα ray: wavelength 1.5418 Å) diffraction, peaks are present at the following positions where the angle of incidence (2θ) is: (A) 28° or more and 29° or less; (B) 45° or more and less than 46°; (C) 46° or more and less than 47°; (D) 47° or more and 48° or less; and (E) 50° or more and 51° or less.

[0045] Since the crystalline phase of the sintered body according to this embodiment contains crystalline structure A, it is possible to change the values ​​of the thermal conductivity, linear expansion coefficient, and Young's modulus of the sintered body, and as a result, the occurrence of cracks is more easily suppressed even when the film is formed at high power.

[0046] The observation of X-ray diffraction peaks at each of the positions (A) to (E) can be confirmed by X-ray diffraction (XRD) measurement, as will be specifically described in the Examples below.

[0047] The sintered body provided in the target according to this embodiment has a crystalline structure with different O element (oxygen element) contents in an element mapping image, with regions with relatively low O element (oxygen element) contents and regions with relatively high O element (oxygen element) contents, and it is preferable that the regions with relatively low O element contents are continuously connected. A structure with a low O element content, i.e., many oxygen defects, has a low resistance value. This continuous connection of crystalline structures with a low O element content makes it possible to maintain a low resistance value for the entire sintered body, and as a result, cracking is more easily suppressed even when film formation is performed at high power. If the resistance value of the sintered body is high, it can cause abnormal discharge and lead to cracking when film formation is performed at high power (high output).

[0048] The elemental mapping image of the sintered body can be evaluated using a scanning electron microscope (SEM)-energy dispersive X-ray spectroscopy (EDS). Hereinafter, the scanning electron microscope-energy dispersive X-ray spectroscopy will be referred to as SEM-EDS.

[0049] In the sintered body provided in the target according to this embodiment, the surface roughness Ra (arithmetic mean roughness) of the sintered body is preferably 0.5 μm or less. Furthermore, in the sintered body provided in the target according to this embodiment, the surface roughness Ra (arithmetic mean roughness) of the sintered body is preferably 0.5 μm or less and has a non-directional ground surface. The surface roughness Ra of the sintered body is more preferably less than 0.5 μm, and even more preferably 0.25 μm or less. When the surface roughness Ra of the sintered body provided in the target according to this embodiment is 0.5 μm or less, preferably 0.5 μm or less, and has a non-directional ground surface, abnormal discharge and particle generation can be prevented. Furthermore, in the sintered body provided in the target according to this embodiment, the surface roughness Rz (maximum height roughness) of the surface of the sintered body is preferably less than 2.0 μm. A surface roughness Rz of less than 2.0 μm makes it easier to obtain a sputtering target with improved crack resistance. As a method for adjusting the surface roughness Ra and surface roughness Rz of the sintered body, there may be mentioned a method described later in the manufacturing process of the sputtering target.

[0050] <Atomic Composition Ratio of Ga Element> As described above, in the sintered body included in the target according to this embodiment, the atomic composition ratio of the Ga element satisfies the following formula (1): 8≦Ga / (In+Ga)≦20 (1).

[0051] In the sintered body provided in the target according to this embodiment, when the atomic composition ratio of Ga (Ga / (In+Ga)) represented by the above formula (1) is 8 or more, it is possible to obtain a sintered body having a sintered body containing Ga and In. ２In film formation using a gas mixture, it is possible to prevent the thin film immediately after deposition from becoming a completely crystalline film or from becoming a thin film containing microcrystals, thereby suppressing the generation of residues during patterning processing during TFT fabrication. If the thin film immediately after deposition is a completely crystalline film or a thin film containing microcrystals, residues will be generated by etching using a weak acid such as oxalic acid during TFT fabrication, making it difficult to obtain the desired TFT characteristics. It is more preferable that Ga / (In+Ga) is 10 or more, and even more preferable that it is 12 or more.

[0052] When the atomic composition ratio of Ga (Ga / (In+Ga)) represented by the above formula (1) is 20 or less, the thin film after deposition can be easily crystallized by heat treatment (annealing) at about 300°C to 450°C without the need for special annealing treatments such as high-temperature annealing and laser annealing. Furthermore, the thin film can be made large without using expensive equipment. If the thin film after annealing is not sufficiently crystallized, a TFT including an insufficiently crystallized thin film may not be able to ensure high mobility and stability. Ga / (In+Ga) is more preferably 18 or less, and even more preferably 16 or less.

[0053] The sintered body provided in the target according to this embodiment may consist essentially of only In (indium), Ga (gallium), and O (oxygen). Here, "substantially" means that the sintered body according to this embodiment may contain other components as long as the effects of the present invention resulting from the combination of In, Ga, and O are achieved. In this case, the sintered body provided in the target according to this embodiment may contain impurity elements. The total content of In and Ga as metal elements in the sintered body is preferably 99 atomic % or more, more preferably 99.5 atomic % or more, and even more preferably 99.9 atomic % or more, based on the total metal elements in the sintered body (100 atomic %). The total content of In and Ga may be 100 atomic % based on the total metal elements in the sintered body. Note that in this specification, atomic % may be expressed as at %.

[0054] Impurities refer to elements that are not intentionally added but are mixed in during raw materials, manufacturing processes, etc. In other words, impurities are inevitable impurities that are inevitably included. The same applies to the following explanation. Examples of impurities include alkali metal elements (elements such as Li (lithium), Na (sodium), K (potassium), and Rb (rubidium)), alkaline earth metal elements (elements such as Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium)), H (hydrogen), B (boron), C (carbon), N (nitrogen), F (fluorine), Si (silicon), and at least one element selected from the group consisting of Cl (chlorine), Zr (zirconium), Al (aluminum), and Sn (tin).

[0055] The sintered body provided in the target according to this embodiment may contain H element (hydrogen element). When the sintered body contains H element, the atomic concentration of H element in the sintered body is 1×10 １６ cm －３ That's it, 1 x 10 １８ cm －３The atomic concentration of H element in the sintered body is preferably less than 3×10 １６ cm －３ More preferably, it is 5×10 or more. １６ cm －３ If the H element concentration in the sintered body is too low, the influence of H elements degassed from the shielding plate of the sputtering chamber during film formation is large, and the degassed H elements are mixed non-uniformly into the formed film, which may lead to a decrease in the in-plane uniformity of the TFT characteristics. The atomic concentration of H elements in the sintered body is 5×10 １７ cm －３ More preferably, it is 3×10 or less. １７ cm －３ If the H element concentration in the sintered body is too high, a large amount of H element is mixed into the formed film, which forms a donor level or an acceptor level, which may result in a significant deterioration in the reliability of the TFT.

[0056] The sintered body provided in the target according to this embodiment may contain C element (carbon element). When the sintered body contains C element, the lower limit of the atomic concentration of C in the sintered body is not particularly limited, and the amount of impurities at the time of manufacturing the target is 1×10 １６ cm －３ When the sintered body contains the C element, the atomic concentration of the C element is 1×10 １６ cm －３ That's it, 1 x 10 １８ cm －３ The atomic concentration of the C element in the sintered body is preferably less than 7×10 １７ cm －３ More preferably, it is 4×10 or less. １７ cm －３ If the atomic concentration of the C element is too high, a large amount of the C element is mixed into the formed film, which forms a donor level or an acceptor level, which may result in a significant deterioration in the reliability of the TFT.

[0057] The sintered body provided in the target according to this embodiment may contain H element (hydrogen element) and C element (carbon element). When the sintered body contains both H element and C element, the atomic concentrations of both H element and C element are 1×10 １６ cm －３ That's it, 1 x 10 １８ cm －３ In this specification and the like, the unit of atomic concentration of H element and C element [atoms / cm ３ ] is [cm －３ ] may be written.

[0058] The atomic concentrations of H and C contained in the sintered body can be determined by secondary ion mass spectrometry (SIMS). A dynamic SIMS device can be used for the SIMS measurement.

[0059] In the sintered body provided in the target according to this embodiment, the sintered body may contain one or more elements (X elements) selected from the group consisting of positive trivalent, positive tetravalent, and positive pentavalent elements as an additive element, within a range that does not impair the effect.

[0060] In this case, the sputtering target according to the present embodiment may, as one aspect, comprise an oxide sintered body containing In, Ga, and O elements, as well as one or more X elements selected from the group consisting of positive trivalent, positive tetravalent, and positive pentavalent elements. ２ O ３ The sintered body of the sputtering target according to this embodiment has a crystal structure represented by the formula (1), the atomic composition ratio of the Ga element in the sintered body satisfies the formula (1), and the flexural strength of the sintered body is 140 MPa or more. ３ The sputtering target according to this embodiment may have a crystalline structure represented by the formula (I), or may have the above-mentioned crystalline structure A. ２ O ３ The average grain size of the crystal structure represented by may be 3 μm or less.

[0061] The X element, which is an additive element, is preferably at least one element selected from the group consisting of, for example, Zn (zinc), Mg (magnesium), Ti (titanium), Fe (iron), Zr (zirconium), Nb (niobium), Hf (hafnium), Sn (tin), Si (silicon), Ge (germanium), Ta (tantalum), W (tungsten), Al (aluminum), B (boron), Y (yttrium), Sc (scandium), and Ln (lanthanoid). Among these, the X element, which is an additive element, is more preferably at least one of Zn (zinc) and Sn (tin). The sintered body provided in the sputtering target in this embodiment may essentially consist of In (indium), Ga (gallium), O (oxygen), and X. "Substantially" has the same meaning as described above. For example, the total content of In, Ga, and X elements as metal elements in the sintered body is preferably 99 atomic % or more, more preferably 99.5 atomic % or more, and even more preferably 99.9 atomic % or more, relative to the total (100 atomic %) of the metal elements in the sintered body. The total content of In, Ga, and X elements may be 100 atomic % relative to the total of the metal elements in the sintered body.

[0062] The amount of the X element, which is an additive element, is preferably 2 at% (2 atomic %) or less, more preferably 1 at% or less, and even more preferably 0.5 at% or less. If the amount of the additive element is 2 at% or less, when a TFT is fabricated using the target according to this embodiment, a TFT with high mobility and high stability is likely to be obtained. If the amount of the additive element is too large, the obtained TFT may suffer from problems such as reduced mobility and reduced stability. The amount of the X element, which is an additive element, is expressed by the following formula (2): 0.02≧(X / (In+Ga+X)) (2)

[0063] In formula (2), In, Ga, and X represent the number of atoms of indium element, gallium element, and X element in the sintered body, respectively.

[0064] The content (atomic ratio) of each metal element in the sintered body can be determined by measuring the amount of each element by ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence) measurement. An inductively coupled plasma optical emission spectrometer can be used for ICP measurement. A thin film X-ray fluorescence analyzer can be used for XRF measurement.

[0065] <Physical properties of sintered body> In the sintered body provided in the target according to this embodiment, the density of the sintered body measured by the Archimedes method was 6.3 g / cm ３ The density of the sintered body measured by the Archimedes method is preferably 6.5 g / cm or more. ３ More preferably, it is equal to or greater than this.

[0066] The relative density of the sintered body is preferably 97% or more, and more preferably 99% or more. The relative density means a percentage obtained by dividing the actual density of the oxide sintered body measured by Archimedes' method by the theoretical density of the oxide sintered body.

[0067] The thickness of the sintered body included in the target according to this embodiment is preferably 2 mm or more and 20 mm or less. The thickness of the sintered body is more preferably 3 mm or more, and even more preferably 4 mm or more. The thickness of the sintered body is more preferably 12 mm or less, even more preferably 9 mm or less, and even more preferably 6 mm or less.

[0068] The sintered body provided in the target according to this embodiment has a flexural strength of 140 MPa or more. The flexural strength is preferably 150 MPa or more, and more preferably 160 MPa or more. When the flexural strength is 140 MPa or more, the flexural strength of the sintered body suppresses the occurrence of cracks when a film is formed by sputtering at high power (high output). The flexural strength of the sintered body is determined as the average value of the three-point bending strength measurements of 30 test pieces according to JIS R 1601:2008.

[0069] The sintered body provided in the target according to this embodiment also exhibits excellent properties in terms of thermal conductivity, linear expansion coefficient, and Young's modulus. The linear expansion coefficient of the sintered body can be measured in accordance with JIS R 1618:2002 at a measurement temperature of 30°C to 500°C, at a heating rate of 10 K / min, and in an air atmosphere. The Young's modulus of the sintered body can be measured in accordance with JIS R 1602:1995 using an ultrasonic flaw detector at room temperature in air. The thermal conductivity of the sintered body can be calculated from the following formula (Formula 1) by measuring the specific heat capacity using the laser flash method (room temperature, in a vacuum) and the thermal diffusivity using the laser flash method (room temperature, in air) in accordance with JIS R 1611:2010: λ (thermal conductivity) = Cp (specific heat capacity) × ρ (density) × α (thermal diffusivity) ... (Formula 1), where ρ is the density of the oxide sintered body.

[0070] The sputtering target according to this embodiment includes an oxide sintered body and a cooling and holding member such as a backing plate provided on the oxide sintered body as needed. The material of the backing plate, which is a member for holding and cooling the oxide sintered body, is preferably a material with excellent thermal conductivity such as copper.

[0071] When the target according to this embodiment includes a cooling and holding member such as a backing plate, the sintered body included in the sputtering target according to this embodiment has a bonding surface that is attached to the holding member and a sputtering surface that is the surface opposite to the bonding surface and is used for sputtering. In this embodiment, it is preferable that the sputtering surface is a smooth surface (i.e., a smooth surface with the above-mentioned surface roughness Ra of 0.5 μm or less), and that the surface opposite to the sputtering surface is used as the bonding surface.

[0072] The shape of the sputtering target is not particularly limited. The sputtering target may be, for example, a plate-like shape as shown by reference numeral 1 in FIG. 1A or a cylindrical shape as shown by reference numeral 1A in FIG. 1B. In the case of a plate-like shape, the planar shape may be a rectangle as shown by reference numeral 1 in FIG. 1A or a circle as shown by reference numeral 1B in FIG. 1C. The oxide sintered body may be integrally molded, or may be a multi-division type in which a plurality of divided oxide sintered bodies (reference numeral 1C) are each fixed to a backing plate 3 as shown in FIG. 1D.

[0073] <Method for manufacturing a sputtering target> An example of a preferred method for manufacturing a target according to this embodiment will be described. The method for manufacturing a sputtering target according to this embodiment preferably includes, for example, the following steps: A step of preparing raw material powder having a particle size of 0.5 μm or less (hereinafter, this may be referred to as the raw material powder preparation step). A step of mixing the raw material powder to obtain a raw material mixture, and then granulating the raw material mixture to obtain raw material granules (hereinafter, this may be referred to as the granulation step). A step of molding the raw material granules to obtain a molded body (hereinafter, this may be referred to as the molding step). A step of sintering the molded body to obtain a sintered body (hereinafter, this may be referred to as the sintering step).

[0074] A preferred method for manufacturing a target according to this embodiment may further include at least one step selected from the group consisting of a step of heat-treating the sintered body (annealing step), a step of at least grinding the sintered body (hereinafter may be referred to as the grinding step), a step of cleaning the ground sintered body (hereinafter may be referred to as the cleaning step), and a step of bonding the sintered body to a backing plate (hereinafter may be referred to as the bonding step).

[0075] (Raw material powder preparation step) In the raw material powder preparation step, raw material powder to be used as a raw material for the sintered body included in the sputtering target according to this embodiment is prepared. The raw material powder prepared in the raw material powder preparation step is indium oxide having an average particle size of 0.5 μm or less and gallium oxide having an average particle size of 0.5 μm or less. As the raw material powder, raw material powder of a compound containing one or more elements selected from the group consisting of positive trivalent, positive tetravalent, and positive pentavalent elements and having an average particle size of 0.5 μm or less may also be prepared, if necessary. The raw material powder may be prepared by obtaining raw material powder having an average particle size of 0.5 μm or less, or by obtaining raw material powder having an average particle size greater than 0.5 μm and adjusting the average particle size of the obtained raw material powder to 0.5 μm or less.

[0076] The average particle size of the raw material powder prepared in the raw material powder preparation step is preferably 0.1 μm or more and 0.5 μm or less. When the average particle size of the raw material powder is 0.1 μm or more, aggregation of the raw material powder particles is easily suppressed, and the raw material powder particles can be mixed in a nearly uniform state. When the average particle size of the raw material powder is 0.5 μm or less, the In contained in the sintered body after sintering can be easily suppressed. ２ O ３ The average particle size of the crystal structure represented by the formula (I) can be easily controlled to 3 μm or less. The average particle size of the raw material powder can be calculated by at least one of particle size evaluation using a particle size distribution measuring device and specific surface area determined by the BET method. The average particle size of the raw material powder can also be confirmed using a SEM device.

[0077] If the average particle size of the obtained raw material powder exceeds 0.5 μm, it is preferable to pre-pulverize the raw material powder to adjust the average particle size of the raw material powder to 0.5 μm or less. Pre-pulverization can be performed using a bead mill, ball mill, jet mill, or the like. The material of the pot used in pre-pulverization is not particularly limited, and examples thereof include agate and alumina. The material of the grinding media (balls) used in pre-pulverization is not particularly limited, and examples thereof include alumina and zirconia. The grinding time in pre-pulverization is preferably 30 minutes or more and 6 hours or less. A grinding time of 30 minutes or more in pre-pulverization achieves sufficient grinding effect, making it easier to adjust the average particle size to a predetermined value. A grinding time of 6 hours or less in pre-pulverization reduces the risk of foreign matter being mixed in due to the scraping of the pot material and the ball material (reduces the risk of contamination). Therefore, when a TFT is fabricated using the target according to this embodiment, a TFT with high mobility and high stability is likely to be obtained. In the preliminary grinding, a binder, a dispersant, an antifoaming agent, etc. may be added as needed before grinding.

[0078] The raw material powders of indium oxide and gallium oxide prepared in the raw material powder preparation step are preferably high in purity. The purity of each raw material powder is preferably 99% by mass or more, more preferably 99.9% by mass or more, and even more preferably 99.99% by mass or more. Furthermore, when using a raw material powder of a compound containing one or more elements selected from the group consisting of positive trivalent, positive tetravalent, and positive pentavalent elements, the raw material powder is also preferably high in purity, similar to the raw material powders of indium oxide and gallium oxide. For example, the purity of the raw material powder of a compound containing one or more elements selected from the group consisting of positive trivalent, positive tetravalent, and positive pentavalent elements is preferably 99% by mass or more, more preferably 99.9% by mass or more, and even more preferably 99.99% by mass or more. Using a high-purity raw material powder results in a sintered body with a dense structure, and the volume resistivity of a sputtering target including the sintered body is low. Furthermore, when a TFT is manufactured using a sputtering target including the sintered body, the formation of defect levels due to impurities can be suppressed, and a TFT with high mobility and high stability can be obtained.

[0079] (Granulation process) In the granulation process, first, the raw material powders prepared in the raw material powder preparation process are mixed to obtain a mixed raw material powder, and a dispersant, a thickener, etc. are added as needed to obtain a raw material mixture. The mixed raw material powder may be used as the raw material mixture as is. Next, the raw material mixture is granulated to obtain a raw material granule. Hereinafter, the raw material granule may be referred to as raw material granule powder.

[0080] [Mixing of Raw Powders] If necessary, a dispersant for deflocculation and a thickener for adjusting the viscosity to a level suitable for granulation in a spray dryer may be added to the raw powder prepared in the raw powder preparation step, and the mixture may be mixed using a wet ball mill, planetary ball mill, bead mill, jet mill, or the like to obtain a raw material mixture. Among these, a bead mill is preferred as the device used for water mixing. Using a bead mill allows the raw material powder to be mixed uniformly, which allows for sufficient sintering even at the sintering temperature described below, making it easier to obtain a sputtering target that can be used for high-power (high-output) sputtering film formation. Examples of dispersants include ammonia-neutralized acrylic acid / methacrylic acid copolymers, and examples of thickeners include polyvinyl alcohol.

[0081] As long as the raw material powders are sufficiently mixed, the mixing time of the raw material powders is not particularly limited. The mixing time of the raw material powders is preferably, for example, 2 hours or more and 48 hours or less. When the mixing time is 2 hours or more, the raw material powders are likely to be sufficiently mixed. When the mixing time is 48 hours or less, the occurrence of re-agglomeration of the raw material powders is likely to be suppressed. Furthermore, when the mixing time is 48 hours or less, the intrusion (contamination) of foreign matter from the material of the pot, the material of the ball, etc. is suppressed.

[0082] [Granulation of Raw Material Powder] The granulation process for granulating the raw material mixture can be carried out using a spray dryer, etc. The shape of the raw material granules obtained in the granulation step is not particularly limited, but is preferably spherical in order to uniformly fill a mold in the molding step described below.

[0083] Granulation conditions are appropriately selected by adjusting the concentration of the raw material mixture after mixing the raw material powders introduced into the spray dryer, the rotation speed of the spray dryer, the hot air temperature used for drying, and the like.

[0084] When a raw material mixture that has not been subjected to a calcination treatment is granulated by a spray drying method, the raw material mixture obtained above may be used as is to prepare the raw material granules. When a raw material mixture that has been subjected to a calcination treatment is used, the calcined raw material mixture may be pulverized again by the method described in the pre-pulverization of raw material powders before use.

[0085] In the target manufacturing method according to this embodiment, the particle size of the raw material granules formed by the granulation process is not particularly limited, and is preferably controlled, for example, within a range of 25 μm or more and 150 μm or less. If the particle size of the raw material granules is 25 μm or more, the slipperiness of the raw material granules relative to the surface of the mold used in the molding process described below is improved, allowing the raw material granules to be sufficiently filled into the mold. If the particle size of the raw material granules is 150 μm or less, it is possible to prevent the particle size from being too large and resulting in a low filling rate in the mold. It is more preferable that the particle size of the raw material granules is 25 μm or more and 75 μm or less.

[0086] The method for obtaining raw granules having a particle size within the desired range is not particularly limited. For example, a method can be used in which the raw granules subjected to a granulation process are sieved to select raw granules belonging to the desired particle size range. The sieve used in this method is preferably a sieve having openings of a size that allows raw granules of the desired particle size to pass through. The sieves used in this method are preferably a first sieve for selecting the raw granules based on the lower limit of the particle size range and a second sieve for selecting the raw granules based on the upper limit of the particle size range. For example, when the particle size of the raw granules is controlled to be within the range of 25 μm or more and 150 μm or less, first, raw granules having a particle size of 25 μm or more are selected using a sieve (first sieve) having openings of a size that allows raw granules less than 25 μm to pass through but does not allow raw granules of 25 μm or more to pass through. Next, the raw material granules after this sorting are sorted into raw material granules in the range of 25 μm to 150 μm using a sieve (second sieve) having openings large enough to allow raw material granules of 150 μm or less to pass through but not raw material granules exceeding 150 μm. The second sieve may be used first, followed by the first sieve. The method for controlling the particle size range of the raw material granules is not limited to the method using a sieve as described above, and any method may be used as long as the raw material granules to be subjected to the molding process can be controlled to fall within the desired range.

[0087] (Forming Step) In the forming step, the raw material granules are formed into a formed body by a method such as die press forming, slip casting, or injection molding. When a sintered body with a high sintering density is to be obtained as a sputtering target, it is preferable that in the forming step, after preforming by die press forming or the like, the sintered body is further consolidated by cold isostatic pressing (CIP) or the like.

[0088] (Sintering Step) In the sintering step, a sintered body is obtained by sintering the compact obtained in the molding step. In the sintering step, a commonly used sintering method such as atmospheric sintering, hot press sintering, or hot isostatic pressing (HIP) sintering can be used. The obtained sintered body becomes a sputtering target material.

[0089] The sintering temperature is preferably 1300°C or higher and 1400°C or lower. When the sintering temperature is 1300°C or higher, the sintering of the compact proceeds sufficiently, which prevents the sintered body from having a large number of pores, and improves the bending strength. When the sintering temperature is 1400°C or lower, the In contained in the sintered body is easily sintered. ２ O ３ It becomes easy to control the average grain size of the crystal structure represented by the formula (I) to a range of 3 μm or less, and the bending strength is easy to improve.

[0090] The sintering time is preferably 12 hours or more and 48 hours or less. When the sintering time is 12 hours or more, the sintering of the molded body proceeds sufficiently, which prevents the formation of a large number of pores in the sintered body and improves the bending strength. When the sintering time is 48 hours or less, the In contained in the sintered body is easily sintered. ２ O ３ It becomes easy to control the average grain size of the crystal structure represented by the formula (I) to a range of 3 μm or less, and the bending strength is easy to improve.

[0091] In the sintering step, the rate of temperature rise from room temperature to the sintering temperature is not particularly limited, but is preferably 0.1° C. / min or more and 3° C. / min or less. During the temperature rise process, the temperature may be held at 700° C. or more and 800° C. or less for 1 hour or more and 10 hours or less, and then the temperature may be held at the predetermined temperature for a predetermined time and then raised to the sintering temperature.

[0092] The atmosphere during sintering may be, for example, air or oxygen gas, an atmosphere containing air or oxygen gas and a reducing gas, or an atmosphere containing air or oxygen gas and an inert gas. Examples of reducing gases include hydrogen gas, methane gas, and carbon monoxide gas. Examples of inert gases include argon gas and nitrogen gas.

[0093] (Heat Treatment Step (Annealing Step)) In the heat treatment step (annealing step), the obtained sintered body is annealed. In the target manufacturing method according to this embodiment, the annealing step is an optional step. When the annealing step is performed, the sintered body is typically treated at a holding temperature of 700°C or higher and 1100°C or lower for a holding time of 1 hour or higher and 5 hours or lower. In the annealing step, the sintered body may be once cooled and then annealed by raising the temperature again, or may be annealed when the temperature is lowered from the sintering temperature. Examples of the atmosphere during annealing include an atmosphere of air or oxygen gas, an atmosphere containing air or oxygen gas and a reducing gas, or an atmosphere containing air or oxygen gas and an inert gas. Examples of reducing gases include hydrogen gas, methane gas, and carbon monoxide gas. Examples of inert gases include argon gas and nitrogen gas.

[0094] (Grinding step) In the grinding step, the obtained sintered body is cut into an appropriate shape, and the surface of the oxide sintered body is polished. Specifically, the sintered body is cut into a shape suitable for installation in a sputtering device, and the surface of the oxide sintered body is polished.

[0095] The abrasive grain size of the grinding stone used in the grinding step is preferably 100 μm or less. If the abrasive grain size of the grinding stone is 100 μm or less, cracking of the sintered body can be prevented. The grinding stone used in the grinding step is preferably a diamond grinding stone. The grinding depth in the grinding step is preferably 0.3 mm or more, more preferably 0.5 mm or more, and even more preferably 2 mm or more. By grinding the surface of the sintered body by 0.3 mm or more, it is possible to remove portions of the crystal structure near the surface that have changed.

[0096] The surface of the sintered body that has undergone the grinding process preferably has a surface roughness Ra (arithmetic mean roughness) of 5 μm or less. The surface of the sintered body that has undergone the grinding process preferably has a surface roughness Rz (maximum height roughness) of less than 2.0 μm. Furthermore, the surface of the sintered body that has undergone the grinding process preferably has a surface roughness Ra (arithmetic mean roughness) of 5 μm or less and is provided with a non-directional ground surface.

[0097] The sintered body may further be subjected to mirror finishing on the sputtered surface. This mirror finishing (polishing) can be performed using known polishing techniques such as mechanical polishing, chemical polishing, and mechanochemical polishing (a combination of mechanical and chemical polishing). For example, the sintered body may be polished to a polishing surface of #2000 or higher using a fixed abrasive polisher (using water as the polishing liquid), or may be lapped with a free abrasive lap (using SiC paste or the like as the abrasive), and then the abrasive may be replaced with diamond paste for lapping. The polishing method is not limited to these methods.

[0098] (Cleaning Process) In the cleaning process, the sintered body ground in the grinding process is cleaned. Examples of cleaning methods include air blowing and running water washing. When removing foreign matter by air blowing, foreign matter can be removed more effectively by using a dust collector to suck air from the opposite side of the air blow nozzle. In addition to the cleaning process using air blowing or running water washing, ultrasonic cleaning or the like may also be performed. An effective ultrasonic cleaning method involves multiple oscillations at frequencies between 25 kHz and 300 kHz. For example, a preferred ultrasonic cleaning method involves multiple oscillations at 12 different frequencies in 25 kHz increments between 25 kHz and 300 kHz.

[0099] (Bonding Step) The bonding step is a step of bonding the sintered body after the processing step to a backing plate with a low melting point metal (for example, metallic indium, metallic gallium, etc.).

[0100] In order to maintain cooling efficiency during sputtering, the bonding rate is preferably 90% or more, more preferably 95% or more, and even more preferably 98% or more. The bonding rate here refers to the area ratio of the surface where the target material and the target support material are bonded via a bonding layer to the area of ​​the overlapping surfaces of the target material and the target support. The bonding rate can be confirmed, for example, by X-ray CT (X-ray Computed Tomography) or ultrasonic flaw detection.

[0101] When the sputtering target according to this embodiment is used for sputtering film formation, crack resistance is improved, allowing stable production of oxide thin films. Furthermore, since the sputtering target according to this embodiment uses a target having the same atomic composition as the sintered body according to this embodiment, the TFT obtained by sputtering has high mobility and high stability.

[0102] [Crystalline Oxide Thin Film] The crystalline oxide thin film according to this embodiment is a crystalline oxide thin film using the sputtering target according to this embodiment. The crystalline oxide thin film according to this embodiment is obtained by deposition using the sputtering target according to this embodiment. The crystalline oxide thin film according to this embodiment is preferably obtained by a manufacturing method including, for example, a step of depositing an oxide thin film by sputtering using the sputtering target according to this embodiment (hereinafter, sometimes referred to as an oxide thin film deposition step), and a step of subjecting the oxide thin film to a heat treatment (hereinafter, sometimes referred to as a heat treatment step). The crystalline oxide thin film according to this embodiment is deposited using a target having the same atomic composition as the sintered body according to this embodiment, and therefore has excellent processability during TFT fabrication, and a TFT with high mobility and high stability can be obtained.

[0103] The crystalline oxide thin film according to this embodiment is a crystalline oxide thin film. The crystalline oxide thin film according to this embodiment is an amorphous (non-crystalline) oxide thin film after sputtering deposition and before heat treatment (annealing treatment), and the crystallinity is improved by annealing treatment after sputtering deposition, turning it into a crystalline oxide thin film. Because the crystalline oxide thin film according to this embodiment is a crystalline oxide thin film, a thin film transistor (TFT) including the crystalline oxide thin film according to this embodiment has high mobility and high stability.

[0104] Whether an oxide thin film is amorphous or crystalline can be confirmed by subjecting each oxide thin film to X-ray diffraction (XRD) measurement. When an oxide thin film is subjected to XRD measurement, if no peak is observed, the oxide thin film is judged to be amorphous, and if a peak is observed, the oxide thin film is judged to be crystalline.

[0105] In the oxide thin film formation process, a gas substantially free of impurity gases is used. Specifically, in the oxide thin film formation process, one or more gases selected from the group consisting of argon, hydrogen, and oxygen, which are substantially free of impurity gases, are used as the sputtering gas. Among these, the sputtering gas is preferably a mixed gas of argon and oxygen, which is substantially free of impurity gases. The phrase "substantially free of impurity gases" means that impurity gases other than argon, hydrogen, and oxygen are not actively introduced, except for adsorbed water introduced during gas insertion and gases that cannot be eliminated (unavoidable impurity gases), such as gases leaking from the chamber or adsorbed gases. In this embodiment, for example, a commercially available mixed gas of high-purity argon and high-purity oxygen can be used as the sputtering gas. It is preferable to eliminate impurities from the sputtering gas, if possible.

[0106] The proportion of impurity gas in the sputtering gas is preferably 0.1% by volume or less, more preferably 0.05% by volume or less. If the proportion of impurity gas is 0.1% by volume or less, crystallization of the oxide thin film proceeds without any problems. The purity of the high-purity argon and high-purity oxygen is preferably 99% by volume or more, more preferably 99.9% by volume or more, and even more preferably 99.99% by volume or more.

[0107] The oxygen partial pressure in the sputtering gas mixture of argon and oxygen is preferably in the range of 0% to 50% by volume, more preferably in the range of 5% to 30% by volume. If the oxygen partial pressure is in the above range, the film will easily crystallize and become a semiconductor when heated. By changing the oxygen partial pressure, the degree of oxidation of the resulting thin film, i.e., the degree of crystallization, can be adjusted. The oxygen partial pressure can be selected appropriately as needed.

[0108] In the heat treatment step, the heat treatment temperature for crystallizing the formed amorphous thin film is preferably in the range of 300°C to 450°C, and more preferably 300°C to 350°C. If the heat treatment temperature is 300°C or higher, the oxide thin film is easily crystallized. If the heat treatment temperature is 450°C or lower, abnormal crystal growth and enlargement of crystal grains can be suppressed.

[0109] In the heat treatment step, the heat treatment time for crystallizing the amorphous thin film after film formation is preferably 0.1 to 5 hours, more preferably 0.3 to 3 hours, and even more preferably 0.5 to 2 hours. If the heat treatment time is 0.1 hours or more, the oxide thin film is likely to crystallize without failing to crystallize. If the heat treatment time is 5 hours or less, it is economically advantageous.

[0110] In the heat treatment step, the temperature rise rate is preferably 2°C / min or more and 40°C / min or less, and more preferably 3°C / min or more and 20°C / min or less. If the temperature rise rate in the heat treatment step is 2°C / min or more, the production efficiency of the oxide thin film is improved compared to when it is less than 1°C / min. If the temperature rise rate in the heat treatment step is 40°C / min or less, the metal element is uniformly diffused during crystallization, and crystals can be formed in which metal is not segregated at grain boundaries.

[0111] The crystalline oxide thin film according to this embodiment can be applied to various integrated circuits such as logic circuits, memory circuits, and differential amplifier circuits, and can be applied to electronic devices, etc. The crystalline oxide thin film according to this embodiment can also be applied as a partial layer of a solar cell, and a partial layer of a display device such as a liquid crystal element, an organic electroluminescence element, an inorganic electroluminescence element, a micro organic EL display, a micro LED (Light Emitting Diode) display, and a mini LED display. Furthermore, the crystalline oxide thin film according to this embodiment can be applied as a partial layer of a solid-state imaging element, an X-ray sensor, a power semiconductor element, a touch panel, an LSI (Large Scale Integrated Circuit), a resistance change type memory, a DRAM (Dynamic Random Access Memory), a ferroelectric memory, a BEOL (Back End of Line), and a microprocessor. The crystalline oxide thin film according to this embodiment can also be used as a semiconductor layer of a field-effect transistor, a static induction transistor, a quantum tunnel field-effect transistor, a Schottky barrier transistor, a Schottky diode, a PN diode, and a resistor element, or as a part of any of these layers.

[0112] [Thin Film Transistor and Electronic Device] The thin film transistor according to this embodiment includes a thin film transistor including the crystalline oxide thin film according to this embodiment. The crystalline oxide thin film according to this embodiment is preferably an oxide semiconductor thin film.

[0113] It is preferable to use the crystalline oxide thin film according to this embodiment as the channel layer of a thin film transistor.

[0114] When the thin film transistor according to this embodiment has the crystalline oxide thin film according to this embodiment as a channel layer, other element configurations in the thin film transistor are not particularly limited, and known element configurations can be adopted.

[0115] The thin film transistor according to this embodiment can be suitably used in electronic devices. Specifically, the thin film transistor according to this embodiment can be suitably used in display devices such as liquid crystal displays and organic EL displays.

[0116] The thickness of the channel layer in the thin film transistor according to this embodiment is usually 10 nm or more and 300 nm or less, and preferably 20 nm or more and 250 nm or less.

[0117] The channel layer in the thin film transistor according to this embodiment is usually used in an N-type region, but can also be used in various semiconductor devices such as a PN junction transistor in combination with various P-type semiconductors, such as a P-type Si-based semiconductor, a P-type oxide semiconductor, and a P-type organic semiconductor.

[0118] The thin film transistor according to this embodiment can be applied to various integrated circuits such as field-effect transistors, logic circuits, memory circuits, and differential amplifier circuits. Furthermore, in addition to field-effect transistors, the thin film transistor can also be applied to static induction transistors, Schottky barrier transistors, Schottky diodes, and resistor elements. That is, the thin film transistor according to this embodiment can be applied to the applications exemplified in the "Applications of Thin Film Transistors" section described later.

[0119] The structure of the thin film transistor according to this embodiment can be selected from known structures such as bottom gate, bottom contact, top gate, and top contact, without any restrictions. The thin film transistor according to this embodiment can be suitably used in a display device.

[0120] Specific examples of thin film transistors are shown in Figures 2 and 3. As shown in Figure 2, a thin film transistor 100 includes a silicon wafer 20, a gate insulating film 30, an oxide thin film 40, a source electrode 50, a drain electrode 60, and interlayer insulating films 70 and 70A.

[0121] The silicon wafer 20 is a gate electrode. The gate insulating film 30 is an insulating film that blocks electrical conduction between the gate electrode and the oxide thin film 40, and is provided on the silicon wafer 20. The oxide thin film 40 is a channel layer and is provided on the gate insulating film 30. The crystalline oxide thin film according to this embodiment is used for the oxide thin film 40.

[0122] The source electrode 50 and the drain electrode 60 are conductive terminals for passing source current and drain current through the oxide thin film 40, and are provided so as to be in contact with the vicinity of both ends of the oxide thin film 40. The interlayer insulating film 70 is an insulating film that blocks conduction between the source electrode 50 and the drain electrode 60 and the oxide thin film 40 except at the contact portions between the source electrode 50 and the drain electrode 60 and the oxide thin film 40. The interlayer insulating film 70A is an insulating film that blocks conduction between the source electrode 50 and the drain electrode 60 and the oxide thin film 40 except at the contact portions between the source electrode 50 and the drain electrode 60 and the oxide thin film 40. The interlayer insulating film 70A is also an insulating film that blocks conduction between the source electrode 50 and the drain electrode 60. The interlayer insulating film 70A also functions as a channel layer protective layer.

[0123] 3, the structure of the thin-film transistor 100A is similar to that of the thin-film transistor 100, except that the source electrode 50 and the drain electrode 60 are provided so as to be in contact with both the gate insulating film 30 and the oxide thin film 40. Another difference is that an interlayer insulating film 70B is provided integrally so as to cover the gate insulating film 30, the oxide thin film 40, the source electrode 50, and the drain electrode 60.

[0124] There are no particular limitations on the materials forming the drain electrode 60, the source electrode 50, and the gate electrode, and any commonly used material can be selected. In the examples shown in Figures 2 and 3, a silicon wafer is used as the substrate, and the silicon wafer also functions as the electrode, but the electrode material is not limited to silicon. For example, indium tin oxide (ITO), indium zinc oxide (IZO), ZnO, and SnO ２ 2 and 3, a transparent electrode such as a metal electrode of Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, Ta, or the like, or a metal electrode or laminated electrode of an alloy containing these can be used. Furthermore, in FIGS. 2 and 3, a gate electrode may be formed on a substrate such as glass.

[0125] There is no particular limitation on the material for forming the interlayer insulating films 70, 70A, and 70B, and any commonly used material can be selected. ｘ , M.N. ｘ , and M.N. ｘ O ｙ (where M is a metal element, and x and y are real numbers greater than 0. The same applies to x and y in the compounds exemplified below.) Specific examples of the material include SiO ２ , SiO ｘ , SiN ｘ , and SiN ｘ O ｙ Furthermore, the material can be, for example, Al ２ O ３ , Ta ２ O ５ , TiO ２ , MgO, ZrO ２ , CeO ２ , K. ２ O, Li ２ O, Na ２ O, Rb ２ O, Sc ２ O ３ , Y ２ O ３ , HfO ２ , CaHfO ３ , PbTiO ３ ,BaTa ２ O ６ , SrTiO ３ , Sm ２ O ３ Compounds such as AlN can also be used. The valence of the anions (oxygen anions and nitrogen anions) in these oxide compounds and nitride compounds is not particularly limited as long as it is a real number greater than 0.

[0126] When the thin film transistor according to this embodiment is a back channel etch type (bottom gate type), it is preferable to provide a protective film on the drain electrode, the source electrode, and the channel layer. By providing a protective film, the durability of the TFT is likely to be improved even when the TFT is driven for a long time. In the case of a top gate type TFT, for example, a gate insulating film is formed on the channel layer.

[0127] The protective film or insulating film can be formed by, for example, CVD, which may require high-temperature processes. Furthermore, the protective film or insulating film often contains impurity gases immediately after deposition, so it is preferable to subject it to a heat treatment (annealing treatment). Removing the impurity gases through the heat treatment results in a stable protective film or insulating film, which facilitates the formation of highly durable TFT elements.

[0128] By using the crystalline oxide thin film according to this embodiment, the film is less susceptible to the effects of temperature in the CVD process and subsequent heat treatment, and therefore the stability of the TFT characteristics can be improved even when a protective film or insulating film is formed.

[0129] Among transistor characteristics, the On / Off characteristics are a factor that determines the display performance of a display. When using thin film transistors to switch liquid crystal, it is preferable that the On / Off ratio be six digits or more. In the case of OLEDs, the On current is important because they are driven by current, but it is also preferable that the On / Off ratio be six digits or more.

[0130] The thin film transistor according to this embodiment has an On / Off ratio of 1×10 ６ The On / Off ratio is determined by determining the ratio [On current value / Off current value], where the value of Id at Vg = -10 V is the Off current value and the value of Id at Vg = 20 V is the On current value. The mobility of the TFT according to this embodiment is 5 cm ２ / Vs or more, and ２ / Vs or more is preferable. The saturation mobility can be determined from the transfer characteristics when a drain voltage of 20 V is applied. Specifically, it can be calculated by creating a graph of the transfer characteristics Id-Vg, calculating the transconductance (Gm) for each Vg, and determining the saturation mobility using the formula for the saturation region. Id is the current between the source and drain electrodes, and Vg is the gate voltage when a voltage Vd is applied between the source and drain electrodes.

[0131] The threshold voltage (Vth) is preferably −3.0 V or more and 3.0 V or less, more preferably −2.0 V or more and 2.0 V or less, and even more preferably −1.0 V or more and 1.0 V or less. When the threshold voltage (Vth) is −3.0 V or more, a thin film transistor with high mobility can be obtained. When the threshold voltage (Vth) is 3.0 V or less, a thin film transistor with a small off-current and a large on-off ratio can be obtained.

[0132] From the graph of transfer characteristics, the threshold voltage (Vth) is calculated as follows: －９ It can be defined as the gate voltage Vg at A. The On / Off ratio is 10 ６ That's it, 10 １２ The following is preferred: ７ That's it, 10 １１ More preferably, 10 or less ８ That's it, 10 １０ More preferably, the On / Off ratio is 10 or less. ６ If the On / Off ratio is 10 or more, the liquid crystal display can be driven. １２ If the On / Off ratio is 10 or less, an organic EL display with high contrast can be driven. １２ If the off-state current is 10 －１１ A or less, and when the thin film transistor is used as a transfer transistor or reset transistor of a CMOS image sensor, it is possible to lengthen the image retention time and improve the sensitivity.

[0133] <Quantum Tunnel Field Effect Transistor> The crystalline oxide thin film according to this embodiment can also be used in a quantum tunnel field effect transistor (FET), which may also be referred to as a quantum tunnel field effect transistor.

[0134] 4 is a schematic diagram (longitudinal cross-sectional view) of a quantum tunnel field effect transistor (FET) according to one embodiment. The quantum tunnel field effect transistor 501 includes a p-type semiconductor layer 503, an n-type semiconductor layer 507, a gate insulating film 509, a gate electrode 511, a source electrode 513, and a drain electrode 515.

[0135] A p-type semiconductor layer 503, an n-type semiconductor layer 507, a gate insulating film 509, and a gate electrode 511 are stacked in this order. A source electrode 513 is provided on the p-type semiconductor layer 503. A drain electrode 515 is provided on the n-type semiconductor layer 507. The p-type semiconductor layer 503 is a p-type Group IV semiconductor layer, and in this case is a p-type silicon layer. In this case, the n-type semiconductor layer 507 is an n-type oxide thin film according to the above embodiment. The source electrode 513 and the drain electrode 515 are conductive films.

[0136] Although not shown in Fig. 4, an insulating layer may be formed on the p-type semiconductor layer 503. In this case, the p-type semiconductor layer 503 and the n-type semiconductor layer 507 are connected via a contact hole, which is a region where the insulating layer is partially opened. Although not shown in Fig. 4, the quantum tunnel field effect transistor 501 may also have an interlayer insulating film covering its upper surface.

[0137] The quantum tunnel field effect transistor 501 is a quantum tunnel field effect transistor (FET) that performs current switching by controlling the current tunneling through an energy barrier formed by a p-type semiconductor layer 503 and an n-type semiconductor layer 507 using the voltage of a gate electrode 511. In this structure, the band gap of the oxide semiconductor that constitutes the n-type semiconductor layer 507 is large, and the off-current can be reduced.

[0138] FIG. 5 shows a schematic diagram (longitudinal cross-sectional view) of a quantum tunnel field-effect transistor 501A according to another embodiment. The quantum tunnel field-effect transistor 501A has the same configuration as the quantum tunnel field-effect transistor 501, except that a silicon oxide layer 505 is formed between a p-type semiconductor layer 503 and an n-type semiconductor layer 507. The presence of the silicon oxide layer reduces the off-state current. The thickness of the silicon oxide layer 505 is preferably 10 nm or less. By making the thickness of the silicon oxide layer 505 10 nm or less, it is possible to prevent tunneling current from flowing, the formation of an energy barrier from being difficult, and changes in barrier height, thereby preventing a decrease or change in the tunneling current. The thickness of the silicon oxide layer 505 is preferably 8 nm or less, more preferably 5 nm or less, even more preferably 3 nm or less, and even more preferably 1 nm or less.

[0139] In the quantum tunnel field effect transistors 501 and 501A, the n-type semiconductor layer 507 is also an n-type oxide semiconductor.

[0140] The oxide thin film constituting the n-type semiconductor layer 507 may be amorphous. When the oxide thin film constituting the n-type semiconductor layer 507 is amorphous, it can be etched with an organic acid such as oxalic acid, the difference in etching rate with other layers becomes large, and etching can be performed satisfactorily without affecting metal layers such as wiring.

[0141] The oxide thin film constituting the n-type semiconductor layer 507 may be crystalline. When the oxide thin film constituting the n-type semiconductor layer 507 is crystalline, the band gap becomes larger than in the case of an amorphous material, and the off-current can be reduced. Since the work function can also be increased, it becomes easier to control the current tunneling through the energy barrier formed by the p-type Group IV semiconductor material and the n-type semiconductor layer 507.

[0142] The method for manufacturing the quantum tunnel field effect transistor 501 is not particularly limited, but the following method can be exemplified. First, as shown in Fig. 6A, an insulating film 505A is formed on a p-type semiconductor layer 503, and a part of the insulating film 505A is opened by etching or the like to form a contact hole 505B. Next, as shown in Fig. 6B, an n-type semiconductor layer 507 is formed on the p-type semiconductor layer 503 and the insulating film 505A. At this time, the p-type semiconductor layer 503 and the n-type semiconductor layer 507 are connected via the contact hole 505B.

[0143] 6C, a gate insulating film 509 and a gate electrode 511 are formed in this order on the n-type semiconductor layer 507. Next, as shown in FIG. 6D, an interlayer insulating film 519 is provided so as to cover the insulating film 505A, the n-type semiconductor layer 507, the gate insulating film 509, and the gate electrode 511.

[0144] Next, as shown in Fig. 6E, a contact hole 519A is formed by opening a portion of the insulating film 505A and interlayer insulating film 519 on the p-type semiconductor layer 503, and a source electrode 513 is provided in the contact hole 519A. Furthermore, as shown in Fig. 6E, a contact hole 519B is formed by opening a portion of the gate insulating film 509 and interlayer insulating film 519 on the n-type semiconductor layer 507, and a drain electrode 515 is formed in the contact hole 519B. Through the above procedure, the quantum tunnel field effect transistor 501 can be manufactured.

[0145] After forming n-type semiconductor layer 507 on p-type semiconductor layer 503, heat treatment is performed at a temperature of 150° C. or higher and 600° C. or lower, thereby forming silicon oxide layer 505 between p-type semiconductor layer 503 and n-type semiconductor layer 507. By adding this step, quantum tunnel field effect transistor 501A can be manufactured.

[0146] The thin film transistor according to this embodiment is preferably a channel-doped thin film transistor, which is a transistor in which carriers in the channel are appropriately controlled by n-type doping rather than by oxygen deficiency, which is susceptible to fluctuations in response to external stimuli such as atmosphere and temperature, and which has the effect of achieving both high mobility and high reliability.

[0147] <Applications of Thin Film Transistor> The thin film transistor according to this embodiment can be suitably used in solar cells, display elements (liquid crystal elements, organic electroluminescence elements, inorganic electroluminescence elements, etc.), and power semiconductor elements. The thin film transistor according to this embodiment can be suitably used as a transistor in active matrix devices such as display devices (liquid crystal displays, organic electroluminescence (EL) displays, micro organic EL displays, micro light-emitting diode (LED) displays, mini LED displays, etc.), solid-state imaging elements, and touch panels. The thin film transistor according to this embodiment can also be applied to various integrated circuits such as field-effect transistors, logic circuits, memory circuits, and differential amplifier circuits, which can be applied to electronic devices, etc. The electronic device according to this embodiment preferably includes a thin film transistor. Furthermore, the thin film transistor according to this embodiment can be applied to static induction transistors and Schottky barrier transistors in addition to field-effect transistors. The thin film transistor according to this embodiment can also be applied as a transistor for sensors such as image sensors, X-ray sensors, and biosensors.

[0148] Hereinafter, the case where the thin film transistor according to this embodiment is used in a display device and a solid-state image sensor will be described.

[0149] First, a case where the thin film transistor according to this embodiment is used in a display device will be described with reference to Figures 7A to 7C. Figure 7A is a top view of the display device according to this embodiment. Figure 7B is a circuit diagram for explaining the circuit of the pixel portion when a liquid crystal element is applied to the pixel portion of the display device according to this embodiment. Also, Figure 7C is a circuit diagram for explaining the circuit of the pixel portion when an organic EL element is applied to the pixel portion of the display device according to this embodiment.

[0150] The thin film transistor according to this embodiment can be used as a transistor disposed in a pixel portion. Since the thin film transistor according to this embodiment can be easily made into an n-channel type, part of a driver circuit that can be configured with an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. By using the thin film transistor described in this embodiment for the pixel portion or the driver circuit, a highly reliable display device can be provided.

[0151] 7A shows an example of a top view of an active matrix display device. A pixel portion 301, a first scanning line driver circuit 302, a second scanning line driver circuit 303, and a signal line driver circuit 304 are formed on a substrate 300 of the display device. A plurality of signal lines are arranged in the pixel portion 301, extending from the signal line driver circuit 304, and a plurality of scanning lines are arranged in the pixel portion 301, extending from the first scanning line driver circuit 302 and the second scanning line driver circuit 303. Pixels each having a display element are arranged in a matrix at the intersections of the scanning lines and the signal lines. The substrate 300 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0152] 7A , the first scanning line driver circuit 302, the second scanning line driver circuit 303, and the signal line driver circuit 304 are formed on the same substrate 300 as the pixel portion 301. This reduces the number of components, such as external driver circuits, and thus reduces costs. Furthermore, if the driver circuits are provided outside the substrate 300, it becomes necessary to extend the wiring, which increases the number of connections between the wiring. If the driver circuits are provided on the same substrate 300, the number of connections between the wiring can be reduced, thereby improving reliability and yield.

[0153] 7B shows an example of a pixel circuit configuration, which is applicable to the pixel portion of a VA-type liquid crystal display device.

[0154] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. This allows the signals applied to each pixel electrode of a multi-domain pixel to be controlled independently.

[0155] The gate wiring 312 of the transistor 316 and the gate wiring 313 of the transistor 317 are separated so as to receive different gate signals. On the other hand, the source or drain electrode 314 functioning as a data line is used in common by the transistors 316 and 317. The thin film transistors according to this embodiment can be used for the transistors 316 and 317. This makes it possible to provide a highly reliable liquid crystal display device.

[0156] The transistor 316 is electrically connected to a first pixel electrode, and the transistor 317 is electrically connected to a second pixel electrode. The first pixel electrode and the second pixel electrode are separated from each other. The shapes of the first pixel electrode and the second pixel electrode are not particularly limited. For example, the first pixel electrode may be V-shaped.

[0157] The gate electrode of the transistor 316 is connected to the gate wiring 312, and the gate electrode of the transistor 317 is connected to the gate wiring 313. By applying different gate signals to the gate wiring 312 and the gate wiring 313, the operation timing of the transistors 316 and 317 can be made different, thereby controlling the alignment of the liquid crystal.

[0158] Furthermore, a storage capacitor may be formed by the capacitor wiring 310, a gate insulating film that functions as a dielectric, and a capacitor electrode that is electrically connected to the first pixel electrode or the second pixel electrode.

[0159] The multi-domain structure has one pixel having a first liquid crystal element 318 and a second liquid crystal element 319. The first liquid crystal element 318 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween, and the second liquid crystal element 319 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0160] The pixel portion is not limited to the configuration shown in Fig. 7B, and may include a switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit.

[0161] Another example of the circuit configuration of a pixel is shown in Fig. 7C, which shows the structure of a pixel portion of a display device using organic EL elements.

[0162] 7C is a diagram showing an example of an applicable circuit for the pixel section 320. Here, an example is shown in which two n-channel transistors are used in one pixel. The crystalline oxide thin film according to this embodiment can be used in the channel formation region of the n-channel transistor. Digital time grayscale driving can be applied to the circuit for the pixel section.

[0163] The thin film transistor according to this embodiment can be used for the switching transistor 321 and the driving transistor 322. This makes it possible to provide a highly reliable organic EL display device.

[0164] The configuration of the circuit in the pixel portion is not limited to the configuration shown in Fig. 7C. A switch, a resistor, a capacitor, a sensor, a transistor, or a logic circuit may be added to the circuit in the pixel portion shown in Fig. 7C. The above is a description of the case where the thin film transistor according to this embodiment is used in a display device.

[0165] Next, a case where the thin film transistor according to this embodiment is used in a solid-state imaging device will be described with reference to FIG.

[0166] A CMOS (Complementary Metal Oxide Semiconductor) image sensor is a solid-state imaging device that holds a potential in a signal charge storage section and outputs that potential to a vertical output line via an amplification transistor. If a leak current occurs in the reset transistor and / or transfer transistor included in the CMOS image sensor, the leak current causes charging or discharging, changing the potential of the signal charge storage section. When the potential of the signal charge storage section changes, the potential of the amplification transistor also changes, resulting in a value that deviates from the original potential, degrading the captured image.

[0167] The operational effect when the thin film transistor according to this embodiment is applied to the reset transistor and transfer transistor of a CMOS image sensor will be described. Either a thin film transistor or a bulk transistor may be applied to the amplifying transistor.

[0168] 8 is a diagram showing an example of the pixel configuration of a CMOS image sensor. A pixel is composed of a photodiode 3002, which is a photoelectric conversion element, a transfer transistor 3004, a reset transistor 3006, an amplifier transistor 3008, and various wirings, and a plurality of pixels are arranged in a matrix to form a sensor. A selection transistor electrically connected to the amplifier transistor 3008 may be provided. The transistor symbols "OS" and "Si" represent oxide semiconductor and silicon, respectively, and represent materials that are preferable for use in the respective transistors. This also applies to the subsequent drawings.

[0169] The photodiode 3002 is connected to the source side of the transfer transistor 3004, and a signal charge storage region 3010 (also called FD: floating diffusion) is formed on the drain side of the transfer transistor 3004. The source of the reset transistor 3006 and the gate of the amplification transistor 3008 are connected to the signal charge storage region 3010. As an alternative configuration, the reset power supply line 3110 can be eliminated. For example, the drain of the reset transistor 3006 can be connected to the power supply line 3100 or the vertical output line 3120 instead of the reset power supply line 3110. Note that the crystalline oxide thin film according to this embodiment may be used for the photodiode 3002, and the same material as the oxide thin films used for the transfer transistor 3004 and the reset transistor 3006 may be used.

[0170] The present invention will be specifically described below based on examples, but the present invention is not limited to these examples.

[0171] [1] Production of sputtering targets (Examples 1, 2, 5, and 6) Sputtering targets including oxide sintered bodies containing In, Ga, and O elements were produced. The specific procedure is as follows.

[0172] First, as a raw material powder, In having an average particle size of 0.3 μm was used. ２ O ３ and Ga with an average particle size of 1 μm ２ O ３ were prepared and weighed to achieve the atomic composition ratios (at %) shown in Tables 1 and 2. In Tables 1 and 2, the notation "metal composition ratio [at %]" corresponds to the above-mentioned atomic composition ratios (at %). The numerical values ​​shown in "at %" indicate the atomic composition ratios of indium, gallium, zinc, and tin expressed as a percentage. The same applies to the notation "metal composition ratio [at %]" in Tables 3 to 8 described below.

[0173] Next, Ga ２ O ３ Water, a binder, a dispersant, and an antifoaming agent are added to the mixture, and Ga ２ O ３ The preliminary grinding was carried out using a bead mill (manufactured by Ashizawa Fine Tech) as the grinding machine, zirconia beads with a diameter of 0.1 mm as the grinding media, and the peripheral speed of the bead mill was set to 14 m / s, and grinding was carried out for 3 hours. ２ O ３ The particle size of the Ga after pre-milling was 0.28 μm or less. ２ O ３ The particle size was confirmed using a particle size distribution measuring device (LA950 manufactured by HORIBA) and an SEM device.

[0174] Next, the prepared In ２ O ３ and pre-ground Ga ２ O ３The raw material powder was mixed to obtain a mixed raw material powder, and then ammonia-neutralized acrylic acid methacrylic acid copolymer (Banstar X754B, manufactured by Sanmei Kasei Co., Ltd.) was added as a dispersant, polyvinyl alcohol as a thickener, and water, and the mixture was mixed and pulverized in a bead mill for 2 hours to obtain a raw material mixture with a solid content of 70% by mass. The obtained raw material mixture was supplied to a spray dryer and granulated at a rotation speed of 12,000 rpm and a hot air temperature of 150°C to obtain a raw material granulated powder.

[0175] Next, the raw material granulated powder was passed through a 100 mesh sieve to remove raw material granulated powder with a particle size exceeding 150 μm, and then passed through a 500 mesh sieve to remove raw material granulated powder with a particle size of less than 25 μm, thereby adjusting the particle size of the raw material granulated powder to a range of 25 μm or more and 150 μm or less.

[0176] Next, the raw granulated powder after particle size adjustment was uniformly filled into a mold having an inner diameter of 300 mm × 600 mm × 9 mm, and pressure-molded using a cold press. After pressure-molding, the mixture was further molded using a cold isostatic pressing (CIP) device at a pressure of 294 MPa to obtain a compact.

[0177] Three compacts were prepared, and the three obtained compacts were heated to 780°C in an oxygen atmosphere in a sintering furnace, held at 780°C for 5 hours, and then heated to 1350°C and held at this sintering temperature (1350°C) for 20 hours. The furnace was then cooled to obtain oxide sintered bodies. The heating rate was 2°C / min.

[0178] The three obtained sintered bodies were each cut and surface ground to obtain three oxide sintered body plates of 142 mm x 305 mm x 5 mmt. Of these, one was used for property evaluation and two were used as G1 targets [142 mm x 610 mm (2-section) x 5 mmt]. For surface grinding, the oxide sintered bodies were surface ground using a surface grinder with a diamond grinding wheel having a grinding wheel grain size of 80 μm. The surface grinding processing conditions are as follows. Surface grinding processing conditions: Feed rate v of the grinding object: 1 m / min Grinding wheel peripheral speed V: 500 m / min Grinding wheel cutting amount (cutting depth t): 5 μm Grinding wheel abrasive grain size d: 80 μm Grinding wheel type: diamond grinding wheel

[0179] After grinding under the above surface grinding conditions, the workpiece was successively ground under the above surface grinding conditions using a diamond grinding wheel with a grit size of 40 μm, then a diamond grinding wheel with a grit size of 20 μm, and finally a grinding wheel with a finer grit size.

[0180] Two of the obtained oxide sintered body plates (142 mm x 305 mm x 5 mm thick) were bonded to a backing plate made of Cu (copper) to produce a G1 target. The surface that had been flat-ground was used as the sputtering surface, and the surface opposite the sputtering surface (the surface that had been roughly polished with a grinding wheel with an abrasive grain size of 130 μm) was used as the bonding surface, and this bonding surface of the oxide sintered body plate was bonded to the backing plate. The bonding rate was 98% or higher for all targets. When the oxide sintered body plate was bonded to the backing plate, no cracks occurred in the oxide sintered body plate, and sputtering targets could be produced satisfactorily. The bonding rate (bonding rate) was confirmed by X-ray CT.

[0181] (Examples 3 and 4) The raw material powder was the same as that of Example 1. ２ O ３ and Ga ２ O ３ In addition, ZnO with an average particle size of 0.8 μm and SnO with an average particle size of 0.4 μm ２ were prepared and weighed to have the atomic composition ratios (at%) shown in Tables 1 and 2. ２ O ３ Preliminary pulverization was carried out under the same conditions as in Example 1. The average particle size of ZnO after preliminary pulverization was 0.32 μm. Except for these, a sintered body was obtained in the same manner as in Example 1. Thereafter, the obtained sintered body was ground and bonded in the same manner as in Example 1 to form a sputtering target, which was evaluated in the same manner as in Example 1.

[0182] (Comparative Examples 1 to 3) First, the same In powder as in Example 1 was used as the raw material powder. ２ O ３ and Ga ２ O ３were prepared and weighed to achieve the atomic composition ratios (at%) shown in Table 3. In Comparative Examples 1 to 3, the raw material powders were not premixed. Next, the raw material powders were mixed for 4 hours in a planetary ball mill. The mixed raw material powders were dried and classified to obtain a raw material mixture. The obtained raw material mixture was molded in the same manner as in Example 1. Three compacts were prepared, and the three obtained compacts were heated to 780°C in an oxygen atmosphere in a sintering furnace, held at 780°C for 5 hours, further heated to 1400°C, and held at this sintering temperature (1400°C) for 20 hours. The resulting oxide sintered body was then cooled in the furnace to obtain an oxide sintered body. The heating rate was 2°C / min. Subsequently, the sputtering targets were ground and bonded in the same manner as in Example 1 to obtain sputtering targets, which were evaluated in the same manner as in Example 1.

[0183] Comparative Examples 4 to 6: The same In powder as in Example 1 was used as the raw material powder. ２ O ３ and Ga ２ O ３ were prepared and weighed so as to have the atomic composition ratios (at %) shown in Table 4, and the same procedures as in Example 1 were carried out to obtain sputtering targets.

[0184] [1-1] Evaluation of sintered body <1-A> Atomic composition ratio The atomic composition ratio of the sintered body was analyzed using an inductively coupled plasma atomic emission spectrometer (ICP-AES, manufactured by Shimadzu Corporation). It was confirmed that the obtained sintered body had the atomic composition ratios shown in Tables 1 to 4.

[0185] <1-B> XRD Measurement and Identification of Crystalline Phase The obtained sintered body was subjected to XRD measurement using an X-ray diffraction measurement device to examine the crystal structure. The measurement conditions for the X-ray diffraction measurement (XRD) were as follows. Device: D8 DISCOVER Plus (Bruker Japan Co., Ltd.) X-ray: CuKα (1.5418 Å)

[0186] <1-C> Measurement of Crystal Grain Size The crystal grain size was measured as follows. The surface of a sintered body produced in the same batch as the sputtering target was divided into 16 equal areas, and 16 centers of each square were cut out to 1 cm squares. The cut sputtering target was embedded in resin and mirror-polished using a polishing device (manufactured by Buehler). The surface was made conductive with an osmium coat, and then placed in a scanning electron microscope (SEM) (manufactured by Hitachi High-Technologies Corporation). The measurement surface was further divided into 9 equal areas, and secondary electron images and backscattered electron images were observed at 2000x magnification at the 9 centers of each square. EDS measurement was also performed during SEM measurement to determine the atomic ratio of each crystal grain. The type of crystal of each crystal grain was identified by comparing it with the crystal structure identified by XRD. Particle diameters were measured from the obtained SEM images, and the average particle diameters of the particles within the 9 boxes were calculated. This operation was performed on each sample cut from 16 locations, and the average value of the particle diameters obtained from a total of 144 SEM images was taken as the average particle diameter. For particles with an aspect ratio of less than 2, the particle diameter of the crystal grain was measured as the circle-equivalent diameter based on JIS R1670:2006. Specifically, the procedure for measuring the circle-equivalent diameter is to place a circular ruler on the grain to be measured in the microstructure photograph and read the diameter equivalent to the area of ​​the grain to be measured. For particles with an aspect ratio of 2 or more, the average value of the longest diameter and the shortest diameter was taken as the particle diameter.

[0187] <1-D> Density The actual density of the obtained oxide sintered body was measured by Archimedes' method. Specifically, it was measured using water at room temperature.

[0188] <1-E> Flexural Strength Thirty test pieces in the shape of a rectangular pillar having a thickness of 3 mm, a width of 4 mm, and a total length of 36 mm were cut out from the obtained oxide sintered body, and the three-point bending strength was measured using a material testing machine (EZ Graph manufactured by Shimadzu Corporation) in accordance with JIS R 1601:2008, and the average value of the three-point bending strength measurements of the 30 test pieces was taken as the flexural strength (flexural strength).

[0189] <1-F> Power Resistance The prepared sputtering target was loaded into a sputtering apparatus and subjected to DC discharge to check for the presence or absence of cracks. Power resistance is the maximum sputtering power at which cracks do not occur in the sputtering target. After discharging the sputtering power at DC 1.5 kW for 1 hour, the chamber was opened and the presence or absence of cracks was visually observed. The sputtering power was then increased to 1.75 kW and discharged at that sputtering power for 1 hour, after which the chamber was opened and the presence or absence of cracks was visually observed. This procedure was repeated by increasing the sputtering power in 0.25 kW increments until cracks were confirmed in the sputtering target. The maximum power at which cracks were not confirmed was used as an index of power resistance. Note that because sputtering power varies depending on the apparatus, the value obtained by dividing the input power by the target area was standardized as the power density. The evaluation conditions for power resistance are as follows:

[0190] <Device> ULVAC SMO-200I

[0191] <Sputtering conditions> Atmospheric gas: Ar (argon) + O ２ (Oxygen) Oxygen partial pressure during discharge: 20% Back pressure before discharge: 2 x 10 －４ Pa Sputtering pressure during discharge: 0.5 Pa

[0192] 9 shows the X-ray diffraction pattern of the sintered body used for the target produced in Example 1. As shown in FIG. 9, the sintered body obtained in Example 1 contains In ２ O ３ and GaInO ３ In addition, it can be seen that peaks are shown at the following positions of the incident angle (2θ): (A) 28° or more and 29° or less, (B) 45° or more and less than 46°, (C) 46° or more and less than 47°, (D) 47° or more and 48° or less, and (E) 50° or more and 51° or less. Therefore, it can be seen that the sintered body obtained in Example 1 contains crystal structure A.

[0193] Fig. 10 shows a mapping image of oxygen atoms in the sintered body used in the target produced in Example 1. As shown in Fig. 10, it can be seen that the regions with a relatively low content of O element are continuous. In Fig. 10, the areas that appear relatively dark indicate the regions with a relatively low content of O element.

[0194]

[0195]

[0196]

[0197]

[0198] [2] Fabrication of Oxide Thin Films and TFTs [2-1] Oxide Thin Films (Examples 1 to 6, and Comparative Examples 1 to 6) Using the sputtering targets fabricated in Examples 1 to 6 and Comparative Examples 1 to 6, a 40 nm oxide thin film (oxide semiconductor thin film layer) was formed on a silicon wafer with a 100 nm thermal oxide film (gate insulating film) by sputtering, via a metal mask. The sputtering was performed using high-purity argon and high-purity oxygen gases as sputtering gases. A sample in which only a 40 nm oxide thin film layer was formed on a glass substrate was also fabricated under the same conditions. The glass substrate used was an ABC-G manufactured by Nippon Electric Glass Co., Ltd.

[0199] [2-2] Formation of Source / Drain Electrodes Next, titanium metal was sputtered onto the oxide thin film of the sample formed in this order, using a metal mask with source / drain contact holes, to form titanium electrodes as source / drain electrodes, thereby producing a laminate, and a thin film transistor (TFT) was manufactured. The resulting laminate was subjected to a heat treatment (annealing treatment) at 350°C in air for 1 hour, and the performance of the thin film transistor (TFT) was evaluated.

[0200] <2-A> Crystalline Properties of Semiconductor Films For samples consisting of a glass substrate and an oxide thin film layer (i.e., a sample in which only an oxide thin film layer with a thickness of 40 nm was formed on a glass substrate), the crystallinity of both the unheated film after sputtering (immediately after film deposition) and the film after heat treatment following film formation under the conditions described in Tables 5 to 8 was evaluated by X-ray diffraction (XRD) measurement. For the film quality before heating and the film quality after heating, if no peak was observed in the XRD measurement, the film was described as amorphous, and if a peak was observed in the XRD measurement and the film was crystallized, the film was described as crystalline.

[0201] <2-B> Evaluation of TFT characteristics The protective insulating film (SiO ２ The linear mobility was evaluated for the TFT before the formation of the thin film. The linear mobility was determined from the transfer characteristics when a drain voltage of 0.1 V was applied. Specifically, a graph of the transfer characteristics Id-Vg was created, the transconductance (Gm) for each Vg was calculated, and the mobility was derived using the linear region equation. Note that Gm is expressed as ∂(Id) / ∂(Vg), and Vg was applied from -10 to 20 V, with the maximum mobility within that range defined as the linear mobility. Unless otherwise specified in the present invention, the linear mobility was evaluated using this method. Id is the current between the source and drain electrodes, and Vg is the gate voltage when a voltage Vd is applied between the source and drain electrodes.

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[0206] 1, 1A, 1B, 1C: oxide sintered body, 3: backing plate, 20: silicon wafer, 30: gate insulating film, 40: oxide thin film, 50: source electrode, 60: drain electrode, 70: interlayer insulating film, 70A: interlayer insulating film, 70B: interlayer insulating film, 100: thin film transistor, 100A: thin film transistor, 300: substrate, 301: pixel section, 302: first scanning line driving circuit, 303: second scanning line driving circuit, 304: signal line driving circuit, 310: capacitance wiring, 312: gate wiring, 313: gate wiring, 314: drain electrode, 316: transistor, 317: transistor, 318: first liquid crystal element, 319: second liquid crystal element, 320: pixel section, 321: switching transistor, 322: driving transistor, 3002: photodiode, 3004: transfer transistor, 3006: reset transistor, 3008: amplification transistor, 3010: signal charge storage section, 3100: power supply line, 3110: reset power supply line, 3120: vertical output line, 501: quantum tunnel field effect transistor, 501A: quantum tunnel field effect transistor, 503: p-type semiconductor layer, 505: silicon oxide layer, 505A: insulating film, 505B: contact hole, 507: n-type semiconductor layer, 509: gate insulating film, 511: gate electrode, 513: source electrode, 515: drain electrode, 519: interlayer insulating film, 519A, 519B: contact holes.

Claims

1. A sputtering target comprising an oxide sintered body containing elements In, Ga, and O, The oxide sintered body is In ２ O ３ It includes a crystal structure represented by, The atomic composition ratio of the Ga element in the oxide sintered body satisfies the following formula (1): The flexural strength of the oxide sintered body is 140 MPa or more. Sputtering target. 8≦Ga / (In+Ga)≦20 (1)

2. The aforementioned In ２ O ３ The average grain size of the crystal structure represented by is 3 μm or less. The sputtering target according to claim 1.

3. The measured density by the Archimedes method was 6.3 g / cm³. ３ That's all. A sputtering target according to claim 1 or claim 2.

4. The oxide sintered body is GaInO ３ Includes a crystal structure represented by, A sputtering target according to claim 1 or claim 2.

5. The oxide sintered body further includes a crystal structure A in which diffraction peaks are observed at the incident angle (2θ) at the positions (A) to (E) below, as determined by X-ray (CuKα-ray) diffraction measurement. A sputtering target according to claim 1 or claim 2. (A) 28° or more, 29° or less (B) 45° or more, less than 46° (C) 46° or more, less than 47° (D) 47° or more, 48° or less (E) 50° or more, 51° or less

6. A method for manufacturing a sputtering target according to claim 1 or claim 2, A step of preparing raw material powder with a particle size of 0.5 μm or less, The process involves mixing the raw material powders to obtain a raw material mixture, then granulating the raw material mixture to obtain raw material granules, The process of forming the aforementioned raw material granules to obtain a molded body, The process includes the step of sintering the molded body to obtain the oxide sintered body. A method for manufacturing a sputtering target.

7. A crystalline oxide thin film using the sputtering target described in claim 1 or claim 2.

8. A thin-film transistor comprising a crystalline oxide thin film as described in claim 7.

9. An electronic device comprising a thin-film transistor as described in claim 8.