MEMORY ACCESS METHOD AND MEMORY ACCESS CONTROL DEVICE

Abstract

This memory access method comprises: a data storage instruction step (Step S11) of issuing a data storage instruction to instruct storage of one piece of data into a first memory or a second memory according to one first logical address; and a first storage path selection step (Step S12) of executing, in response to the data storage instruction, first selection of whether to execute a first storage step or a second storage step on the basis of the first logical address included in the data storage instruction. The first storage path selection step (Step S12) involves executing the first selection on the basis of a first interleaving rule or a second interleaving rule, executing the first selection on the basis of the first interleaving rule in response to one or a plurality of data storage instructions, and executing the first selection on the basis of the second interleaving rule in response to one or a plurality of subsequent data storage instructions.

Description

[Technical Field]

[0001] The present disclosure relates to a memory access method and a memory access control device. [Background technology]

[0002] One technique for improving the efficiency of memory access is memory interleaving, which divides memory into multiple areas that can operate simultaneously and allocates memory access appropriately to those areas, thereby improving overall access efficiency.

[0003] For example, Patent Document 1 discloses a technique in which the lowest few bits of an access address (logical address) are referenced and the area to which the access is to be allocated is determined from the information of the lowest few bits. For example, the lowest three bits are referenced, and access is allocated to eight areas based on eight different three-bit information. This method is easy to implement and functions as intended as long as the access type is to consecutive addresses. In other words, it is possible to allocate accesses evenly to each area.

[0004] However, if the access type is not to consecutive addresses, but to a group of addresses where the address difference increases by 8, such as X, X+8, X+16, X+24, etc., the rule above that associates the eight types of information in the lowest 3 bits with the access area will always result in accessing the same area.

[0005] In response to this, for example, Patent Document 2 discloses a technique for devising a rule for converting an access address (logical address) into a physical address. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 5-210579 [Patent Document 2] Patent No. 4771654 Summary of the Invention [Problem to be solved by the invention]

[0007] However, the conversion rule disclosed in Patent Document 2 is a fixed rule that cannot be applied to various access modes, and there is room for improvement.

[0008] Therefore, the present disclosure provides a memory access method that can accommodate various access modes. [Means for solving the problem]

[0009] A memory access method according to the present disclosure includes a data storage instruction step of issuing a data storage instruction including a first logical address, instructing that one piece of data be stored in a first memory or a second memory having a physical address different from that of the first memory, according to the first logical address; and a first storage path selection step of making a first selection of whether to execute a first storage step or a second storage step in response to the data storage instruction, based on the first logical address included in the data storage instruction, wherein the first storage step includes a step of storing the one piece of data in the first memory via a first path in response to the data storage instruction. the first storage step is a step of storing the one piece of data in the second memory via a second path in response to the data storage instruction, and the first storage path selection step makes the first selection based on a first interleaving rule or a second interleaving rule that assigns a physical address to the first logical address, makes the first selection based on the first interleaving rule for one or more of the data storage instructions, and makes the first selection based on the second interleaving rule for one or more subsequent data storage instructions.

[0010] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a recording medium such as a computer-readable CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium. [Effects of the Invention]

[0011] A memory access method according to one aspect of the present disclosure can accommodate various access modes. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a configuration diagram illustrating an example of a memory access control device according to an embodiment. [Figure 2] FIG. 2 is a flowchart illustrating an example of a memory access method according to the embodiment. [Figure 3] FIG. 3 is a flowchart showing a specific example of a memory access method according to an embodiment. [Figure 4] FIG. 4 is a flowchart showing an example of a process at the time of reading in the memory access method according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] A memory access method according to one aspect of the present disclosure includes: a data storage instruction step of issuing a data storage instruction including a first logical address, the data storage instruction instructing that one piece of data be stored in a first memory or a second memory having a physical address different from that of the first memory, according to the first logical address; and a first storage path selection step of making a first selection of whether to execute a first storage step or a second storage step in response to the data storage instruction, based on the first logical address included in the data storage instruction, wherein the first storage step is performed by transmitting data to the first memory via a first path in response to the data storage instruction. the first storage step is a step of storing the one piece of data in the second memory via a second path in response to the data storage instruction, and the first storage path selection step makes the first selection based on a first interleaving rule or a second interleaving rule that assigns a physical address to the first logical address, makes the first selection based on the first interleaving rule for one or more of the data storage instructions, and makes the first selection based on the second interleaving rule for one or more subsequent data storage instructions.

[0014] This allows the interleaving rule to be switched, making it possible to accommodate various access modes.

[0015] For example, in the first storage path selection step, the first interleaving rule may be switched to the second interleaving rule based on a history of the results of the first selection. Specifically, in the first storage path selection step, the first interleaving rule may be switched to the second interleaving rule when a difference between the number of times the first storage step was selected within a predetermined time and the number of times the second storage step was selected within the predetermined time in the history of the results of the first selection becomes greater than a first predetermined number.

[0016] According to this, if there is a bias in the first selection based on the history of the first selection of which memories with different physical addresses to store data in, the interleaving rule is switched, thereby making it possible to suppress the bias in the first selection. For example, if there is a large difference in the number of times each storage step is selected within a predetermined time, it can be determined that there is a bias in the first selection.

[0017] For example, in the first storage path selection step, the first interleaving rule may be switched to the second interleaving rule based on a history of the first logical addresses included in the data storage instructions. Specifically, in the first storage path selection step, the first interleaving rule may be switched to the second interleaving rule when a history of the first logical addresses forms a predetermined pattern, and the predetermined pattern may be set before starting an access operation to the first memory or the second memory.

[0018] According to this, by switching the interleaving rule when the history of a plurality of first logical addresses conforms to a predetermined pattern set in advance, it is possible to suppress bias in the first selection.

[0019] For example, in the first storage step, the process may be stopped based on a predetermined condition and switched to the process in the second storage step. Specifically, the predetermined condition may be that, after the first selection in the first storage path selection step, the number of unexecuted first storage steps is greater than the number of unexecuted second storage steps by a second predetermined number.

[0020] According to this, when processing of a certain storage step is being executed, the processing of the certain storage step can be stopped based on a predetermined condition, and processing of another storage step can be executed. Specifically, if the number of unexecuted storage steps for the certain storage step becomes large after the first selection (i.e., if there is a bias in the execution of storage steps), the processing of the certain storage step can be stopped and processing of another storage step can be executed. Therefore, bias in the execution of storage steps can be suppressed.

[0021] For example, the first storing step may include a second storing path selecting step for making a second selection of whether to continue processing in the first storing step or to switch to processing in the second storing step, and the second storing path selecting step may make the second selection based on a third interleaving rule or a fourth interleaving rule. Specifically, the third interleaving rule may be a rule that makes it more likely to select to continue processing in the first storing step than to select to switch to processing in the second storing step, and the fourth interleaving rule may be a rule that makes it less likely to select to continue processing in the first storing step than to select to switch to processing in the second storing step.

[0022] This allows the second selection of whether to continue processing a certain storage step or switch to processing another storage step to be made based on the interleaving rule. Specifically, the interleaving rule can increase or decrease the number of selections to continue processing a certain storage step, thereby suppressing uneven execution of storage steps.

[0023] For example, in the second storage path selection step, if the number of unexecuted first storage steps becomes greater than the number of unexecuted second storage steps by a second predetermined number after the first selection in the first storage path selection step, the interleaving rule may be switched from the third interleaving rule to the fourth interleaving rule.

[0024] According to this, after the first selection, if the difference in the number of unexecuted storage steps becomes large for each storage step, the interleaving rule is switched, thereby making it possible to suppress bias in the execution of storage steps.

[0025] For example, in the second storage path selection step, the third interleaving rule may be switched to the fourth interleaving rule based on whether the first memory is accessible or not and whether the second memory is accessible or not. Specifically, the first memory accessibility state and the second memory accessibility state may be based on whether a refresh period is in progress. Alternatively, the first memory accessibility state and the second memory accessibility state may be based on whether a retraining period is in progress.

[0026] According to this, when there is inaccessible memory, specifically when there is memory in the refresh period or when there is memory in the retraining period, the interleaving rule can be switched to suppress imbalances in the execution of storage steps.

[0027] For example, in the second storage path selection step, when the chip temperature of the first memory becomes higher than the chip temperature of the second memory by a predetermined amount, the interleaving rule may be switched from the third interleaving rule to the fourth interleaving rule.

[0028] According to this, by switching the interleaving rule when the difference in chip temperature between the memories becomes large, it is possible to suppress imbalance in the execution of the storage steps.

[0029] For example, the first storage path selection step may further include a first address translation recording step of recording combination information of the first logical address included in the data storage instruction and whether the first selection was based on the first interleaving rule or the second interleaving rule. Alternatively, for example, the first storage path selection step may further include a second address translation recording step of recording combination information of the first logical address included in the data storage instruction and an assigned physical address.

[0030] Such combined information can be stored for when the data is to be read.

[0031] For example, the method may further include a data read instruction step of issuing a data read instruction including a second logical address that instructs reading one piece of data from the first memory or the second memory in accordance with one second logical address, and a read path selection step of making a third selection of whether to execute a first read step or a second read step in response to the data read instruction based on the second logical address included in the data read instruction, wherein the first read step is a step of reading the one piece of data from the first memory via the first path in response to the data read instruction, and the second read step is a step of reading the one piece of data from the second memory via the second path in response to the data read instruction, and the read path selection step may make the third selection based on the combination information corresponding to the first logical address that is equal to the second logical address.

[0032] According to this, when reading out data, the stored data can be read out by using the combination information stored when the data was stored.

[0033] A memory access control device according to one aspect of the present disclosure includes a data storage instruction unit that issues a data storage instruction including a first logical address, the data storage instruction instructing a first memory or a second memory having a physical address different from that of the first memory to store one piece of data according to the first logical address; a first storage unit that stores the one piece of data in the first memory via a first path in response to the data storage instruction; a second storage unit that stores the one piece of data in the second memory via a second path in response to the data storage instruction; and a previous instruction included in the data storage instruction. and a first storage path selection unit that makes a first selection of whether to perform storage by the first storage unit or storage by the second storage unit based on the first logical address, wherein the first storage path selection unit makes the first selection based on a first interleaving rule or a second interleaving rule that assigns a physical address to the first logical address, makes the first selection based on the first interleaving rule for one or more of the data storage instructions, and makes the first selection based on the second interleaving rule for one or more subsequent data storage instructions.

[0034] This makes it possible to provide a memory access control device that can accommodate various access modes.

[0035] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0036] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0037] (Embodiment) A memory access method and a memory access control device according to an embodiment will be described below.

[0038] FIG. 1 is a configuration diagram showing an example of a memory access control device 1 according to an embodiment.

[0039] The memory access control device 1 is a device that performs memory interleaving, which divides a memory into multiple areas (banks) that can operate simultaneously and appropriately allocates access to the memory to those areas, thereby improving overall access efficiency. In the following, for simplicity of explanation, the multiple areas will be described focusing on two areas, storage devices 60a and 60b, but access may be allocated to three or more areas.

[0040] The memory access control device 1 includes a master 10, a storage device selection unit 20, storage device control units 30a and 30b, a command monitoring unit 40, and rule storage units 51 and 52. The memory access control device 1 may or may not include storage devices 60a and 60b. The memory access control device 1 is a computer including a processor and memory. The memory may be a read-only memory (ROM) or a random access memory (RAM), and can store programs executed by the processor. The master 10, the storage device selection unit 20, the storage device control units 30a and 30b, and the command monitoring unit 40 are realized by a processor that executes programs stored in the memory. The rule storage units 51 and 52 are realized by a memory, a group of registers, etc. The rule storage units 51 and 52 may be memories separate from the memories in which the programs are stored.

[0041] The storage device 60a is an area of ​​memory also called a bank and is an example of a first memory. The storage device 60b is a bank different from the storage device 60a and is an example of a second memory. The storage devices 60a and 60b have different physical addresses.

[0042] The master 10 is an example of a data storage instruction unit that executes a data storage instruction step of issuing a data storage instruction to instruct the storage device 60a or the storage device 60b to store one piece of data according to one first logical address. The data storage instruction includes the first logical address. The master 10 is also an example of a data read instruction unit that executes a data read instruction step of issuing a data read instruction to instruct the storage device 60a or the storage device 60b to read one piece of data according to one second logical address. The data read instruction includes the second logical address.

[0043] The storage device selector 20 is a component that converts logical addresses into physical addresses and determines an access path. Specifically, the storage device selector 20 is an example of a first storage path selector that performs a first storage path selection step in response to a data storage instruction, in which the storage device selector 20 selects (referred to as a first selection) whether to perform storage by the storage device control unit 30a (first storage step) or storage by the storage device control unit 30b (second storage step) based on a first logical address included in the data storage instruction. The storage device selector 20 performs the first selection based on a first interleaving rule or a second interleaving rule that assigns physical addresses to first logical addresses and is stored in the rule storage unit 51. The storage device selector 20 performs the first selection based on the first interleaving rule in response to one or more data storage instructions, and performs the first selection based on the second interleaving rule in response to one or more subsequent data storage instructions. In addition, the memory device selection unit 20 is an example of a read path selection unit that performs a read path selection step in response to a data read instruction, which makes a third selection of whether to perform reading by the memory device control unit 30a (first read step) or reading by the memory device control unit 30b (second read step) based on a second logical address included in the data read instruction.

[0044] The storage device control unit 30a is an example of a first storage unit that executes a first storage step of storing one piece of data in the storage device 60a via a first path in response to a data storage instruction. The first path is a path that connects the storage device selection unit 20 and the storage device 60a via the storage device control unit 30a. The storage device control unit 30a is also an example of a first reading unit that executes a first reading step of reading one piece of data from the storage device 60a via the first path in response to a data reading instruction.

[0045] Furthermore, the storage device control unit 30a includes a command distribution unit 31a and a command storage unit 32a, and by including the command distribution unit 31a, the storage device control unit 30a can halt processing in the first storage step and switch to processing in the second storage step based on a predetermined condition. The predetermined condition is that after the first selection in the first storage path selection step, the number of unexecuted first storage steps is greater than the number of unexecuted second storage steps by a second predetermined number.

[0046] The command distribution unit 31a is an example of a second storage path selection unit that executes a second storage path selection step of selecting whether to continue processing in the storage device control unit 30a or switch to processing in the storage device control unit 30b (referred to as a second selection). The command distribution unit 31a makes the second selection based on the third interleaving rule or the fourth interleaving rule stored in the rule storage unit 52.

[0047] An access command is temporarily stored in the command storage unit 32a. The command storage unit 32a stores an access command when the command distribution unit 31a selects that processing by the storage device control unit 30a should continue. The command storage unit 32a executes the access command when it is executable, thereby storing data in the storage device 60a. When execution of the access command is complete, the command storage unit 32a deletes the access command from the command storage unit 32a. For example, the command storage unit 32a executes the access command depending on whether access to the storage device 60a is permitted or not. The access permit / prohibited state is determined based on whether the storage device 60a is in a refresh period or whether the storage device control unit 30a is in a retraining period for the storage device 60a. During this retraining period, the storage device control unit 30a adjusts timing, but normal access to the target storage device 60a is not permitted. When the storage device 60a is in a refresh period or a retraining period, the access command stored in the command storage unit 32a is not executed, and access commands may accumulate in the command storage unit 32a.

[0048] The storage device control unit 30b is an example of a second storage unit that executes a second storage step of storing one piece of data in the storage device 60b via a second path in response to a data storage instruction. The second path is a path that connects the storage device selection unit 20 and the storage device 60b via the storage device control unit 30b. The storage device control unit 30b is also an example of a second reading unit that executes a second reading step of reading one piece of data from the storage device 60b via the second path in response to a data reading instruction.

[0049] Furthermore, the storage device control unit 30b includes a command distribution unit 31b and a command storage unit 32b, and by including the command distribution unit 31b, the storage device control unit 30b can halt processing in the second storage step and switch to processing in the first storage step based on a predetermined condition. The predetermined condition is that after the first selection in the second storage path selection step, the number of unexecuted second storage steps is greater than the number of unexecuted first storage steps by a second predetermined number.

[0050] The command distribution unit 31b is an example of a second storage path selection unit that executes a second storage path selection step of making a second selection of whether to continue processing in the storage device control unit 30b or switch to processing in the storage device control unit 30a. The command distribution unit 31b makes the second selection based on the third interleaving rule or the fourth interleaving rule stored in the rule storage unit 52.

[0051] An access command is temporarily stored in the command storage unit 32b. The command storage unit 32b stores an access command when the command distribution unit 31b selects that processing in the storage device control unit 30b should be continued. The command storage unit 32b executes the access command if it is executable, thereby storing data in the storage device 60b, and deletes the access command from the command storage unit 32b when execution of the access command is completed. For example, the command storage unit 32b executes the access command depending on whether access to the storage device 60b is possible or not. The access status is determined based on whether the storage device 60b is in a refresh period or a retraining period. When the storage device 60b is in a refresh period or a retraining period, the access command stored in the command storage unit 32b is not executed, and access commands may accumulate in the command storage unit 32b.

[0052] The command monitoring unit 40 monitors the result of the first selection made by the storage device selection unit 20. Specifically, the command monitoring unit 40 monitors the result of whether the storage device selection unit 20 selected to execute the first storage step or the second storage step by monitoring the storage device control units 30a and 30b. Then, the command monitoring unit 40 determines an optimal interleaving rule based on the history of the results of the first selection, and stores the determined interleaving rule in the rule storage unit 51. For example, if a different interleaving rule is stored in the rule storage unit 51, it is rewritten to the determined interleaving rule.

[0053] Furthermore, the command monitoring unit 40 monitors the multiple first logical addresses included in the multiple data storage instructions. Specifically, the command monitoring unit 40 monitors the multiple first logical addresses included in the data storage instructions issued sequentially by the master 10 by monitoring the storage device control units 30a and 30b. Then, the command monitoring unit 40 determines an optimal interleaving rule based on the history of the multiple logical addresses, and stores the determined interleaving rule in the rule storage unit 51.

[0054] For example, by rewriting the interleaving rule stored in the rule storage unit 51 from the first interleaving rule to the second interleaving rule, the storage device selection unit 20 can switch the interleaving rule used when making the first selection from the first interleaving rule to the second interleaving rule.

[0055] Furthermore, after the first selection, the command monitoring unit 40 monitors the number of unexecuted first storage steps and the number of unexecuted second storage steps. Specifically, the command monitoring unit 40 monitors the number of unexecuted access commands for each of the command storage units 32a and 32b by monitoring the storage device control units 30a and 30b. Then, the command monitoring unit 40 determines an optimal interleaving rule based on the magnitude relationship between the numbers of unexecuted access commands for each, and stores the determined interleaving rule in the rule holding unit 52.

[0056] Furthermore, the command monitoring unit 40 monitors whether access to the storage device 60a and whether access to the storage device 60b is possible. Specifically, the command monitoring unit 40 monitors whether access to the storage device 60a by the command storage unit 32a and whether access to the storage device 60b by the command storage unit 32b is possible by monitoring the storage device control units 30a and 30b. Then, the command monitoring unit 40 determines an optimal interleaving rule based on the respective accessibility states and stores the determined interleaving rule in the rule holding unit 52.

[0057] Furthermore, the command monitoring unit 40 monitors the chip temperatures of the storage devices 60a and 60b. Although not shown, specifically, the command monitoring unit 40 monitors the chip temperatures of the storage devices 60a and 60b by monitoring the storage devices 60a and 60b (or by monitoring the output of a sensor or the like that senses the chip temperatures of the storage devices 60a and 60b). Then, the command monitoring unit 40 determines an optimal interleaving rule based on the respective chip temperatures, and stores the determined interleaving rule in the rule holding unit 52.

[0058] For example, by rewriting the interleaving rule stored in the rule storage unit 51 from the third interleaving rule to the fourth interleaving rule, the command distribution units 31a and 31b can switch the interleaving rule used when making the second selection from the third interleaving rule to the fourth interleaving rule.

[0059] The rule storage unit 51 stores the interleaving rules determined by the command monitoring unit 40. Here, one interleaving rule among the various interleaving rules determined by the command monitoring unit 40 is referred to as a first interleaving rule, and an interleaving rule different from the first interleaving rule is referred to as a second interleaving rule. The first interleaving rule and the second interleaving rule are rules for assigning a physical address to a first logical address.

[0060] The rule storage unit 52 stores the interleaving rules determined by the command monitoring unit 40. Here, among the various interleaving rules determined by the command monitoring unit 40, one interleaving rule is referred to as a third interleaving rule, and an interleaving rule different from the third interleaving rule is referred to as a fourth interleaving rule.

[0061] For example, the third interleave rule for the command distributor 31a is a rule that selects to continue the processing in the first storage step more often than to switch to the processing in the second storage step. Specifically, the third interleave rule is a rule that performs the processing in the first storage step three times and the processing in the second storage step two times, or a rule that performs the processing in the first storage step five times and the processing in the second storage step once.

[0062] For example, the fourth interleaving rule for the command distributor 31a is a rule that selects continuing the processing in the first storage step less often than selecting switching to the processing in the second storage step. Specifically, the fourth interleaving rule is a rule that performs the processing in the first storage step twice and the processing in the second storage step three times, or a rule that performs the processing in the first storage step once and the processing in the second storage step five times.

[0063] The third interleaving rule for the command distribution unit 31b is a rule that makes it more likely to choose to continue processing in the second storage step than to choose to switch to processing in the first storage step, and the fourth interleaving rule for the command distribution unit 31b is a rule that makes it less likely to choose to continue processing in the second storage step than to choose to switch to processing in the first storage step.

[0064] Next, an outline of the operation of the memory access control device 1 will be explained with reference to FIG.

[0065] Fig. 2 is a flowchart showing an example of a memory access method according to an embodiment. Note that the memory access method is a method executed by the memory access control device 1, and therefore Fig. 2 is also a flowchart showing an example of the operation of the memory access control device 1 according to the embodiment.

[0066] First, the master 10 issues a data storage instruction to the storage device 60a or the storage device 60b to store one piece of data according to one first logical address (step S11: data storage instruction step).

[0067] Next, the storage device selection unit 20 makes a first selection of whether to execute the first storage step or the second storage step in response to the data storage instruction, based on the first logical address included in the data storage instruction (step S12: first storage path selection step). For example, the storage device selection unit 20 makes the first selection based on only one first logical address included in one data storage instruction as the logical address. Note that the storage device selection unit 20 may also make the first selection based on multiple first logical addresses included in multiple data storage instructions as the logical addresses. Here, the storage device selection unit 20 makes the first selection based on the first interleaving rule or the second interleaving rule. Here, it is assumed that the storage device selection unit 20 first makes the first selection based on the first interleaving rule.

[0068] Next, the storage device control unit 30a or 30b executes the selected storage step (step S13). If the selection is made to execute the first storage step, the storage device control unit 30a executes the first storage step. The first storage step is a step of storing one piece of data in the storage device 60a via the first path in response to a data storage instruction. If the selection is made to execute the second storage step, the storage device control unit 30b executes the second storage step. The second storage step is a step of storing one piece of data in the storage device 60b via the second path in response to a data storage instruction.

[0069] Next, the command monitor 40 determines whether or not the condition for switching the interleaving rule is met (step S14). The condition for switching the interleaving rule will be described later.

[0070] If it is determined that the conditions for switching the interleaving rule are not met (No in step S14), the interleaving rule is not switched, an instruction to store the next data is issued in step S11, and processing from step S12 onwards is performed using the same interleaving rule as the previous time (for example, the first interleaving rule).

[0071] If it is determined that the conditions for switching the interleaving rule are met (Yes in step S14), the storage device selection unit 20 switches the interleaving rule (step S15), the next data storage instruction is issued in step S11, and processing from step S12 onwards is performed using an interleaving rule different from the previous one (for example, the second interleaving rule).

[0072] In this way, the storage device selection unit 20 makes a first selection based on the first interleaving rule for one or more data storage instructions, and makes a first selection based on the second interleaving rule for one or more subsequent data storage instructions. Note that in step S13, a second selection is made as to whether to continue processing in the first storage step or switch to processing in the second storage step, which will be described in FIG. 3.

[0073] Next, the operation of the memory access control device 1 will be described in detail with reference to FIG.

[0074] Fig. 3 is a flowchart showing a specific example of a memory access method according to an embodiment. Fig. 3 is also a flowchart showing a specific example of the operation of the memory access control device 1 according to an embodiment. Steps S21 to S24 in part A shown in Fig. 3 are processed by the storage device selection unit 20, and steps S25 to S29 in part B are processed by the storage device control unit 30a or 30b (specifically, the command distribution unit 31a or 31b).

[0075] First, the storage device selection unit 20 receives the access command issued by the master 10 (step S21).

[0076] Next, the storage device selection unit 20 determines whether or not the interleaving rule held in the rule holding unit 51 has been changed by the command monitoring unit 40 (step S22). For example, it is assumed that the rule holding unit 51 holds a first interleaving rule.

[0077] For example, if the difference between the number of times the first storage step was selected within a predetermined time and the number of times the second storage step was selected within a predetermined time in the history of the results of the first selection becomes larger than a first predetermined number, the command monitoring unit 40 may change the interleaving rule stored in the rule storage unit 51 from the first interleaving rule to the second interleaving rule. In other words, if there is a bias in the selection of either the first storage step or the second storage step by the storage device selection unit 20 within a predetermined time, the interleaving rule may be changed from the first interleaving rule to the second interleaving rule.

[0078] Furthermore, for example, when the history of the multiple first logical addresses included in the multiple data storage instructions conforms to a predetermined pattern, the command monitoring unit 40 may change the interleaving rule stored in the rule storage unit 51 from the first interleaving rule to the second interleaving rule. The history of the multiple first logical addresses is a list of one first logical address included in each data storage instruction sequentially issued by the master 10, arranged in order of issuance, up to the first logical address included in the latest data storage instruction. The history of the multiple first logical addresses is, for example, a history of logical addresses such as "····000," "····001," "····010," and "····011" (only the lowest three bits of the addresses are shown here). The predetermined pattern is, for example, a pattern of specific bits of the multiple first logical addresses, such as a pattern of the least significant bits. A specific example of the predetermined pattern is a pattern in which the least significant bits of the multiple first logical addresses are 0, 0, 0, 0, . . .

[0079] For example, suppose the first interleaving rule is a rule that selects to execute the first storage step when the value of the least significant bit is 0, and selects to execute the second storage step when the value of the least significant bit is 1. Also, suppose the second interleaving rule is a rule that selects to execute the first storage step when the value of the bit immediately above the least significant bit is 0, and selects to execute the second storage step when the value of the bit immediately above the least significant bit is 1. When the first interleaving rule is stored in rule storage unit 51, if a data storage instruction is issued in which the first logical address changes continuously, such as "...000", "...001", "...010", and "...011", the least significant bit will be 0, 1, 0, 1, ..., and the first storage step and the second storage step can be selected equally. On the other hand, if a data storage instruction is issued in which the first logical address changes by 2, such as "····000," "····010," "····100," or "····110," the least significant bits will be 0, 0, 0, 0, ···, and only the first storage step will continue to be selected, resulting in a bias in selection.

[0080] Therefore, when the history of the multiple first logical addresses included in the multiple data storage instructions conforms to a predetermined pattern, that is, when the least significant bits of the multiple first logical addresses are 0, 0, 0, 0, . . ., the interleaving rule held in the rule holding unit 51 is changed from the first interleaving rule to the second interleaving rule. Since the bits one above the least significant bits of the multiple first logical addresses are 0, 1, 0, 1, . . ., the second interleaving rule makes it possible to select the first storage step and the second storage step equally.

[0081] For example, the predetermined pattern is set before the start of an access operation to the storage device 60a or 60b. For example, if the type of access mode is known to some extent in advance, a predetermined pattern and interleaving rule according to the type of access mode are set, and the interleaving rule is switched when an imbalance in access is detected.

[0082] If the storage device selection unit 20 determines that the command monitoring unit 40 has changed the interleaving rule stored in the rule storage unit 51 (Yes in step S22), it selects a storage device to access based on the new rule (e.g., the second interleaving rule) (step S23).

[0083] When the command monitoring unit 40 changes the interleaving rule, the storage device selecting unit 20 switches from the first interleaving rule to the second interleaving rule based on the history of the first selection results. Specifically, when the difference between the number of times the first storage step was selected within a predetermined time and the number of times the second storage step was selected within a predetermined time becomes greater than a first predetermined number, the storage device selecting unit 20 switches from the first interleaving rule to the second interleaving rule. Alternatively, when the command monitoring unit 40 changes the interleaving rule, the storage device selecting unit 20 switches from the first interleaving rule to the second interleaving rule based on the history of multiple first logical addresses included in multiple data storage instructions. Specifically, when the history of multiple first logical addresses conforms to a predetermined pattern, the storage device selecting unit 20 switches from the first interleaving rule to the second interleaving rule.

[0084] If the storage device selection unit 20 determines that the command monitoring unit 40 has not changed the interleaving rule stored in the rule storage unit 51 (No in step S22), it selects a storage device to access based on the previous rule (e.g., the first interleaving rule) (step S24).

[0085] Next, the command distribution unit 31a or 31b receives the access command from the storage device selection unit 20 (step S25). Here, for example, it is assumed that the storage device selection unit 20 selects the first storage step as the first selection, and the command distribution unit 31a receives the access command.

[0086] Next, the command distributing unit 31a determines whether or not the interleaving rule held in the rule holding unit 52 has been changed by the command monitoring unit 40 (step S26). For example, it is assumed that the rule holding unit 52 holds a third interleaving rule.

[0087] For example, the command monitoring unit 40 may change the interleaving rule held in the rule holding unit 52 from the third interleaving rule to the fourth interleaving rule when the number of unexecuted first storage steps becomes larger by a second predetermined number than the number of unexecuted second storage steps after the first selection by the storage device selecting unit 20. That is, when the number of unexecuted access commands stored in the command storage unit 32a becomes larger by a second predetermined number than the number of unexecuted access commands stored in the command storage unit 32b, the interleaving rule may be changed from the third interleaving rule to the fourth interleaving rule.

[0088] Furthermore, for example, the command monitor 40 may change the interleaving rule stored in the rule storage unit 52 from the third interleaving rule to the fourth interleaving rule based on the accessibility status of the storage device 60a and the accessibility status of the storage device 60b. For example, the command monitor 40 may change the interleaving rule from the third interleaving rule to the fourth interleaving rule when the accessibility status of the storage device 60a indicates that the storage device 60a is in a refresh period or a retraining period, and the accessibility status of the storage device 60b indicates that the storage device 60b is not in a refresh period or a retraining period. When the storage device 60a is in a refresh period or a retraining period, it may be impossible to execute the access commands stored in the command storage unit 32a to store data in the storage device 60a, and the number of unexecuted access commands stored in the command storage unit 32a may be greater than the number of unexecuted access commands stored in the command storage unit 32b. In such a case, the interleaving rule may be changed from the third interleaving rule to the fourth interleaving rule.

[0089] Furthermore, for example, when the chip temperature of the storage device 60a becomes higher than the chip temperature of the storage device 60b by a predetermined amount, the command monitor 40 may change the interleaving rule held in the rule holding unit 52 from the third interleaving rule to the fourth interleaving rule. When the chip temperature of the storage device 60a is high, the access commands stored in the command storage unit 32a may be executed frequently, and access commands may continue to be stored in the command storage unit 32a one after another. Therefore, the number of unexecuted access commands stored in the command storage unit 32a may become larger than the number of unexecuted access commands stored in the command storage unit 32b. In such a case, the interleaving rule may be changed from the third interleaving rule to the fourth interleaving rule.

[0090] When the command distribution unit 31a determines that the interleaving rule held in the rule holding unit 52 has been changed by the command monitoring unit 40 (Yes in step S26), the command distribution unit 31a selects a storage device to access based on the new rule (for example, the fourth interleaving rule) (step S27). For example, in this case, the command distribution unit 31a does not store the access command in the command storage unit 32a, but stores the access command in the command storage unit 32b (step S29).

[0091] When the command monitoring unit 40 changes the interleaving rule, the command distributing unit 31a switches from the third interleaving rule to the fourth interleaving rule if the number of unexecuted first storage steps becomes greater than the number of unexecuted second storage steps by a second predetermined number after the first selection by the storage device selecting unit 20. Alternatively, when the command monitoring unit 40 changes the interleaving rule, the command distributing unit 31a switches from the third interleaving rule to the fourth interleaving rule based on the accessibility status of the storage device 60a and the accessibility status of the storage device 60b. Alternatively, when the command monitoring unit 40 changes the interleaving rule, the command distributing unit 31a switches from the third interleaving rule to the fourth interleaving rule if the chip temperature of the storage device 60a becomes higher than the chip temperature of the storage device 60b by a predetermined amount.

[0092] If the command distribution unit 31a determines that the interleaving rule held in the rule holding unit 52 has not been changed by the command monitoring unit 40 (No in step S26), the command distribution unit 31a selects a storage device to access based on the previous rule (for example, the third interleaving rule) (step S28). For example, in this case, the command distribution unit 31a continues to store the access command in the command storage unit 32a (step S29).

[0093] Here, we will explain why, after the memory device selection unit 20 selects whether to store the data in memory device 60a or 60b, the command distribution units 31a and 31b again select whether to store the data in memory device 60a or 60b.

[0094] For example, if the storage device selector 20 operates to store data equally between the storage devices 60a and 60b, the command distributors 31a and 31b may be unnecessary. However, although only one master 10 is shown here, the storage device controllers 30a and 30b may receive access commands from multiple masters. In such cases, a bias in the execution of the storage step may occur between the storage device controllers 30a and 30b, resulting in a decrease in access efficiency. Furthermore, for example, the accessibility status of the storage devices 60a and 60b (during a refresh period or a retraining period) or some other reason may also cause a bias in the execution of the storage step, resulting in a decrease in access efficiency. For this reason, the command distributors 31a and 31b also select either the storage device 60a or 60b in which to store data. Here, the accessibility status can be determined, for example, from the status of the storage device controllers 30a and 30b. Furthermore, if there is an imbalance in access due to some reason, the temperature of the memory chip with a high access frequency will be relatively high as a result, and by knowing the chip temperature, the imbalance in access can be determined.

[0095] Next, the memory access method and operation of the memory access control device 1 when reading data will be explained with reference to Figure 4. In order to read data, when storing data, the storage device selection unit 20 executes a first address translation recording step of recording information combining a first logical address included in a data storage instruction and whether the first selection was based on the first interleaving rule or the second interleaving rule. Alternatively, when storing data, the storage device selection unit 20 executes a second address translation recording step of recording information combining a first logical address included in a data storage instruction and an assigned physical address. Furthermore, when storing data, the command distribution units 31a and 31b a first logical address included in the data storage instruction; and A third address translation recording step is executed to record combination information indicating whether the second selection is based on the third interleaving rule or the fourth interleaving rule. Note that the second address translation recording step to record combination information of the first logical address included in the data storage instruction and the assigned physical address may be executed by the command distribution units 31a and 31b.

[0096] 4 is a flowchart showing an example of processing during reading in the memory access method according to the embodiment. Note that FIG. 4 is also a flowchart showing an example of the operation during reading of the memory access control device 1 according to the embodiment.

[0097] First, the master 10 issues a data read instruction to instruct reading one piece of data from the storage device 60a or the storage device 60b in accordance with one second logical address (step S31: data read instruction step).

[0098] Next, the storage device selection unit 20 performs a third selection of whether to execute the first read step or the second read step based on the second logical address included in the data read instruction (step S32: read path selection step). Here, the storage device selection unit 20 performs the third selection based on the combination information corresponding to the first logical address that is equal to the second logical address. In other words, when reading data according to the second logical address that is equal to the first logical address when the data was stored, the information when the data was stored is referenced.

[0099] Then, the storage device control unit 30a or 30b executes the selected read step (step S33). If the selection is made to execute the first read step, the storage device control unit 30a executes the first read step. The first read step is a step of reading one piece of data from the storage device 60a via the first path in response to a data read instruction. If the selection is made to execute the second read step, the storage device control unit 30b executes the second read step. The second read step is a step of reading one piece of data from the storage device 60b via the second path in response to a data read instruction.

[0100] In this way, when reading out data, the stored data can be read out by using the combination information stored when the data was stored.

[0101] As described above, the memory access method and memory access control device 1 of the present disclosure can accommodate various access patterns because the interleaving rule can be switched. Furthermore, the first selection of whether to execute the first storage step or the second storage step is performed based on the switchable interleaving rule, thereby suppressing bias in the first selection. Furthermore, after the first selection, the second selection of whether to continue processing in the first storage step or switch to processing in the second storage step is performed, thereby suppressing bias in the execution of the storage steps. In this way, access efficiency can be improved.

[0102] (Other embodiments) While the memory access method and memory access control device 1 according to one or more aspects of the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. Various modifications conceivable by those skilled in the art to each embodiment, and configurations constructed by combining components of different embodiments, may also be included within the scope of one or more aspects of the present disclosure, provided they do not deviate from the spirit of the present disclosure.

[0103] For example, in the above embodiment, the processing in the first storage step is stopped and switched to the processing in the second storage step, but this switching need not be performed. In other words, the memory access control device 1 does not need to include the command distribution units 31a and 31b.

[0104] For example, the present disclosure can be realized as a program for causing a processor to execute steps included in a memory access method. Furthermore, the present disclosure can be realized as a non-transitory computer-readable recording medium, such as a CD-ROM, on which the program is recorded.

[0105] For example, when the present disclosure is realized as a program (software), each step is performed by running the program using hardware resources such as a computer's CPU, memory, input / output circuits, etc. In other words, each step is performed by the CPU acquiring data from memory or input / output circuits, etc., performing calculations on the data, and outputting the calculation results to memory or input / output circuits, etc.

[0106] In the above embodiment, each component included in the memory access control device 1 may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may also be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0107] Some or all of the functions of the memory access control device 1 according to the above-described embodiment are typically realized as an LSI, which is an integrated circuit. These may be implemented individually on a single chip, or some or all of them may be integrated on a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized using a dedicated circuit or a general-purpose processor. It is also possible to use an FPGA (Field Programmable Gate Array), which can be programmed after LSI manufacturing, or a reconfigurable processor, which allows the connections and settings of circuit cells within an LSI to be reconfigured.

[0108] Furthermore, various modifications made to the embodiments of the present disclosure within the scope that would occur to a person skilled in the art are also included in the present disclosure, as long as they do not deviate from the gist of the present disclosure. [Industrial Applicability]

[0109] The present disclosure is applicable to devices in which memory interleaving is performed. [Explanation of symbols]

[0110] 1. Memory access control device 10 Master 20 Storage device selection section 30a, 30b storage device control unit 31a, 31b Command distribution section 32a, 32b Command storage section 40 Command Monitoring Unit 51, 52 Rule Maintenance Section 60a, 60b storage device

Claims

1. A memory access method, comprising: a data storage instruction step of issuing a data storage instruction including a first logical address to instruct a first memory or a second memory having a physical address different from that of the first memory to store one piece of data in accordance with the first logical address; a first storage path selection step of making a first selection of whether to execute a first storage step or a second storage step in response to the data storage instruction based on the first logical address included in the data storage instruction, the first storing step is a step of storing the one piece of data in the first memory via a first path in response to the data storage instruction, the second storing step is a step of storing the piece of data in the second memory via a second path in response to the data storage instruction, In the first storage path selection step, performing the first selection based on a first interleaving rule or a second interleaving rule for allocating physical addresses to the first logical addresses; performing the first selection based on the first interleaving rule for one or more of the data storage instructions, and performing the first selection based on the second interleaving rule for one or more subsequent data storage instructions; A memory access method comprising:

2. In the first storage path selection step, switching from the first interleaving rule to the second interleaving rule is performed based on a history of results of the first selection; 2. The memory access method according to claim 1, wherein:

3. in the first storage path selection step, when a difference between the number of times the first storage step was selected within a predetermined time period and the number of times the second storage step was selected within the predetermined time period in a history of the results of the first selection becomes larger than a first predetermined number, switching from the first interleaving rule to the second interleaving rule; 3. The memory access method according to claim 2, wherein:

4. In the first storage path selection step, switching from the first interleaving rule to the second interleaving rule is performed based on a history of the first logical addresses included in the data storage instructions; 4. The memory access method according to claim 1, wherein:

5. In the first storage path selection step, when a history of the plurality of first logical addresses conforms to a predetermined pattern, the first interleaving rule is switched to the second interleaving rule; the predetermined pattern is set before the start of an access operation to the first memory or the second memory; 5. The memory access method according to claim 4, wherein:

6. In the first storing step, the processing in the first storing step is stopped based on a predetermined condition, and the processing is switched to the processing in the second storing step; 6. The memory access method according to claim 1, wherein:

7. the predetermined condition is that the number of the first storage steps that have not been executed after the first selection in the first storage path selection step is greater than the number of the second storage steps that have not been executed by a second predetermined number; 7. The memory access method according to claim 6, wherein:

8. the first storing step includes a second storing path selection step of making a second selection between continuing the processing in the first storing step and switching to the processing in the second storing step; in the second storage path selection step, the second selection is performed based on a third interleaving rule or a fourth interleaving rule; 8. The memory access method according to claim 1, wherein:

9. the third interleaving rule is a rule that selects to continue processing in the first storage step more often than to select to switch to processing in the second storage step; the fourth interleaving rule is a rule that makes it less likely that the user will select to continue processing in the first storage step than that that the user will select to switch to processing in the second storage step; 9. The memory access method according to claim 8, wherein:

10. in the second storage path selection step, when the number of the first storage steps that have not been executed becomes larger than the number of the second storage steps that have not been executed by a second predetermined number after the first selection in the first storage path selection step, switching from the third interleaving rule to the fourth interleaving rule; 10. The memory access method according to claim 8 or 9,

11. in the second storage path selection step, switching from the third interleaving rule to the fourth interleaving rule based on a state of accessibility to the first memory and a state of accessibility to the second memory; 11. The memory access method according to claim 8, wherein:

12. a state of whether or not access to the first memory and a state of whether or not access to the second memory is possible are determined based on whether or not a refresh period is in progress; 12. The memory access method according to claim 11,

13. a state of whether or not the first memory can be accessed and a state of whether or not the second memory can be accessed are determined based on whether or not a retraining period is in progress; 13. The memory access method according to claim 11 or 12,

14. in the second storage path selection step, when a chip temperature of the first memory becomes higher than a chip temperature of the second memory by a predetermined amount, switching from the third interleaving rule to the fourth interleaving rule; The memory access method according to any one of claims 8 to 13,

15. the first storage path selection step further includes a first address conversion recording step of recording combination information of the first logical address included in the data storage instruction and whether the first selection is based on the first interleaving rule or the second interleaving rule; 15. The memory access method according to claim 1, wherein:

16. the first storage path selection step further includes a second address translation recording step of recording information on a combination of the first logical address included in the data storage instruction and an assigned physical address; 15. The memory access method according to claim 1, wherein:

17. a data read instruction step of issuing a data read instruction including a second logical address, which instructs reading one piece of data from the first memory or the second memory in accordance with the second logical address; a read path selection step of performing a third selection of whether to execute the first read step or the second read step in response to the data read instruction based on the second logical address included in the data read instruction, the first read step is a step of reading the one piece of data from the first memory via the first path in response to the data read instruction, the second read step is a step of reading the one piece of data from the second memory via the second path in response to the data read instruction, the read path selecting step performs the third selection based on the combination information corresponding to the first logical address that is equal to the second logical address; 17. The memory access method according to claim 15 or 16,

18. A memory access control device, a data storage instruction unit that issues a data storage instruction including a first logical address, instructing a first memory or a second memory having a physical address different from that of the first memory to store one piece of data in accordance with the first logical address; a first storage unit that stores the one piece of data in the first memory via a first path in response to the data storage instruction; a second storage unit that stores the one piece of data in the second memory via a second path in response to the data storage instruction; a first storage path selection unit that, in response to the data storage instruction, makes a first selection of whether to store data by the first storage unit or by the second storage unit based on the first logical address included in the data storage instruction, The first storage path selection unit performing the first selection based on a first interleaving rule or a second interleaving rule for allocating physical addresses to the first logical addresses; performing the first selection based on the first interleaving rule for one or more of the data storage instructions, and performing the first selection based on the second interleaving rule for one or more subsequent data storage instructions; A memory access control device comprising:

Images