Transmission circuit

Abstract

According to the present invention, a primary-side transmitter 600 drives a primary-side input 512 of an insulation barrier 510 in response to the transition of an input signal Din. A secondary-side receiver 700 generates an output signal Dout having a logical value corresponding to a signal generated in a secondary-side output 514 of the insulation barrier 510. A secondary-side transmitter 800 drives a secondary-side input 516 of the insulation barrier 510, on the basis of an output signal Dout. A primary-side receiver 900 generates a return signal Dreturn having a logical value corresponding to a signal generated in a primary-side output 518 of the insulation barrier 510. The primary-side transmitter 600 repeats driving the primary-side input 512 of the insulation barrier 510 until the logical values of the input signal Din and the return signal Dreturn match.

Description

[Technical Field]

[0001] The present disclosure relates to signal transmission between two isolated domains. [Background technology]

[0002] In systems such as commercial power supplies, motors, measuring instruments, and other automotive, industrial, and medical equipment, high electrical insulation is required for digital signal transmission between semiconductor chips for the following purposes: (i) to protect humans and equipment from surge currents and high voltages, (ii) to prevent malfunctions by isolating noise, and (iii) to protect transistors in signal transmission between areas with large potential differences.

[0003] As signal transmission methods that ensure insulation, wireless methods, photocoupler methods, capacitor methods, transformer methods, GMR (Giant Magneto Resistive) methods, etc. have been proposed.

[0004] In digital signal transmission through an isolation barrier, even if there is no transition in the input logic signal, malfunctions can occur due to external noise such as large changes in the common voltage (reference voltage), resulting in inconsistencies in the logic signal levels between the primary side (transmitting TX side) and the secondary side (receiving RX side).

[0005] This problem is difficult to tolerate in systems that require high reliability, such as medical equipment, aerospace equipment, and automotive and industrial equipment.

[0006] For this reason, electrical measures are taken to improve the common mode transient immunity (CMTI) of the communication ICs between the isolation barriers, as well as system-wide measures.

[0007] The following systemic measures have been proposed:

[0008] (Conventional Example 1) In Conventional Example 1, even if there is no input logic transition for a certain period of time, the TX side compensates for transmission failures or logic inconsistencies between TX and RX when there is no signal by sending periodic refresh pulses using a timer. On the RX side, if there is no logic signal transition for a certain period of time, the watchdog timer sets the output to a predetermined safe level.

[0009] (Conventional example 2) Conventional example 2 uses OOK (On-Off Keying) or FSK (Frequency Shift Keying) to always determine the logic state of either L or H. Even if a signal changes due to a malfunction, it can be immediately corrected to the correct value.

[0010] The following electrical measures are generally adopted:

[0011] A transformer with magnetic field coupling is used to prevent noise transmission between the primary and secondary circuits due to the electric field.

[0012] Signals are transmitted between the primary and secondary circuits using differential signals. This is almost essential for the capacitor method (capacitive coupling) which has a low CMTI.

[0013] Increase the transmission power to improve the S / N ratio. This method has limitations due to the increased power.

[0014] Standard circuit designs can be used to eliminate noise using filters, employ circuits with hysteresis, etc. However, there are limitations when the S / N ratio of the frequency or voltage level is low. [Prior art documents] [Patent documents]

[0015] [Patent Document 1] U.S. Patent No. 8,873,644 [Patent Document 2] U.S. Patent No. 9,853,749 [Non-patent literature]

[0016] [Non-Patent Document 1] Wei Zhang, Mateo Begue, "Common Mode Transient Immunity (CMTI) for UCC2122x Isolated Gate Drivers", Texas Instruments, Application Report: SLUA909, August 2018 Summary of the Invention [Problem to be solved by the invention]

[0017] The present inventors have studied conventional countermeasures and have come to recognize the following problems.

[0018] (Conventional Example 1) When a logic mismatch occurs between the primary and secondary circuits, recovery is delayed due to the timer period. Furthermore, if the refresh period is long, it is necessary to tolerate a logic mismatch for a long period of time. On the other hand, shortening the refresh period increases power consumption. Furthermore, it is difficult to determine the optimal period, which varies depending on the situation.

[0019] Furthermore, even if transmission failures continue, the RX side will not be corrected to the correct signal level because the RX side watchdog timer is not intended for logic consistency, but rather as a fail-safe function in the event of a failure or other condition that makes transmission impossible.

[0020] Both TX and RX require peripheral circuits (such as oscillators) for timers that operate steadily, which consume power even when there is no signal and increase the area cost.

[0021] (Conventional example 2) Transmitting a carrier frequency consumes a lot of power, even when there is no signal. The demodulation circuit also requires a constant current for bias circuits, which increases the area cost. Furthermore, the carrier frequency inevitably increases EMI (Electromagnetic Interference), and countermeasure circuits (spread spectrum) inevitably increase power consumption and circuit area.

[0022] As described above, conventional approaches have many drawbacks, such as excessive complexity, the need for many components, and the large area required. Therefore, these circuits are difficult to implement, which creates a barrier to reducing cost and power consumption.

[0023] The present disclosure has been made in view of the above-mentioned problems, and an exemplary purpose of an embodiment thereof is to provide an isolated signal transmission circuit that can resolve logic mismatches with low power consumption. [Means for solving the problem]

[0024] One aspect of the present disclosure relates to a transmission circuit. The transmission circuit includes an isolation barrier, a primary-side transmitter that drives a primary-side input of the isolation barrier in response to a transition of an input signal, a secondary-side receiver that generates an output signal having a logic value corresponding to the signal generated at the secondary-side output of the isolation barrier, the secondary-side transmitter that drives the secondary-side input of the isolation barrier based on the output signal, and the primary-side receiver that generates a return signal having a logic value corresponding to the signal generated at the primary-side output of the isolation barrier. The primary-side transmitter repeatedly drives the primary-side input of the isolation barrier until the logic values ​​of the input signal and the return signal match.

[0025] Any combination of the above components or conversion of the present disclosure into methods, devices, etc. are also valid aspects of the present invention. [Effects of the Invention]

[0026] According to an aspect of the present disclosure, logic inconsistencies can be resolved with low power consumption. [Brief explanation of the drawings]

[0027] [Figure 1] FIG. 1 is a circuit diagram of a transmission circuit according to an embodiment. [Figure 2] FIG. 2 is a time chart of the transmission circuit of FIG. 1 under normal conditions. [Figure 3] FIG. 3 is a time chart showing the transmission circuit of FIG. 1 when an error occurs. [Figure 4] FIG. 4 is a block diagram of a transmission circuit according to the first embodiment. [Figure 5] FIG. 5 is a time chart illustrating signal transmission in the first embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of the primary-side transmitter. [Figure 7] FIG. 7 is a circuit diagram showing a specific example of the configuration of the primary-side transmitter. [Figure 8] FIG. 8 is a circuit diagram showing an example of the configuration of the secondary receiver. [Figure 9] FIG. 9 is a circuit diagram showing an example of the overall configuration of the transmission circuit. [Figure 10] 10(a) to 10(c) are time charts showing the operation of the transmission circuit of FIG. [Figure 11] 11A and 11B are circuit diagrams of a transmission circuit according to a second embodiment. [Figure 12] 12(a) and 12(b) are time charts illustrating the problem that occurs in the transmission circuit of FIG. [Figure 13] FIG. 13 is a circuit diagram illustrating a configuration of the primary side of a transmission circuit according to a third embodiment. [Figure 14] FIG. 14 is a circuit diagram illustrating a configuration of the secondary side of the transmission circuit according to the third embodiment. [Figure 15] FIG. 15 is a time chart illustrating the operation of the transmission circuit according to the third embodiment. [Figure 16] FIG. 16 is a circuit diagram of a secondary receiver according to the first modification. [Figure 17] FIG. 17 is a circuit diagram of a secondary receiver according to the second modification. [Figure 18] FIG. 18 is a circuit diagram of an isolated converter equipped with a transmission circuit. [Figure 19] FIG. 19 is a circuit diagram of a half-bridge converter including a transmission circuit. DETAILED DESCRIPTION OF THE INVENTION

[0028] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not an exhaustive overview of all possible embodiments, nor does it limit essential elements of the embodiments. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0029] A transmission circuit according to one embodiment includes an isolation barrier, a primary-side transmitter that drives a primary-side input of the isolation barrier in response to a transition of an input signal, a secondary-side receiver that generates an output signal having a logic value corresponding to a signal generated at a secondary-side output of the isolation barrier, a secondary-side transmitter that drives the secondary-side input of the isolation barrier based on the output signal, and a primary-side receiver that generates a return signal having a logic value corresponding to the signal generated at the primary-side output of the isolation barrier. The primary-side transmitter repeatedly drives the primary-side input of the isolation barrier until the logic values ​​of the input signal and the return signal match.

[0030] In this transmission circuit, by adding a return channel that sends information back from the secondary side to the primary side, the primary-side transmitter can know whether the information is being transmitted correctly. Then, by repeating signal transmission until the information is transmitted correctly, the signal can be transmitted reliably to the secondary side. Because signal retransmission is minimized, matching can be achieved with low power consumption. Note that the primary-side input and primary-side output of the isolation barrier may be independent ports or the same port. Similarly, the secondary-side input and secondary-side output of the isolation barrier may be independent ports or the same port.

[0031] In one embodiment, the primary-side transmitter may include a first comparison circuit that compares the logical values ​​of the input signal and the return signal, a first oscillation circuit whose oscillation and stopping are controlled according to the comparison result by the first comparison circuit, and a first output unit that drives the primary-side input of the isolation barrier according to the input signal and a first pulse signal generated by the first oscillation circuit. With this configuration, the primary-side input of the isolation barrier can be repeatedly driven while the input signal and the return signal do not match.

[0032] In one embodiment, the first oscillator circuit may include a ring oscillator.

[0033] In one embodiment, the primary-side transmitter may pulse the primary side of the isolation barrier with a first polarity when the input signal is high and pulse the primary side of the isolation barrier with a second polarity when the input signal is low.

[0034] In one embodiment, the isolation barrier may include a first transformer having a primary winding connected to a primary-side transmitter and a secondary winding connected to a secondary-side receiver. The primary-side transmitter may supply a pulse current of a first polarity to a primary winding of the first transformer when an input signal is high, and generate a pulse current of a second polarity when the input signal is low. The secondary-side receiver may include a latch circuit having a set terminal connected to one end of a secondary winding of the first transformer and a reset terminal connected to the other end of the secondary winding of the transformer, a first switch provided between the set terminal and a common voltage node where a common voltage is generated, the first switch being turned on when an output of the latch circuit is high, and a second switch provided between the common voltage node and the reset terminal being turned on when an output of the latch circuit is low.

[0035] With this configuration, by controlling the first and second switches according to the state of the latch circuit and controlling the state of the secondary winding of the first transformer, it is possible to achieve operation equivalent to that of a pulse set / reset type transmission circuit with a single transformer.This configuration enjoys the advantages of the pulse set / reset type, but because only one transformer is required, the circuit area can be reduced and it is free from the transmission speed limitations caused by skew variations between the two transformers, enabling even higher speed transmission.

[0036] In one embodiment, the secondary receiver may further include a switch control unit that controls the first switch and the second switch according to the state of the latch circuit. The switch control unit may turn off the second switch after the transition of the pulse current of the first polarity ends, and may turn off the first switch after the transition of the pulse current of the second polarity ends. This makes it possible to suppress a jump in the terminal voltage of the secondary winding and improve stability.

[0037] In one embodiment, the switch control unit may turn off the second switch a predetermined time after the first switch is turned on, and may turn off the first switch a predetermined time after the second switch is turned on. This inserts a period in which both the first switch and the second switch are on and fixes the voltages of the set terminal and the reset terminal, thereby making it possible to prohibit state transition of the latch circuit and further stabilize circuit operation.

[0038] In one embodiment, the primary-side transmitter may additionally drive the primary-side input of the isolation barrier once after the logical values ​​of the input signal and the return signal match. The secondary-side transmitter may repeatedly drive the secondary-side input of the isolation barrier while the current output signal and the previous output signal do not match. With this configuration, the secondary-side transmitter stops operating after the return signal is correctly transmitted, making it resistant to abnormalities in the return channel.

[0039] In one embodiment, the secondary-side transmitter may include a second comparison circuit that compares a previous logical value of the output signal with a current logical value of the output signal, a second oscillation circuit whose oscillation and stopping are controlled according to a comparison result by the second comparison circuit, and a second output section that drives the secondary-side input of the isolation barrier according to a second pulse signal generated by the second oscillation circuit while the second oscillation circuit is oscillating.

[0040] In one embodiment, the transmission circuit may further comprise a deglitching circuit for removing glitches from the output of the secondary receiver.

[0041] In one embodiment, the common voltage may be a ground voltage, and the first switch and the second switch may be NMOS transistors.

[0042] In one embodiment, the common voltage may be a power supply voltage, and the first switch and the second switch may be PMOS transistors.

[0043] In one embodiment, the latch circuit may include a first NOR gate and a second NOR gate cross-connected.

[0044] In one embodiment, the latch circuit may include a first NAND gate and a second NAND gate cross-connected.

[0045] In one embodiment, the common voltage is a ground voltage, and the first switch and the second switch may be NMOS transistors. The transmission circuit may further include a first inverter having an input node receiving an inverted output of the latch circuit and an output node connected to the gate of the first switch, and a second inverter having an input node receiving the output of the latch circuit and an output node connected to the gate of the second switch.

[0046] In one embodiment, the common voltage is a ground voltage, and the first switch and the second switch may be NMOS transistors. The transmission circuit may further include a first NAND gate having a first input node receiving an inverted output of the latch circuit and an output node connected to the gate of the first switch, a first delay circuit delaying the output of the first NAND gate, a second NAND gate having a first input node receiving the output of the latch circuit, a second input node receiving the output of the first delay circuit, and an output node connected to the gate of the second switch, and a second delay circuit delaying the output of the second NAND gate and supplying the delayed output to the second input node of the first NAND gate.

[0047] In one embodiment, the common voltage is a power supply voltage, and the first switch and the second switch may be PMOS transistors. The transmission circuit may further include a third inverter having an input node receiving an output of the latch circuit and an output node connected to the gate of the first switch, and a fourth inverter having an input node receiving an inverted output of the latch circuit and an output node connected to the gate of the second switch.

[0048] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are merely examples and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0049] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0050] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0051] 1 is a circuit diagram of a transmission circuit 500 according to an embodiment. The transmission circuit 500 includes an isolation barrier 510, a primary-side transmitter 600, a secondary-side receiver 700, a secondary-side transmitter 800, and a primary-side receiver 900. The transmission circuit 500 receives an input signal D in and input signal D in An output signal D having a logic value according to out occurs.

[0052] The isolation barrier 510 is composed of passive elements such as a transformer and a capacitor, and ensures electrical isolation between the primary side 502 and the secondary side 504. The isolation barrier 510 has a primary side input 512, a secondary side output 514, a secondary side input 516, and a primary side output 518. When the primary side input 512 is driven, the electrical state of the secondary side output 514 changes. Similarly, when the secondary side input 516 is driven, the electrical state of the primary side output 518 changes. Note that the primary side input 512 and the primary side output 518 may be the same port, and the secondary side output 514 and the secondary side input 516 may be the same port.

[0053] The primary side transmitter 600 receives an input signal D in 5. The primary side input 512 of the isolation barrier 510 is driven in response to the transition of the primary side transmitter 600. The secondary side output 514 of the isolation barrier 510 receives the electrical signal S RX2 The driving form of the primary side transmitter 600 (this is the driving signal S TX1 The input signal D in transitions from low to high and the input signal D in When the signal S goes from high to low, it transitions differently, resulting in the secondary output 514 having different distinguishable electrical signals S RX2 occurs.

[0054] The secondary-side receiver 700 receives the electrical signal S 1 generated at the secondary-side output 514 of the isolation barrier 510. RX2 That is, the output signal D has a logic value according to the electrical state of the secondary output 514. out When the signal is transmitted normally, the output signal D out and the input signal D in The logical values ​​of are the same.

[0055] The primary-side transmitter 600 and the secondary-side receiver 700 receive an input signal D in from the primary side 502 to the secondary side 504.

[0056] The secondary transmitter 800 outputs the output signal Dout When the voltage Vcc changes, it drives the secondary side input 516 of the isolation barrier 510. The primary side output 518 of the isolation barrier 510 outputs an electrical signal S responsive to the driving of the secondary side transmitter 800. RX1 The driving mode of the secondary side transmitter 800 (driving signal S TX2 The pattern, waveform, and polarity of the output signal D out transitions from low to high and the output signal D out transition from high to low, and as a result, the primary output 518 has different distinguishable electrical signals S RX1 occurs.

[0057] The primary-side receiver 900 receives the signal S 1 generated at the primary-side output 518 of the isolation barrier 510. RX1 That is, the return signal D has a logic value according to the electrical state of the primary side output 518. return Generate.

[0058] The secondary-side transmitter 800 and the primary-side receiver 900 generate an output signal D out form a return channel that sends the signal from the secondary side 504 back to the primary side 502.

[0059] The primary side transmitter 600 receives an input signal D in and return signal D return The primary input 512 of the isolation barrier 510 is repeatedly driven until the logic values ​​of

[0060] Furthermore, the electrical signal S TX1 ,S RX2 ,S TX2 ,S RX1 may be a voltage signal or a current signal.

[0061] The above is the basic configuration of the transmission circuit 500. Next, the operation will be explained.

[0062] 2 is a time chart of the transmission circuit 500 in FIG. 1 under normal conditions. At time t0, the input signal D inWhen transitions from low to high, the primary-side transmitter 600 enters a first state φ H The electrical signal S TX1 As a result, the secondary output 514 of the isolation barrier 510 is driven in the first state φ H The electrical signal S RX2 The secondary receiver 700 is in the first state φ H The electrical signal S RX2 When it detects out Output.

[0063] The secondary transmitter 800 outputs the output signal D out When transitions to high, the first state φ H The electrical signal S TX2 As a result, the primary output 518 of the isolation barrier 510 generates a first state φ H The electrical signal S RX1 The primary receiver 900 is in the first state φ H The electrical signal S RX1 When it detects a high return signal D return Output.

[0064] When the transmission circuit 500 operates normally, the input signal D in As soon as D transitions to high, the return signal D return transitions high and the input signal D in and return signal D return Therefore, the primary-side transmitter 600 is in the first state φ H The electrical signal S TX1 stops generating the next input signal D in Wait for the transition of

[0065] At time t1, the input signal D in When transitions from high to low, the primary-side transmitter 600 enters a second state φ L The electrical signal S TX1 As a result, the secondary output 514 of the isolation barrier 510 is in the second state φ L The electrical signal S RX2 The secondary receiver 700 is in the second state φ L The electrical signal SRX2 When it detects out Output.

[0066] The secondary transmitter 800 outputs the output signal D out When transitions to low, the second state φ L The electrical signal S TX2 As a result, the primary output 518 of the isolation barrier 510 is driven in the second state φ L The electrical signal S RX1 The primary receiver 900 is in the second state φ L The electrical signal S RX1 When it detects a low return signal D return Output.

[0067] When the transmission circuit 500 operates normally, the input signal D in As soon as the transition goes low, the return signal D return transitions to low, and the input signal D in and return signal D return Therefore, the primary-side transmitter 600 is in the second state φ L The electrical signal S TX1 stops generating the next input signal D in Wait for the transition of

[0068] 3 is a time chart showing the time when an error occurs in the transmission circuit 500 of FIG. 1. At time t0, the input signal D in When transitions from low to high, the primary-side transmitter 600 enters a first state φ H The electrical signal S TX1 Generate.

[0069] Due to some abnormality, the secondary side output 514 of the isolation barrier 510 is in the first state φ H The electrical signal S RX2 does not occur. The secondary receiver 700 is in the first state φ H The electrical signal S RX2 Therefore, the output signal D out remains low.

[0070] In this case, the output signal D out Since no change in state occurs, the secondary-side transmitter 800 does not drive the secondary-side input 516 of the isolation barrier 510. Therefore, no change in state occurs at the primary-side output 518 of the isolation barrier 510, and the return signal D return remains low.

[0071] Return signal D return and input signal D in Therefore, the primary-side transmitter 600 again enters the first state φ H The electrical signal S TX1 At this time, due to some abnormality, the secondary side output 514 of the insulating barrier 510 is in the first state φ H The electrical signal S RX2 In this case, as in the previous case, the secondary receiver 700 is in the first state φ H The electrical signal S RX2 Since the output signal D out remains low.

[0072] Output signal D out , the secondary-side transmitter 800 does not drive the secondary-side input 516 of the isolation barrier 510, and the return signal D return remains low.

[0073] Return signal D return and input signal D in Therefore, at time t2, the primary-side transmitter 600 is in the first state φ H The electrical signal S TX1 This electrical signal S TX1 is successfully transmitted to the secondary side, the secondary output 514 of the isolation barrier 510 is H The electrical signal S RX2 and the secondary-side receiver 700 outputs a high output signal D out Output.

[0074] The secondary transmitter 800 outputs the output signal Dout When transitions to high, the first state φ H The electrical signal S TX2 As a result, the primary output 518 of the isolation barrier 510 generates a first state φ H The electrical signal S RX1 The primary receiver 900 is in the first state φ H The electrical signal S RX1 When it detects a high return signal D return Output.

[0075] As a result, the return signal D return and input signal D in Then, the primary-side transmitter 600 is in the first state φ H The electrical signal S TX1 Stop generating.

[0076] The above is the operation of the transmission circuit 500. In this transmission circuit 500, by adding a return channel that sends information back from the secondary side 504 to the primary side 502, the primary side transmitter 600 can know whether the information is being transmitted correctly. Then, by repeating signal transmission until the information is transmitted correctly, the signal can be transmitted reliably to the secondary side 504.

[0077] This transmission circuit 500 has the advantage that it stops operating after the signal has been transmitted correctly, so there is only a small increase in power consumption and EMI can also be suppressed.

[0078] The present disclosure or the present invention encompasses various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or that are derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present invention, but to aid in understanding and clarify the essence and operation of the invention.

[0079] Example 1 4 is a block diagram of a transmission circuit 500A according to a first embodiment. An isolation barrier 510 includes a transformer T1 for a forward channel and a transformer T2 for a return channel. The transformers T1 and T2 each have a primary winding Wp and a secondary winding Ws. The primary winding Wp of the transformer T1 corresponds to a primary-side input 512, and the secondary winding Ws of the transformer T1 corresponds to a secondary-side output 514. The secondary winding Ws of the transformer T2 corresponds to a secondary-side input 516, and the primary winding Wp of the transformer T2 corresponds to a primary-side output 518.

[0080] The primary-side transmitter 600 transmits a drive signal I to the primary winding Wp of the transformer T1. TX1 The secondary winding Ws of the transformer T1 supplies the current signal I TX1 Voltage signal V according to RX2 The current signal I TX1 and the voltage signal V RX2 is the electrical signal S in Figure 1. TX1 , R RX2 Corresponds to.

[0081] The voltage V generated in the secondary winding Ws of the transformer T1 RX2 is expressed by equation (1). V RX2 =M dI TX1 / dt …(1) M is the mutual conductance, M=k√(L TX L RX ), where k is the coupling coefficient. L TX , L RX is the self-inductance of the primary winding Wp and the secondary winding Ws.

[0082] 5 is a time chart illustrating signal transmission in the first embodiment. In this embodiment, the primary side transmitter 600 receives an input signal D in The polarity (direction) of the current signal I changes in response to the level change of TX1 is supplied to the primary winding Wp. Specifically, the input signal D in When transitions from low to high, the current signal I TX1 is a pulse current Ip of the first polarity, which is the electrical signal S TX1 The first state φH On the other hand, the input signal D in When transitions from high to low, the current signal I TX1 becomes a pulse current In of the second polarity, which is the electrical signal S TX1 The second state φ L Corresponds to.

[0083] The secondary winding Ws of the transformer T1 is supplied with a driving current I TX1 A pulse-shaped voltage signal V having a polarity corresponding to the polarity of RX2 The secondary receiver 700 generates a voltage signal V RX2 The polarity of the output signal D out In this example, the logic value of the positive voltage signal V RX2 Depending on out transitions high and the negative voltage signal V RX2 Depending on out transitions low.

[0084] Returning to Figure 4, the primary side transmitter 600 receives an input signal D in is high, return signal D return During the mismatch period when the input signal D is low, the primary transmitter 600 repeatedly generates a positive polarity pulse current Ip. in is low, return signal D return During the mismatch where I is high, a negative polarity pulse current In is repeatedly generated.

[0085] The return channel, which includes the secondary transmitter 800, the primary receiver 900, and the transformer T2, can employ the same transmission method as the forward channel. Specifically, the secondary transmitter 800 transmits a driving current I to the secondary winding Ws of the transformer T2. TX2 Output signal D out When transitions to high, the current signal I TX2 is a pulse current Ip of the first polarity, which is the electrical signal S TX2 The first state φ H Conversely, the output signal D outWhen transitions to low, the current signal I TX2 is a pulse current of the second polarity, which is the electrical signal S TX2 The second state φ L Corresponds to.

[0086] The primary winding Wp of the transformer T2 carries the current signal I TX2 Voltage signal V according to RX1 The primary side receiver 900 generates a voltage signal V RX1 The polarity of the return For example, a positive voltage signal V RX1 Depending on return transitions high and the negative voltage signal V RX1 Depending on return transitions low.

[0087] 6 is a circuit diagram showing a configuration example of a primary-side transmitter 600A. The primary-side transmitter 600A includes a first comparison circuit 610, a first oscillation circuit 620, and a first output section 630. The first comparison circuit 610 receives an input signal D in and return signal D return The first oscillator circuit 620 compares the logical values ​​of the first and second pulse signals Ip and In. The comparison result from the first comparator circuit 610 is input to the enable terminal of the first oscillator circuit 620, and when the comparison result is a mismatch, the first oscillator circuit 620 enters an enabled state (oscillates) and generates a first pulse signal Sp1 of a predetermined frequency. When the comparison result is a match, the first oscillator circuit 620 enters a disabled state (stops). The frequency of the first pulse signal Sp1 determines the repetition period for signal transmission retries, and the pulse width of the first pulse signal Sp1 determines the pulse widths of the pulse currents Ip and In.

[0088] The first output section 630 receives the input signal D in and the first pulse signal Sp1, the primary side input 512 of the isolation barrier 510 is driven. Specifically, the input signal D in is high and the first pulse signal Sp1 is at the active level, the first polarity drive current I TX1 (Pulse signal Ip) Output Input signal D inis low and the first pulse signal Sp1 is at the active level, the second polarity drive current I TX2 (Pulse current In) is output.

[0089] 7 is a circuit diagram showing a specific example of the configuration of the primary-side transmitter 600A. The first output section 630 is an H-bridge circuit, and includes a pair of push-pull output stages (inverters) 632, 634. One output stage 632 receives an input signal D in is inverted and supplied to one end of the primary winding Wp. in is high, the output Vo1 of the output stage 632 is low (GND1), and the input signal D in is low, the output Vo1 of the output stage 632 is high (VDD1).

[0090] The output stage 634 receives the control pulse D from the first oscillator circuit 620. delay The control pulse D (pulse signal Sp1 in FIG. 6) is inverted and supplied to the other end of the primary winding Wp. delay is high, the output Vo2 of the output stage 634 is low (GND1), and the control pulse D delay is low, the output Vo2 of the output stage 634 is high (VDD1).

[0091] The first comparison circuit 610 includes, for example, an XOR (exclusive OR) gate 612, and compares the input signal D in and return signal D return The first oscillator circuit 620 generates a signal indicating whether the two signals match or mismatch, and supplies the signal to an enable terminal (negative logic) ENB of the first oscillator circuit 620.

[0092] The first oscillation circuit 620 can be understood as a type of ring oscillator, and in this specification is referred to as a pulse output type (or intermittent oscillation type) ring oscillator 621. The pulse output type ring oscillator 621 oscillates while a high signal is input to the enable terminal EN, and generates a control pulse D delay The pulse output type ring oscillator 621 generates a control pulse D delay The signal includes at least one delay element D1, D2 that defines the frequency (period) of the signal.

[0093] An AND gate 622 and XOR gates 623 and 624 are inserted in the pulse output type ring oscillator 621. The AND gate 622 shuts off the pulse output type ring oscillator 621 while the enable signal EN is low, stopping the oscillation. The combination of this AND gate 622 and the inverting delay element D3 also controls the control pulse D delay A duty cycle of 1 / 2 is defined.

[0094] The XOR gate 623 receives the input signal D in and the output logic value of the AND gate 622, the control pulse D delay The XOR gate 624 reverses the polarity of the control pulse D delay and return signal D return Depending on the logic value of delay Reverse the polarity of

[0095] 8 is a circuit diagram showing an example of the configuration of the secondary receiver 700. The secondary receiver 700 includes a latch circuit 710, a switch control section 720C, a first switch swp, and a second switch swn.

[0096] The latch circuit 710 has a set terminal (S) connected to one end of the secondary winding Ws of the transformer T1, and a reset terminal (R) connected to the other end of the secondary winding Ws of the transformer T1.

[0097] The latch circuit 710 may have any logic polarity or configuration as long as it has two inputs, set and reset. In this embodiment, the latch circuit 710 is a NOR-type SR latch, and includes two cross-connected NOR gates 712 and 714.

[0098] The first switch swp is connected to the common voltage V COM is provided between the common voltage node COM where out is high. The second switch swn is provided between the common voltage node COM and the reset terminal (R), and is turned on when the output of the latch circuit 710 is low. In this example,COM is the ground voltage GND2, and the first switch swp and the second switch swn are NMOS transistors. The common voltage VCOM may be the power supply voltage VDD2, in which case the first switch swp and the second switch swn may be PMOS transistors.

[0099] The switch control section 720C determines the state of the latch circuit 710, i.e., the output signal D out The first switch swp and the second switch swn are controlled according to the logical value of

[0100] The switch control section 720C outputs a current pulse I TX That is, the switch control unit 720C waits until the transition (trailing edge) of the first polarity pulse current I TX After the transition of TX After the transition is completed, the first switch swp is turned off.

[0101] Here, the switch control unit 720C may use a simple delay, but in this embodiment, a delay by a non-overlap circuit is adopted, and the switch control unit 720C turns off the second switch swn after a predetermined time has elapsed since the first switch swp was turned on, and turns off the first switch swp after a predetermined time has elapsed since the second switch swn was turned on. This creates an on period for both the first switch swp and the second switch swn, and the voltage V of the set terminal and the reset terminal RXS ,V RXR By fixing both to ground GND2, the signal is further stabilized.

[0102] The switch control section 720C includes a first NAND gate 726, a first delay circuit 728, a second NAND gate 730, and a second delay circuit 732.

[0103] The first NAND gate 726 has a first input node connected to the inverted output D of the latch circuit 710. outbThe first delay circuit 728 receives the output V of the first NAND gate 726 and has an output node connected to the gate of the first switch swp. RST1 The second NAND gate 730 receives the output D of the latch circuit 710 at its first input node. out The second delay circuit 732 receives the output V of the second NAND gate 730 at its second input node, and the output node is connected to the gate of the second switch swn. RST2 is delayed and provided to the second input node of the first NAND gate 726.

[0104] 9 is a circuit diagram showing an example of the overall configuration of the transmission circuit 500A. The configurations of the primary-side transmitter 600 and the secondary-side receiver 700 are the same as those in FIGS. 7 and 8. The primary-side receiver 900 can be configured in the same way as the secondary-side receiver 700.

[0105] The secondary-side transmitter 800 includes a pre-driver 840 and a second output section 830. The second output section 830 is an H-bridge circuit and includes a pair of push-pull output stages (inverters) 832, 834. One output stage 832 outputs an output signal D out is inverted and supplied to one end of the secondary winding Ws of the transformer T2. out is high, the output Vo1 of the output stage 832 is low (GND2), and the output signal D out is low, the output Vo1 of the output stage 832 is high (VDD2).

[0106] The output stage 834 receives a control pulse D from the pre-driver 840. odelay is inverted and supplied to the other end of the secondary winding Ws of the transformer T2. odelay is high, the output Vo2 of the output stage 834 is low (GND12), and the control pulse D odelay is low, the output Vo2 of the output stage 834 is high (VDD2).

[0107] The pre-driver 840 outputs the output signal D out Delay the control pulse D odelay The delay circuit 842 generates

[0108] The above is an example of the configuration of the transmission circuit 500A. Next, the operation of the transmission circuit 500A will be described.

[0109] 10(a) to 10(c) are time charts showing the operation of the transmission circuit 500A of FIG. 9. FIG. 10(a) shows the operation when the input signal D in When transitions high, the return signal D return Since the first oscillator circuit 620 does not match the first polarity, the first oscillator circuit 620 is enabled, and as a result, a pulse current Ip of the first polarity is generated.

[0110] When the pulse current Ip is correctly transmitted to the secondary side 504, the output signal D out goes high and the return signal D return The input signal D in and return signal D return As a result, the first oscillation circuit 620 stops, and the pulse current Ip also stops.

[0111] Input signal D in When goes low, the return signal D return When the pulse current In is correctly transmitted to the secondary side 504, the output signal D out goes low and the return signal D return The input signal D in and return signal D return As a result, the first oscillation circuit 620 stops, and the pulse current In also stops.

[0112] FIG. 10(b) shows the operation when the transmission of the pulse current Ip1 from the primary-side transmitter 600 to the secondary-side receiver 700 fails.

[0113] Input signal D in When transitions high, the return signal D returnSince the first oscillator circuit 620 does not match the first polarity, the first oscillator circuit 620 is enabled, and as a result, a pulse current Ip1 of the first polarity is generated.

[0114] If the transmission of the pulse current Ip1 fails, the output signal D out remains low, so the input signal D in and output signal D out Return signal D indicating return As a result, the first oscillator circuit 620 continues to oscillate, causing the primary-side transmitter 600 to generate a second pulse current Ip2. If the transmission of the pulse current Ip2 is successful, the output signal D out transitions high and the input signal D in and output signal D out Return signal D indicating return As a result, the first oscillation circuit 620 is disabled and stops operating, and the pulse current Ip is no longer generated.

[0115] FIG. 10(c) shows the operation when the input of the secondary receiver 700 changes due to the influence of noise or the like, even though the input signal Din remains unchanged.

[0116] One end V of the secondary winding Ws of the transformer T1 RXR2 When noise Nx occurs in the output signal D out transitions to low and the return signal D return As a result, the input signal D in and return signal D return When the input signal D in is high, a pulse current Ipx of the first polarity is generated. When this pulse current Ipx is transmitted to the secondary side 504, an output signal D out transitions high and the return signal D return As a result, the input signal D in and return signal D return match, and the first oscillator circuit 620 is disabled.

[0117] The above is the operation of the transmission circuit 500 A. According to this transmission circuit 500, when mismatch occurs between the primary side 502 and the secondary side 504, it is possible to achieve matching with a small number of additional transmission pulses Ip, In.

[0118] Furthermore, because it can be configured only with logic circuits that do not flow steady-state current, the current consumption is zero when there are no signal transitions. As a result, it can operate with only the current consumption proportional to the data transmission speed, significantly reducing power consumption.

[0119] Example 2 11(a) and 11(b) are circuit diagrams of a transmission circuit 500B according to a second embodiment. In the transmission circuit 500B, the secondary-side receiver 700 further includes a glitch removal circuit 740. As shown in FIG. 11(b), the glitch removal circuit 740 includes a hysteresis flip-flop 742 and a delay circuit 744.

[0120] The delay circuit 744 delays the input signal (i.e., the output of the secondary-side receiver 700). The hysteresis flip-flop 742 receives the input signal at a first input node and the output of the delay circuit 744 at a second input node. The hysteresis flip-flop 742 is also called a Muller C-element, and holds the previous output value when the logic of the two inputs IN1 and IN2 does not match, outputs low when both inputs IN1 and IN2 are low, and outputs high when both inputs IN1 and IN2 are high.

[0121] According to the second embodiment, in the situation shown in FIG. 10(c), the output signal D out Glitches occurring in the signal line 740 and having a pulse width shorter than the delay of the delay circuit 744 can be removed.

[0122] Example 3 In the first embodiment, if an abnormality occurs in the return channel, power may be wasted or the mismatch may not be resolved.

[0123] 12(a) and 12(b) are time charts illustrating a problem that occurs in the transmission circuit 500A of FIG. 9. FIG. 12(a) shows the return signal D return In this case, the output signal D out and input signal D in Although the logic values ​​of the return signal D return and input signal D in Since the values ​​of Ip and Ip do not match, the primary-side transmitter 600 repeatedly generates a pulse current Ip, which wastes power.

[0124] Figure 12(b) shows the return signal D due to noise Ny. return 10 shows a case where the voltage Ip of the primary side transmitter 600 transitions to an erroneous level. In this case, the primary side transmitter 600 repeatedly generates a pulse current Ip of the first polarity, which wastes power.

[0125] In addition, the mismatch in Fig. 12(a) and (b) is caused by the input signal D in The error will not be resolved until the transition occurs.

[0126] A configuration that can solve this problem will be described in a third embodiment. Fig. 13 is a circuit diagram showing the configuration of a primary side 502C of a transmission circuit 500C according to the third embodiment.

[0127] In the third embodiment, the primary-side transmitter 600C receives an input signal D in and return signal D return After the logic values ​​of the input signal D match, the primary input 512 of the isolation barrier is driven once more. in When is high, it generates an additional pulse current Ip and input signal D in When is low, it generates an additional pulse of current In.

[0128] The primary-side transmitter 600C includes a first oscillation circuit 620C and an oscillator controller 640. The first oscillation circuit 620C is a pulse output type ring oscillator 621 with an enable, and further includes a level-sensitive latch (D latch) 626 in addition to the first oscillation circuit 620 of FIG. 7. The level-sensitive latch 626 outputs a return signal D to an input node D. return The enable signal ENB is input to the gate (inverted logic), and while the enable signal ENB is low, the return signal D return Let pass.

[0129] In addition to the first comparison circuit 610, the oscillator controller 640 includes a D flip-flop 642 and an OR gate 644. The first comparison circuit 610 receives the input signal D in and return signal D return Determine whether the values ​​match or mismatch.

[0130] The D flip-flop 642 holds the output of the previous first comparison circuit 610. The OR gate 644 outputs the logical sum of the output of the first comparison circuit 610 and the output of the D flip-flop 642. The enable signal (negative logic) ENB, which is the output of the OR gate 644, is generated for two consecutive cycles after the input signal D in and return signal D return When they match, it is asserted (low).

[0131] According to this configuration, the input signal D in and return signal D return After the logic values ​​of the inputs match, the primary input 512 of the isolation barrier is driven once more to generate the input signal D in and return signal D return Control pulse D is output until the logical values ​​of idelay can continue to generate.

[0132] FIG. 14 is a circuit diagram illustrating a configuration of a secondary side 504C of a transmission circuit 500C according to the third embodiment.

[0133] The glitch removal circuit 740C includes an OR gate 746 and a D flip-flop 748 in addition to a hysteresis flip-flop 742 and a delay circuit 744. When a voltage signal is generated in the secondary winding Ws of the transformer T1, the output of the OR gate 746 becomes high, and the value of the output of the delay circuit 744 is captured in the D flip-flop 748. The D flip-flop 748 receives the previous output signal D out is maintained.

[0134] The secondary transmitter 800C of the transmission circuit 500C outputs a current output signal D out0 and the previous output signal D out1 While there is a mismatch, the secondary side of the isolation barrier, i.e., the secondary winding Ws of the transformer T2, is repeatedly driven.

[0135] The secondary-side transmitter 800C can be configured similarly to the primary-side transmitter 600 of Fig. 7, and includes a second comparison circuit 810, a second oscillation circuit 820, and a second output section 830. The second comparison circuit 810 compares the previous output signal D out1 and the current output signal D out0 The second oscillation circuit 820 is a pulse output type ring oscillator with an enable function.

[0136] The above is the configuration of the transmission circuit 500C according to the embodiment 3. Fig. 15 is a time chart showing the operation of the transmission circuit 500C according to the embodiment 3.

[0137] According to the third embodiment, the secondary transmitter 800 receives a return signal D return After the signal is transmitted correctly, the operation stops, and the system can be made resistant to abnormalities in the return channel.

[0138] The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each treatment process, and that such modifications are also within the scope of the present invention or this disclosure. Such modifications will be described below.

[0139] The configuration of the secondary receiver 700 is not limited to that shown in Fig. 8. The following modifications are also applicable to the primary receiver 900.

[0140] (Variation 1) 16 is a circuit diagram of a secondary-side receiver 700 according to Modification 1. The switch control unit 720 can be configured with two inverters 722 and 724. The input node of the first inverter 722 is connected to the inverted output QB of the latch circuit 710, and the output node is connected to the gate of the first switch swp. The input node of the second inverter 724 is connected to the output Q of the latch circuit 710, and the output node is connected to the gate of the second switch swn.

[0141] (Variation 2) 17 is a circuit diagram of a secondary receiver 700 according to Modification 2. In the above description, the common voltage V COM In this second modification, the common voltage V COM is set to the power supply voltage VDD2. The first switch swp and the second switch swn are configured with PMOS transistors.

[0142] In the second modification, the latch circuit 710 includes a first NAND gate 716 and a second NAND gate 718 that are cross-connected. The latch circuit 710 is a negative logic circuit, and the voltage V RX1 When the transition from high to low occurs, the voltage V at the reset terminal RB RX2 A high-to-low transition resets it.

[0143] The switch control section 720 includes a third inverter 734 and a fourth inverter 736. The third inverter 734 receives the output D of the latch circuit 710 at its input node. out The fourth inverter 736 receives the inverted output D of the latch circuit 710 at its input node and connects it to the gate of the first switch swp. outb , and the output node is connected to the gate of the second switch swn.

[0144] The switch control unit 720 may be the switch control unit 720C in FIG.

[0145] (Variation 3) The configurations of the secondary receiver 700 and the primary receiver 900 are not limited to those described above, and may be configured using known techniques.

[0146] (Variation 4) The configurations of the first and second oscillation circuits are not limited to those described above, and the order of the components may be reversed, or the positive / negative logic polarity may be reversed.

[0147] (Variation 5) In the first to third embodiments, the insulating barrier 510 includes two transformers, but this is not limiting and the insulating barrier 510 may include a capacitor. In this case, the configurations of the primary-side transmitter 600, secondary-side receiver 700, secondary-side transmitter 800, and primary-side receiver 900 may be changed based on a known technique known as a capacitor system. Alternatively, the insulating barrier 510 may include one transformer, and signals may be transmitted and received in both directions using this one transformer.

[0148] (Application) Finally, the use of the transmission circuit 500 will be described.

[0149] 18 is a circuit diagram of an isolated converter 1000 including a transmission circuit 500. A controller 1100 is arranged on the secondary side and controls an output voltage V OUT The transmission circuit 500 generates a pulse signal Sp so that the input signal D approaches the target value. in and transmits it to the primary side of the isolated converter 1000. The gate driver 1200 receives the output signal D out The primary side switching transistor M1 is driven by a gate signal corresponding to the

[0150] 19 is a circuit diagram of a half-bridge converter 2000 including a transmission circuit 500. The half-bridge converter 2000 includes a high-side transistor MH and a low-side transistor ML. A gate driver 2002 drives the low-side transistor ML in response to a PWM signal.

[0151] The high-side transistor MH is an N-channel transistor. A drive circuit 2004 for the high-side transistor MH controls the voltage V of the switching node, which is the connection node between the high-side transistor MH and the switching transistor ML. SW The power supply voltage (VDD2) of the drive circuit 2004 is generated by a bootstrap circuit.

[0152] The transmission circuit 500 transmits the PWM signal from a domain based on the ground voltage GND1 to a domain based on the ground voltage GND2 (=Vsw).

[0153] The present invention has been described using specific terms based on the embodiments, but the embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present invention defined in the claims. [Industrial Applicability]

[0154] The present disclosure can be used in electronic circuits. [Explanation of symbols]

[0155] 500 Transmission Circuit 510 Insulation Barrier 512 Primary side input 514 Secondary output 516 Secondary side input 518 Primary side output T1 transformer T2 transformer 600 Primary Transmitter 610 1st comparison circuit 612 XOR gate 620 First Oscillator Circuit 621 Pulse Output Ring Oscillator 622 AND Gate 623,624 XOR gates 630 First Output Unit 632,634 Output stage 700 Secondary Receiver swp 1st switch swn Second switch 710 Latch Circuit 720 Switch control section 740 Glitch Elimination Circuit 742 Hysteresis Flip-Flop 744 Delay Circuit 800 Secondary Transmitter 810 Second comparison circuit 820 Second oscillator circuit 830 Second output section 840 Pre-driver 900 Primary Receiver Wp Primary winding Ws Secondary winding COM Common voltage node

Claims

1. an insulating barrier; a primary-side transmitter that drives a primary-side input of the isolation barrier in response to a transition of an input signal; a secondary-side receiver that generates an output signal having a logic value corresponding to a signal generated at a secondary-side output of the isolation barrier; a secondary-side transmitter that drives a secondary-side input of the isolation barrier based on the output signal; a primary-side receiver that generates a return signal having a logic value corresponding to a signal generated at a primary-side output of the isolation barrier; Equipped with The primary side transmitter comprises: a first comparison circuit that compares the logical values ​​of the input signal and the return signal; a first oscillation circuit whose oscillation and stopping are controlled according to a comparison result by the first comparison circuit; a first output section that drives a primary side input of the isolation barrier in response to the input signal and a first pulse signal generated by the first oscillation circuit; and repeatedly driving the primary-side input of the isolation barrier until the logic values ​​of the input signal and the return signal match.

2. 2. The transmission circuit according to claim 1, wherein the first oscillation circuit includes a ring oscillator.

3. 3. The transmission circuit of claim 1, wherein the primary-side transmitter pulses the primary side of the isolation barrier with a first polarity when the input signal is high, and pulses the primary side of the isolation barrier with a second polarity when the input signal is low.

4. the isolation barrier includes a first transformer having a primary winding connected to the primary-side transmitter and a secondary winding connected to the secondary-side receiver; 4. The transmission circuit according to claim 1, wherein the primary-side transmitter supplies a pulse current of a first polarity to the primary winding of the first transformer when the input signal is high, and generates a pulse current of a second polarity when the input signal is low.

5. The secondary receiver includes: a latch circuit having a set terminal connected to one end of the secondary winding of the first transformer and a reset terminal connected to the other end of the secondary winding of the first transformer; a first switch that is provided between a common voltage node at which a common voltage is generated and the set terminal and that is turned on when the output of the latch circuit is high; a second switch that is provided between the common voltage node and the reset terminal and that is turned on when the output of the latch circuit is low; The transmission circuit according to claim 4 , comprising:

6. an insulating barrier; a primary-side transmitter that drives a primary-side input of the isolation barrier in response to a transition of an input signal; a secondary-side receiver that generates an output signal having a logic value corresponding to a signal generated at a secondary-side output of the isolation barrier; a secondary-side transmitter that drives a secondary-side input of the isolation barrier based on the output signal; a primary-side receiver that generates a return signal having a logic value corresponding to a signal generated at a primary-side output of the isolation barrier; Equipped with the primary-side transmitter repeatedly drives the primary-side input of the isolation barrier until the logic values ​​of the input signal and the return signal match; the isolation barrier includes a first transformer having a primary winding connected to the primary-side transmitter and a secondary winding connected to the secondary-side receiver; the primary-side transmitter supplies a pulsed current of a first polarity to the primary winding of the first transformer when the input signal is high, and generates a pulsed current of a second polarity when the input signal is low; The secondary receiver includes: a latch circuit having a set terminal connected to one end of the secondary winding of the first transformer and a reset terminal connected to the other end of the secondary winding of the first transformer; a first switch that is provided between a common voltage node at which a common voltage is generated and the set terminal and that is turned on when the output of the latch circuit is high; a second switch that is provided between the common voltage node and the reset terminal and that is turned on when the output of the latch circuit is low; a transmission circuit including:

7. the secondary-side receiver further includes a switch control unit that controls the first switch and the second switch in accordance with a state of the latch circuit; 7. The transmission circuit according to claim 5, wherein the switch control unit turns off the second switch after a transition of the pulse current of the first polarity has ended, and turns off the first switch after a transition of the pulse current of the second polarity has ended.

8. 8. The transmission circuit according to claim 7, wherein the switch control unit turns off the second switch after a predetermined time has elapsed since the first switch was turned on, and turns off the first switch after a predetermined time has elapsed since the second switch was turned on.

9. the primary-side transmitter additionally drives the primary-side input of the isolation barrier once after the logical values ​​of the input signal and the return signal match; 9. The transmission circuit according to claim 1, wherein the secondary-side transmitter repeatedly drives the secondary-side input of the isolation barrier while a current output signal and a previous output signal do not match.

10. an insulating barrier; a primary-side transmitter that drives a primary-side input of the isolation barrier in response to a transition of an input signal; a secondary-side receiver that generates an output signal having a logic value corresponding to a signal generated at a secondary-side output of the isolation barrier; a secondary-side transmitter that drives a secondary-side input of the isolation barrier based on the output signal; a primary-side receiver that generates a return signal having a logic value corresponding to a signal generated at a primary-side output of the isolation barrier; Equipped with the primary-side transmitter repeatedly drives the primary-side input of the isolation barrier until the logic values ​​of the input signal and the return signal match; the primary-side transmitter additionally drives the primary-side input of the isolation barrier once after the logical values ​​of the input signal and the return signal match; A transmission circuit, wherein the secondary-side transmitter repeatedly drives the secondary-side input of the isolation barrier while the current output signal and the previous output signal are inconsistent.

11. The secondary-side transmitter comprises: a second comparison circuit for comparing a previous logic value of the output signal with a current logic value of the output signal; a second oscillation circuit whose oscillation and stopping are controlled according to a comparison result by the second comparison circuit; a second output section that drives a secondary-side input of the insulation barrier in response to a second pulse signal generated by the second oscillation circuit while the second oscillation circuit is oscillating; 11. The transmission circuit according to claim 9 or 10, comprising:

12. 12. The transmission circuit according to claim 1, further comprising a deglitching circuit for deglitching glitches from the output of the secondary receiver.

Images