Semiconductor Devices

Abstract

To provide a semiconductor device which can be embedded into an organism.SOLUTION: A semiconductor device which can be embedded into an organism is provided, and includes: a communication portion; a control portion; a storage portion; a calculation portion; and a sensor portion. The control portion has a function for controlling: the communication portion; the calculation portion; and the storage portion. The storage portion has a function for holding identification information. Also, the calculation portion has a function for generating third information by using first information and second information which is supplied from the sensor portion. The control portion includes a function causing the calculation portion to perform a calculation processing in accordance with a signal input through the communication portion. The control portion includes a function for outputting one or both of the identification information and the third information to an external portion via the communication portion in accordance with the signal input via the communication portion. The calculation portion includes a transistor containing an oxide semiconductor in a channel formation region. The semiconductor device is preferably coated with a coating material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, and electronic devices may include semiconductor elements and semiconductor circuits. Therefore, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] In recent years, there has been progress in the development of authentication devices that use biometric information such as human biometric characteristics, such as fingerprints, palm prints, vein patterns, voiceprints, iris patterns, retinal patterns, face shapes, and body shapes. For example, vein authentication devices that use vein patterns have been put to practical use in bank ATMs. Furthermore, Patent Document 1 discloses electronic devices, such as smartphones, that are capable of fingerprint authentication. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-79415 Summary of the Invention [Problem to be solved by the invention]

[0006] Because biometric information is difficult to forge, authentication devices that use biometric information can achieve highly accurate identification. However, if biometric information changes due to injury, illness, aging, or other factors, it can become difficult to identify individuals.

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that can be implanted in a living body. Another object is to provide a semiconductor device that enables highly accurate individual identification. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device implantable in a living body, the semiconductor device including a communication unit, a control unit, a memory unit, a calculation unit, and a sensor unit. The memory unit has a function of retaining identification information. The calculation unit has a function of retaining first information and a function of generating third information using the first information and second information supplied from the sensor unit. The control unit has a function of outputting one or both of the identification information and the third information to the outside via the communication unit in response to a signal input via the communication unit. The calculation unit is a semiconductor device including a transistor including an oxide semiconductor in a channel formation region.

[0010] The oxide semiconductor preferably contains at least one of indium and zinc.

[0011] The calculation unit may have a function of performing a product-sum calculation. For example, the first information is weight information. Furthermore, the semiconductor device according to an aspect of the present invention is preferably covered with a covering material. [Effects of the Invention]

[0012] According to one embodiment of the present invention, a semiconductor device that can be implanted in a living body, that enables highly accurate individual identification, that has high reliability, that consumes less power, or that is a novel semiconductor device can be provided.

[0013] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0014] [Figure 1] Fig. 1A is a perspective view of a semiconductor device 100. Fig. 1B and Fig. 1C are diagrams illustrating an example of how the semiconductor device 100 is used. [Figure 2] 2A, 2B, 2C, 2D, and 2E are diagrams illustrating examples of use of the semiconductor device 100. FIG. [Figure 3] FIG. 3 is a block diagram illustrating the configuration of the communication unit. [Figure 4] FIG. 4 is a block diagram illustrating an example of the configuration of a semiconductor device. [Figure 5] 5A and 5B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6] 6A and 6B are diagrams illustrating configuration examples of a memory circuit. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of an arithmetic circuit. [Figure 8] FIG. 8 is a diagram illustrating an example of the operation of the semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a CPU. [Figure 10] 10A and 10B are diagrams illustrating an example of the configuration of a CPU. [Figure 11] FIG. 11 is a diagram illustrating an example of the configuration of a CPU. [Figure 12] FIG. 12 is a diagram illustrating an example of the structure of a semiconductor device. [Figure 13] 13A and 13B are diagrams illustrating examples of the structure of a transistor. DETAILED DESCRIPTION OF THE INVENTION

[0015] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0016] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0017] (Embodiment 1) A semiconductor device 100 according to one embodiment of the present invention will be described. Fig. 1A is a perspective external view of the semiconductor device 100 that can be implanted into a living body. The semiconductor device 100 has a communication unit 110, a calculation unit 120, a control unit 130, a memory unit 140, and a sensor unit 150. The semiconductor device 100 is covered with a covering material 190.

[0018] The communication unit 110 has a function of receiving signals sent from an external device (not shown) via wireless communication and transmitting signals to the external device. The communication unit 110 also has a function of receiving power supplied from the external device in a contactless manner.

[0019] The semiconductor device 100 may be provided with a battery. The battery has a function of storing power required for the operation of the semiconductor device 100 and a function of supplying the power required for the operation. The battery may be a primary battery or a secondary battery. The secondary battery may be, for example, a lithium-ion secondary battery.

[0020] The calculation unit 120 has a calculation circuit 121 and a memory circuit 122. The calculation circuit 121 has a function of performing calculation processing using information stored in the memory circuit 122. The calculation circuit 121 also has a function of performing calculation processing using information stored in the memory circuit 122 and information acquired by the sensor unit 150. The calculation circuit 121 also has a function of performing calculation processing using information stored in the memory unit 140. The calculation results are stored in the memory unit 140.

[0021] The storage unit 140 has a function of holding identification information of the semiconductor device 100. The storage unit 140 also has a function of saving programs and parameters related to the operation of the semiconductor device 100. The storage unit 140 may be a random access memory (RAM) such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a nonvolatile memory such as a read only memory (ROM). At least a part of the storage unit 140 is preferably a rewritable memory.

[0022] The control unit 130 has a function of controlling the operations of the communication unit 110, the calculation unit 120, the storage unit 140, and the sensor unit 150. The control unit 130 has a function of converting analog signals supplied from the sensor unit 150 and the like into digital signals. The control unit 130 has a function of transmitting identification information and / or calculation results to an external device in response to a signal supplied from the external device via the communication unit 110.

[0023] A sensor capable of detecting various types of information can be used as the sensor unit 150. For example, the sensor unit 150 may have a function of detecting at least one of temperature, vibration, pressure, gradient, acceleration, oxygen concentration, chemical substance, etc. The sensor unit 150 may also have a function of converting an analog signal into a digital signal.

[0024] The semiconductor device 100 is preferably covered with a covering material 190. By using the covering material 190, it is possible to reduce the occurrence of inflammatory reactions, allergic reactions, and the like after implantation in a living body. Furthermore, by covering the semiconductor device 100 with the covering material 190, it is possible to prevent damage to the living body, such as blood vessels and nerve tissues, adjacent to the implanted site. Materials that can be used for the covering material 190 include polymeric materials such as biocompatible glass, silicone resin, and fluororesin.

[0025] 1B and 1C are schematic diagrams showing a state in which the semiconductor device 100 is implanted in a living organism 10. Fig. 1B shows a state in which the semiconductor device 100 is implanted subcutaneously between the thumb and index finger of the living organism 10. Fig. 1C shows a state in which the semiconductor device 100 is implanted subcutaneously around the neck of the living organism 10.

[0026] The semiconductor device 100 embedded in the living body 10 can acquire biological information such as the body temperature and heart rate of the living body 10. Furthermore, by providing the semiconductor device 100 with identification information unique to the living body 10, the semiconductor device 100 can function as a personal identification tag (for example, a personal number card (My Number card)), a driver's license, a health insurance card, a passport, a cash card, a credit card, etc.

[0027] 2A, by placing the semiconductor device 100 implanted in the living body 10 over an external device 900, information on the living body 10 can be read out. The external device 900 has a function of transmitting a signal to the semiconductor device 100 and a function of receiving a signal transmitted from the semiconductor device 100. The external device 900 functions as a reader / writer.

[0028] Furthermore, the semiconductor device 100 can be embedded in various living organisms. For example, as shown in Figures 2B to 2E, the semiconductor device 100 can be embedded in living organisms 21, 22, 23, 24, etc. By using the semiconductor device 100, it is possible to prevent theft, grasp the behavior, and manage the health status of the living organisms 21 to 24.

[0029] <<Communication unit 110>> 3 is a block diagram illustrating the configuration of the communication unit 110. The communication unit 110 has an RF circuit 111 and an information processing circuit 117. The RF circuit 111 also has a resonance circuit 112, a power supply circuit 113, a clock generation circuit 114, a demodulation circuit 115, and a modulation circuit 116.

[0030] The resonant circuit 112 is connected to a power supply circuit 113, a clock generating circuit 114, a demodulation circuit 115, and a modulation circuit 116. The resonant circuit 112 has a function of converting electromagnetic waves emitted from an external device into an AC signal. The signal contains information such as operation commands. The power supply circuit 113 has a function of generating power used to operate the semiconductor device 100 from the signal. The clock generating circuit 114 has a function of generating a synchronization signal required for operation of the semiconductor device 100 from the signal. The demodulation circuit 115 has a function of extracting information such as operation commands from the signal.

[0031] The information processing circuit 117 has a function of extracting a command from the information extracted from the demodulation circuit 115 and transmitting the command to the control unit 130. The information processing circuit 117 also has a function of supplying a signal supplied from the control unit 130 to the modulation circuit 116. The modulation circuit 116 has a function of mixing the signal supplied from the control unit 130 with a carrier wave. The resonant circuit 112 also has a function of transmitting the signal mixed by the modulation circuit 116 to the outside.

[0032] <<Arithmetic unit 120>> A semiconductor device 300 that can be used in the arithmetic unit 120 will be described. An arithmetic circuit 360, which will be described later, corresponds to the arithmetic circuit 121 of the arithmetic unit 120. A storage circuit 350, which will be described later, corresponds to the storage circuit 122 of the arithmetic unit 120.

[0033] The semiconductor device 300 described in this embodiment is a semiconductor device that has excellent computational efficiency and can operate with extremely low power consumption. In other words, it is a semiconductor device that can function as a computer that has the potential to mimic the functions of the human brain (also called a Brain Morphic Computer: BMC).

[0034] <Block diagram> 4 shows a block diagram illustrating the configuration of semiconductor device 300. Semiconductor device 300 has a CPU 310, a bus 320, and an accelerator 330. CPU 310 has a CPU core 311 and a backup circuit 312. Accelerator 330 has a plurality of operation blocks 331 as well as a control unit 332 for controlling input and output of data between operation blocks 331.

[0035] The CPU 310 has the function of performing general-purpose processing such as running an operating system, controlling data, and executing various calculations and programs. The CPU 310 has a CPU core 311. The CPU core 311 corresponds to one or more CPU cores.

[0036] The CPU 310 also has a backup circuit 312 that can retain data in the CPU core 311 even if the supply of power supply voltage is stopped. The supply of power supply voltage can be controlled by electrically disconnecting it from the power domain using a power switch or the like. The power supply voltage is sometimes called a drive voltage.

[0037] For example, an OS memory having an OS transistor is suitable for the backup circuit 312. Note that the OS memory refers to a memory having a transistor (OS transistor) having an oxide semiconductor in a channel formation region, such as NOSRAM. Note that "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM."

[0038] Metal oxides suitable for OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for OS transistors because they can provide transistors with excellent electrical properties, such as field-effect mobility, by adjusting the ratio of elements. Furthermore, the oxide containing indium and zinc may contain one or more elements selected from the group consisting of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0039] To improve the reliability and electrical characteristics of OS transistors, the metal oxide used in the semiconductor layer is preferably a metal oxide having a crystalline portion, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for cloud-aligned composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0040] OS transistors have an extremely small leakage current, the current that flows between the source and drain when they are off. NOSRAM can be used as nonvolatile memory by utilizing its extremely small leakage current characteristics to retain a charge corresponding to the data within the memory circuit. NOSRAM is particularly suitable for parallel processing of product-sum operations in neural networks, which require repeated data read operations, because it can read the stored data without destroying it (non-destructive readout).

[0041] Because the band gap of metal oxides that function as oxide semiconductors is 2.5 eV or more, OS transistors have extremely small off-state currents. For example, when the source-drain voltage is 3.5 V and the temperature is room temperature (25°C), the off-state current per 1 μm of channel width is 1×10 -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 Therefore, in the OS memory, the amount of charge leaking from the retention node via the OS transistor is extremely small. Therefore, the OS memory can function as a nonvolatile memory circuit, which enables power gating of the CPU 310.

[0042] The backup circuit 312, which is made up of OS transistors, can be stacked with the CPU core 311, which can be made up of transistors having silicon in their channel formation regions (Si transistors). Because the area of ​​the backup circuit 312 is smaller than the area of ​​the CPU core 311, the backup circuit 312 can be placed on the CPU core 311 without increasing the circuit area. The backup circuit 312 has a function of retaining data in the registers of the CPU core 311. The backup circuit 312 is also referred to as a data retention circuit. Note that the semiconductor layer including the channel formation region of the Si transistor may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0043] The control unit 332 has an internal memory circuit such as an SRAM. The control unit 332 stores output data obtained from the multiple operation blocks 331 in the memory circuit. The control unit 332 is configured to output the output data stored in the memory circuit to multiple semiconductor devices. This configuration enables parallel calculation using multiple semiconductor devices with an increased parallelism.

[0044] The bus 320 electrically connects the CPU 310 and the accelerator 330. That is, the CPU 310 and the accelerator 330 can transmit data via the bus 320.

[0045] <Operation block> The accelerator 330 described above executes a program (also called a kernel or kernel program) called from a host program. The accelerator 330 can perform, for example, parallel processing of matrix operations in graphics processing, parallel processing of product-sum operations in neural networks, and parallel processing of floating-point operations in scientific and technological calculations. Here, a configuration example of an operation block 331 in the accelerator 330 that performs parallel processing of multiple pieces of data (parallel processing) will be described.

[0046] As shown in Fig. 5A, the operation block 331 has a plurality of operation units 340. The operation unit 340 has a memory circuit 350 and an operation circuit 360. As shown in Figs. 5A and 5B, the memory circuit 350 and the operation circuit 360 are provided on different layers in a direction approximately perpendicular to the XY plane in the figure (Z direction in Fig. 5A). In other words, the memory circuit 350 and the operation circuit 360 are provided in a stacked manner.

[0047] Note that "substantially perpendicular" refers to a state in which the substrate is arranged at an angle of 85 degrees or more and 95 degrees or less. In this specification, the X direction, Y direction, and Z direction shown in Figure 5B and other figures are perpendicular to or intersect with each other. The X direction and Y direction are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0048] The memory circuit 350 has a plurality of memory cells. Writing and reading of data to the memory cells is controlled by a driver circuit 341 and a driver circuit 342. The driver circuits 341 and 342 are also referred to as data control circuits.

[0049] The information (data) stored in the memory cells of the storage circuit 350 is data (weight data) corresponding to weight parameters used in product-sum calculations of the neural network. By using digital data as the weight data, the semiconductor device can be made noise-resistant and capable of high-speed calculations. The weight data may also be analog data.

[0050] The memory circuit 350 is connected to the arithmetic circuit 360 via wiring. The memory cells of the memory circuit 350 include OS transistors. The wiring connecting the memory circuit 350 and the arithmetic circuit 360 is used to transmit weight data from the memory circuit 350 to the arithmetic circuit 360. To quickly read the weight data from the memory circuit 350 to the wiring or to reduce energy consumption associated with charging and discharging, it is preferable to shorten the wiring. That is, the wiring can be configured to extend in the z direction, as shown by arrow 351 in FIG. 5B. By shortening the physical distance between the arithmetic circuit 360 and the memory circuit 350, for example, by stacking the wiring, the parasitic capacitance generated in the signal line can be reduced, thereby enabling lower power consumption.

[0051] The arithmetic circuit 360 has a function of executing arithmetic processing such as a product-sum operation. The input and output of data to the arithmetic circuit 360 is controlled by control circuits 343 and 344. The control circuits 343 and 344 are also called data input / output circuits.

[0052] The arithmetic circuit 360 performs a product-sum operation on the input data input from the control circuit 343 and the weight data provided from the memory circuit 350. The input data may be biological information detected by the sensor unit 150. The obtained product-sum operation data is output to the control circuit 344. The input data and weight data may be analog data or digital data. It is preferable that the input data and weight data are digital data. Digital data is less susceptible to noise. Therefore, digital data is suitable for performing arithmetic processing that requires highly accurate calculation results.

[0053] By configuring the arithmetic circuit 360 using Si transistors, it can be stacked with OS transistors. That is, the memory circuit 350 configured using OS transistors can be stacked with the arithmetic circuit 360, which can be configured using Si transistors. This increases the area in which the memory circuit 350 can be arranged without increasing the circuit area. By providing the memory circuit 350 on the substrate on which the arithmetic circuit 360 is provided, it is possible to increase the memory capacity required for arithmetic processing in the accelerator 330 compared to when the memory circuit 350 and the arithmetic circuit 360 are arranged on the same layer. The increased memory capacity reduces the number of times data used for arithmetic processing is transferred from an external storage device to the semiconductor device, thereby reducing power consumption.

[0054] <Memory circuit> A configuration example of a NOSRAM, which is a memory cell included in the storage circuit 350, will be described. 6A illustrates write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and wirings LBL_1 to LBL_N, which are arranged in a matrix of M rows and N columns (M and N are natural numbers of 2 or more). Also illustrated are memory cells 352 connected to each word line and bit line.

[0055] 6B is a diagram illustrating an example of a circuit configuration applicable to the memory cell 352. The memory cell 352 includes a transistor 353, a transistor 354, a transistor 355, and a capacitor 356 (also referred to as a capacitor).

[0056] One of the source or drain of the transistor 353 is connected to the write bit line WBL. The gate of the transistor 353 is connected to the write word line WWL. The other of the source or drain of the transistor 353 is connected to one electrode of the capacitor 356 and the gate of the transistor 354. One of the source or drain of the transistor 354 and the other electrode of the capacitor 356 are connected to a wiring that applies a fixed potential, such as a ground potential. The other of the source or drain of the transistor 354 is connected to one of the source or drain of the transistor 355. The gate of the transistor 355 is connected to the read word line RWL. The other of the source or drain of the transistor 355 is connected to a wiring LBL. The wiring LBL is connected to the arithmetic circuit 360 (not shown) via a wiring that extends in a direction substantially perpendicular to the surface of the substrate on which the Si transistors of the arithmetic circuit 360 are provided.

[0057] As an example, the circuit configuration of memory cell 352 shown in FIG. 6B corresponds to a three-transistor (3T) gain cell NOSRAM. Transistors 353 to 355 are OS transistors. OS transistors have an extremely small leakage current, i.e., a current that flows between the source and drain when they are off. NOSRAM can be used as a nonvolatile memory by utilizing its extremely small leakage current characteristic to retain charge corresponding to data within the memory circuit.

[0058] <Arithmetic circuit> FIG. 7 shows a specific example of the configuration of the arithmetic circuit 360. FIG. 7 illustrates an example of the configuration of the arithmetic circuit 360 that can perform a product-sum operation on weight data W and input data A. FIG. 7 illustrates a multiplication circuit 361, an addition circuit 362, and a register 363. The data multiplied by the multiplication circuit 361 is input to the addition circuit 362. The output of the addition circuit 362 is held in the register 363, and is added to the data multiplied by the multiplication circuit 361 in the addition circuit 362 to perform the product-sum operation. The register 363 is controlled by a clock signal CLK and a reset signal reset_B. With this configuration, data MAC corresponding to the product-sum operation on the weight data W and input data A can be obtained.

[0059] <Example of operation> Next, an example of the operation of the semiconductor device when part of the calculations of the program executed by the CPU 310 is executed by the accelerator 330 will be described.

[0060] FIG. 8 is a diagram illustrating an example of an operation when part of the calculations of a program executed by a CPU is executed by an accelerator.

[0061] The host program is executed by the CPU (host program execution; step S1).

[0062] When the CPU confirms an instruction to reserve an area for data required for calculations using the accelerator in a memory circuit (memory) (memory reserve instruction; step S2), it reserves the area for data in the memory circuit (memory) (memory reserve; step S3).

[0063] Next, the CPU transmits weight data, which is input data, from the main memory or an external storage device to the memory circuit (memory) (data transmission; step S4). The memory circuit (memory) receives the weight data and stores it in the area reserved in step S2 (data reception; step S5).

[0064] When the CPU confirms an instruction to start the kernel program (start kernel program; step S6), the accelerator starts executing the kernel program (start operation; step S7).

[0065] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from a state performing calculations to a PG (power gating) state (PG state transition; step S8). In this case, immediately before the accelerator finishes executing the kernel program, the CPU is switched from the PG state to a state performing calculations (PG state stop step S9). By keeping the CPU in the PG state during the period from step S8 to step S9, it is possible to suppress power consumption and heat generation in the entire calculation processing system.

[0066] When the accelerator finishes executing the kernel program, the output data is stored in a storage unit that holds the calculation results in the accelerator (computation end; step S10).

[0067] After the execution of the kernel program is completed, if the CPU confirms an instruction to transmit the output data stored in the memory unit to the main memory or an external storage device (data transmission request; step S11), the output data is transmitted to the main memory or the external storage device and stored in the main memory or the external storage device (data transmission; step S12).

[0068] By repeating the above steps S1 to S12, the accelerator can execute part of the computations executed by the CPU while suppressing the power consumption and heat generation of the CPU and the accelerator. The semiconductor device according to one embodiment of the present invention may have a non-von Neumann architecture. The non-von Neumann architecture can perform computations with significantly less power consumption than the von Neumann architecture, which consumes more power as the processing speed increases.

[0069] <CPUコア> Next, an example of a CPU 310 having a CPU core 311 capable of power gating will be described.

[0070] 9 shows an example of the configuration of the CPU 310. The CPU 310 has a CPU core 311, an L1 (level 1) cache memory device (L1 Cache) 371, an L2 cache memory device (L2 Cache) 372, a bus interface unit (Bus I / F) 373, power switches 315 to 317, and a level shifter (LS) 318. The CPU core 311 has a flip-flop 314.

[0071] The CPU core 311, the L1 cache memory device 371, and the L2 cache memory device 372 are interconnected by a bus interface unit 373.

[0072] The PMU 313 generates a clock signal GCLK1 and various PG (power gating) control signals in response to externally input interrupt signals (Interrupts) and signals such as a SLEEP1 signal issued by the CPU 310. The clock signal GCLK1 and the PG control signals are input to the CPU 310. The PG control signals control power switches 315 to 317 and a flip-flop 314.

[0073] Power switches 315 and 316 control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line), respectively. A power switch 317 controls the supply of a voltage VDDH to a level shifter (LS) 318. A voltage VSSS is input to the CPU 310 and PMU 313 without passing through a power switch. A voltage VDDD is input to the PMU 313 without passing through a power switch.

[0074] The voltages VDDD and VDD1 are drive voltages for the CMOS circuit. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is the drive voltage for the OS transistors and is higher than the voltage VDDD.

[0075] Each of the L1 cache memory device 371, the L2 cache memory device 372, and the bus interface unit 373 has at least one power domain that can be power-gated. The power domain that can be power-gated has one or more power switches. These power switches are controlled by a PG control signal.

[0076] The flip-flop 314 is used as a register. A backup circuit is provided for the flip-flop 314. The flip-flop 314 will be described below.

[0077] 10A shows an example of the circuit configuration of the flip-flop 314. The flip-flop 314 has a scan flip-flop 319 and a backup circuit 312.

[0078] The scan flip-flop 319 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 319A.

[0079] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 319A. The analog switch of scan flip-flop 319 is connected to nodes CK1 and CKB1 of clock buffer circuit 319A. Node RT is an input node for a reset signal.

[0080] The signal SCE is a scan enable signal and is generated by the PMU 313. The PMU 313 generates signals BK and RC. The level shifter 318 level-shifts the signals BK and RC to generate signals BKH and RCH. The signal BK is a backup signal, and the signal RC is a recovery signal.

[0081] The circuit configuration of the scan flip-flop 319 is not limited to that shown in Fig. 10A, and any flip-flop available in a standard circuit library can be applied.

[0082] The backup circuit 312 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitive element C11.

[0083] The node SD_IN is an input node for scan test data and is connected to the node Q1 of the scan flip-flop 319. The node SN11 is a storage node of the backup circuit 312. The capacitive element C11 is a storage capacitor for storing the voltage of the node SN11.

[0084] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0085] The transistors M11 to M13 are OS transistors, similar to the transistors 353 to 355 included in the memory cell 352. The transistors M11 to M13 are illustrated as having back gates. The back gates of the transistors M11 to M13 are connected to a power supply line that supplies the voltage VBG1.

[0086] At least the transistors M11 and M12 are preferably OS transistors. The OS transistor's extremely low off-state current prevents a voltage drop at the node SN11 and consumes almost no power to retain data, making the backup circuit 312 nonvolatile. Because data is rewritten by charging and discharging the capacitive element C11, the backup circuit 312 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and it can write and read data with little power.

[0087] It is highly preferred that all transistors in the backup circuit 312 are OS transistors. As shown in Figure 10B, the backup circuit 312 can be stacked on a scan flip-flop 319 made of silicon CMOS circuitry.

[0088] Since the backup circuit 312 has an extremely small number of elements compared to the scan flip-flop 319, stacking the backup circuit 312 does not require changing the circuit configuration and layout of the scan flip-flop 319. In other words, the backup circuit 312 is a highly versatile backup circuit. Furthermore, since the backup circuit 312 can be provided in the region where the scan flip-flop 319 is formed, even if the backup circuit 312 is incorporated, it is possible to eliminate any increase in the area occupied by the flip-flop 314. Therefore, providing the backup circuit 312 in the flip-flop 314 enables power gating of the CPU core 311. Because the power required for power gating is small, the CPU core 311 can be power gated with high efficiency.

[0089] By providing backup circuit 312, a parasitic capacitance due to transistor M11 is added to node Q1, but since this is small compared to the parasitic capacitance due to the logic circuit connected to node Q1, it does not affect the operation of scan flip-flop 319. In other words, even if backup circuit 312 is provided, the performance of flip-flop 314 does not substantially deteriorate.

[0090] For example, a clock gating state, a power gating state, or a sleep state can be set as the low power consumption state of the CPU core 311. The PMU 313 selects the low power consumption mode of the CPU core 311 based on an interrupt signal, a signal SLEEP1, etc. For example, when transitioning from a normal operating state to a clock gating state, the PMU 313 stops generating the clock signal GCLK1.

[0091] For example, when transitioning from a normal operating state to a hibernation state, the PMU 313 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 313 turns off the power switch 315 and turns on the power switch 316 to input the voltage VDD1 to the CPU core 311. The voltage VDD1 is a voltage that does not cause data to be lost in the scan flip-flop 319. When performing frequency scaling, the PMU 313 reduces the frequency of the clock signal GCLK1.

[0092] When the CPU core 311 is transitioned from the normal operation state to the power gating state, an operation is performed to back up the data in the scan flip-flop 319 to the backup circuit 312. When the CPU core 311 is returned from the power gating state to the normal operation state, an operation is performed to recover the data in the backup circuit 312 to the scan flip-flop 319.

[0093] 11 shows an example of a power gating sequence for the CPU core 311. In FIG. 11, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 315 to 317, and are generated by the PMU 313. When the signal PSE0 is "H" / "L", the power switch 315 is on / off. The same applies to the signals PSE1 and PSE2.

[0094] Before time t1, the system is in a normal operation state (Normal Operation). The power switch 315 is on, and the voltage VDDD is input to the CPU core 311. The scan flip-flop 319 performs normal operation. At this time, the level shifter 318 does not need to operate, so the power switch 317 is off, and the signals SCE, BK, and RC are "L". Since the node SE is "L", the scan flip-flop 319 stores the data at the node D1. In the example of FIG. 11, at time t1, the node SN11 of the backup circuit 312 is "L".

[0095] The operation during backup will be described. At time t1, the PMU 313 stops the clock signal GCLK1 and sets the signals PSE2 and BK to "H." The level shifter 318 becomes active and outputs the signal BKH at "H" to the backup circuit 312.

[0096] The transistor M11 of the backup circuit 312 turns on, and the data at the node Q1 of the scan flip-flop 319 is written to the node SN11 of the backup circuit 312. If the node Q1 of the scan flip-flop 319 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0097] The PMU 313 sets the signals PSE2 and BK to "L" at time t2, and sets the signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 311 transitions to the power gating state. Note that the signal PSE0 may also fall at the same timing as the signal BK falls.

[0098] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at node Q1 is lost. Node SN11 continues to hold the data at node Q1 at time t3.

[0099] The operation during recovery will be explained below. At time t4, the PMU 313 sets the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage on the V_VDD line reaches VDDD (time t5), the PMU 313 sets the signals PSE2, RC, and SCE to "H".

[0100] Transistor M12 turns on, and the charge of capacitive element C11 is distributed between node SN11 and node SD. If node SN11 is "H," the voltage of node SD rises. Since node SE is "H," the data of node SD is written to the input latch circuit of scan flip-flop 319. When clock signal GCLK1 is input to node CK at time t6, the data of the input latch circuit is written to node Q1. In other words, the data of node SN11 has been written to node Q1.

[0101] At time t7, the PMU 313 sets the signals PSE2, SCE, and RC to "L", and the recovery operation ends.

[0102] The backup circuit 312 using OS transistors consumes low dynamic and static power, making it highly suitable for normally-off computing. A CPU 310 including a CPU core 311 with a backup circuit 312 using OS transistors can be called an NoffCPU (registered trademark). The NoffCPU has nonvolatile memory and can stop power supply when operation is not required. Even if the flip-flop 314 is installed, it is possible to minimize the degradation of performance of the CPU core 311 and the increase in dynamic power consumption.

[0103] The CPU core 311 may have multiple power domains that can be power-gated. Each of the multiple power domains is provided with one or more power switches for controlling the input of voltage. The CPU core 311 may also have one or more power domains in which power gating is not performed. For example, a power domain in which power gating is not performed may be provided with a power gating control circuit for controlling the flip-flop 314 and the power switches 315 to 317.

[0104] The application of the flip-flop 314 is not limited to the CPU 310. In the CPU 310, the flip-flop 314 can be applied to a register provided in a power domain that is capable of power gating.

[0105] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0106] (Embodiment 2) In this embodiment, a structural example of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0107] FIG. 12 shows a part of a cross-sectional structure of the semiconductor device. The semiconductor device shown in FIG. 12 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 13A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 13B is a cross-sectional view of the transistor 500 in the channel width direction. For example, the transistor 500 corresponds to an OS transistor included in the memory circuit 350 described in the above embodiment, that is, a transistor having an oxide semiconductor in a channel formation region. The transistor 550 corresponds to a Si transistor included in the arithmetic circuit 360 described in the above embodiment, that is, a transistor having silicon in a channel formation region. The capacitor 600 corresponds to a capacitor included in the memory circuit 350.

[0108] The transistor 500 is an OS transistor. An OS transistor has an extremely low off-state current. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of refresh operations of the storage node can be reduced or no refresh operations are required, thereby reducing the power consumption of the semiconductor device.

[0109] In FIG. 12, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0110] The transistor 550 is provided on a substrate 411. The substrate 411 is, for example, a p-type silicon substrate. The substrate 411 may be an n-type silicon substrate. The oxide layer 414 is preferably an insulating layer (also referred to as a BOX layer) formed by buried oxide in the substrate 411, for example, silicon oxide. The transistor 550 is provided on a single-crystal silicon substrate provided on the substrate 411 with the oxide layer 414 interposed therebetween, a so-called SOI (Silicon On Insulator) substrate. Therefore, in this embodiment and the like, the transistor 550 is a Si transistor.

[0111] A substrate 411 in the SOI substrate is provided with an insulator 413 that functions as an element isolation layer. The substrate 411 also has a well region 412. The well region 412 is a region that is given n-type or p-type conductivity depending on the conductivity type of the transistor 550. A semiconductor region 415, and low-resistance regions 416a and 416b that function as source and drain regions are provided in the single crystal silicon of the SOI substrate. A low-resistance region 416c is also provided on the well region 412.

[0112] The transistor 550 can be provided overlapping a well region 412 to which an impurity element imparting conductivity is added. The well region 412 can function as a bottom gate electrode of the transistor 550 by independently changing the potential through the low-resistance region 416c. This allows the threshold voltage of the transistor 550 to be controlled. In particular, applying a negative potential to the well region 412 can increase the threshold voltage of the transistor 550 and reduce its off-state current. Therefore, applying a negative potential to the well region 412 can reduce the drain current when the potential applied to the gate electrode of the Si transistor is 0 V. As a result, the power consumption of a semiconductor device including the transistor 550 can be reduced, and the operating efficiency can be improved.

[0113] The transistor 550 is preferably a so-called fin type transistor in which the top surface of the semiconductor layer and the side surfaces in the channel width direction are covered with a conductor 418 via an insulator 417. By using the fin type transistor 550, the effective channel width can be increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0114] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0115] The conductor 418 may function as a first gate (also referred to as a top gate) electrode. The well region 412 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the well region 412 can be controlled via the low-resistance region 416c.

[0116] The region where the channel of the semiconductor region 415 is formed, the region nearby, the low-resistance region 416a and low-resistance region 416b that serves as the source or drain region, and the low-resistance region 416c connected to an electrode that controls the potential of the well region 412 preferably contain a semiconductor such as a silicon-based semiconductor, and preferably single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) by using GaAs and GaAlAs, or the like.

[0117] Well region 412, low resistance region 416a, low resistance region 416b, and low resistance region 416c contain, in addition to the semiconductor material applied to semiconductor region 415, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0118] The conductor 418 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, including an element that provides n-type conductivity, such as arsenic or phosphorus, or an element that provides p-type conductivity, such as boron. The conductor 418 can also be made of a silicide, such as nickel silicide.

[0119] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and tungsten is particularly preferable in terms of heat resistance.

[0120] The low-resistance regions 416a, 416b, and 416c may be formed by stacking another conductor, for example, a silicide such as nickel silicide. This structure can increase the conductivity of the regions that function as electrodes. In this case, an insulator that functions as a sidewall spacer (also referred to as a sidewall insulating layer) may be provided on the side surface of the conductor 418 that functions as a gate electrode and the side surface of the insulator 417 that functions as a gate insulating film. This structure can prevent electrical conduction between the conductor 418 and the low-resistance regions 416a and 416b.

[0121] An insulator 420, an insulator 422, an insulator 424, and an insulator 426 are stacked in this order to cover the transistor 550.

[0122] The insulators 420, 422, 424, and 426 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0123] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0124] The insulator 422 may function as a planarizing film that flattens steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 422 may be planarized by planarization treatment such as chemical mechanical polishing (CMP) to improve the planarity.

[0125] The insulator 424 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 411, the transistor 550, or the like to a region where the transistor 500 is provided.

[0126] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0127] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorbed hydrogen from the insulator 424 is calculated as 10×10 per area of ​​the insulator 424 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0128] Note that the insulator 426 preferably has a lower dielectric constant than the insulator 424. For example, the relative dielectric constant of the insulator 426 is preferably less than 4, more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 426 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 424. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0129] Conductors 428 and 430, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 420, 422, 424, and 426. The conductors 428 and 430 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, part of a conductor may function as a wiring, and part of a conductor may function as a plug.

[0130] The materials for each plug and wiring (conductor 428, conductor 430, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0131] A wiring layer may be provided over the insulator 426 and the conductor 430. For example, in FIG. 12, the insulator 450, the insulator 452, and the insulator 454 are stacked in this order. The conductor 456 is formed over the insulator 450, the insulator 452, and the insulator 454. The conductor 456 functions as a plug or wiring connected to the transistor 550. Note that the conductor 456 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0132] Note that, for example, the insulator 450 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 424. The conductor 456 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 450 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0133] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 450 having a barrier property against hydrogen.

[0134] A wiring layer may be provided over the insulator 454 and the conductor 456. For example, in FIG. 12, an insulator 460, an insulator 462, and an insulator 464 are stacked in this order. A conductor 466 is formed in the insulator 460, the insulator 462, and the insulator 464. The conductor 466 functions as a plug or a wiring. The conductor 466 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0135] Note that, for example, the insulator 460 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 424. The conductor 466 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 460 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0136] A wiring layer may be provided over the insulator 464 and the conductor 466. For example, in FIG. 12, an insulator 470, an insulator 472, and an insulator 474 are stacked in this order. A conductor 476 is formed in the insulator 470, the insulator 472, and the insulator 474. The conductor 476 functions as a plug or a wiring. The conductor 476 can be formed using a material similar to that of the conductors 428 and 430.

[0137] Note that, for example, the insulator 470 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 424. The conductor 476 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 470 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0138] A wiring layer may be provided over the insulator 474 and the conductor 476. For example, in FIG. 12, an insulator 480, an insulator 482, and an insulator 484 are stacked in this order. A conductor 486 is formed in the insulator 480, the insulator 482, and the insulator 484. The conductor 486 functions as a plug or a wiring. The conductor 486 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0139] Note that, for example, the insulator 480 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 424. The conductor 486 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 480 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0140] Although the above describes a wiring layer including the conductor 456, a wiring layer including the conductor 466, a wiring layer including the conductor 476, and a wiring layer including the conductor 486, the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 456, or there may be five or more wiring layers similar to the wiring layer including the conductor 456.

[0141] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 484. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen and hydrogen.

[0142] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region from the substrate 411 or a region where the transistor 550 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 424 can be used.

[0143] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 500 and the transistor 550.

[0144] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0145] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0146] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 420. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film or a silicon oxynitride film.

[0147] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0148] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0149] Above the insulator 516 is the transistor 500 .

[0150] As shown in Figures 13A and 13B, transistor 500 has conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, insulator 522 arranged on insulator 516 and conductor 503, insulator 524 arranged on insulator 522, oxide 530a arranged on insulator 524, oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, insulator 580 arranged on conductors 542a and 542b and having an opening formed therebetween overlapping conductors 542a and 542b, insulator 545 arranged on the bottom and side surfaces of the opening, and conductor 560 arranged on the surface on which insulator 545 is formed.

[0151] 13A and 13B, it is preferable that insulator 544 be disposed between oxide 530a, oxide 530b, conductor 542a, and conductor 542b and insulator 580. It is preferable that conductor 560 have conductor 560a disposed inside insulator 545 and conductor 560b disposed so as to be embedded inside conductor 560a. It is preferable that insulator 574 be disposed on insulator 580, conductor 560, and insulator 545, as shown in FIGS.

[0152] In this specification and other documents, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0153] Note that although the transistor 500 has a structure in which two layers of the oxide 530a and the oxide 530b are stacked in and around the channel formation region, the present invention is not limited to this. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0154] Although the transistor 500 has a two-layer structure in which the conductor 560 is stacked, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 shown in FIGS. 12, 13A, and 13B is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0155] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0156] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0157] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0158] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0159] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like differs from the fin type configuration and the planar type configuration. By adopting the S-channel configuration, the transistor can be made more resistant to the short channel effect, in other words, less susceptible to the short channel effect.

[0160] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductors 503a and 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0161] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0162] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0163] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single-layer structure.

[0164] The insulator 522 and the insulator 524 function as a second gate insulating film.

[0165] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen." In other words, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V OH.) functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0166] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0167] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O The reaction "H → Vo + H" occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO, which may be removed from the oxide 530 or an insulator near the oxide 530. Some of the hydrogen may also be gettered to the conductor 542a or the conductor 542b.

[0168] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0169] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0170] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0171] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0172] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the conductor 503. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0173] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0174] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0175] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0176] 13A and 13B, the second gate insulating film has a three-layer structure including the insulators 522 and 524. However, the second gate insulating film may have a single-layer structure, a two-layer structure, or a four- or more-layer structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0177] The transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, the oxide 530 may be a metal oxide such as In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like).

[0178] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in other embodiments.

[0179] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0180] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0181] Note that oxide 530 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of element M to In in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0182] The energy of the conduction band minimum of the oxide 530a is preferably higher than that of the oxide 530b, or in other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.

[0183] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxide 530a and the oxide 530b. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0184] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, a gallium oxide, or the like.

[0185] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0186] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0187] 13A shows the conductor 542a and the conductor 542b as a single layer, they may be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0188] Other examples include a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0189] 13A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0190] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0191] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0192] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0193] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later process. Note that if the conductors 542a and 542b are made of oxidation-resistant materials or materials whose conductivity does not decrease significantly even when they absorb oxygen, the insulator 544 is not an essential component. It can be designed appropriately depending on the desired transistor characteristics.

[0194] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. The insulator 544 can also prevent the conductors 542a and 542b from being oxidized by excess oxygen contained in the insulator 580.

[0195] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0196] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0197] By providing the insulator 545 as an insulator containing excess oxygen, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545.

[0198] Furthermore, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0199] Note that the insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a layered structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a layered structure that is thermally stable and has a high dielectric constant can be achieved.

[0200] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 13A and 13B, but may have a single-layer structure or a laminated structure of three or more layers.

[0201] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The oxygen-suppressing function of the conductor 560a can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 545, which can reduce the conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, an oxide semiconductor that can be used for the oxide 530 can be used for the conductor 560a. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0202] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Because the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0203] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of an excess oxygen region in a later step.

[0204] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0205] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0206] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0207] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0208] For example, the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0209] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0210] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0211] Furthermore, conductors 540a and 540b are arranged in openings formed in insulators 581, 574, 580, and 544. Conductor 540a and 540b are arranged opposite each other with conductor 560 interposed therebetween. Conductor 540a and 540b have the same configuration as conductors 546 and 548, which will be described later.

[0212] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0213] In particular, aluminum oxide has a high blocking effect against both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0214] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 420. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0215] Furthermore, conductors 546, 548, etc. are embedded in insulators 522, 524, 544, 580, 574, 581, 582, and 586.

[0216] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 428 and the conductor 430.

[0217] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0218] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0219] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0220] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0221] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0222] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0223] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 420. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0224] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0225] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments. [Explanation of symbols]

[0226] 10: living body, 100: semiconductor device, 110: communication unit, 111: RF circuit, 112: resonance circuit, 113: power supply circuit, 114: clock generation circuit, 115: demodulation circuit, 116: modulation circuit, 117: information processing circuit, 120: calculation unit, 121: calculation circuit, 122: memory circuit, 130: control unit, 140: memory unit, 150: sensor unit, 190: coating material

Claims

[Claim 1] A semiconductor device that can be implanted in a living body, The device includes a communication unit, a control unit, a storage unit, a calculation unit, and a sensor unit, the sensor unit has a function of acquiring biological information, the storage unit has a function of storing identification information of the semiconductor device, the calculation unit includes a memory circuit having a function of storing weight information, and a calculation circuit having a function of performing a product-sum calculation using the weight information and the biological information to obtain a calculation result; the control unit has a function of outputting either or both of the identification information and the calculation result to an external device via the communication unit in response to a signal input via the communication unit; the operating unit includes a transistor including an oxide semiconductor in a channel formation region; Semiconductor device.

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