Memory system and command determination method

Abstract

To provide a memory system capable of improving a processing capacity.SOLUTION: The memory system includes memory chips 110a,110b connected to a first channel, and a memory controller. The memory controller includes command queues 241-0, 241-1, and an arbiter that determines commands to be executed by a first memory chip and a second memory chip. The commands include a first command and a second command. A period in a state where the memory chips do not accept a command is longer when the first command is executed than when the second command is executed. The arbiter determines a command to be executed based on a first signal indicating whether or not the first memory chip and the second memory chip are not in a state of accepting a command and a second signal indicating one of the first command and the second command to which a command stored in a first command queue and a command stored in a second command queue correspond.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a memory system and a command determination method. [Background technology]

[0002] Solid-state drives (SSDs) equipped with NAND flash memory are known as one type of memory system. SSDs employ a technology called bank interleaving, which allows multiple memory chips connected to the same channel to operate in parallel on a bank-by-bank basis. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-16954 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a memory system and a command determination method that can improve processing performance. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a first channel, a second channel, a nonvolatile memory including a first bank and a second bank, and a memory controller for controlling the nonvolatile memory. The first bank includes a first nonvolatile memory chip and a third nonvolatile memory chip. The second bank includes a second nonvolatile memory chip and a fourth nonvolatile memory chip. The first nonvolatile memory chip and the second nonvolatile memory chip are connected to the first channel, and the third nonvolatile memory chip and the fourth nonvolatile memory chip are connected to the second channel. The memory controller includes a first controller for controlling the first nonvolatile memory chip and the second nonvolatile memory chip, a first command queue for storing commands to be sent to the first nonvolatile memory chip, a second command queue for storing commands to be sent to the second nonvolatile memory chip, and an arbiter for determining commands to be executed by the first nonvolatile memory chip and the second nonvolatile memory chip. Each of the first nonvolatile memory chip and the second nonvolatile memory chip outputs a first signal indicating whether or not it is ready to accept a command. The commands include a first command and a second command. The period during which the nonvolatile memory chip that executed the first command does not accept a command is longer than the period during which the nonvolatile memory chip that executed the second command does not accept a command. The memory controller generates a second signal indicating whether the commands stored in the first command queue and the second command queue correspond to the first command or the second command. The arbiter determines the commands to be executed by the first nonvolatile memory chip and the second nonvolatile memory chip based on the first signal and the second signal. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the configuration of a memory system according to an embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of a controller 240-0 and the connection relationship between the controller 240-0 and memory chips 110a, 110b, and 110c. [Figure 3]4 is a flowchart showing a first command determination method according to the embodiment. [Figure 4] 10 is a flowchart showing a second command determination method according to the embodiment. [Figure 5] 10 is a flowchart showing a third command determination method according to the embodiment. [Figure 6] FIG. 4 is a diagram showing an example of commands stored in a command queue according to the embodiment. [Figure 7] FIG. 4 is a diagram showing changes over time in commands stored in a command queue according to the embodiment. [Figure 8] FIG. 4 is a diagram showing changes over time in commands input to the arbiter according to the embodiment. [Figure 9] 5 is a timing chart showing the order of commands executed by the first command determination method according to the embodiment. [Figure 10] 6 is a timing chart showing the order of commands executed by a first command determination method according to a first comparative example. [Figure 11] FIG. 10 is a diagram showing another example of commands stored in a command queue according to the embodiment. [Figure 12] 10 is another timing chart showing the order of commands executed by the first command determination method according to the embodiment. [Figure 13] 10 is another timing chart showing the order of commands executed by the command determination method according to the second comparative example. [Figure 14] FIG. 10 is a diagram showing another example of commands stored in a command queue according to the embodiment. [Figure 15] 10 is a timing chart showing the order of commands executed by a fourth command determination method according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment will be described with reference to the drawings.

[0008] FIG. 1 is a block diagram showing the configuration of a memory system according to an embodiment. The memory system 1 is connectable to a host device 2. The memory system 1 can receive access requests (such as read requests and write requests) from the host device 2. Signals are transmitted and received between the memory system 1 and the host device 2 in accordance with, for example, PCIe, which is one of the interface standards. The host device 2 is an information processing device external to the memory system 1. The host device 2 is, for example, an information processing device such as a personal computer or a server, a tester device, a manufacturing device, an imaging device such as a still camera or a video camera, a mobile terminal such as a tablet computer or a smartphone, a game device, or a car navigation system (in-vehicle terminal).

[0009] The memory system 1 includes a nonvolatile memory 100, a memory controller 200, a first channel ch0, a second channel ch1, a third channel ch2, and a fourth channel ch3. Hereinafter, when there is no need to distinguish between them, they will be referred to as channels ch.

[0010] The nonvolatile memory 100 is a memory that stores data in a nonvolatile manner. The nonvolatile memory 100 is, for example, a NAND flash memory, such as a Magnetoresistive Random Access Memory (MRAM), a Phase Change Random Access Memory (PRAM), a Resistive Random Access Memory (ReRAM), or a Ferroelectric Random Access Memory (FeRAM).

[0011] The memory controller 200 controls the nonvolatile memory 100. For example, the memory controller 200 writes data to the nonvolatile memory 100 in response to a write instruction from the host device 2, and reads data from the nonvolatile memory 100 in response to a read instruction from the host device 2 and transmits the data to the host device 2.

[0012] A channel ch is a group of wirings. A channel ch includes I / O signal lines and control signal lines. The I / O signal lines are, for example, signal lines for transmitting and receiving data, addresses, and commands. The control signal lines are, for example, signal lines for transmitting and receiving a WE (write enable) signal, an RE (read enable) signal, a CLE (command latch enable) signal, an ALE (address latch enable) signal, and a WP (write protect) signal. The chip enable signal is a signal for enabling the memory chip 110, and is asserted at a low level.

[0013] Next, we will explain the internal configuration of the nonvolatile memory 100. The nonvolatile memory 100 includes multiple banks (banks #0, #1, and #2). When there is no need to distinguish between banks #0, #1, and #2, they will be referred to as bank #.

[0014] Each bank is a collection of multiple memory chips. Bank #0 includes memory chips 110a, 110d, 110g, and 110j. Bank #1 includes memory chips 110b, 110e, 110h, and 110k. Bank #2 includes memory chips 110c, 110f, 110i, and 110l. Hereinafter, when there is no need to distinguish between memory chips 110a to 110l, they will be referred to as memory chips 110 or memory chips.

[0015] The memory chip 110 is an IC chip (non-volatile memory chip) that includes multiple non-volatile elements. The memory chip 110 writes and reads data in units called pages, each of which includes multiple memory cells. Each page is assigned a unique physical address.

[0016] Next, the internal configuration of the memory controller 200 will be described. The memory controller 200 includes a RAM (Random Access Memory) 210, a ROM (Read Only Memory) 220, a host interface (host I / F) 230, multiple controllers 240-0, 240-1, and 240-3, and a processor 250. The memory controller 200 is configured, for example, as an SoC (System-on-a-Chip) or multiple chips. Hereinafter, when there is no need to distinguish between the controllers 240-0, 240-1, and 240-3, they will be referred to as the controller 240. The RAM 210, ROM 220, host interface 230, controller 240, and processor 250 are connected to one another via a bus. Note that the RAM 210, ROM 220, host I / F 230, controller 240, and part of the processor 250 may be disposed outside the memory controller 200.

[0017] The RAM 210 is a memory that functions as a cache, a buffer, and a working area. The RAM 210 is, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination thereof. The RAM 210 stores data received from the host device 2. The RAM 210 also stores data read from the nonvolatile memory 100. The RAM 210 may be provided outside the memory controller 200.

[0018] The ROM 220 is a memory from which recorded information can be read but new information cannot be written. For example, firmware used by the processor 250 is stored in the ROM 220. The firmware is software that includes data and the like regarding multiple commands related to the memory chip 110. The multiple commands related to the memory chip 110 include, for example, a read sense command, a program command, a data-in command, and a data-out command. The firmware may also be stored in the non-volatile memory 100.

[0019] The host interface (host I / F) 230 is a circuit configured to execute communication with the outside. The host interface 230 transmits and receives information (access requests, responses, data) between the host device 2 and the memory controller 200.

[0020] The controller 240 is hardware for controlling the memory chips 110. The controller 240-0 is connected to the memory chips 110a, 110b, 110c, and 110d via a first channel ch0. The controller 240-1 is connected to the memory chips 110d, 110e, and 110f via a second channel ch1. The controller 240-2 is connected to the memory chips 110g, 110h, and 110i via a third channel ch2. The controller 240-3 is connected to the memory chips 110l, 110k, and 110l via a fourth channel ch3. The controller 240-0 can operate multiple memory chips connected to channel ch0 in parallel (bank interleaving). The same applies to the controllers 240-1, 240-2, and 240-3.

[0021] The processor 250 is hardware for executing an instruction set recorded in software. The processor 250 is, for example, a central processing unit (CPU). The processor 250 controls the entire memory controller 200 by executing firmware.

[0022] The firmware contains the data necessary to generate a busy period signal that indicates whether the busy period of the memory chip 110 executing the read sense command is longer than a certain period.

[0023] Similarly, the firmware includes data necessary to generate a busy period signal that indicates whether the busy period of the memory chip 110 executing a program command, a data-in command, or a data-out command is longer than a certain period. A busy period is a period during which the memory chip 110 does not accept commands (instructions) from the outside.

[0024] The processor 250 generates a busy period signal (second signal) based on the above data, and outputs the generated busy period signal.

[0025] The time that a read sense command or program command sent to the memory chip 110 occupies the I / O signal line is shorter than the time that a data-in command or data-out command sent to the memory chip 110 occupies the I / O signal line.

[0026] The busy period required for the memory chip 110 to execute a read sense command or a program command is longer than the busy period required for the memory chip 110 to execute a data-in command or a data-out command.

[0027] 2 is a diagram showing the configuration of controller 240-0 and the connection relationship between controller 240-0 and memory chips 110a to 110c. Controllers 240-0 to 240-3 have the same configuration. Memory chips 110a to 110l also have the same configuration. Therefore, a description of the configuration of controllers not shown in FIG. 2 and a description of the connection relationship between controllers not shown in FIG. 2 and memory chips will be omitted.

[0028] The memory chip 110a in bank #0, the memory chip 110b in bank #1, and the memory chip 110c in bank #2, which are connected to the controller 240-0, share a single I / O signal line. That is, the multiple memory chips 110 belonging to the same channel ch are connected to a single I / O signal line.

[0029] Memory chip 110a outputs a ready / busy signal Ry / By-0 (first signal) indicating whether it is in a busy state or a ready state (a state in which it can accept commands from the outside). Memory chip 110b outputs a ready / busy signal Ry / By-1 (first signal) indicating whether it is in a busy state or a ready state. Memory chip 110c outputs a ready / busy signal Ry / By-1 (first signal) indicating whether it is in a busy state or a ready state. Hereinafter, when there is no need to distinguish between Ry / By-0, Ry / By-1, and Ry / By-2, they will be referred to as Ry / By#.

[0030] The controller 240-0 includes a queue unit 241, an arbiter 242, and a memory interface controller (memory I / F controller) 243.

[0031] The queue unit 241 includes three command queues 241-0, 241-1, and 241-2 corresponding to the three banks #0, #1, and #2 (the three memory chips 110a, 110b, and 110c). The command queues 241-0, 241-1, and 241-2 correspond one-to-one to the banks #0, #1, and #3. Hereinafter, when there is no need to distinguish between the command queues 241-0, 241-1, and 241-2, they will be referred to as command queue 241-#. The command queue 241-# has a queue structure capable of holding multiple commands. The queue structure may be, for example, a FIFO (First-n First-Out) structure or a FILO (First-In, Last-Out) structure. The command queue 241-# stores either commands whose busy period is longer than a certain period or commands whose busy period is shorter than a certain period, or both. Hereinafter, the busy period will be referred to as the busy period. A command whose busy period is longer than a certain period is called a first command. A command whose busy period is shorter than a certain period is called a second command.

[0032] Commands to be executed by memory chip 110a of bank #0 are stored in command queue 241-0. Commands are sent from processor 250. The commands are stored in command queue 241-0 in the order they are received.

[0033] Command queue 241-1 stores commands to be executed by memory chip 110b in bank #1. The commands are sent from processor 250. The commands are stored in command queue 241-1 in the order they are received.

[0034] Command queue 241-2 stores commands to be executed by memory chip 110c in bank #2. The commands are sent from processor 250. The commands are stored in command queue 241-2 in the order they are received.

[0035] The command queue 241-0 outputs the command stored at the top. The output command is input to the arbiter 242. The command queue 241-1 outputs the command stored at the top. The output command is input to the arbiter 242. The command queue 241-2 outputs the command stored at the top. The output command is input to the arbiter 242.

[0036] The arbiter 242 receives as input the ready / busy signal Ry / By-0 output from the memory chip 110a, the ready / busy signal Ry / By-1 output from the memory chip 110b, and the ready / busy signal Ry / By-2 output from the memory chip 110c. Additionally, the arbiter 242 receives as input a busy period signal (second signal) Sa output from the processor 250.

[0037] Based on the ready / busy signals Ry / By-0, Ry / By-1, Ry / By-2 and busy period signal Sa, the arbiter 242 determines which of the multiple commands input from the command queues 241-0, 241-1, 241-2 is to be executed by the memory chip 110, in accordance with a command determination method according to an embodiment described below.

[0038] The arbiter 242 transmits a signal Sb to the memory interface controller 243. When a first command is determined according to the command determination method of the embodiment, the signal Sb includes information indicating the first command. The signal Sb including the information indicating the first command is referred to as signal Sb1. When a second command is determined according to the command determination method of the embodiment, the signal Sb includes information indicating the second command. The signal Sb including the information indicating the second command is referred to as signal Sb2.

[0039] The memory interface controller 243 controls the transmission / reception of data between the RAM 210 and the memory chip 110 based on the signal Sb.

[0040] When executing a read sense command, the memory interface controller 243 instructs the memory chip 110 to prepare for reading data. For example, when reading data from memory chip 110a among memory chips 110a to 100c of channel ch0, a low-level chip enable signal is sent to memory chip 110a, and a high-low level chip enable signal is sent to memory chips 110b and 100c. Execution of the read sense command involves a waiting time. However, execution of the read sense command does not involve occupancy of the I / O line.

[0041] When executing a data-out command, the memory interface controller 243 reads data (read data) prepared in the memory chip 110. For example, when a low-level chip enable signal is sent to the memory chip 110a and a high-low level chip enable signal is sent to the memory chips 110b and 110c, data can be read from the memory chip 110a using a single I / O signal line. The data-out command uses the I / O line. Therefore, execution of the data-out command involves the occupation of the I / O line.

[0042] When executing a data-in command, the memory interface controller 243 instructs the memory chip 110 to prepare for writing data. For example, when writing data to the memory chip 110a among the memory chips 110a, 100b, and 100c on channel ch0, a low-level chip enable signal is sent to the memory chip 110a, and a high-low level chip enable signal is sent to the memory chips 110b and 100c. The data-in command uses an I / O line. Therefore, execution of the data-in command involves the occupation of the I / O line.

[0043] When executing a program command, the memory interface controller 243 writes data (write data) prepared in the memory chip 110 to the memory chip. For example, if a low-level chip enable signal is sent to the memory chip 110a and a high-low level chip enable signal is sent to the memory chips 110b and 110c, data can be written to the memory chip 110a using a single I / O signal line. Execution of a program command involves a waiting time. However, execution of a program command does not involve the occupation of an I / O line.

[0044] Next, a first command determination method according to an embodiment performed by the arbiter 242 will be described. Fig. 3 is a flowchart showing the first command determination method according to an embodiment. The first command determination method is a method for determining the next command to be executed from among the commands stored in the command queue 241-#.

[0045] The arbiter 242 determines whether or not the first command is present in the command queue 241-# based on the busy period signal Sa (S1).

[0046] If a first command exists in the command queue 241-# (S1 Yes), the arbiter 242 executes a second command determination method (S2). The second command determination method is a method for determining whether an executable first command is stored in the command queue 241-#.

[0047] After the second command determination method has been executed, the arbiter 242 determines whether or not there is a first command that should be executed with priority over the second command (S3).

[0048] If there is a first command that has priority to be executed over the second command (S3 Yes), the arbiter 242 sends a signal Sb1 to the memory interface controller 243. Upon receiving the signal Sb1, the memory interface controller 243 causes the memory chip 110 to execute the first command (S4). If there is a first command that has priority to be executed over the second command, this is the case when the process (S13) described below has been executed.

[0049] After executing the first command (S4), the arbiter 242 ends the first command determination method (END).

[0050] If the first command does not exist in the command queue 241-# (S1 No), or if the first command exists in the command queue 241-# but the first command that has priority to be executed over the second command does not exist (S3 No), the arbiter 242 determines whether the second command exists in the command queue 241-# based on the busy period signal Sa (S5). If the first command that has priority to be executed over the second command does not exist, this is the case where the result of the process (S14) described below is Yes.

[0051] If a second command exists in the command queue 241-# (S5 Yes), the arbiter 242 executes a third command determination method (S6). The third command determination method is a method for determining whether or not an executable second command is stored in the command queue 241-#.

[0052] After the execution of the third command determination method is completed, the arbiter 242 determines whether or not a second command to be executed exists in the command queue 241-# (S7).

[0053] If a second command to be executed exists in the command queue 241-# (S7 Yes), the arbiter 242 transmits a signal Sb2 to the memory interface controller 243. Upon receiving the signal Sb2, the memory interface controller 243 causes the memory chip 110 to execute the second command (S8). The case where a second command to be executed exists refers to the case where a process (S23) described below has been executed.

[0054] After executing the second command (S8), the arbiter 242 ends the first command determination method (END).

[0055] If the second command does not exist in the command queue 241-# (S5 No), the arbiter 242 determines whether the first command exists (S1).

[0056] If the second command to be executed does not exist in the command queue 241-# (S7 No), the arbiter 242 determines whether the first command exists (S1). If the second command to be executed does not exist, this is the case when the processing (S24) described below is Yes.

[0057] Next, the second command determination method will be described with reference to Fig. 4, which is a flowchart showing the second command determination method according to the embodiment.

[0058] The arbiter 242 selects one bank # in accordance with the rotation order using the round robin (S11).

[0059] Next, the arbiter 242 determines whether the memory chip of the selected bank # is in a busy state based on the ready / busy signal Ry / By# (S12).

[0060] If the memory chips in the selected bank # are not busy (S12 No), the arbiter 242 determines that the first command to be executed by the memory chips in the selected bank # is the command to be executed (S13).

[0061] When the first command to be executed by the memory chip of the selected bank # is determined to be the command to be executed (S13), the arbiter 242 ends the second command determination method (END).

[0062] If the memory chip of the selected bank # is busy (S12 Yes), the arbiter 242 determines whether it has confirmed whether the memory chips of all banks other than the selected bank # are busy (S14).

[0063] If it has not been confirmed whether the memory chips of all banks other than the selected bank # are busy (No in S14), the arbiter 242 selects one bank # (S11).

[0064] If it is confirmed that the memory chips of all banks other than the selected bank # are busy (S14 Yes), the arbiter 242 ends the second command determination method (END).

[0065] Next, the third command determination method will be described with reference to Fig. 5, which is a flowchart showing the third command determination method according to the embodiment.

[0066] The arbiter 242 selects one bank # in accordance with the rotation order using the round robin (S21).

[0067] Next, the arbiter 242 determines whether the memory chip of the selected bank # is in a busy state based on the ready / busy signal Ry / By# (S22).

[0068] If the memory chip of the selected bank # is not busy (No in S22), the arbiter 242 determines that the second command to be executed by the memory chip of the selected bank # is the command to be executed (S23).

[0069] When the second command to be executed by the memory chip of the selected bank # is determined to be the command to be executed (S23), the arbiter 242 ends the third command determination method (END).

[0070] If the memory chip of the selected bank # is busy (S22 Yes), the arbiter 242 determines whether it has confirmed whether the memory chips of all banks other than the selected bank # are busy (S24).

[0071] If it has not been confirmed whether the memory chips of all banks other than the selected bank # are busy (No in S24), the arbiter 242 selects one bank # (S21).

[0072] If it is confirmed that the memory chips of all banks other than the selected bank # are busy (S24 Yes), the arbiter 242 ends the third command determination method (END).

[0073] Next, the first command determination method according to the embodiment will be described using specific commands as examples. Fig. 6 is a diagram showing examples of commands stored in command queues 241-0, 241-1, and 241-2. In Fig. 6, Rs indicates a read sense command, Do indicates a data-out command, Di indicates a data-in command, and Do indicates a data-out command.

[0074] 7(a) to 7(l) are diagrams showing changes over time in commands stored in command queues 241-0, 241-1, and 241-2. For simplification, reference numerals 241-0, 241-1, and 241-2 are omitted in FIGS. 7(b) to 7(l).

[0075] Figures 8(a) to 8(l) are diagrams showing changes over time in commands input to the arbiter 242. For simplicity, reference numeral 242 is omitted in Figures 8(b) to 8(l). In Figures 8(b) to 8(l), commands in entries marked with shaded dots are commands that the arbiter 242 has determined as commands to be executed with priority.

[0076] Fig. 9 is a timing chart showing the order of commands executed by the first command determination method according to the embodiment. In Fig. 9, tR indicates the period (wait time) during which the memory chip executing Rs is busy, and tP indicates the period during which the memory chip executing Pr is busy. Fig. 9 also shows a timing chart of signals Rs', Do', Di', and Pr' flowing through the I / O signal lines. Signals Rs', Do', Di', and Pr' correspond to commands Rs, Do, Di, and Pr, respectively.

[0077] 6, Rs (first command) is stored at the head of command queue 241-0, Rs (first command) is stored at the head of command queue 241-1, and Di (second command) is stored at the head of command queue 241-2. As a result, Rs, Rs, and Di are input to arbiter 242 as shown in FIG. 8(a).

[0078] The arbiter 242 performs the processing of S1, S2, and S3 in FIG. 3. As a result, as shown in FIG. 8(a), Rs in the upper row is determined as the command to be executed. The determined command (Rs) is executed by the memory chip in bank #0 (FIG. 9).

[0079] 7(b), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Rs (first command), and the command at the top of command queue 241-2 is Di (second command). As a result, Do, Rs, and Di are input to arbiter 242 as shown in FIG. 8(b).

[0080] The arbiter 242 performs the process S1, the process S2, and the process S3 in Figure 3. As a result, as shown in Figure 8(b), Rs in the middle row is determined as the command to be executed. The determined command (Rs) is executed by the memory chip in bank #1 (Figure 9).

[0081] 7(c), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Do, and the command at the top of command queue 241-2 is Di (second command). As a result, Do, Do, and Di are input to arbiter 242 as shown in FIG. 8(c).

[0082] The arbiter 242 performs the processes S1, S5, S6, and S7 in Figure 3. As a result, as shown in Figure 8(c), the command to be executed by Di in the lower row is determined. The determined command (Rs) is executed by the memory chip in bank #2 (Figure 9).

[0083] 7(d), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Do (second command), and the command at the top of command queue 241-2 is Pr (first command). As a result, Do, Do, and Pr are input to arbiter 242 as shown in FIG. 8(d).

[0084] The arbiter 242 performs the process S1, the process S2, and the process S3 in Figure 3. As a result, as shown in Figure 8(d), the command to be executed is determined as Pr in the lower row. The determined command (Pr) is executed by the memory chip in bank #2 (Figure 9).

[0085] 7(e), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Do, and the command at the top of command queue 241-2 is Rs (first command). As a result, Do, Do, and Rs are input to arbiter 242 as shown in FIG. 8(e).

[0086] The arbiter 242 performs the processes S1, S2, S3, S5, S6, and S7 in Figure 3. As a result, as shown in Figure 8(e), the upper row Do is determined as the command to be executed. The determined command (Do) is executed by the memory chip in bank #0 (Figure 9).

[0087] 7(f), the command at the top of command queue 241-0 is Rs (first command), the command at the top of command queue 241-1 is Do (second command), and the command at the top of command queue 241-2 is Rs. As a result, Rs, Do, and Rs are input to arbiter 242 as shown in FIG.

[0088] The arbiter 242 performs the processes S1, S2, and S3 in Fig. 3. As a result, as shown in Fig. 8(f), the upper Rs (corresponding to the Rs at the top of the command queue 241-0 in Fig. 7(f)) is determined as the command to be executed. The determined command (Rs) is executed by the memory chip in bank #0 (Fig. 9).

[0089] 7(g), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Do (second command), and the command at the top of command queue 241-2 is Rs (first command). As a result, Do, Do, and Rs are input to arbiter 242 as shown in FIG. 8(g).

[0090] The arbiter 242 performs the processes S1, S2, S3, S5, S6, and S7 in Figure 3. As a result, as shown in Figure 8(g), Do in the middle row is determined as the command to be executed. The determined command (Do) is executed by the memory chip in bank #1 (Figure 9).

[0091] 7(h), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Di (second command), and the command at the top of command queue 241-2 is Rs (first command). As a result, Do, Di, and Rs are input to arbiter 242 as shown in FIG. 8(h).

[0092] The arbiter 242 performs the processes S1, S2, and S3 in Figure 3. As a result, as shown in Figure 8(g), Rs in the lower row is determined as the command to be executed. The determined command (Rs) is executed by the memory chip in bank #2 (Figure 9).

[0093] 7(i), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Di (second command), and the command at the top of command queue 241-2 is Do (second command). As a result, Do, Di, and Do are input to arbiter 242 as shown in FIG. 8(i).

[0094] The arbiter 242 performs the processes S1, S5, S6, and S7 in Figure 3. As a result, as shown in Figure 8(i), Di in the middle stage is determined as the command to be executed. The determined command (Di) is executed by the memory chip in bank #1 (Figure 9).

[0095] 7(j), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Pr (first command), and the command at the top of command queue 241-2 is Do (second command). As a result, Do, Pr, and Do are input to arbiter 242 as shown in FIG. 8(j).

[0096] The arbiter 242 performs (processing S1, processing S2) and processing S3 in Figure 3. As a result, as shown in Figure 8(j), Pr in the middle row is determined as the command to be executed. The determined command (Pr) is executed by the memory chip in bank #1 (Figure 9).

[0097] 7(k), the command at the top of command queue 241-0 is Do (second command), the command at the top of command queue 241-1 is Null (no command), and the command at the top of command queue 241-2 is Do (second command). As a result, Do, Null, and Do are input to arbiter 242 as shown in FIG. 8(k).

[0098] The arbiter 242 performs the processes S1, S5, S6, and S7 in Figure 3. As a result, as shown in Figure 8(k), the command to be executed is determined as Do in the lower row. The determined command (Do) is executed by the memory chip in bank #2 (Figure 9).

[0099] 7(l), the command at the head of command queue 241-0 is Do (second command), the command at the head of command queue 241-1 is Null (no command), and the command at the head of command queue 241-2 is Null. As a result, Do is input to arbiter 242 as shown in FIG. 8(l).

[0100] The arbiter 242 performs the processes S1, S5, S6, and S7 in Figure 3. As a result, as shown in Figure 8(l), the upper row Do is determined as the command to be executed. The determined command (Do) is executed by the memory chip in bank #0 (Figure 9).

[0101] By adopting a command determination method that gives priority to executing the first command (a command with a longer busy period), it becomes possible to continuously and uninterruptedly send multiple command signals through a single I / O signal line, as shown in Fig. 9. Therefore, according to this embodiment, it becomes possible to improve the processing capacity of the memory system and reduce power consumption.

[0102] Next, a command determination method according to a first comparative example will be described. Fig. 10 is a timing chart showing the order of commands executed by the command determination method according to the first comparative example. The command determination method according to the first comparative example differs from the first command determination method according to this embodiment in that the method of executing the first command preferentially is not adopted. As shown in Fig. 10, the command determination method according to the first comparative example generates periods (periods indicated by hatched lines) during which no command signals flow through the I / O signal lines.

[0103] Fig. 11 is a diagram showing another example of commands stored in the queue section 241 (command queues 241-0, 241-1, and 241-2). Fig. 11 corresponds to Fig. 6. In Fig. 11, Rs indicates a read sense command (first command), Do indicates a data out command (second command), Di indicates a data in command (second command), Er indicates an erase command (first command), and St indicates a status read command (second command).

[0104] The time that a read sense command or erase command sent to the memory chip 110 occupies the I / O signal line is shorter than the time that a data in command, data out command or status read command sent to the memory chip 110 occupies the I / O signal line.

[0105] The busy period required for the memory chip 110 to execute a read sense command or an erase command is longer than the busy period required for the memory chip 110 to execute a data-in command, a data-out command, or a status read command.

[0106] 12 is another timing chart showing the order of commands executed by the first command determination method according to the embodiment. FIG. 12 corresponds to FIG. 9. As shown in FIG. 12, it is possible to continuously and uninterruptedly transmit multiple command signals through a single I / O signal line. This makes it possible to improve the processing performance of the memory system and reduce power consumption.

[0107] 13 is another timing chart showing the order of commands executed by the command determination method according to the second comparative example. The command determination method according to the second comparative example differs from the first command determination method according to this embodiment in that the method of executing the first command preferentially is not adopted. As shown in FIG. 13, the command determination method according to the second comparative example generates three periods (periods indicated by hatched lines) during which no command signals flow through the I / O signal lines.

[0108] 14 is a diagram showing another example of commands stored in command queues 241-0, 241-1, and 241-2 according to an embodiment. In FIG. 14, command queues 241-0 and 241-1 have entries in which no commands are stored.

[0109] Next, a second command determination method according to the embodiment will be described. Fig. 15 is a timing chart showing the order of commands executed by the second command determination method according to the embodiment.

[0110] The second command determination method according to the embodiment differs from the first command determination method according to the embodiment in that it temporarily prohibits the selection of banks other than a specific bank. In the case of FIG. 15, during the period T-lock, bank #2 is selected, and banks #0 and #1 are not selected. Even when the second command determination method according to the embodiment is used, it is possible to continuously and uninterruptedly send multiple command signals to the I / O signal lines. This makes it possible to improve the processing performance of the memory system and reduce power consumption.

[0111] The embodiments are merely examples, and the scope of the invention is not limited thereto. [Explanation of symbols]

[0112] 1. Memory system 2...Host device 100...Non-volatile memory 200...Memory controller 210...RAM 220...ROM 230...Host interface 240-0, 240-1, 240-2, 240-3... Controller 241...Queue section 241-0, 241-1, 241-2... Command queue 242...Arbiter 243...Memory interface controller 250...processor ch0, ch1, ch2, ch3...channel #0,#1,#2...Bank 110a~110l...Memory chip Ry / By-0, Ry / By-1, Ry / By-2...Ready / Busy signal (first signal) Sa... Busy period signal (second signal) Sb,Sb1,Sb2…signal

Claims

1. a first channel; a second channel; and a non-volatile memory including a first bank and a second bank; a memory controller that controls the nonvolatile memory, the first bank includes a first non-volatile memory chip and a third non-volatile memory chip; the second bank includes a second non-volatile memory chip and a fourth non-volatile memory chip; the first non-volatile memory chip and the second non-volatile memory chip are connected to the first channel; the third nonvolatile memory chip and the fourth nonvolatile memory chip are connected to the second channel; The memory controller a first controller that controls the first nonvolatile memory chip and the second nonvolatile memory chip; a first command queue in which commands to be sent to the first nonvolatile memory chip are stored; a second command queue in which commands to be sent to the second nonvolatile memory chip are stored; an arbiter that determines commands to be executed by the first nonvolatile memory chip and the second nonvolatile memory chip; each of the first nonvolatile memory chip and the second nonvolatile memory chip outputs a first signal indicating whether or not it is in a state to accept the command; the commands include a first command and a second command; a period during which the nonvolatile memory chip that executed the first command is in a state of not accepting a command is longer than a period during which the nonvolatile memory chip that executed the second command is in a state of not accepting a command; the memory controller generates a second signal indicating whether each command stored in the first command queue and the second command queue corresponds to the first command or the second command; the arbiter determines commands to be executed by the first nonvolatile memory chip and the second nonvolatile memory chip based on the first signal and the second signal. Memory system.

2. the arbiter determines whether the first command is present in the first command queue or the second command queue; If the first command is present, the arbiter determines whether an executable first command is stored in the first command queue or the second command queue; If the executable first command is stored, the arbiter determines whether or not there is a first command that should be executed with priority over the second command.

10. The memory system of claim 1.

3. If the first command is present, the arbiter selects the first bank or the second bank; When the first bank is selected, the arbiter determines that the first command is a command to be executed if the first non-volatile memory chip is in a state to accept the first command; When the second bank is selected, the arbiter determines that the first command is a command to be executed if the second nonvolatile memory chip is in a state to accept the first command.

3. The memory system of claim 2.

4. When there is a first command that is to be executed with priority over the second command, If the first command is stored in the first command queue, the first controller causes the first non-volatile memory chip to execute the first command; If the first command is stored in the second command queue, the first controller causes the second nonvolatile memory chip to execute the first command.

4. The memory system of claim 3.

5. If the first command to be executed with priority over the second command does not exist, the arbiter determines whether the second command exists in the first command queue or the second command queue; If the second command is present, the arbiter determines whether the second command is executable; If the second command is executable, the arbiter determines whether there is a second command to execute.

4. The memory system of claim 3.

6. If there is a second command to be executed, If the second command is stored in the first command queue, the first controller causes the first nonvolatile memory chip to execute the second command; If the second command is stored in the second command queue, the first controller causes the second nonvolatile memory chip to execute the second command.

6. The memory system of claim 5.

7. If the second command is present, the arbiter selects one of the first bank and the second bank; When the first bank is selected, the arbiter determines that the second command is a command to be executed if the first nonvolatile memory chip is in a state to accept the second command; When the second bank is selected, the arbiter determines that the second command is a command to be executed if the second nonvolatile memory chip is in a state to accept the second command.

7. The memory system of claim 6.

8. the first command includes a read sense command, a program command, or an erase command; the second command includes a data out command, a data in command, or a status read command; 8. The memory system according to claim 1.

9. 9. The memory system according to claim 1, wherein the first nonvolatile memory chip and the second nonvolatile memory chip belonging to the first bank are connected to a single I / O signal.

10. A command determination method for determining a command to be executed by a memory system including a first channel, a second channel, a first bank, a second bank, a first command queue, and a second command queue, the method comprising: the first bank includes a first non-volatile memory chip and a third non-volatile memory chip; the second bank includes a second non-volatile memory chip and a fourth non-volatile memory chip; the first non-volatile memory chip and the second non-volatile memory chip are connected to the first channel; the third nonvolatile memory chip and the fourth nonvolatile memory chip are connected to the second channel; the first command queue stores commands to be sent to the first nonvolatile memory chip; the second command queue stores commands to be sent to the second nonvolatile memory chip; the commands include a first command and a second command; a period during which the nonvolatile memory chip that executed the first command is in a state of not accepting a command is longer than a period during which the nonvolatile memory chip that executed the second command is in a state of not accepting a command; determining whether the first command is present in the first command queue or the second command queue; If the first command is executable, determining whether there is a first command that should be executed with priority over the second command; Command determination method.

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