Semiconductor device and display device

Abstract

To upgrade display quality by minimizing malfunction of a circuit.SOLUTION: A drive circuit is composed of plural pulse output circuits each including first to third transistors and first to fourth signal lines. A first clock signal is supplied onto the first signal line, and a pre-stage signal is supplied onto the second signal line. A second clock signal is supplied onto the third signal line, and an output signal is outputted from the fourth signal line. The duty ratios of the first clock signal and second clock signal are different from each other. A period during which the second clock signal changes from low to high after the first clock signal changes from high to low is made longer than a period during which the pre-stage signal changes from low to high.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] Semiconductor device, display device, liquid crystal display device, light-emitting device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a display device, a liquid crystal display device, a light emitting device, or a driving method thereof. electronic equipment having the display device, the liquid crystal display device, or the light-emitting device . [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single-crystal semiconductors are used to form a pixel portion. The technology of configuring drive circuits such as gate drivers on the board is expected to significantly reduce costs and improve reliability. In order to make a significant contribution, active development is underway (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-293299 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to improve display quality by reducing malfunction of a circuit. Another object of one embodiment of the present invention is to reduce distortion or delay of a signal. Another object of one embodiment of the present invention is to suppress deterioration of the characteristics of a transistor. Another object of one embodiment of the present invention is to reduce the channel width of a transistor. An object of one embodiment of the present invention is to reduce the layout area. An object of one embodiment of the present invention is to narrow the frame of a display device. Another object of the present invention is to provide a display device with high resolution. The description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not necessarily solve all of the above problems. [Means for solving the problem]

[0005] One embodiment of the present invention is a semiconductor device including first to third transistors and first to fourth signal lines. a first terminal to a fourth terminal connected to the signal line; a pixel including a liquid crystal element, The terminal is electrically connected to the first signal line, the second terminal is electrically connected to the fourth signal line, and the second The transistor has a gate and a first terminal electrically connected to a third signal line. The first terminal of the transistor is electrically connected to the third signal line, and the gate is electrically connected to the second signal line. The gate of the first transistor, the second terminal of the second transistor, and the second terminal of the third transistor are connected to each other. A method for driving a liquid crystal display device in which terminals are electrically connected to each other, the method comprising: a first clock signal is supplied to the first signal line, and a second clock signal is supplied to the second signal line; The third signal line is supplied with a previous signal, and the fourth signal line is used to output an output signal. The liquid crystal display device has a first clock signal and a second clock signal with different duty ratios.

[0006] In one aspect of the present invention, the first signal is generated from the period until the preceding signal is switched from the L signal to the H signal. After the first clock signal has switched from H to L, the second clock signal Alternatively, the liquid crystal display device may take a longer period of time to switch from the ON state to the H state.

[0007] In one aspect of the present invention, the drive circuit includes a control circuit, a first terminal electrically connected to the fourth signal line, and a second terminal electrically connected to the fourth signal line. a fourth transistor, the second terminal of which is electrically connected to a wiring that supplies a low power supply potential; and the first terminal is connected to the gate of the first transistor, the second terminal of the second transistor, and the third transistor. and a second terminal of the capacitor are electrically connected to a node electrically connected to each other, and the second terminal is connected to a low voltage a fifth transistor electrically connected to a wiring that supplies a source potential, and the control circuit The gate of the first transistor, the second terminal of the second transistor, and the second terminal of the third transistor and the gate of the fourth transistor are electrically connected to each other. The liquid crystal display device may also be configured to control the potential of the gate of the fifth transistor.

[0008] In one embodiment of the present invention, the first to fifth transistors are transistors of the same polarity. The display device may be a liquid crystal display device.

[0009] In one aspect of the present invention, a first clock signal is input to a first terminal of a pulse output circuit in an odd-numbered stage. The second terminal is supplied with a second clock signal, and the first terminal of the pulse output circuit of the even-numbered stage is a liquid crystal display device to which a third clock signal is supplied to the first terminal and a fourth clock signal is supplied to the second terminal; You may do so.

[0010] The switch may take various forms. For example, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific type as long as it can control the current. Examples include transistors (e.g., bipolar transistors, MOS transistors, etc.) ), diodes (e.g., PN diodes, PIN diodes, Schottky diodes) , MIM (Metal Insulator Metal) diode, MIS (Met Al Insulator Semiconductor Diode, Diode Connection These include mechanical switches, transistors, and logic circuits that combine these. One example of this technology is a MEMS (Micro Electro Mechanical Systems) device, such as a Digital Micromirror Device (DMD). There is a switch that uses microelectromechanical system technology. The switch has a mechanically movable electrode, and the movement of the electrode changes the state of conduction and non-conduction. It operates by controlling conduction.

[0011] When a transistor is used as a switch, the transistor is treated as a simple switch. Since the transistor operates as a transistor, the polarity (conductivity type) of the transistor is not particularly limited.

[0012] As a switch, both N-channel and P-channel transistors are used. Alternatively, a CMOS type switch may be used.

[0013] Note that a display element, a display device which is a device having a display element, a light-emitting element, and a light-emitting element A light-emitting device, which is a device for emitting light, can take various forms or have various elements. An example of a display element, a display device, a light-emitting element, or a light-emitting device is an EL (electroluminescence) Luminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements) , LED (white LED, red LED, green LED, blue LED, etc.), transistor (electric current-dependent light-emitting transistors), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices child, grating light valve (GLV), plasma display panel (PDP), Digital micromirror device (DMD), piezoelectric ceramic display, carbon nanotube The contrast, brightness, reflectivity, transmittance, etc. are controlled by electromagnetic effects such as nanotubes. An example of a display device using an EL element is an EL An example of a display device using electron-emitting devices is a field-effect display. Mission Display (FED) or SED type flat panel display (SED: Sur face-conduction Electron-emitter Display) An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal Displays, semi-transmissive LCD displays, reflective LCD displays, direct-view LCD displays Display using electronic ink or electrophoretic elements. An example of a display device is electronic paper.

[0014] An example of a liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be constructed by a pair of electrodes and a liquid crystal layer. The optical modulation effect of the liquid crystal is achieved by applying an electric field (horizontal electric field, vertical electric field or oblique electric field) to the liquid crystal. Specifically, an example of a liquid crystal element is a matic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermo Lyotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PD LC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma address Examples of LCDs include PALC and banana-shaped LCDs. The following are available: TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode ted Nematic mode, IPS (In-Plane-Switching) mode Mode, FFS (Fringe Field Switching) mode, MVA (Mu lti-domain Vertical Alignment) mode, PVA(Pa tterned Vertical Alignment) mode, ASV (Advan ced Super View) mode, ASM (Axially Symmetric aligned micro-cell mode, OCB (Optically Coated compensated birefringence mode, ECB (Electric FLC (Fe rferoelectric Liquid Crystal) mode, AFLC (Anti Ferroelectric Liquid Crystal mode, PDLC (Po lymer Dispersed Liquid Crystal) mode, guest host There are various modes, including the blue phase mode and the blue phase mode. Various liquid crystal elements and driving methods thereof can be used.

[0015] Note that transistors with various structures can be used. The type of transistor used is not limited. An example of the transistor is an amorphous silicon transistor. silicon, polycrystalline silicon, microcrystalline (microcrystalline, nanocrystalline, semi-amorphous Thin film transistors (TF) have non-single crystal semiconductor films, typically silicon. T) can be used.

[0016] Examples of transistors include ZnO, a-InGaZnO, SiGe, and GaA Compound semiconductors such as s, IZO, ITO, SnO, TiO, and AlZnSnO (AZTO) or a transistor having an oxide semiconductor, or a transistor having these compound semiconductors or oxide semiconductors. Thin film transistors can be used. This allows the manufacturing temperature to be lowered. This allows, for example, the manufacture of transistors at room temperature. Forming transistors directly on a substrate with low resistance, such as a plastic substrate or film substrate These compound semiconductors or oxide semiconductors can be used as the transistor chips. It can be used not only for the channel part but also for other purposes. The compound semiconductor or oxide semiconductor is used for wiring, a resistor element, a pixel electrode, or a light-transmitting electrode. These can be formed as films or layers at the same time as the transistors. This allows costs to be reduced.

[0017] An example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at low vacuum, or can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, after forming the film on the entire surface, This method wastes less material and is less costly than the conventional etching method.

[0018] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. This allows transistors to be mounted on a flexible substrate. A semiconductor device using such a substrate can be made resistant to shocks. This can be done.

[0019] Note that transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A transistor or the like can be used.

[0020] An example of a transistor is a multi-gate transistor having two or more gate electrodes. When a multi-gate structure is used, the channel regions are connected in series. Therefore, a structure in which multiple transistors are connected in series is formed.

[0021] An example of a transistor is a transistor having a structure in which gate electrodes are arranged above and below a channel. A transistor with a structure in which gate electrodes are arranged above and below the channel can be applied. By using this structure, the circuit configuration becomes like a plurality of transistors connected in parallel.

[0022] An example of a transistor is a transistor in which a gate electrode is disposed above a channel region. a structure in which the gate electrode is located below the channel region, a forward staggered structure, an inverted staggered structure a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or A transistor having a structure in which channel regions are connected in series can be used.

[0023] An example of a transistor is a transistor having a source electrode or a gate electrode in the channel region (or a part thereof). A transistor having an overlapping drain electrode structure can be used.

[0024] As an example of the transistor, a transistor having a structure provided with an LDD region can be used. do.

[0025] Note that a transistor can be formed using various substrates. The substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate (e.g., a single crystal substrate or silicon substrate), SOI substrate, glass substrate, quartz substrate, plastic substrate, metal Substrate, stainless steel substrate, substrate with stainless steel foil, tungsten substrate, tungsten foil substrate, flexible substrate, laminated film, fibrous Examples of glass substrates include paper or substrate films containing barium phosphate. Examples include borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of the flexible substrate include polyethylene terephthalate (PET) and polyethylene naphthalate (PENA). Plastics such as polyethersulfone (PEN) and polyethersulfone (PES) or aluminum Examples of laminating films include flexible synthetic resins such as polypropylene. Examples of suitable materials include polypropylene, polyester, vinyl, polyvinyl fluoride, and polyvinyl chloride. Examples of the substrate film include polyester, polyamide, polyimide, and inorganic vapor deposition film. These include books, magazines, or papers.

[0026] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. As the substrate, in addition to the substrate on which the above-mentioned transistor can be formed, a paper substrate, a cellophane substrate, etc. substrate, stone substrate, wood substrate, fabric substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, Polyurethane, polyester) or recycled fiber (acetate, cupra, rayon, recycled Examples include raw polyester), leather substrates, or rubber substrates.

[0027] All circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate such as a silicon substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. This reduces the cost by reducing the number of components, or reduces the number of connections to circuit components. This can improve reliability.

[0028] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function is formed on a certain substrate. Another part of the circuitry required to achieve a given function is formed on a different substrate. For example, some of the circuits required to realize a specific function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. (or SOI substrate). The single crystal substrate (also called IC chip) on which another part of the circuit required for the semiconductor device is formed is called COG ( By using the IC chip on glass, the IC is connected to the glass substrate. It is possible to place the chip on the board. Alternatively, the IC chip can be mounted on the board using TAB (Tape Auto) technology. omated Bonding), COF(Chip On Film), SMT(Su Surface Mount Technology, or a printed circuit board, etc. It is possible to connect it to the base board.

[0029] A transistor is defined as a transistor having at least three terminals including a gate, a drain, and a source. The element has a channel region between a drain region and a source region. A current can flow through the drain region, the channel region, and the source region. Here, the source and drain vary depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source or the drain. The region that functions as a source and the region that functions as a drain are called the source and the drain, respectively. In this case, for example, one of the source and the drain may be connected to the first terminal, The other of the source and drain is referred to as the second terminal, the second electrode, or the first region. It may be referred to as two areas.

[0030] The transistor has at least three terminals including a base, an emitter, and a collector. In this case, the element may also have one of an emitter and a collector. The first terminal, the first electrode, or the first region is referred to as the emitter or the collector. It may be written as the second terminal, the second electrode, or the second region. When a polar transistor is used, the term gate can be interchangeably referred to as base. It is Noh.

[0031] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) Therefore, the predetermined connection relationship For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0032] An example of an electrical connection between A and B is The elements that function as One or more diodes (e.g., diodes) can be connected between A and B.

[0033] An example of a functional connection between A and B is a connection that allows the functional connection between A and B. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between A and B. For example, even if another circuit is inserted between A and B, the signal output from A is transmitted to B, A and B are said to be functionally connected.

[0034] When it is explicitly stated that A and B are electrically connected, it means that A and B are electrically connected. When A and B are electrically connected (i.e., when another element or circuit is placed between A and B) A and B are functionally connected (i.e., there is no connection between A and B) When A and B are connected directly, the two are functionally connected via another circuit. (i.e., when A and B are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply The same applies if the document is explicitly stated as being connected to the

[0035] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed on A in direct contact with it. This also includes cases where A and B are not in agreement, i.e., where another object is present between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0036] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When described, it means that layer B is formed directly on layer A, and layer A is formed on layer B. Another layer (such as layer C or layer D) is formed directly on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be formed as follows: It may be a single layer or multiple layers.

[0037] Furthermore, the same applies to cases where it is explicitly stated that B is formed above A. It is not limited to B being directly on A, and there is another object between A and B. For example, if layer B is formed above layer A, In this case, there are two cases: when layer B is formed directly on top of layer A, and when layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be used as single layers. It may be a multi-layer structure.

[0038] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that "B" is formed, this also includes the case where B is formed diagonally above. .

[0039] The same applies to the case where B is below A, or B is below A.

[0040] In addition, it is preferable that anything explicitly stated as singular be in the singular. However, it is not limited to this, and plurals are also possible. It is preferable that the items described in the table be plural. However, this is not limited to this. It is also possible for the term to be singular.

[0041] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0042] The diagrams are merely diagrams showing ideal examples, and are not limited to the shapes or values ​​shown in the diagrams. For example, variations in shape due to manufacturing technology, variations in shape due to errors, and noise Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Alternatively, it is possible to include variations in current.

[0043] Note that technical terms may be used to describe specific embodiments or examples. However, one aspect of the present invention is not to be construed as being limited by technical terms. .

[0044] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It can be used as a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. The terms defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0045] It should be noted that the terms first, second, third, etc., refer to various elements, members, regions, layers, and sections as distinct from one another. Therefore, the words "first," "second," "third," etc. are used to distinguish between elements, parts, etc. It is not intended to limit the number of materials, regions, layers, areas, etc. It is possible to replace "second" or "third" etc.

[0046] In addition, "up," "upward," "down," "downward," "sideways," "right," "left," Spatial arrangement such as "diagonally," "in the back," "in front," "inside," "outside," or "inside" The location phrases should be used to easily illustrate the relationship of one element or feature to another. However, it is not limited to this and is often used to indicate the spatial arrangement of these. The phrase "above A" can include other directions in addition to the direction shown in the drawing. For example, When explicitly indicated as B, B is not limited to being above A. can be flipped or rotated 180 degrees, so it can include B being below A. In this way, the word "upon" can be used to refer to the direction of "up" as well as the direction of "down." The devices shown may include, but are not limited to, various orientations. Since it is possible to rotate the word "on" in addition to the directions "on" and "under" "Sideways", "Right", "Left", "Diagonally", "Back", "Front", "Inside", "Outside" It is possible to include other directions such as "into" or "into"; It is possible to interpret this as: [Effects of the Invention]

[0047] According to one embodiment of the present invention, display quality can be improved by reducing malfunction of a circuit. Alternatively, one aspect of the present invention can reduce distortion or delay of a signal. According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. According to one embodiment of the present invention, the channel width of a transistor can be reduced. In addition, one embodiment of the present invention is a display device. Alternatively, one embodiment of the present invention is to provide a display device with high resolution. Alternatively, one embodiment of the present invention can reduce costs. [Brief explanation of the drawings]

[0048] [Figure 1]FIG. 1 is a circuit diagram of a semiconductor device. [Figure 2] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 3] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 4] 1 is a timing chart for explaining the operation of the semiconductor device. [Figure 5] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 6] 1 is a timing chart for explaining the operation of the semiconductor device. [Figure 7] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 8] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 9] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 10] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 11] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 12] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 13] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 14] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 15] 1A and 1B are schematic diagrams for explaining the operation of a semiconductor device; [Figure 16] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 17] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 18] FIG. 1 is a block diagram of a display device. [Figure 19] FIG. 1 is a block diagram of a display device. [Figure 20] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 21] FIG. 2 is a circuit diagram of a protection circuit. [Figure 22] FIG. 2 is a circuit diagram of a protection circuit. [Figure 23] FIG. 1 is a cross-sectional view of a transistor. [Figure 24] 1A and 1B are a top view and a cross-sectional view of a display device; [Figure 25] 1A to 1C are cross-sectional views illustrating a manufacturing process of a transistor. [Figure 26] FIG. 1 is a diagram illustrating an electronic device. [Figure 27] FIG. 1 is a diagram illustrating an electronic device. [Figure 28] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart for explaining the operation of the semiconductor device; [Figure 29] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 30] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 31] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 32] FIG. 1 is a circuit diagram of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0049] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention may be embodied in many different ways without departing from the spirit and scope thereof. It will be readily apparent to those skilled in the art that various modifications may be made to the modes and details of the present invention. It should not be construed as being limited to the description of the form. Therefore, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the same parts are denoted by the same reference numerals in different drawings. A detailed description of some parts or parts having similar functions will be omitted.

[0050] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of You can do things like:

[0051] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0052] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, , and many more diagrams can be constructed.

[0053] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. For example, it is used in a shift register, a gate driver, a source driver, or a display device. Note that the semiconductor device of this embodiment mode can be referred to as a driver circuit. be.

[0054] First, a semiconductor device functioning as a shift register of a driver circuit will be described with reference to FIGS. 1 to 6. The semiconductor device 100 includes a first pulse output circuit 101_1 to an N-th pulse output circuit 101_2. The semiconductor device shown in FIG. 1A has a plurality of output circuits 101_N (N≧2). The first pulse output circuit 101_1 to the Nth pulse output circuit 101_N of the semiconductor device 100 In each stage, a first clock signal CK1 is transmitted from a first wiring 102, and a second clock signal CK2 is transmitted from a second wiring 103. The third clock signal CK3 is transmitted through the third wiring 104, the second clock signal CK2 is transmitted through the fourth wiring A fourth clock signal CK4 is input from 105. Start pulse SP or output signal from the previous pulse output circuit (previous signal OUT_N- 1) is input. Also, the pulse output circuit of each stage outputs a gate line or a data line The pulse output circuit outputs an output signal OUT_N to be output to the display unit, etc. A dummy stage may be provided to output a signal that does not contribute to the display of the gate driver. In a configuration used in a shift register to output pulses sequentially to n gate lines, n≦N The number of outputs of the output signal may be determined depending on the load to which the output signal is to be output. A configuration in which multiple output signals are output according to the load may be used. , signal distortion or delay can be reduced.

[0055] The third clock signal CK3 is, for example, 180° from the first clock signal CK1. The first clock signal CK1 is a signal with a duty cycle of 50%. The third clock signal CK3 is an inverted clock signal of the first clock signal CK1. The fourth clock signal CK4 may be, for example, a clock signal equal to the second clock signal CK2. It is a signal that is 180° out of phase with

[0056] The first clock signal CK1, the third clock signal CK3, and the second clock The signal CK2 and the fourth clock signal CK4 are connected to the pulse output circuits of the odd-numbered stages and the pulse output circuits of the even-numbered stages. In the output circuit, the input signals are swapped. Specifically, as shown in Figure 1(B), In the pulse output circuit 101_1 of the stage (here, as an example, the first stage), a first terminal is connected to the first A clock signal CK1 is input to the first terminal, a second clock signal CK2 is input to the second terminal, and A start pulse SP (previous stage signal OUT_N-1 for odd-numbered stages from the third stage onwards) is input to terminal 3. The fourth terminal outputs the output signal OUT_N. In the pulse output circuit 101_2 of the even stage (here, as an example, the second stage), The third clock signal CK3 is input to the first terminal, and the fourth clock signal CK4 is input to the second terminal. , the third terminal is the previous stage signal OUT_1 (for even-numbered stages from the fourth stage onwards, the previous stage signal OUT_N-1) is input, and the output signal OUT_2 is output from the fourth terminal. K1 and the third clock signal CK3, and the second clock signal CK2 and the fourth clock signal CK4. The clock signal CK4 switches between a high signal (high power supply potential level, also called the high level) and a low signal at regular intervals. (also called L level, low power supply potential level) is a signal that repeats.

[0057] Next, an example of the circuit configuration of the pulse output circuit will be described with reference to FIG. As an example, the configuration of an odd-numbered pulse output circuit will be described. As mentioned above, the difference between the pulse output circuits of the even-numbered and even-numbered stages is the first clock signal CK the first and third clock signals CK3, or the second clock signal CK2 and the fourth clock The point is where the input signals are switched, such as signal CK4.

[0058] The pulse output circuit includes a first transistor 111 to a fifth transistor 115 and a control circuit. 131. In FIG. 1D, the signals input to the first to fourth terminals are In addition to the signal, a higher power supply potential VDD is applied from the first power supply line 141 and a lower power supply potential VDD is applied from the second power supply line 142. In FIG. 1(D), the first terminal is connected to the first The wiring for inputting the clock signal CK1 is the first signal line 151, and the second terminal is the second clock signal The wiring for inputting CK2 is the second signal line 152, and the third terminal is the input of the previous stage signal OUT_N-1. The wiring for outputting the output signal OUT_N to the fourth terminal is referred to as the third signal line 153, and the wiring for outputting the output signal OUT_N to the fourth terminal is referred to as the fourth signal line For the sake of explanation, as shown in FIG. 1(D), the gate of the first transistor 111 is a second terminal of the second transistor 112; a second terminal of the third transistor 113; The connection point of the first terminal of the fifth transistor 115 is referred to as node A. The connection point of the gate of the fourth transistor 114 and the gate of the fifth transistor 115 is node B. (nodeB).

[0059] The first transistor 111 has a first terminal connected to the first signal line 151 and a second terminal connected to the fourth transistor 112. The first terminal of the transistor 114 is connected to the fourth signal line 154, and the gate is connected to the node A. The second transistor 112 has a first terminal connected to the gate of the second transistor 112. , a first terminal of the third transistor 113 and a third signal line 153 are connected, and a second terminal of the third transistor 113 is connected to the first terminal of the third transistor 113 and a third signal line 153. The gate is connected to the first terminal of the second transistor 112 and the gate is connected to the first terminal of the third transistor 11 3 and a third signal line 153. The third transistor 113 is The first terminal is the gate of the second transistor 112, the first terminal of the second transistor 112, and The second terminal is connected to the third signal line 153, the second terminal is connected to the node A, and the gate is connected to the second signal line 15 The fourth transistor 114 has a first terminal connected to the first transistor 111. and a fourth signal line 154, and the second terminal is connected to the second power supply line 142. , and the gate is connected to node B. The fifth transistor 115 has a first terminal connected to node A, a second terminal is connected to the second power supply line 142, and a gate is connected to node B. The control circuit 131 has a function of controlling the level of the potential at the node B in accordance with the potential at the node A. The circuit is connected to node A, the first power supply line 141, the second power supply line 142, and node B. It continues.

[0060] Between the gate and the second terminal of the first transistor 111, A separate capacitance element is provided to perform bootstrap operation by floating the gate. The boot load may be generated by the parasitic capacitance between the gate and the second terminal of the first transistor 111. If strapping can be performed, it can also be reduced.

[0061] Note that voltage often refers to the potential difference with respect to the ground potential. , the potential difference can be expressed by substituting

[0062] Note that the first to fifth transistors 111 to 115 have the same polarity. is preferable, and is often an N-channel type. However, it is not limited to this, and the first transistor The fifth transistor 111 to the fifth transistor 115 can be P-channel.

[0063] Before describing the circuit operation of this embodiment in detail, the above-described The operation of the circuit configuration described in Patent Document 1 will be explained, and the advantages of the configuration described in this embodiment will be explained. The comparative example described in FIGS. 28 to 32 is similar to that shown in FIGS. (D) to (E), and all of the configurations disclosed in this specification. It should be noted that this is not a

[0064] FIG. 28(A) shows a transistor constituting the shift register described in FIGS. 5 and 6 of Patent Document 1. The circuit configuration described in Patent Document 1 is shown in FIG. 28(B) ) based on the timing chart, the gate driver output signal OUT_N The fall time can be shortened. Next, in FIG. 28(B), the first period T1 , the second period T2, the third period T3, the fourth period T4, and the fifth period T5. The on / off state of the transistor and the potential of each wiring are explained below. , simply called "H" (signal based on high power supply potential, H signal), "L" (signal based on low power supply potential) The explanation will be given as a clock signal CK and an output L signal. The waveform of the signal OUT_N is specifically shown in the same manner as in FIG. 8 of Patent Document 1. The descriptions in Figures 28(A) to 28(C) are the same as those in Figures 6 to 8 of Patent Document 1. Therefore, for detailed explanation, Patent Document 1 is referred to. The transistors M3, M5, and M8 in the area enclosed by 80 are connected to the potential of node A. This corresponds to a control circuit having the function of controlling the potential of node B accordingly. This control circuit controls the conduction or non-conduction of the transistor M4. This circuit has the same function as the control circuit 131 described in FIG. 1 of the first embodiment.

[0065] In the first period T1, the first half of the operation is shown as period T1-1 in FIG. 29(A). The "first half" here refers to the period in which a predetermined potential is supplied to the first period T1. First, the previous signal OUT_N-1 is a H signal, and the clock signal CK is a L signal. The signal OUT_N+2 (hereinafter referred to as the reset signal) for resetting the output terminals OUT_N and OUT_N+2 becomes an L signal. As a result, node A is at the voltage equal to the low power supply potential VSS plus the threshold voltage (VSS+V th), and the transistors M1 and M3 become conductive as shown in the figure (transistors without As shown in FIG. 29(A), the other transistors M5, M7, and M8 are conductive. However, transistors M2, M4, and M6 are non-conductive (transistors marked with an X in the figure). As a result, a current flows as indicated by the dotted arrow in FIG. 29(A). Next, the behavior of the second half of the first period T1 The period T1-2 is shown in FIG. 29(B). The "second half" here refers to the first period. A predetermined potential is applied during T1, and the device goes through a transient state before reaching a steady state. As shown in Figure 29(A), a current flows, and the potential of node A rises to the high power supply voltage. The potential rises to a value (VDD-Vth) obtained by subtracting the threshold voltage from the potential VDD. As shown in (B), the transistor M7 becomes non-conductive. At this time, the node A becomes floating. Then, the potential of each wiring in the first period T1 is determined as shown in FIG. 28(B).

[0066] In FIG. 28(B), as shown in FIG. 28(C), another signal that becomes the previous stage signal OUT_N-1 is The waveform of the output signal OUT_N of the stage is delayed compared to the rising edge of the clock signal CK. The delay of the previous stage signal OUT_N-1 is the rise of the potential of node A, the rise of the potential of node B, This is reflected in the drop in the potential of the wiring connected to the rear stage of the transistor M1. This is due to the increased load of the transistors. Therefore, the gate capacitance of the transistor M1 increases, and the transistor M1 is in a conducting state or When the transistor M1 switches to the non-conducting state, the charge on the gate of the transistor M1 is charged or discharged. This will result in a longer time taken to generate the signal, which will appear as a delay in the rise or fall of the signal. (Dash-two-dot line 281 in FIG. 28(B)). A circuit malfunction during the first period T1 due to a delay in the fall is unlikely to occur.

[0067] Next, in the second period T2, the clock signal CK becomes an H signal, and the previous stage signal OUT_N- 1, and the reset signal OUT_N+2 becomes an L signal. As a result, The potential rises, and the potential of node A, which is floating due to the bootstrap operation, rises. Current flows as shown by the dotted arrow in Figure 30(A), and the output signal OUT_N outputs an H signal. This will be the case.

[0068] Next, in the third period T3, the clock signal CK, the previous stage signal OUT_N-1, and the reset At this time, the potential of the node A is Because the value is higher than (VDD+Vth) due to the bootstrap operation, The transistor M1 remains in a conducting state, and the output signal OUT_N, which was at a high level, is output. The output signal OUT _N decreases to the L level. Then, due to the capacitive coupling caused by the parasitic capacitance of transistor M1, As a result, the potential of the node A decreases to approximately (VDD-Vth). T_N becomes L level. In the third period T3, the potential of node A is maintained at a high value. During the third period T3, the transistor M1 is kept in a conducting state. By making the transistor M1 conductive, the clock signal CK at L level is input to the The channel width of the transistor M1 can be Since it is used to drive the gate line, the channel width is larger than that of other transistors, so This allows a current of 100 volts to flow, shortening the fall time of the output signal OUT_N. .

[0069] Next, in the fourth period T4, first, each of the periods immediately after the transition from the third period T3 to the fourth period T4 The conductive and non-conductive states of the wiring and transistors are explained as the period T4-1 in FIG. During the period T4-1, the clock signal CK is an H signal, and the previous signal OUT_N-1 is an L signal. At this time, the reset signal OUT_N+2 becomes an H signal, but the preceding signal OU As with T_N-1, a delay in the rising or falling edge of the signal appears (Figure 28(B) Therefore, as shown in FIG. 28(C), the reset signal OUT_N The output signal OUT_N of another stage, which becomes +2, is delayed compared to the rising edge of the clock signal CK. Therefore, the reset signal OUT_N+2 is an L signal for a short period of time T4-1, and the clock As a result, the signal acts as an H signal. A) Current flows as shown by the dotted arrow, and the potential of the output signal OUT_N can be maintained at the L level. Instead, it appears as noise as shown by the two-dot chain line 283 in FIG. After T4-1, as shown in FIG. 31(B), during the period T4-2, the reset signal OUT_N+ 2 becomes an H signal, the transistors M2, M4, and M6 are turned on, and As shown by the dotted arrow in (A), current flows and the charge at node A is discharged, resulting in the output signal OUT_ The potential of N is set to L level.

[0070] The next fifth period T5 will be described with reference to FIG. 32. In the fifth period T5, the clock signal C K becomes an H signal or an L signal, and the previous stage signal OUT_N-1 and the reset signal OUT_N +2 becomes an L signal. At this time, the charge at node A is discharged, so transistor M3 becomes non-conductive, and the transistors M2 and M4 become conductive. The current flows as indicated by the arrow, and the potential of the output signal OUT_N is maintained at the L level.

[0071] As described above, in the conventional technique (Patent Document 1), during the period T4-1, the transistor M While 1 is on, the clock signal CK may go high, which may cause unintended The output signal OUT_N may be supplied to the gate line, resulting in a display defect. It can also be the cause of

[0072] Next, a basic circuit that can be used in the semiconductor device of this embodiment will be described with reference to FIG. Advantages of the present invention compared with the conventional circuits shown in FIGS. 28 to 32 are described in detail. The configuration disclosed in this embodiment shortens the fall time of the output signal OUT_N. This makes it possible to provide a gate driver that prevents a rise in the potential of the output signal OUT_N. Cut.

[0073] Next, the circuit of FIG. 2(A) is a circuit diagram of the first transistor among the wiring and transistors described in FIG. The first transistor 111, the second transistor 112, and the third transistor 113 are The figure focuses on the first signal line 151 to the fourth signal line 154. The connections between the terminals of each transistor in the circuit of FIG. 2(A) are the same as those in FIG. 1(D). A detailed description will be omitted. In order to specifically explain the operation of the circuit shown in Figure 2(A), In the timing chart, there are a first period T1, a second period T2, a third period T3, a fourth period T4, and a In the following description, the first transistor 111 to the third transistor 112 will be described. The transistor 113 is an N-channel transistor, and the gate-source voltage (V When the gate voltage (gs) exceeds the threshold voltage (Vth), the transistor is in a conductive state. In the timing chart shown in B), the first clock signal CK1, the third clock signal C K3, the second clock signal CK2, the fourth clock signal CK4, the previous stage signal OUT_N-1 , node A, and the waveform of the output signal OUT_N. The high and low power supply potential levels of each signal, except for node A, are VDD and This explanation will be given assuming that the two are VSS.

[0074] The first clock signal CK1, the third clock signal CK3, and the second clock signal C As shown in FIG. 2B, the fourth clock signal CK2 and the fourth clock signal CK4 have different duty ratios. For example, as shown in FIG. 2B, the first clock signal CK1 and The third clock signal CK3 is a clock signal with a duty ratio of 50%, and the second clock signal CK2 and the fourth clock signal CK4 are clock signals with a duty ratio of less than 50%. That is why.

[0075] In the first period T1, the first half of the operation is shown as period T1-1 in FIG. The term "first half" used here refers to the period of time during which a predetermined potential is supplied to each signal line during the first period T1. The period T1-1 is the period before the second clock signal CK2 becomes an H signal. The preceding signal OUT_N-1 is an H signal, the first clock signal CK1 is an L signal, and the second clock As a result, the node A is set to the low power supply potential VSS by the threshold voltage VSS. The voltage VSS is equal to the sum of the voltage VSS and Vth of the first transistor 111. , the second transistor 112 is conductive and the third transistor 113 is non-conductive. Current flows as shown by the dotted arrow in Figure 3(A). Then, the value of node A becomes (VSS+Vth When the voltage rises from (VDD-Vth) to (VDD-Vth), the first transistor 111 becomes non-conductive. Next, the period T1-2 is shown in FIG. 3(B) as the operation in the latter half of the first period T1. Here, the "second half" refers to the predetermined potentials supplied to the signal lines during the first period T1, The state during which the second clock signal CK2 is a H signal, or a H signal followed by a L signal. During the period T1-2, the preceding signal OUT_N-1 is an H signal, and the first clock signal CK 1 becomes an L signal, and the second clock signal CK2 becomes an H signal (later an L signal). Then, node A The value of does not change from (VDD-Vth), and as shown in the figure, the first transistor 111 The first transistor 112 is turned on, the second transistor 112 is turned off, and the third transistor 113 is turned on or off. becomes non-conductive, and current flows as shown by the dotted arrow in Figure 3(B).

[0076] An example of the periods T1-1 and T1-2 in the first period T1 is shown in FIG. As shown in FIG. 4, during the first period T1, the second clock signal CK2 The period from the L signal to the H signal is defined as period T1-1, and the period thereafter is defined as period T In the example shown in FIG. 2B, the period T1-2 is represented by an H signal and an L signal. However, it may be configured to hold the H signal. As shown in the figure, 1-1 is held low until the previous signal OUT_N-1 switches from an L signal to an H signal. It is desirable to set this period longer than the period t1 in the above.

[0077] In FIG. 2B, as in FIG. 28B, the previous stage signal OUT_N-1 is output from another stage. The waveform of the output signal OUT_N is delayed compared to the rising edge of the first clock signal CK1. The explanation for the delay of the waveform is the same as in FIG. 28(B).

[0078] Next, in the second period T2, the first clock signal CK1 becomes an H signal, and the previous stage signal OU T_N-1 and the second clock signal CK2 become L signals. As a result, the output signal OUT The potential of _N rises, and the potential of node A, which is floating due to the bootstrap operation, rises. The current flows as shown by the dotted arrow in Figure 3(C), and the output signal OUT_N outputs a high signal. This will be done.

[0079] Next, regarding the third period T3, the first half of the operation is shown in FIG. 5(A) as period T3-1. The "first half" here refers to the period during which the signals are supplied to each signal line during the third period T3. This refers to the period before the second clock signal CK2 becomes an H signal during the constant potential. At T3-1, the first clock signal CK1, the previous stage signal OUT_N-1, and the second clock signal CK2 are input. At this time, the potential of the node A is at the same level as the bootstrap voltage in the second period T2. Because the trapping action makes the value higher than (VDD+Vth), the first transistor The output signal OUT_N, which was at H level, is output. The output signal OUT_N is generated by the current flowing from the terminal connected to the Then, the capacitance of the parasitic capacitance of the first transistor 111 decreases. As a result, the potential of node A decreases to approximately (VDD-Vth). OUT_N becomes L level. In the period T3-1 of the third period T3, the potential of the node A is set to high. By keeping the voltage Vcc at a low value, the first transistor 111 remains in a conducting state. By making the first transistor 111 conductive during the period T3-1 of the period T3, L The first clock signal CK1 at the level is outputted to the output signal OU via the first transistor 111. The channel width of the first transistor 111 can be set to Since it is used to drive the transistor, it has a larger channel width than other transistors, so it can carry a large amount of current. This allows the fall time of the output signal OUT_N to be shortened. The operation in the latter half of the third period T3 is shown in FIG. 5B as a period T3-2. The "second half" refers to the period from the second clock to the third clock, during which the predetermined potential is supplied to each signal line in the third period T3. This refers to the state of the period when the clock signal CK2 is a H signal, or a L signal after a H signal. At T3-2, the previous stage signal OUT_N-1 is an L signal, the first clock signal CK1 is an L signal, The second clock signal CK2 becomes an H signal (later an L signal). As a result, a current flows as shown by the arrows, and the second transistor 112 is non-conductive and the third transistor The transistor 113 becomes conductive, causing the potential at node A to go low.

[0080] An example of the period T3-1 and the period T3-2 in the third period T3 is shown in FIG. As shown in FIG. 6, during the third period T3, the second clock signal CK2 The period from the L signal to the H signal is defined as period T3-1, and the period thereafter is defined as period T In the example shown in FIG. 2B, the period T3-2 is represented by the H signal and the L signal. However, it may be a signal that holds the H signal (CK 2-1). The H signal in the period T3-2 is maintained as an H signal after the third period T3. The signal may be such a signal (CK2-2 in FIG. 6). Similarly, during the third period T3, the output signal OUT_N+1 (not shown) changes from an L signal to an H signal. It is desirable to set this period longer than the period until the output signal OUT The first clock signal CK1 is generated during the period from when the first clock signal CK1 changes from an L signal to an H signal. After the signal changes from H to L, the second clock signal CK2 changes from L to H. It is desirable to set the period until the switching (period T3-1 in FIG. 6) long.

[0081] Next, in the fourth period T4, the second clock signal CK2 first becomes an L signal. The conductive and non-conductive states of each wiring and transistor during this period are shown in Figure 7( A) will be described as a period T4-1. In the period T4-1, the preceding signal OUT_N-1 is an L signal. The first clock signal CK1 alternates between H and L signals. At this time, the potential of the node A is at the potential of the L signal due to the operation in the third period T3. Therefore, the first transistor 111 remains in a non-conductive state. The signal _N becomes L level. The operation of the second half of the fourth period T4 is shown in FIG. 7B during the period T4-2. The "second half" here refers to the period from when the second clock signal CK2 goes high in the fourth period T4 to when the second clock signal CK2 goes high in the fourth period T5. In the period T4-2, the previous signal OUT_N-1 is an L signal, In the period 4-2, the first clock signal CK1 becomes an L signal. Since the signal 2 is H, the third transistor 113 is turned on, and the first transistor The first transistor 111 and the second transistor 112 are in a non-conductive state. ) and the current flows as shown by the dotted arrow in the figure. The third transistor 113 becomes conductive, causing the potential of the node A to be at the L level.

[0082] As described above, by using the configuration of this embodiment shown in FIG. 1, During the period T3-1 of FIG. 3, the second clock signal CK2 is set to the L level and then to the H level. By this, the first clock signal CK1 at L level is output through the first transistor 111. This allows the fall time of the output signal OUT_N to be shortened. In addition, during the period T3-2 of the third period T3, the second clock signal CK2 is set to the L level. By setting the first clock signal CK1 to H level after the first clock signal CK2 has reached H level, the first clock signal CK1 is output before the first clock signal CK2 reaches H level again. Since the first transistor 111 can be made non-conductive, the first clock Therefore, the clock signal CK1 can be prevented from being output via the first transistor 111. Therefore, the fall time of the output signal OUT_N is shortened while the fall time of the output signal OUT_ It is possible to prevent the potential of N from rising.

[0083] Note that a configuration different from the configuration of the odd-numbered stage pulse output circuit shown in FIG. 2(A) is shown in FIG. 8(A). The difference between the configuration shown in FIG. 8(A) and the configuration shown in FIG. 2(A) is that the third transistor A first terminal of the capacitor 113 is connected to a second power supply line 142 to which a low power supply potential VSS is supplied. Another configuration is shown in FIG. 8(B). The configuration shown in FIG. 8(B) is the same as that shown in FIG. ) is different from the configuration shown in FIG. 1 in that the first terminal of the third transistor 113 is connected to the first clock signal The difference is that the signal CK1 is connected to the first signal line 151 to which the signal CK1 is supplied. The configuration shown in FIG. 8(C) differs from the configuration shown in FIG. 2(A) in that the third The first terminal of the transistor 113 is connected to the signal line 15 through which the fourth clock signal CK4 is supplied. 8(A) to 8(C) are connected to the fifth signal line 5. By doing so, the signal input to the gate of the third transistor 113 is This can prevent the signal from propagating to the previous stage signal OUT_N-1 input to 53. For example, in FIG. 2A, there is a line between the gate of the third transistor 113 and the third signal line 153. , there is a parasitic capacitance. The parasitic capacitance causes the second clock signal CK2 to The configurations of FIGS. 8(A) to 8(C) are such that the parasitic capacitance In addition, in the configurations of Fig. 8(B) and Fig. 8(C), the third The first terminal or the second terminal of the transistor 113 is connected to the first clock signal CK1 or the fourth clock signal CK2. Since the clock signal CK4 is input, the current when the third transistor 113 is turned on is Therefore, a reverse bias voltage in the opposite direction to the voltage applied to the third transistor 1 can be applied. 13 is in a conductive state, electrons are trapped, and this reduces the deterioration of the transistor. It is possible.

[0084] It should be noted that the configuration of the pulse output circuit of odd stages shown in FIG. 2(A) and FIG. 8(A) to (C) may be different. Regarding the configuration, specifically, the configuration in which the third transistor 113 is replaced with a diode element The configuration shown in FIG. 9(A) differs from the configuration shown in FIG. 2(A) in that the third A diode element 413 is provided in place of the transistor 113, and the diode element A first terminal of the 413 is connected to the second signal line 152 to which the second clock signal CK2 is supplied. , the second terminal of the diode element 413 is connected to the node A. The difference between the configuration shown in FIG. 9B and the configuration shown in FIG. 2A is as follows: , a diode-connected third transistor 513 instead of the third transistor 113 The first terminal of the third transistor 513 is connected to the second clock signal CK2. The gate and second terminal of the third transistor 513 are connected to the second signal line 152 to which the The point where the child is connected to node A. In the circuit configuration of FIG. 9(B), ), the duty ratio of the second clock signal CK2 is 50% or more. It is preferable that the period of the H level is longer than the period of the L level. In the configuration (B), the wiring that controls the potential of the transistor gate can be reduced. In addition, in the configuration of FIG. 9B, the voltage applied to the transistor 513 is in the opposite direction to the voltage applied to the transistor 513 when the transistor 513 is turned on. Since a reverse bias can be applied, when the transistor 513 is turned on, electrons This can mitigate the deterioration of the transistor due to trapping of ions.

[0085] In the configuration of the odd-numbered pulse output circuit, as shown in FIG. 10(A), A signal line 156 (also called a fifth signal line) connected to the first terminal of the transistor 112 is connected to a high voltage A configuration for supplying a potential VDD, a third clock signal CK3, or a second clock signal CK2 The configuration shown in FIG. 10(A) differs from the configuration shown in FIG. 2(A) in that the second transistor The first terminal of the transistor 112 is connected to a high power supply potential VDD, a third clock signal CK3, or a third clock signal CK4. The second clock signal CK2 is connected to a signal line 156. In the configuration of the odd-numbered pulse output circuit, as shown in FIG. 10(B), The third clock is input to a signal line 157 (also called a sixth signal line) connected to the gate of the clock generator 112. Alternatively, the first clock signal CK3 or the second clock signal CK2 may be supplied. 2A is different from the structure shown in FIG. 2A in that the gate of the second transistor 112 a signal line 1 for supplying the third clock signal CK3 or the second clock signal CK2 to the 10(A) and 10(B), the transistor A reverse bias voltage opposite to the voltage used to turn on the transistor 112 can be applied. When the transistor 112 is turned on, electrons are trapped and the transistor In the configuration of FIG. 10B, the deterioration of the transistor 112 can be reduced. The third clock signal CK3 or the second clock signal CK2 is switched between a conductive state and a non-conductive state. Therefore, the previous stage signal OUT_N-1 is applied to node A at regular intervals. As a result, the potential of the node A can be kept stable.

[0086] As described above, the semiconductor device of this embodiment can reduce malfunctions caused by input signals. As a result, it is possible to reduce display defects. There is no need to provide a correction circuit to reduce the noise, which improves display quality, reduces the size of the display device, and reduces cost. This can produce secondary effects such as a smaller screen and a narrower frame.

[0087] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0088] (Embodiment 2) In this embodiment, an example of a semiconductor device will be specifically described. The device is the semiconductor device of the first embodiment, specifically the configuration of FIG. 1(D). The semiconductor device of this embodiment includes a flip-flop, a shift register, a gate It can be used in a gate driver, a source driver, a display device, etc. The semiconductor device of the embodiment can be represented as a flip-flop or a driver circuit.

[0089] First, an example of a semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device of FIG. 11(A) is the same as that of FIG. 1(D), and the timing circuit of FIG. 11(B) The chart is the same as that shown in FIG. 2(B), so for a detailed description, refer to the first embodiment. The following text is incorporated by reference.

[0090] In the first period T1, the operation in the first half is shown as period T1-1 in FIG. The "first half" here refers to the period T1 at which a predetermined potential is supplied to each signal line. The period T1-1 is the period before the second clock signal CK2 becomes an H signal. In this case, the previous stage signal OUT_N-1 is an H signal, the first clock signal CK1 is an L signal, and the second clock As a result, the node A is connected to the low power supply potential VSS by a threshold voltage. The voltage difference between the first and second transistors 11 and 12 is VSS+Vth. 1. The second transistor 112 is conductive and the third transistor 113 is non-conductive; and 12A, a current flows through the first transistor 111 as indicated by the dotted arrow in FIG. And when the value of node A rises from (VSS+Vth) to (VDD-Vth), Therefore, the first transistor 111 is turned off. Also, when the potential of the node A is lower than (VDD-Vth ), the control circuit 131 controls the potential of the node B to decrease, The fourth transistor 114 and the fifth transistor 115 are turned off. The operation of the latter half of the period T1 is shown in the period T1-2 in FIG. The second half of the first period T1 is a period in which the predetermined potential is supplied to each signal line during the second clock This is the period when the signal CK2 is an H signal, or an L signal after an H signal. In this case, the previous stage signal OUT_N-1 is an H signal, the first clock signal CK1 is an L signal, and the second clock The clock signal CK2 becomes a high signal (later a low signal). The value of node A is (VDD - Vt h), the first transistor 111 is conductive and the second transistor The fourth transistor 112, the fourth transistor 114, and the fifth transistor 115 are turned off. As a result, the third transistor 113 becomes conductive or non-conductive. The current flows as shown by the arrow.

[0091] Next, in the second period T2, the first clock signal becomes an H signal, and the previous stage signal OUT_N -1 and reset signal OUT_N+2 become L signals. As a result, the output signal OUT_N The potential of node A, which is floating due to the bootstrap operation, rises. , current flows as shown by the dotted arrow in FIG. 13, and the output signal OUT_N outputs an H signal. In addition, since the potential of node A is higher than (VDD-Vth), Similarly to the first period, the control circuit 131 controls the potential of the node B to decrease, and the fourth transistor The fifth transistor 114 and the fifth transistor 115 are in a non-conductive state.

[0092] Next, regarding the third period T3, the operation in the first half is shown in FIG. 14(A) as period T3-1. The "first half" here refers to the period of time during which the signals are supplied to the signal lines during the third period T3. This refers to the state of the predetermined potential during the period before the second clock signal CK2 becomes an H signal. In the period T3-1, the first clock signal CK1, the previous stage signal OUT_N-1, and the second At this time, the potential of the node A becomes the L signal. Because the potential is higher than (VDD+Vth) due to the strap operation, The resistor 111 remains in a conducting state. Since the potential of node B is high, the control circuit 131 lowers the potential of node B as in the previous period. The fourth transistor 114 and the fifth transistor 115 are controlled to be non-conductive. The output signal OUT_N, which was at H level, is output from the terminal shown in Fig. As current flows as shown by the dotted arrow in 14(B), the output signal OUT_N becomes L level. Then, due to the capacitive coupling caused by the parasitic capacitance of the first transistor 111, The potential of node A decreases to approximately (VDD-Vth). During the period T3-1 of the third period T3, the potential of the node A is maintained at a high value. This keeps the first transistor 111 in a conductive state. By making the first transistor 111 conductive during the period T3-1, the first The clock signal CK1 is supplied to the output signal OUT_N via the first transistor 111. The channel width of the first transistor 111 is set to 1 / 2 sq.m. Other transistors (fourth transistor 114, fifth transistor 115) are used for ) is larger than the channel width of the output signal OUT_N, so a large current can flow. Next, as the second half of the third period T3, the period T 3-2 is shown in FIG. 14(B). Note that the "second half" here refers to the third period T3. Of the predetermined potentials supplied to the line, the second clock signal CK2 is an H signal or an H signal. In the period T3-2, the previous signal OUT_N-1 becomes an L signal. The first clock signal CK1 is an L signal, and the second clock signal CK2 is an H signal (later an L signal). Then, current flows as shown by the dotted arrow in Figure 14(B), and the second The third transistor 112 is non-conductive and the third transistor 113 is conductive, so that the potential of the node A is When the potential of the node A becomes L level, the control circuit 131 The potential of the node B is controlled to rise, and the fourth transistor 114 and the fifth transistor The resistor 115 is in a conducting state.

[0093] Next, in the fourth period T4, the second clock signal CK2 first becomes an L signal. The conductive and non-conductive states of each wiring and transistor during this period are shown in FIG. (A) will be described as a period T4-1. During the period T4-1, the previous stage signal OUT_N-1 is L. signal, and the first clock signal CK1 alternates between H and L signals. At this time, the potential of the node A becomes the potential of the L signal due to the operation in the third period T3. Therefore, the first transistor 111 remains in a non-conductive state, and the control circuit 131 The fourth transistor 114 and the fifth transistor 115 remain conductive. As a result, the output signal OUT_N becomes L level. The period T4-2 is shown in FIG. 15(B). Note that the "second half" here refers to the fourth period T4. In the period T4-2, the clock signal CK2 of the previous stage becomes a high level. OUT_N-1 is an L signal, and the first clock signal CK1 is an L signal. Since the second clock signal CK2 is an H signal, the third transistor 113 The first transistor 111 and the second transistor 112 are in a non-conductive state. As a result, a current flows as shown by the dotted arrow in Figure 15(B). , the second transistor 112 is non-conductive, and the third transistor 113 is conductive, and the node A The potential of node A is set to L level. The path 131 controls the potential of the node B to increase, and the fourth transistor 114 and the fifth transistor The transistor 115 is in a conductive state.

[0094] As described above, by using the configuration of this embodiment shown in FIG. 1, During the period T3-1 of FIG. 3, the second clock signal CK2 is set to the L level and then to the H level. By this, the first clock signal CK1 at L level is output through the first transistor 111. This allows the fall time of the output signal OUT_N to be shortened. In addition, during the period 3-2 of the third period T3, the second clock signal CK2 is set to the L level. By setting the first clock signal CK1 to H level after the first clock signal CK2 has been set to H level, the first clock signal CK2 is set to H level before the first clock signal CK2 has been set to H level again. Since the transistor 111 can be made non-conductive, the first clock The signal CK1 can be prevented from being output via the first transistor 111. Therefore, the fall time of the output signal OUT_N can be shortened while maintaining the output signal OUT_N This can prevent the potential of the electrode from rising.

[0095] Next, in this embodiment, a specific circuit configuration of the control circuit 131 shown in FIG. An example will be given to explain this.

[0096] The control circuit 131 shown in FIG. 16A controls the node A and the node B as shown in FIG. , a first power supply line 141 to which a high power supply potential is supplied, and a second power supply line 142 to which a low power supply potential is supplied. , and an n-channel transistor 1601 and a transistor 1602 are connected to The transistor 1601 has a first terminal connected to the first power supply line 141 as a gate. The transistor 1602 has a gate connected to the node A and a second terminal connected to The second terminal of the transistor 1601 is connected to the second power supply line 142. The first terminal of 602 and the node B are connected to each other. In the control circuit 131 having the above configuration, the first power supply line 1 to which the node A, the node B, and the high power supply potential are supplied is connected. 41, connected to a second power supply line 142 to which a low power supply potential is supplied, and Transistor 1601, transistor 1602, transistor 1603, and transistor 1 The transistor 1601 has a first terminal 604 connected to the first power supply line 141. The gate of the transistor 1602 is connected to node A and the transistor The first terminal is connected to the gate of the transistor 1604, and the second terminal is connected to the second power supply line 142. The second terminal of the transistor 1601, the first terminal of the transistor 1602, and the second terminal of the transistor 160 The gates of the transistors 1603 and 1604 are connected to each other. The first terminal of the transistor 1603 is connected to the first power supply line 1. 41. The second terminal of the transistor 1604 is connected to the second power supply line 142. The second terminal of the transistor 1603, the first terminal of the transistor 1604, and the Node B is connected to each other.

[0097] In addition, a circuit configuration different from that shown in FIGS. 16(A) and 16(B) will be described. 11A, the control circuit 131 is different from the control circuit 131 in that a high power supply potential is supplied to the nodes A and B. a first power supply line 141 to which a low power supply potential is supplied, a second power supply line 142 to which a low power supply potential is supplied, and a third clock signal C K3 is connected to the wiring 1651 (also called the signal line), and The transistor 1601, the transistor 1602, and the transistor 1605 are included. The transistor 1601 has a first terminal connected to the first power supply line 141 and a gate connected to the first terminal. The transistor 1602 has a gate connected to the node A and a second terminal connected to the second power supply line 142. The second terminal of the transistor 1601 and the first terminal of the transistor 1602 are connected to , the first terminal of the transistor 1605, and the node B are connected to each other. The gate of the capacitor 1605 is connected to the wiring 1651, and the second terminal is connected to the second power supply line 142. In a control circuit 131 having another configuration shown in FIG. 17(B), nodes A and B are connected. A first power supply line 141 to which a high power supply potential is supplied, and a second power supply line 142 to which a low power supply potential is supplied. 142, connected to a wiring 1651 to which a third clock signal CK3 is supplied, transistor 1601, transistor 1602, transistor 1603, The transistor 1604, the transistor 1605, and the transistor 1606. The transistor 1601 has a first terminal connected to the first power supply line 141 and a gate connected to the first terminal. The gate of the transistor 1602 is connected to the node A and the gate of the transistor 1604. The second terminal of the transistor 1601 is connected to the second power supply line 142. , the first terminal of the transistor 1602, the first terminal of the transistor 1605, and the The gates of the transistors 1603 are connected to each other. The second terminal of the transistor 1604 is connected to the second power supply line 142. The gate of the transistor 1605 is connected to the wiring 1651 and the transistor 1 The first terminal is connected to the gate of the transistor 606, and the second terminal is connected to the second power supply line 142. the second terminal of transistor 1603, the first terminal of transistor 1604, and the first terminal of transistor 1606 The terminals A and B are connected to each other. The third clock signal CK3 is input to the gate. By providing a transistor 1605 connected to the node B, the potential of the node B is Therefore, the transistor 11 can be made to alternate between the H level and the L level. 4, and the period during which the transistor 115 is in a conducting state can be reduced, and the Deterioration can be suppressed.

[0098] Also, a circuit configuration different from that shown in FIGS. 16(A), (B), 17(A), and (B) will be described. The control circuit 131 shown in FIG. 17C differs from that shown in FIG. 11A in that the nodes A and B , a wiring 1651 to which a first clock signal is supplied, a second power supply line 1652 to which a low power supply potential is supplied, 42, and has a capacitor element 1611 and an n-channel transistor 1612. The capacitor 1611 has a first electrode (also referred to as a first terminal or one electrode) connected to the wiring 165. 1. The transistor 1602 has a gate connected to node A and a second terminal is connected to the second power supply line 142. The second electrode (second terminal, the other an electrode), a first terminal of the transistor 1602, and a node B are connected to each other. By providing the capacitor 1611, the same operation as when a transistor is provided can be performed. This allows the steady-state current to be reduced while maintaining the normal operation, thereby achieving low power consumption.

[0099] In addition, regarding circuit configurations other than those shown in Figures 16(A), (B), 17(A), (B), and (C), The control circuit 131 shown in FIG. 17D is different from that shown in FIG. 11A in that the nodes A, Node B, a wiring 1651 to which a first clock signal is supplied, a second wiring 1652 to which a low power supply potential is supplied, The transistor 1601 is connected to the power supply line 142, and the transistor 1602 is an n-channel transistor. 602, transistor 1603, and transistor 1604. The first terminal of the transistor 1651 is connected to the gate of the transistor 1651. 602 has a gate connected to node A and the gate of transistor 1604, and a second terminal connected to The second terminal of the transistor 1601 is connected to the second power supply line 142. The first terminal of the transistor 602 and the gate of the transistor 1603 are connected to each other. The first terminal of the transistor 1603 is connected to the wiring 1651. The second terminal of the transistor 1603 is connected to the second power supply line 142. The first terminal of the transistor 1604 and the node B are connected to each other. By configuring the control circuit, the potential of the node B is switched between the H level and the L level during the fourth period T4. Therefore, the transistor 114 and the transistor This reduces the period during which transistor 115 is in a conducting state, and This can suppress the deterioration of the resistor 115. In addition, when the node B outputs an H signal, Increasing the voltage between the gate and source of transistor 114 and transistor 115 Therefore, the channel widths of the transistors 114 and 115 can be set to The delay of the output signal can be reduced.

[0100] As described above, the semiconductor device of this embodiment, like the first embodiment, This can reduce malfunctions caused by these factors, and as a result, can reduce display defects. Therefore, there is no need to provide a correction circuit or the like to reduce malfunction of the circuit, and the display device can be made smaller. This can also produce secondary effects such as lower costs and narrower frames.

[0101] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0102] (Embodiment 3) In this embodiment, an example of a display device will be described.

[0103] First, an example of a system block of a liquid crystal display device will be described with reference to FIG. 18(A). The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, a circuit 5363_3, a circuit 5363_4, a circuit 5363_5, a circuit 5363_6, a circuit 5363_7, a circuit 5363_8, a circuit 5363_9, a circuit 5363_10, a circuit 5 2, a pixel portion 5364, a circuit 5365, and a lighting device 5366. In the figure, a plurality of wirings 5371 are arranged extending from a circuit 5362, and a plurality of wirings 5372 are arranged in a circuit. The wiring 5363_1 and the wiring 5363_2 are arranged to extend from each other. The intersections of the line 5371 and the wirings 5372 each have a display element such as a liquid crystal element. Pixels 5367 corresponding to the pixel area are arranged in a matrix.

[0104] The circuit 5361 is connected to the circuit 5362, the circuit 5363_1, the circuit 5364, the circuit 5365, and the circuit 5366 in response to the video signal 5360. 363_2 and the circuit 5365, and has a function of supplying a signal, a voltage, a current, or the like to the controller, control circuit, timing generator, power supply circuit, regulator, etc. In this embodiment, as an example, the circuit 5361 can function as a 362, a start signal for the signal line driver circuit (SSP), a clock signal for the signal line driver circuit ( SCK), inverted clock signal for signal line driver circuit (SCKB), data for video signal (DA TA), and a latch signal (LAT). Then, a start signal for the scanning line driving circuit (G SP), a clock signal for the scanning line driving circuit (GCK), and an inverted clock for the scanning line driving circuit Alternatively, the circuit 5361 may supply a signal (GCKB) to the circuit 5365. The circuit is intended to provide a backlight control signal (BLC), but is not limited to this. 5361 also transmits various other signals, various voltages, or various currents to a circuit 5362, a circuit The signal can be supplied to a circuit 5363_1, a circuit 5363_2, and a circuit 5365.

[0105] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB) supplied from the circuit 5361. , DATA, LAT) to output video signals to multiple wirings 5371. The circuit 5363_1 and the circuit 536_2 can function as a signal line driver circuit. 3_2 runs in response to the signals (GSP, GCK, GCKB) supplied from the circuit 5361. It has a function of outputting scanning signals to a plurality of wirings 5372 and functions as a scanning line driver circuit. The circuit 5365 performs the following in response to the signal (BLC) supplied from the circuit 5361: By controlling the amount or time of power supplied to the lighting device 5366, the lighting device It has the function of controlling the brightness (or average brightness) of 5366 and can function as a power supply circuit. It is possible.

[0106] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 The wirings 53 can function as lines, video signal lines, source lines, or the like. When a scanning signal is input to 72, the plurality of wirings 5372 are signal lines, scanning lines, or gate lines. It can function as a line, etc., but is not limited to this.

[0107] Note that the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2. In this case, the circuit 5363_1 outputs scan signals to the wirings 5372 and the circuit 5363 The timing of the scanning signals output from the _2 to the multiple wirings 5372 is approximately the same. Therefore, the loads driven by the circuits 5363_1 and 5363_2 are reduced. Therefore, the display device can be made larger. Alternatively, the circuits 5363_1 and 5363_2 may have high resolution. Since the channel width of the transistor can be reduced, a display device with a narrow frame can be obtained. However, the present invention is not limited to this, and the circuit 5361 can be implemented by a circuit 5363_1 and a circuit 536 It is possible to supply separate signals to 3_2.

[0108] Note that one of the circuit 5363_1 and the circuit 5363_2 can be omitted.

[0109] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 may be newly added. This newly added circuit outputs signals such as scanning signals to the newly added wiring. It is possible.

[0110] The pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 18(B), the display element can emit light, so that the circuit 5 365 and the lighting device 5366 can be omitted. In order to supply power, a plurality of wirings 5373 that can function as power supply lines are provided in the pixel portion 53 64. The circuit 5361 distributes a power supply voltage called voltage (ANO). The wiring 5373 is connected to each color element of the pixel. It can be connected to all pixels in common.

[0111] Note that in FIG. 18B, as an example, the circuit 5361 includes a circuit 5363_1 and a circuit 536 3_2. The circuit 5361 is a circuit for a scanning line driver circuit. Start signal (GSP1), clock signal for scanning line driving circuit (GCK1), and scanning line driving The circuit 5363_1 is supplied with signals such as an inverted clock signal (GCKB1) for the operating circuit. The circuit 5361 outputs a start signal (GSP2) for the scanning line driving circuit, Clock signal (GCK2), inverted clock signal for scanning line driver circuit (GCKB2), etc. In this case, the circuit 5363_1 supplies the signal to the circuit 5363_2. 72, and the circuit 5363_2 scans only the odd-numbered wirings among the plurality of wirings 5372. That is, only the wirings in the even rows can be scanned. Since the driving frequency of the circuit 5363_2 can be reduced, power consumption can be reduced. Alternatively, the area in which one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. However, the present invention is not limited to this. As in FIG. 18A, the circuit 5361 can be The same signal can be output to the circuit 5363_1 and the circuit 5363_2.

[0112] 18B, the circuit 5361 in FIG. 18A is the same as the circuit 5363 in FIG. It is possible to provide separate signals to the circuit 5363_1 and the circuit 5363_2.

[0113] An example of the system block of the display device has been described above.

[0114] Next, an example of the configuration of the display device will be described with reference to FIGS. 19(A), (B), (C), (D), and ( Please refer to E) for further explanation.

[0115] In FIG. 19A, a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, a circuit 5363_1, and a circuit 5363_2 are formed on the same substrate as the pixel portion 5364. The circuit 5361 is formed on a substrate different from the pixel portion 5364. This reduces the number of external components, thereby reducing costs. Since the number of signals or voltages input to the board 5380 is reduced, the board 5380 and the external components can be The number of connections can be reduced, which can improve reliability and yield. can.

[0116] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta Flexible PCB (Flexible Printed Circuit) Alternatively, the substrate may be , the pixel part 5364 is mounted on the same substrate 538 by the COG (Chip on Glass) method. It is possible to implement it in 0.

[0117] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is formed on a single crystal semiconductor. Therefore, it is possible to form a transistor using the substrate. The circuit has the advantages of improved drive frequency, improved drive voltage, and reduced output signal variation. You can get the points.

[0118] A signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0119] In FIG. 19(B), circuits with low drive frequencies (for example, circuit 5363_1, circuit 5363_ 2) is formed on the same substrate 5380 as the pixel portion 5364. The circuit 5362 is formed on a substrate different from that of the pixel portion 5364. The transistors make it possible to configure circuits formed on the substrate 5380. The semiconductor layer of the transistor may be made of a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, It is possible to use an organic semiconductor, an oxide semiconductor, or the like. This allows for larger size, a reduction in the number of steps, cost reduction, and an improvement in yield.

[0120] As shown in FIG. 19C, a part of the circuit 5362 (circuit 5362a) is connected to the pixel portion 53 The remaining circuit 5362 (circuit 5362b) is formed on the same substrate 5380 as the pixel section 564. The circuit 5362a can be formed on a different substrate from the circuit 364. Circuits that can be configured using transistors (e.g., shift registers, selectors, The circuit 5362b has high mobility and characteristic variations. A circuit (e.g., a shift register) that is preferably constructed using transistors with low They often have a built-in amplifier (e.g., a phase shifter, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, etc.) By doing so, as in FIG. 19(B), a non-single layer can be used as the semiconductor layer of the transistor. A crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used. This makes it possible to further reduce the number of external parts.

[0121] In FIG. 19D, a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, circuit 5363_1, and circuit 5363_2, etc.), and controlling these circuits A circuit having a function (for example, a circuit 5361) is formed on a substrate different from that of the pixel portion 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. Therefore, the yield can be improved.

[0122] As in FIG. 19(D), in FIGS. 19(A) to 19(C), the circuit 5363_1 and The circuit 5363_2 can be formed on a substrate different from that of the pixel portion 5364.

[0123] In FIG. 19E, a part of the circuit 5361 (circuit 5361a) is on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a is formed on a substrate. The circuit 5361a is formed by a transistor with low mobility. In some cases, the device has a circuit that can be switched (for example, a switch, a selector, a level shift circuit, etc.). The circuit 5361b uses transistors with high mobility and small variations. A circuit (for example, a shift register, a timing generator, an These often include a resistor, regulator, or analog buffer.

[0124] 19(A) to 19(D), the circuit 5361a and the pixel section 5364 are mounted on the same substrate. The circuit 5361b can be formed on a substrate different from that of the pixel portion 5364.

[0125] Here, the circuit 5363_1 and the circuit 5363_2 are the circuits according to the first embodiment or the second embodiment. It is possible to use a semiconductor device or a shift register of the second embodiment. In this case, the circuit 536 3_1, the circuit 5363_2 and the pixel portion are formed on the same substrate. The polarity of all transistors formed on the plate can be N-channel or P-channel. Therefore, it is possible to reduce the number of processes, improve yield, improve reliability, or reduce costs. This can be achieved by reducing the power consumption, especially when all transistors are N-channel type. The semiconductor layer of the transistor may be made of a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, or an organic semiconductor. Therefore, it is possible to use organic semiconductors, oxide semiconductors, or the like. This can reduce costs or improve yields.

[0126] Alternatively, the semiconductor device or shift register according to the first or second embodiment may be This allows the channel width of the transistor to be reduced, thereby reducing the layout area. This allows the frame to be smaller, or the layout area to be reduced. Therefore, the resolution can be increased.

[0127] Alternatively, the semiconductor device or shift register according to the first or second embodiment may have a parasitic capacitance. Therefore, the power consumption can be reduced. The current capacity of the circuit can be reduced, or the size of the external circuit or the The size of the display device having the path can be reduced.

[0128] Note that the semiconductor may be a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. A transistor using a semiconductor layer such as a silicon dioxide film has characteristics such as an increase in threshold voltage or a decrease in mobility. However, in the semiconductor device of the first or second embodiment, The shift register can suppress the deterioration of transistor characteristics, thereby extending the life of the display device. It can prolong life.

[0129] Note that the semiconductor device of Embodiment 1 or 2, or For example, the circuit 5362a may be a shift register. Alternatively, the semiconductor device according to Embodiment 2 or a shift register may be included.

[0130] (Fourth embodiment) In this embodiment, an example of a signal line driver circuit will be described. It can be referred to as a conductor device or a signal generating circuit.

[0131] An example of a signal line driver circuit will be described with reference to FIG. The circuit 2002 includes circuits 2002_1 to 2002_2. It has 2_N (N is a natural number) circuits. Circuits 2002_1 to 2002_N are Each transistor is made up of multiple transistors 2003_1 to 2003_k (k is a natural number). The transistors 2003_1 to 2003_k are assumed to be N-channel type. However, the present invention is not limited to this, and the transistors 2003_1 to 2003_k may be P-channel transistors. The switch may be of the CMOS type or may be of the CMOS type.

[0132] The connection relationship of the signal line driver circuit will be described using the circuit 2002_1 as an example. The first terminals of the terminals 2003_1 to 2003_k are connected to the wirings 2004_1 to 2004_k, respectively. The second terminals of the transistors 2003_1 to 2003_k are connected to the wiring S The gates of the transistors 2003_1 to 2003_k are connected to the wiring 20 Connected to 04_1.

[0133] The circuit 2001 outputs high-level signals to the wirings 2005_1 to 2005_N in order. Or, it has a function of selecting the circuits 2002_1 to 2002_N in order. In this way, the circuit 2001 functions as a shift register. The circuit 2001 is not limited to the wiring 2005_1 to 2005_N. Alternatively, the circuits 2002_1 to 2002_N can be configured to output various signals. In this way, the circuit 2001 functions as a decoder. It is possible to have a function.

[0134] The circuit 2002_1 controls the conduction state between the wirings 2004_1 to 2004_k and the wirings S1 to Sk. Alternatively, the circuit 2002_1 has a function of controlling the wirings 2004_1 to 2004_k. The circuit 2002_1 has a function of supplying the potential of the transistor S1 to the wirings S1 to Sk. However, it is not limited to this. The circuits 2002_2 to 2002_N can have the same function as the circuit 2002_1. be.

[0135] The transistors 2003_1 to 2003_N are connected to the wirings 2004_1 to 2004_k, respectively. The transistor 2003 has a function of controlling electrical continuity with the wirings S1 to Sk. 1 to 2003_N respectively connect the potentials of the wirings 2004_1 to 2004_k to the wirings S1 to Sk. For example, the transistor 2003_1 is connected to the wiring 2004_1. The transistor 2003_1 has a function of controlling the conduction state between the wiring S1 and the transistor 2003_2. The transistor 20 has a function of supplying the potential of the transistor 2004_1 to the wiring S1. Each of 03_1 to 2003_N can function as a switch. However, it is not limited to this.

[0136] In many cases, signals are input to the wirings 2004_1 to 2004_k. In many cases, the signal is an analog signal corresponding to image information or an image signal. The signal can function as a video signal. 1 to 2004_k can function as signal lines. For example, depending on the pixel configuration, it may be a digital signal or an analog signal. It can be an analog voltage or it can be an analog current.

[0137] Next, the operation of the signal line driver circuit of FIG. 20(A) will be explained with reference to the timing chart of FIG. 20(B). In FIG. 20B, signals 2015_1 to 2015_N and An example of signals 2014_1 to 2014_k is shown below. Signals 2015_1 to 2015_N are respectively The signals 2014_1 to 2014_k are examples of output signals of the circuit 2001. 2004_1 to 2004_k. The operation period corresponds to one gate selection period in the display device. The period is divided into a period T0 and periods T1 to TN. This is the period during which a precharge voltage is simultaneously applied to the pixels belonging to the same pixel. Each of the periods T1 to TN belongs to a selected row. This is the period for writing video signals to the pixels to be recorded, and functions as a writing period. It is possible.

[0138] First, in a period T0, the circuit 2001 applies high-level Then, for example, in the circuit 2002_1, the transistor 20 03_1~2003_k will be turned on, so wiring 2004_1~2004_k and wiring S At this time, the wirings 2004_1 to 2004_k are connected to each other. Therefore, the precharge voltage Vp is supplied to the transistor 2003. The signals are output to the wirings S1 to Sk via the precharge signals _1 to 2003_k. The voltage Vp is written to the pixels in the selected row. The pixel is precharged.

[0139] During the period T1 to the period TN, the circuit 2001 transmits a high-level signal to the wirings 2005_1 to 2005_2. For example, in the period T1, the circuit 2001 outputs a high level Then, the signal of the line 2005_1 is output to the wiring 2005_2. _k is turned on, so that the wiring 2004_1 to 2004_k and the wiring S1 to Sk are in a conductive state. At this time, the wiring 2004_1 to 2004_k are connected to Data(S1) to Data(S2). a(Sk) is input. Data(S1) to Data(Sk) are the transistors Among the pixels belonging to the selected row via 2003_1 to 2003_k, the pixels in the 1st to kth columns In this way, during the periods T1 to TN, the pixels belonging to the selected row are written. First, the video signal is written in k columns in order.

[0140] As described above, the video signal is written to the pixels in multiple columns. Therefore, the number of connections to external circuits can be reduced. This allows for improved yield, improved reliability, reduced component count, and / or reduced costs. Alternatively, the video signal can be written to the pixels in multiple columns at a time. This allows the write time to be extended, preventing insufficient writing of video signals. Therefore, the display quality can be improved.

[0141] By increasing k, the number of connections to external circuits can be reduced. If k is too large, the time required to write to the pixel becomes short. Therefore, it is preferable that k≦6. It is preferable that k≦3. It is further preferable that k=2. However, the present invention is not limited to this.

[0142] In particular, when the number of color elements of a pixel is n (n is a natural number), k=n or k=n×d (d is a natural number). For example, if the color components of a pixel are red (R), green (G), and blue (B), When the number of divisions is three, it is preferable that k=3 or k=3×d. For example, a pixel may have m (m is a natural number) sub-pixels (hereinafter referred to as sub-pixels or When the pixel is divided into subpixels, it is preferable that k=m or k=m×d. For example, if a pixel is divided into two sub-pixels, then k=2 is preferred, or When the number of color elements of a pixel is n, it is preferable that k=m×n or k=m×n×d. However, it is not limited to this.

[0143] As shown in FIG. 20C, the driving frequency of the circuit 2001 and the driving frequency of the circuit 2002 are Since the frequency is often slow, the circuit 2001 and the circuit 2002 are connected to the pixel portion 2007. In this way, the substrate on which the pixel portion is formed and the substrate on which the external circuit is formed can be formed on the same substrate. The number of connections to the circuit can be reduced, improving yield, reliability, and reducing the number of parts. In particular, the signal line driver circuit 2006 and the pixel portion 2 By forming it on the same substrate as 007, the number of connections to external circuits can be further reduced. However, the present invention is not limited to this. For example, as shown in FIG. 20(D), The circuit 2001 is formed on a substrate different from that of the pixel portion 2007, and the circuit 2002 is formed on the same substrate as that of the pixel portion 2007. In this case, the substrate on which the pixel part is formed and the external circuit This reduces the number of connections, improving yield, reliability, reducing the number of parts, Alternatively, it is possible to reduce costs. Since there is less circuitry, the frame can be made smaller.

[0144] The circuit 2001 may be the semiconductor device or shift In this case, all the transistors in the circuit 2001 are The polarity of the capacitor can be N-channel or P-channel. This can reduce the number of parts, improve yield, or reduce costs.

[0145] In addition to the circuit 2001, all the transistors included in the circuits 2002_1 to 2002_N are The polarity of the transistor can be either N-channel or P-channel. The circuit 2001 and the circuits 2002_1 to 2002_N are formed on the same substrate as the pixel section. In this case, it is possible to reduce the number of steps, improve the yield, or reduce costs. By making the polarity of all transistors N-channel, the semiconductor layer of the transistor and Examples of the semiconductor include non-single-crystal semiconductors, amorphous semiconductors, microcrystalline semiconductors, organic semiconductors, and oxide semiconductors. The reason is that the circuit 2001 and the circuits 2002_1 to 2002_2 can be used. This is because the drive frequency of N is often low.

[0146] (Embodiment 5) In this embodiment, an example of a protection circuit will be described.

[0147] First, an example of a protection circuit will be described with reference to FIG. , a semiconductor device (for example, a transistor, a capacitor, a circuit, etc.) connected to the wiring 3011 ) are installed to prevent damage caused by ESD (electrostatic discharge). The protection circuit 3000 includes a transistor 3001 and a transistor 3002. The resistor 3001 and the transistor 3002 are often N-channel types. However, it is not limited to this and can be a P-channel type.

[0148] A first terminal of the transistor 3001 is connected to a wiring 3012. The second terminal of the transistor 3001 is connected to a wiring 3011. A first terminal of the transistor 3002 is connected to a wiring 3013. A second terminal of the transistor 3002 is connected to a wiring 3011. The gate is connected to a wiring 3013 .

[0149] The wiring 3011 is connected to, for example, a signal (for example, a scanning signal, a video signal, a clock signal, Start signal, reset signal, or select signal), or voltage (negative power supply voltage, ground A voltage, a positive power supply voltage, etc.) can be supplied to the wiring 3012. A positive power supply voltage (VDD) is supplied to the wiring 3013. The power supply voltage (VSS) or ground voltage is supplied. However, this is not limited to this. It will not be done.

[0150] When the potential of the wiring 3011 is between VSS and VDD, the transistors 3001 and 3002 The transistor 3002 is turned off. is supplied to the semiconductor device connected to the wiring 3011. However, the influence of static electricity, etc. As a result, a potential higher than the power supply voltage or a potential lower than the power supply voltage is supplied to the wiring 3011. A potential higher than the power supply voltage or a potential lower than the power supply voltage may be applied. This may destroy the semiconductor device connected to the wiring 3011. In order to prevent electrostatic breakdown of semiconductor devices, a potential higher than the power supply voltage is applied to the wiring 3011. When the potential is supplied, the transistor 3001 is turned on. Then, the charge on the wiring 3011 is The potential of the wiring 3011 is reduced because the potential of the wiring 3012 is transferred through the transistor 3001. On the other hand, when a potential lower than the power supply voltage is supplied to the wiring 3011, Then, the charge in the wiring 3011 is transferred to the transistor 3002. The potential of the wiring 3011 rises. Electrostatic damage to semiconductor devices connected to the semiconductor device 1 can be prevented.

[0151] In the configuration described in FIG. 21(A), as shown in FIG. 21(B), transistor 3 21(A) can be omitted. As shown in FIG. 1(C), the transistor 3001 can be omitted. This is not limited to:

[0152] In the configuration described in FIGS. 21(A) to 21(C), as shown in FIG. 21(D), A transistor can be connected in series between the gate electrode 3011 and the wiring 3012. In this case, a transistor can be connected in series between the wiring 3011 and the wiring 3013. A first terminal of the transistor 3003 is connected to a wiring 3012. The second terminal of transistor 3003 is connected to the first terminal of transistor 3001, and the second terminal of transistor 3003 is connected to the first terminal of transistor 3002. The gate of transistor 3003 is connected to the first terminal of transistor 3001. A first terminal of the transistor 3004 is connected to a wiring 3013, and a second terminal of the transistor 3004 is connected to a wiring 3014. The gate of the transistor 3004 is connected to the first terminal of the transistor 3002. 3004. However, this is not limiting. For example, As shown in 21(E), the gate of transistor 3001 and the gate of transistor 3003 Alternatively, the gate of the transistor 3002 and the transistor 3003 may be connected. The gate of the star 3004 can be connected.

[0153] In the configuration described in FIGS. 21(A) to 21(E), as shown in FIG. 21(F), A transistor can be connected in parallel between the transistor 011 and the wiring 3012. Alternatively, a transistor can be connected in parallel between the wiring 3011 and the wiring 3013. A first terminal of the transistor 3003 is connected to a wiring 3012. The second terminal of the transistor 3003 is connected to the wiring 3011. The first terminal of the transistor 3004 is connected to a wiring 3011. The second terminal of the transistor 3004 is connected to a wiring 3013. The second terminal of the transistor 3004 is connected to the wiring 3011. The gate of 004 ​​is connected to the wiring 3013 .

[0154] In the configurations described in Figs. 21(A) to 21(F), as shown in Fig. 21(G), Between the gate and the first terminal of the transistor 3001, a capacitance element 3005 and a resistance element 3006 are provided. Alternatively, the gate and the first terminal of the transistor 3002 may be connected in parallel. A capacitance element 3007 and a resistance element 3008 can be connected in parallel between the This prevents the protection circuit 3000 itself from being damaged or deteriorated. For example, when a potential higher than the power supply voltage is supplied to the wiring 3011, the transistor 30 Therefore, the Vgs of the wiring 3001 becomes large, and the transistor 3001 turns on. However, the potential of the transistor 3001 is decreased between the gate and the second terminal. Since a large voltage is applied, the transistor 3001 may be destroyed or deteriorated. To prevent this, the potential of the gate of the transistor 3001 is increased. To achieve this, the Vgs of the transistor 3001 is reduced. When the transistor 3001 is turned on, the first terminal of the transistor 3001 Then, due to the capacitive coupling of the capacitor 3005, the transistor 30 The potential of the gate of transistor 3001 increases. This reduces the Vgs of transistor 3001. This can prevent the transistor 3001 from being damaged or deteriorated. Similarly, when a potential lower than the power supply voltage is supplied to the wiring 3011, The potential of the first terminal of the transistor 3002 is instantly reduced. The potential of the gate of the transistor 3002 is reduced by the capacitive coupling of the transistor 3002. Since the Vgs of the transistor 3002 can be reduced, the breakdown of the transistor 3002 can be prevented. Alternatively, deterioration can be suppressed.

[0155] The protection circuits shown in Figures 21(A) to 21(G) can be used in a variety of places. FIG. 22A shows an example of a configuration in which a protection circuit is provided for a gate signal line. In this case, the wiring 3012 and the wiring 3013 are connected to the gate driver 3100. This allows you to connect the power supply to any of the wiring. The number of wirings can be reduced. As an example, in Figure 22(B), This shows a configuration in which a protection circuit is provided on a terminal to which a signal or voltage is supplied. 3012 and wiring 3013 can be connected to any of the external terminals. For example, the wiring 3012 is connected to the terminal 3101a, and the wiring 3013 is connected to the terminal 3101b. In this case, in the protection circuit provided at the terminal 3101a, the transistor 3001 can be omitted. Similarly, the protection circuit provided at the terminal 3101b can be omitted. In this case, the transistor 3002 can be omitted. Since the number of transistors can be reduced, the layout area can be reduced.

[0156] (Sixth embodiment) In this embodiment, examples of the structure of a transistor are shown in FIGS. ) will be referred to for explanation.

[0157] FIG. 23A shows an example of a structure of a top-gate transistor or a structure of a display device. 23B is a diagram showing an example of a structure of a bottom-gate transistor, 23(C) is a diagram showing an example of the structure of a display device manufactured using a semiconductor substrate. 1A and 1B are diagrams illustrating an example of a structure of a transistor.

[0158] An example of the transistor in FIG. 23A includes a substrate 5260 and a An insulating layer 5261, and regions 5262a, 5262b, and a semiconductor layer 5262 having regions 5262c, 5262d, and 5262e; An insulating layer 5263 formed to cover the semiconductor layer 5262 and the insulating layer 52 A conductive layer 5264 formed on the insulating layer 5263 and a conductive layer 5264 formed on the insulating layer 5263 and an insulating layer 5265 having an opening, and a layer on the insulating layer 5265 and in the opening of the insulating layer 5265. and a conductive layer 5266 formed in the portion.

[0159] An example of a transistor in FIG. 23B includes a substrate 5300 and a A conductive layer 5301, an insulating layer 5302 formed to cover the conductive layer 5301, and the conductive layer 5302 301 and a semiconductor layer 5303a formed on the insulating layer 5302, and a semiconductor layer 5303b formed on the insulating layer 5302; A conductive layer 5304 is formed on the insulating layer 5302 and a conductive layer 5304 is formed on the insulating layer 5302. an insulating layer 5305 having an opening; and a conductive layer 5306 formed on the insulating film 5304.

[0160] An example of the transistor in FIG. 23C is a semiconductor substrate having a region 5353 and a region 5355. a plate 5352, an insulating layer 5356 formed on the semiconductor substrate 5352, and a semiconductor substrate 53 An insulating layer 5354 is formed on the insulating layer 5356, and a conductive layer 535 is formed on the insulating layer 5356. 7, and an insulating layer 5354, an insulating layer 5356, and a conductive layer 5357 are formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357, and an opening is formed. and an insulating layer 5358 having a conductive film formed on the insulating layer 5358 and in the opening of the insulating layer 5358. The region 5350 and the region 5351 each have a conductive layer 5359. A transduction device is created.

[0161] In the transistor structure described in FIGS. 23(A) to 23(C), 5266 and the insulating layer 5265 on the transistor, An insulating layer 5267 having an opening, and a metal film formed on the insulating layer 5267 and in the opening of the insulating layer 5267. and a conductive layer 5268 formed on the insulating layer 5267 and on the conductive layer 5268, An insulating layer 5269 having an opening, and a metal film formed on the insulating layer 5269 and in the opening of the insulating layer 5269 a light-emitting layer 5270 formed on the insulating layer 5269 and on the light-emitting layer 5270; Layer 5271 and a layer 5272 can be formed.

[0162] In the transistor structure described in FIGS. 23(A) to 23(C), 5305 and the conductive layer 5306. forming a liquid crystal layer 5307 and a conductive layer 5308 formed on the liquid crystal layer 5307; is possible.

[0163] The insulating layer 5261 can function as a base film. The insulating layer 5263, the insulating layer 5302, and the insulating layer 5303 function as an isolation layer (for example, a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as gate electrodes. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are interlayer films or flat films. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5305 can function as a conductive film. 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a partition wall. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode, a common electrode, or the like. It is possible to do this.

[0164] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, and a single crystal substrate ( For example, silicon substrates, SOI substrates, plastic substrates, metal substrates, stainless steel substrates, Substrate with stainless steel foil, tungsten substrate, tungsten foil Examples of glass substrates include barium borosilicate glass substrates. Examples of flexible substrates include glass and aluminoborosilicate glass. Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone Plastics such as polyethersulfone (PES) or flexible synthetic resins such as acrylic Other examples include laminated films (polypropylene, polyester, vinyl, poly vinyl fluoride, vinyl chloride, etc.), paper containing fibrous materials, base film (polyester , polyamide, polyimide, inorganic vapor deposition film, paper, etc.

[0165] The semiconductor substrate 5352 is, for example, a single-crystal Si substrate having n-type or p-type conductivity. The region 5353 is, for example, a semiconductor substrate 5352 having impurities. For example, if the semiconductor substrate 5352 is a p-type When the region 5353 has a conductivity type of n-type, the region 5353 functions as an n-well. On the other hand, if the semiconductor substrate 5352 has n-type conductivity, the region 5353 has p-type conductivity. The region 5355 has a conductivity type and functions as a p-well. It is a region doped in the plate 5352 and functions as a source region or a drain region. In the semiconductor substrate 5352, an LDD region can be formed.

[0166] An example of the insulating layer 5261 is silicon oxide (SiO x ) film, silicon nitride (SiN x ) membrane, acid Silicon nitride (SiO x N y ) (x>y>0) film, silicon oxynitride (SiN x O y )(x>y >0) film, or a laminated structure of these. As an example of a two-layer structure, the first insulating layer is a silicon nitride film. The insulating layer 5261 can be formed on the insulating film 5262, and a silicon oxide film can be formed as the second insulating layer. As an example of a three-layer structure, a silicon oxide film is provided as the first insulating layer, and a second insulating layer is provided as the second insulating layer. A silicon nitride film is provided as the first insulating layer, and a silicon oxide film is provided as the third insulating layer. It is possible.

[0167] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single layer. Crystalline semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon) semiconductors (e.g., SiGe, GaAs), single crystal semiconductors, compound semiconductors (e.g., SiGe, GaAs), oxide semiconductors Conductors (e.g., ZnO, InGaZnO, IZO (indium zinc oxide), ITO (indium Indium tin oxide), SnO, TiO, AlZnSnO (AZTO), organic semiconductors, Examples include carbon nanotubes.

[0168] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, when impurities are added to the region 5262a, the region 5262a functions as a channel region. The impurity added to the region 5262a can be added to the region 5262b, the region 5262c, and the region 5262d. 2c, region 5262d, or region 5262e. It is preferable that the region 5262b and the region 5262d are not included in the region 5262c or the region 5262e. It is a region where impurities are added at a lower concentration than that of the LDD (Lightly Doped Diode). However, the area 5262b and the area 5262 The region 5262c and the region 5262e are regions containing highly concentrated impurities. The material is added to the semiconductor layer 5262 and functions as a source region or a drain region. do.

[0169] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0170] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0171] An example of the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 is silicon oxide (Si O x ) film, silicon nitride (SiN x ) film, silicon oxynitride (SiO x N y )(x>y>0) membrane, Silicon oxynitride (SiN x O y ) (x>y>0) film, or a film containing oxygen or nitrogen; These include laminated structures.

[0172] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, Conductive layer 5304, conductive layer 5306, conductive layer 5308, conductive layer 5357, and conductive layer 53 An example of the conductive film 59 is a conductive film having a single layer structure or a laminated structure thereof. Examples of these include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum (Mo). Mo, Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni ), platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C), scandium (Sc), zinc (Zn), gallium (Ga), indium (In) tin (Sn), zirconium (Zr), and cerium (Ce) A single film of one element selected from the group, or a compound containing one or more elements selected from the group, etc. The simple films or compounds include phosphorus (P), boron (B), arsenic (As), and and / or oxygen (O). Examples of such compounds include the aforementioned An alloy containing one or more elements selected from a plurality of elements (e.g., indium tin oxide) Indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide with silicon oxide ( ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), Aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum Aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum ceramic Al-Ce, Magnesium-Silver (Mg-Ag), Molybdenum-Niobium (Mo-Nb ), molybdenum tungsten (Mo-W), molybdenum tantalum (Mo-Ta), etc. gold material), a compound of nitrogen with one or more elements selected from the above elements ( For example, nitride films such as titanium nitride, tantalum nitride, and molybdenum nitride), or the above-mentioned composites. Compounds of silicon with one or more elements selected from several elements (e.g., tungsten Titanium silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Other examples include carbon nanotubes. nanotube materials such as nanotubes, organic nanotubes, inorganic nanotubes, or metallic nanotubes There is a fee.

[0173] The conductive layer may have a single layer structure or a multilayer structure. .

[0174] Insulating layer 5265, insulating layer 5267, insulating layer 5269, insulating layer 5305, and insulating layer 535 An example of the insulating layer 8 is a single-layer insulating layer or a laminated structure of these layers. One example is silicon oxide (SiO x ) film, silicon nitride (SiN x ) film, or silicon oxynitride Element (SiO x N y ) (x>y>0) film, silicon oxynitride (SiN x O y )(x>y>0) membrane films containing oxygen or nitrogen, such as DLC (diamond-like carbon) Film, or siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol , benzocyclobutene, or organic materials such as acrylic.

[0175] Note that an insulating layer functioning as an alignment film is provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0176] Note that a color filter, a black matrix, or a protrusion may be formed on the conductive layer 5308. An insulating layer or the like that functions as an alignment film can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0177] The transistor of this embodiment is used in the shift registers described in the first and second embodiments. In the shift registers described in the first and second embodiments, Since the deterioration of the transistor can be suppressed, in FIG. 23(B), , non-single-crystal semiconductors such as amorphous semiconductors or microcrystalline semiconductors, organic semiconductors, or oxides Therefore, it is possible to reduce the manufacturing process, reduce manufacturing costs, and This can improve retention or allow for larger display devices.

[0178] (Embodiment 7) In this embodiment, an example of a cross-sectional structure of a display device will be described with reference to FIGS. Please refer to C) for explanation.

[0179] 24A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. , or a signal line driver circuit.

[0180] FIG. 24(B) shows an example of the AB cross section of FIG. 24(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; a conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; a liquid crystal layer 5407 formed on the insulating layer 5405; 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0181] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a wiring, a pixel electrode, or a planarization film. The insulating layer 5408 can function as a polarizer or a reflector. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0182] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. Or, the power consumption will increase. However, as shown in Figure 24(B), As shown in FIG. 5B, an insulating layer 5408 that can function as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 is reduced. This is because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. Therefore, the output signal of the driver circuit 5392 or the potential of each node is Alternatively, the power consumption of the driver circuit 5392 can be reduced. This can be done.

[0183] As shown in FIG. 24C, a film that functions as a sealant is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. The parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the potential of each node. However, it is not limited to this, and a film that functions as a sealant can be provided on the driver circuit 5392. It is possible that the insulating layer 5408 is not formed.

[0184] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0185] The structure of the display device of this embodiment and the shift register described in the first and second embodiments For example, an amorphous semiconductor can be used as a semiconductor layer of a transistor. Non-single-crystal semiconductors such as solid or microcrystalline semiconductors, organic semiconductors, or oxide semiconductors are used. In this case, the channel width of the transistor is often large. Thus, if the parasitic capacitance of the driver circuit can be reduced, the channel width of the transistor can be reduced. Therefore, the layout area can be reduced, and the display device can be made narrower. The display can be edged or can be high definition.

[0186] (Embodiment 8) In this embodiment, an example of a manufacturing process of a transistor and a capacitor will be described. A manufacturing process in the case where an oxide semiconductor is used for the layer will be described.

[0187] 25A to 25C, an example of a manufacturing process of a transistor and a capacitor will be described. 25A to 25C show a transistor 5441 and a capacitor 5442. The transistor 5441 is an example of an inverted staggered thin film transistor. and a wiring is provided on the oxide semiconductor layer via a source electrode or a drain electrode. This is an example of a transistor.

[0188] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. The conductive layers 5421 and 5422 are used as wirings, gate electrodes, or electrodes of a capacitor. After this, the resist mask is removed.

[0189] Next, an insulating layer 5423 is formed on the entire surface by plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer, and the conductive layer 5421 The insulating layer 5423 is formed to cover the insulating layer 5424 and the conductive layer 5422. It is often between 100 and 250 nm.

[0190] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After this, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After forming the contact hole 5424, the contact hole 5424 can be formed. The cross-sectional view of this corresponds to FIG. 25(A).

[0191] Next, an oxide semiconductor layer is formed on the entire surface by sputtering. The oxide semiconductor layer is formed by sputtering, and a buffer layer (e.g., For example + The oxide semiconductor layer can be formed with a thickness of 5 nm to 2 00nm in most cases.

[0192] Next, the oxide semiconductor layer is selectively etched using a third photomask. Then, the resist mask is removed.

[0193] Next, a second conductive layer is formed on the entire surface by sputtering. The second conductive layer is selectively formed using a resist mask formed by a photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the conductive layer 5429, the conductive layer 5430, and the conductive layer 5431. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. The cross section at this stage corresponds to Figure 25(B).

[0194] Next, a heat treatment is carried out at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. The treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal layer. As shown above, the distortion that inhibits carrier movement is released by heat treatment (including optical annealing). The timing of this heat treatment is not limited, and various methods can be used after the formation of the oxide semiconductor. It can be done at the right time.

[0195] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 has a single-layer structure. For example, the insulating layer 5432 may be an organic thin film. When an insulating layer is used, a composition that is a material for the organic insulating layer is applied, and the applied composition is heated under an air atmosphere or nitrogen atmosphere. Heat treatment is carried out at 200°C to 600°C in an atmosphere to form an organic insulating layer. By forming an organic insulating layer in contact with the oxide semiconductor layer, a thin film with high reliability in electrical properties can be obtained. A thin film transistor can be manufactured. Note that an organic insulating layer is used as the insulating layer 5432. In this case, a silicon nitride film or a silicon oxide film can be provided under the organic insulating layer.

[0196] Next, a third conductive layer is formed on the entire surface. Next, a photolithography process is performed using a fifth photomask. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. A cross-sectional view of the process up to this stage is shown in FIG. 25(C). The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, and the like. The conductive layer 5434 can function as a photo-transistor or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, the conductive layer 5422 can function as an electrode of the capacitor 5442. However, it is not limited to this, and any other material having the function of connecting the first conductive layer and the second conductive layer may be used. For example, by connecting the conductive layer 5433 and the conductive layer 5434, The conductive layer 5422 and the conductive layer 5430 are connected to a third conductive layer (conductive layer 5433 and conductive layer 543 4) can be connected via

[0197] Through the above steps, the transistor 5441 and the capacitor 5442 can be manufactured. .

[0198] As shown in FIG. 25D, an insulating layer 5435 is formed over the oxide semiconductor layer 5425. It is possible to do this.

[0199] As shown in FIG. 25(E), after the second conductive layer is patterned, the oxide semiconductor layer 5425 can be formed.

[0200] The substrate, insulating layer, conductive layer, and semiconductor layer of this embodiment may be the same as those of other embodiments. Materials described or similar to those described herein can be used.

[0201] The transistor of this embodiment may be used in the shift register described in the first and second embodiments, or By using this in a display device, the display area can be enlarged. can make the display high-definition.

[0202] (Embodiment 9) In this embodiment, an example of an electronic device will be described.

[0203] 26(A) to 26(H) and 27(A) to 27(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED Lamp 5004, operation key 5005 (power switch or operation to control the operation of the display device) switch), connection terminal 5006, sensor 5007 (force, displacement, position, velocity, acceleration , angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, The function of measuring current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared 5008, etc.

[0204] FIG. 26(A) shows a mobile computer, which includes, in addition to the above components, a switch 5009, It may have an infrared port 5010, etc. FIG. 26(B) shows a portable device equipped with a recording medium. A type of image reproducing device (for example, a DVD reproducing device), which, in addition to the above, also has a second display 26(C) shows a GOG In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. FIG. 26(D) shows a portable game machine. In addition to the above, it can have a recording medium reading unit 5011, etc. In addition to the components described above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 26(F) shows a portable gaming machine, which, in addition to the above, has a second display unit 26(G) shows a television receiver. In addition to the components described above, the image sensor may also include a tuner, an image processor, etc. 26(H) is a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 27(A) is a display, and the above-mentioned In addition to the above, it may have a support stand 5018, etc. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 27(C) is a computer, In addition, there are a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 27(D) shows a mobile phone, which can have the above-mentioned 2, an antenna 5014, a 1-segment partial reception service tuner for mobile phones and mobile terminals It may have a lens, etc.

[0205] The electronic devices shown in FIGS. 26(A) to 26(H) and 27(A) to 27(D) are various For example, various information (still images, videos, text images, etc.) Function to display on the display, touch panel function, calendar, date or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, The function of transmitting or receiving various data using the program or The data can be read out and displayed on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another is used A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a three-dimensional image. In electronic devices with an image receiving unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to save the captured image to a recording medium (external or camera). It can have functions such as saving the captured image to a built-in memory, displaying the captured image on the display, etc. Note that the electronic devices shown in FIGS. 26(A) to 26(H) and 27(A) to 27(D) The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0206] The electronic device described in this embodiment has a display unit for displaying some information. In particular, the display device is characterized by the shift register described in the first and second embodiments. When a display device has a capacitor, it is possible to prevent malfunction of the circuit, thereby improving the display quality. It is possible.

[0207] Next, application examples of the semiconductor device will be described.

[0208] FIG. 27(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. 025, etc. The semiconductor device is a wall-mounted type that is integrated with the building, and the installation space is limited. It can be installed without requiring a large space.

[0209] FIG. 27(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 as a unit. The display panel 5026 becomes viewable.

[0210] In this embodiment, a wall and a unit bath are used as examples of buildings. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various buildings.

[0211] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0212] 27G is a diagram showing an example in which the semiconductor device is provided in an automobile. 5028 is attached to the body 5029 of the automobile, and is The information entered can be displayed on demand. It may be possible.

[0213] FIG. 27(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 27(H) shows a passenger plane with a display panel 5031 mounted on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge part 5032 are attached together, and the extension and contraction of the hinge part 5032 This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0214] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorails, etc.), It can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0215] 100 Semiconductor device 101 Pulse output circuit 102 Wiring 103 Wiring 104 Wiring 105 Wiring 111 Transistor 112 transistors 113 Transistor 114 transistors 115 transistors 131 Control circuit 141 Power line 142 Power line 151 Signal Line 152 signal line 153 Signal Line 154 signal line 155 Signal Line 156 Signal Line 157 Signal Line 280 dotted line 281 Dash line 282 dashed line 283 Dash line 413 Diode Element 513 Transistor 1601 Transistor 1602 transistor 1603 Transistor 1604 transistor 1605 transistor 1606 Transistor 1611 Capacitor element 1651 Wiring 2000 circuits 2001 Circuit 2002 Circuit 2003 Transistor 2004 Wiring 2005 Wiring 2006 Signal line driver circuit 2007 Pixel section 2014 signal 2015 signal 3000 protection circuit 3001 Transistor 3002 transistor 3003 Transistor 3004 Transistor 3005 Capacitor 3006 Resistor element 3007 Capacitor element 3008 Resistor element 3011 Wiring 3012 Wiring 3013 Wiring 3100 Gate Driver 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection Lens 5260 board 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulation layer 5268 Conductive layer 5269 Insulation layer 5270 luminous layer 5271 Conductive layer 5300 board 5301 Conductive layer 5302 Insulation layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5360 video signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 input terminal 5391 Circuit Board 5392 drive circuit 5393 Pixel section 5400 board 5401 Conductive layer 5402 Insulation layer 5404 Conductive layer 5405 Insulation layer 5406 Conductive layer 5408 Insulation layer 5409 Conductive layer 5410 PCB 5420 PCB 5421 Conductive layer 5422 Conductive layer 5423 Insulation layer 5424 Contact Hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulation layer 5433 Conductive layer 5434 Conductive layer 5435 Insulation layer 5441 Transistor 5442 Capacitor element 3101a terminal 3101b terminal 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a circuit 5361b circuit 5362a circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer

Claims

1. having first to ninth transistors, one of the source and the drain of the first transistor is always electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate line; one of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the second transistor is always electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is always electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is always electrically connected to a second gate line; a gate of the second transistor is always electrically connected to the second gate line; the gate of the third transistor is always electrically connected to the second clock signal line; one of the source and the drain of the fourth transistor is always electrically connected to the first gate line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fourth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the other of the source and the drain of the sixth transistor; a gate of the eighth transistor is always electrically connected to the other of the source and the drain of the sixth transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; the high and low timing of the signal on the second clock signal line is different from that of the signal on the first clock signal line; A semiconductor device in which the channel width of the first transistor is larger than the channel widths of the second to ninth transistors.

2. A driving circuit unit and a pixel, the drive circuit unit has first to ninth transistors, one of the source and the drain of the first transistor is always electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is always electrically connected to a first gate line; one of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the second transistor is always electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is always electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the second transistor is always electrically connected to a second gate line; a gate of the second transistor is always electrically connected to the second gate line; the gate of the third transistor is always electrically connected to the second clock signal line; one of the source and the drain of the fourth transistor is always electrically connected to the first gate line; the other of the source and the drain of the fourth transistor is always electrically connected to a power supply line; one of the source and the drain of the fifth transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the fifth transistor is always electrically connected to the power supply line; a gate of the fifth transistor is always electrically connected to a gate of the fourth transistor; one of the source and the drain of the sixth transistor is always electrically connected to the gate of the fourth transistor; one of the source and the drain of the seventh transistor is always electrically connected to the gate of the fourth transistor; the other of the source and the drain of the seventh transistor is always electrically connected to the power supply line; a gate of the seventh transistor is always electrically connected to a gate of the first transistor; one of the source and the drain of the eighth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the eighth transistor is always electrically connected to the other of the source and the drain of the sixth transistor; a gate of the eighth transistor is always electrically connected to the other of the source and the drain of the sixth transistor; one of the source and the drain of the ninth transistor is always electrically connected to the gate of the sixth transistor; the other of the source and the drain of the ninth transistor is always electrically connected to the power supply line; a gate of the ninth transistor is always electrically connected to a gate of the first transistor; the high and low timing of the signal on the second clock signal line is different from that of the signal on the first clock signal line; a channel width of the first transistor is larger than a channel width of the second to ninth transistors; The pixel is connected to the first gate line, The pixel has a liquid crystal element, A display device in which the liquid crystal element is driven in an FFS mode.

Images