Trace data acquisition device, integrated circuit, trace data acquisition method and program

Abstract

To provide a relatively large amount of trace information and to make the amount of trace data to be stored in memory relatively small when storing trace data of CPU operations in memory. [Solution] The trace data acquisition device comprises a standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU including data indicating the privileged mode of the CPU; a data volume reduced trace data acquisition means for acquiring data volume reduced trace data, which is trace data from the standard trace data with information indicating the privileged mode of the CPU deleted; a transmission means for transmitting the standard trace data; and a memory writing means for storing the data volume reduced trace data in memory.

Description

[Technical Field]

[0001] The present invention relates to a trace data acquisition device, an integrated circuit, a trace data acquisition method, and a program. [Background technology]

[0002] Trace data of CPU activity may be stored in memory. For example, the debug device described in Patent Document 1 stores the value of a program counter and the state of the debug device resulting from the execution of an instruction sequence in a data memory when the instruction sequence is executed. When the debug device receives a trace data read request, it reads the data from the data memory and outputs it. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-002934 Summary of the Invention [Problem to be solved by the invention]

[0004] From the viewpoint of analyzing CPU operation in more detail, it is preferable to obtain as much information as possible from trace data (trace information). On the other hand, when storing trace data in memory with limited capacity, it is preferable to keep the amount of trace data as small as possible.

[0005] An example of an objective of the present disclosure is to provide a trace data acquisition device, an integrated circuit, a trace data acquisition method, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0006] According to a first aspect of the present disclosure, a trace data acquisition device comprises a standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of a CPU including data indicating the privileged mode of the CPU; a data volume reduced trace data acquisition means for acquiring data volume reduced trace data, which is trace data from the standard trace data with information indicating the privileged mode of the CPU deleted; a transmission means for transmitting the standard trace data; and a memory writing means for storing the data volume reduced trace data in a memory.

[0007] According to a second aspect of the present disclosure, an integrated circuit comprises a CPU, a standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU including data indicating a privileged mode of the CPU, a data volume reduced trace data acquisition means for acquiring data volume reduced trace data, which is trace data from which information indicating the privileged mode of the CPU has been deleted from the standard trace data, a transmission means for transmitting the standard trace data, and a memory writing means for storing the data volume reduced trace data in a memory.

[0008] According to a third aspect of the present disclosure, a trace data acquisition method includes a trace data acquisition device acquiring standard trace data, which is trace data of the operation of a CPU, including data indicating a privileged mode of the CPU, acquiring reduced-data-volume trace data, which is trace data from the standard trace data in which information indicating the privileged mode of the CPU has been deleted, transmitting the standard trace data, and storing the reduced-data-volume trace data in a memory.

[0009] According to a fourth aspect of the present disclosure, a program causes an integrated circuit including a CPU to acquire standard trace data, which is trace data of the operation of the CPU and includes data indicating the privileged mode of the CPU; acquire reduced-data-volume trace data, which is trace data from the standard trace data from which information indicating the privileged mode of the CPU has been deleted; transmit the standard trace data; and store the reduced-data-volume trace data in a memory. [Effects of the Invention]

[0010] According to one aspect of the present disclosure, it is possible to provide a relatively large amount of trace information, while keeping the amount of trace data stored in memory (e.g., the amount of data for the entire execution of a program) relatively small. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 illustrates an example configuration of an on-chip debug circuit according to at least one embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of input and output of data in an LSI according to at least one embodiment. [Figure 3] FIG. 2 is a diagram illustrating an example of signal names and contents used by an Ingress Port of a debug target circuit according to at least one embodiment. [Figure 4] 1A-1C illustrate example trace messages used by on-chip debug circuitry according to at least one embodiment. [Figure 5] FIG. 10 illustrates an example of sending a trace message in single-step mode according to at least one embodiment. [Figure 6] FIG. 10 illustrates an example of privileged mode transitions in single-step mode according to at least one embodiment. [Figure 7] FIG. 10 illustrates an example trace message in single-step mode with privileged mode information removed, according to at least one embodiment. [Figure 8] FIG. 1 illustrates an example of a trace encoder configuration according to at least one embodiment. [Figure 9] FIG. 1 illustrates an example of data input and output in a trace encoder according to at least one embodiment. [Figure 10] FIG. 2 illustrates an example of when privileged modes change after execution of multiple instructions in at least one embodiment. [Figure 11] FIG. 1 illustrates an example of the configuration of a trace data acquisition device according to at least one embodiment. [Figure 12] FIG. 1 illustrates an example of the configuration of an integrated circuit according to at least one embodiment. [Figure 13] FIG. 1 is a diagram illustrating an example of a processing procedure in a trace data acquisition method according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] The following describes embodiments of the present invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0013] First Embodiment 1 is a diagram illustrating an example of the configuration of an on-chip debug circuit according to at least one embodiment, which shows a debug target circuit 110 and an on-chip debug circuit 130 in an LSI 100, which is an LSI (Large Scale Integration) to be debugged.

[0014] 1, a debug target circuit 110 includes a CPU (Central Processing Unit) 120. An on-chip debug circuit 130 includes a trace encoder 140 and an internal RAM (Random Access Memory) 150. Here, an example will be described in which the trace data is used for debugging, such as debugging a program executed by the CPU 120 or debugging CPU hardware. However, the use of trace data in the LSI 100 is not limited to debugging. For example, the trace data may be used for tuning a program, such as improving the speed or optimizing the program executed by the CPU 120.

[0015] Data for tracing the operation of CPU 120 is referred to as trace data of the operation of CPU 120, or simply as trace data. The trace data may include data indicating instructions executed by CPU 120. The trace data may also include data indicating the operating mode of CPU 120 or data indicating the state of debug target circuit 110 while CPU 120 is operating, such as the values ​​of registers in debug target circuit 110 while CPU 120 is operating. The information indicated by trace data is also called trace information. Trace data in the form of text (strings) is also called a trace message. A trace message is an example of trace data.

[0016] The LSI 100 is an LSI in which a CPU 120 and an on-chip debug circuit 130 are integrated into one chip. The LSI 100 is an example of a trace data acquisition device and an example of an integrated circuit (IC).

[0017] The CPU 120 executes various processes by executing programs. The debug target circuit 110 is a part of the LSI 100 that is to be debugged. In addition to the CPU 120, the debug target circuit 110 may include peripheral circuits of the CPU 120, such as a memory and an input / output circuit. The debug target circuit 110 outputs trace data to the trace encoder 140 .

[0018] The on-chip debug circuit 130 converts the trace data output by the debug target circuit 110 into a trace message, and outputs and records the trace message. The trace encoder 140 converts the trace data output by the debug target circuit 110 into trace messages. The internal RAM 150 stores trace messages.

[0019] FIG. 2 is a diagram showing an example of data input / output in the LSI 100. As shown in FIG. In the following, we will explain an example in which the CPU 120 is a CPU based on the RISC-V (registered trademark) architecture, and the debug target circuit 110 outputs information about the instructions executed by the CPU 120 and information about the state of the debug target circuit 110 as trace data via an Ingress Port.

[0020] The Ingress Port is the CPU trace information output signal specified in the "TG RISC-V Nexus Trace Specification." However, the CPU 120 is not limited to a CPU with a specific instruction set architecture (ISA), and the format in which the debug target circuit 110 outputs trace data is not limited to a specific format.

[0021] 3 is a diagram showing examples of signal names and contents used by the debug target circuit 110 at the Ingress Port. FIG. 3 shows information about signals used by the debug target circuit 110 at the Ingress Port in a table format, with information about one type of signal shown per line. The Signal column shows the signal name. The Function column shows the content of the signal shown in the Signal column. In FIG. 3, the reference symbols R11 to R19 are assigned in order from the top row.

[0022] "itype" indicates the type of all retired instructions. Instruction retirement here refers to the operation of updating the state of the debug target circuit 110 at the final stage of instruction execution by the CPU. "Cause" indicates the cause of the exception or interrupt. "tval" indicates the associated trap value when the exception or interrupt occurs.

[0023] "priv" indicates the privilege level (privileged mode) of all retired instructions. The privileged mode here is a CPU operating mode that defines the restrictions on the operations that the CPU can perform. The privileged mode is also called the CPU mode. RISC-V has three privileged modes: U-mode (User Mode), HS-mode (Hypervisor-extended Supervisor Mode), and M-mode (Machine Mode), as well as D-mode (Debug Mode), a privileged mode for debugging.

[0024] "iaddr" indicates the address of the first instruction retired. "context" indicates the context of all retired instructions. "time" indicates time information. "iretire" indicates the number of instructions retired. "ilastsize" indicates the size of the retired instruction.

[0025] The trace encoder 140 uses an ingress port input from the debug target circuit 110 to generate a trace message using a processor branch trace based on the "TG RISC-V Nexus Trace Specification." Processor branch tracing is a method for tracing the branch history of instructions executed by a CPU.

[0026] In processor branch tracing, the flow of program execution can be traced by recording the address of the branch destination each time the program branches. Using the trace messages generated by the trace encoder 140, it is possible to restore historical information on the state of the program counter (PC), and to represent the flow of program execution by the CPU 120. The on-chip debug circuit 130 outputs the trace messages generated by the processor branch trace to the outside and also stores them in the internal RAM 150. Storing data in memory is also referred to as storing data in memory.

[0027] 4 is a diagram showing an example of a trace message used by the on-chip debug circuit 130. FIG. 4 shows information about the trace messages used by the on-chip debug circuit 130 in a table format, with one type of trace message information shown per line. The trace message name column shows the name of the trace message. The content column shows the content of the trace message shown in the trace message name column. In FIG. 4, the reference symbols R21 to R27 are assigned in order from the top row.

[0028] "Ownership Trace" is used to trace context switches. "Program Trace.Direct Branch" shows a program trace where there is a change in program flow and the target address is branched to or the target address is statically known by a subroutine call instruction.

[0029] "Program Trace.Indirect Branch" shows the program trace when the program flow is changed at run time by a subroutine call, a return instruction, an asynchronous interrupt / trap, or an indirect instruction. "Program Trace.Indirect Branch" is output every time the target address is determined.

[0030] "Error" indicates what type of error was generated, and if there are multiple clients on the device, "Error" also indicates which client generated the error. "Program Trace.Synchronization" indicates trace information that a development tool periodically synchronizes with the program flow. The development tool in this case is a tool that restores and encodes historical information about the state of trace messages. "Program Trace.Synchronization" is also used during trace development.

[0031] "Program Trace.Rsource Full" is a trace message that notifies trace information so that information is not lost when the internal memory that stores trace data becomes full. "Program Trace.Correlation" correlates trace flow with termination.

[0032] The trace encoder 140 reduces the amount of data in a trace message in single-step mode.

[0033] FIG. 5 is a diagram showing an example of trace message transmission in single-step mode. FIG. 5 also shows, in table format, an example of a trace message that the trace encoder 140 transmits to the outside of the LSI 100 in single-step mode. The trace data that the debug target circuit 110 outputs to the trace encoder 140 is shown in the "trace data" column, and the trace message that the trace encoder 140 transmits based on that trace data is shown in the "trace message" column. Also, in FIG. 5, time flows from the top to the bottom of the diagram. That is, the upper part of the diagram shows older information, and the lower part shows newer information.

[0034] FIG. 6 is a diagram showing an example of privileged mode transitions in single-step mode. FIG. 6 also shows, in table format, an example of a time series of the operating status of the CPU 120 in single-step mode. The operating status of the CPU 120 is shown in the "CPU operating status" column, and the trace messages sent by the trace encoder 140 during that operating status are shown in the "trace message" column. In addition, time flows from the top to the bottom of FIG. 6. In other words, the upper part of the figure shows older information, and the lower part shows newer information.

[0035] 6, the CPU 120 executes instructions by switching between normal mode (U-mode) and debug mode (D-mode) for each instruction. The debug target circuit 110 notifies the trace encoder 140 of privilege mode change information during instruction execution in single-step mode using the Ingress Port "priv" shown in the row R14 in FIG. 3. Thus, in single-step mode, the CPU 120 executes instructions one by one, and the debug target circuit 110 outputs trace information in response to the execution of the instructions.

[0036] The trace encoder 140 outputs "Program Trace.Correlation" shown in line R27 of Figure 4 when transitioning to debug mode in accordance with the "TG RISC-V Nexus Trace Specification." When privileged mode transitions back to normal mode, the trace encoder 140 outputs "Program Trace.Synchronization" shown in line R25 of Figure 4. This allows the trace encoder 140 to notify the stop and start of the trace flow for each instruction.

[0037] Here, it is considered that real-time performance is important for the trace messages output externally by the trace encoder 140, and that information that represents the current state is required, whereas the trace messages stored in the internal RAM 150 are taken out after the program ends and are used to check the operation of the series of programs.

[0038] Since the privileged mode change information is not necessary for restoring the history information of the program counter state, the trace encoder 140 stores the trace message, from which the privileged mode information has been deleted, in the internal RAM 150. FIG. 7 shows an example of a trace message in single-step mode with privileged mode information removed. FIG. 7 also shows, in table format, an example of a trace message that the trace encoder 140 stores in the internal RAM 150 in single-step mode. The trace data that the debug target circuit 110 outputs to the trace encoder 140 is shown in the "Trace Data" column, and the trace message that the trace encoder 140 stores in the internal RAM 150 based on that trace data is shown in the "Trace Message" column. Also, in FIG. 7, time flows from top to bottom. That is, the upper part of the figure shows older information, and the lower part shows newer information.

[0039] Comparing the example in Figure 5 with the example in Figure 7, the example in Figure 5 shows "Program Trace.Synchronization" output when transitioning to normal mode (U) and "Program Trace.Correlation" output when transitioning to debug mode (D). In contrast, the example in Figure 7 has deleted "Program Trace.Synchronization" and "Program Trace.Correlation."

[0040] Note that the "Program Trace.Synchronization" shown in Fig. 7 is output when the execution of the instruction sequence starts, and is different from the "Program Trace.Synchronization" output when transitioning to normal mode (U). Also, the "Program Trace.Correlation" shown in Fig. 7 is output when the execution of the instruction sequence ends, and is different from the "Program Trace.Correlation" output when transitioning to debug mode (D).

[0041] Fig. 8 is a diagram showing an example of the configuration of the trace encoder 140. In the configuration shown in Fig. 8, the trace encoder 140 includes a filter control unit 141, a trace information control unit 142, an external output message generation unit 143, an external output message transmission FIFO 144, an internal RAM message generation unit 145, and an internal RAM message transmission FIFO 146.

[0042] FIG. 9 is a diagram showing an example of data input and output in the trace encoder 140. The filter control unit 141 extracts information necessary for generating a trace message from the data of the ingress port input from the CPU 120 . The filter control unit 141 outputs the extracted information to the trace information control unit 142 . Processing by known techniques may be used as the processing performed by the filter control unit 141. For example, the filter control unit 141 may perform known processing that is performed when acquiring trace data in RISC-V.

[0043] The trace information control unit 142 analyzes the information input from the filter control unit 141 and generates information necessary to generate a trace message for external output (external transmission). A trace message for external output is also called a standard trace message. A standard trace message is also called standard trace data, as it is treated as an example of trace data.

[0044] The trace information control unit 142 may analyze the information input from the filter control unit 141 and generate information necessary for generating a trace message for external output using a known technique. For example, the trace information control unit 142 may perform known processing that is performed when acquiring trace data in RISC-V.

[0045] Furthermore, the trace information control unit 142 removes privileged mode information from the information necessary for generating a standard trace message, and generates this information as the information necessary for generating a trace message to be stored in the internal RAM 150. Specifically, the trace information control unit 142 removes the "priv" information for the Ingress Port shown in row R14 of FIG. 3 from the information necessary for generating a standard trace message, and generates this information as the information necessary for generating a trace message to be stored in the internal RAM 150.

[0046] The trace messages stored in the internal RAM 150 are also referred to as "reduced data volume trace messages." The internal RAM 150 is an example of a memory that stores reduced data volume trace messages. The reduced data volume trace messages are also referred to as "reduced data volume trace data," treating them as an example of trace data.

[0047] Trace information control unit 142 outputs information necessary for generating a standard trace message to external output message generation unit 143. Trace information control unit 142 also outputs information necessary for generating a data amount reduced trace message to internal RAM message generation unit 145.

[0048] The external output message generation unit 143 generates a standard trace message using information input from the trace information control unit 142. Specifically, the external output message generation unit 143 converts the trace data input from the trace information control unit 142 into text (character strings). The external output message generation unit 143 may use a process based on a known technique to convert the trace data into text. For example, the external output message generation unit 143 may perform a known process that is performed when converting trace data into a trace message in RISC-V. The external output message generating unit 143 outputs the generated standard trace message to the external output message sending FIFO.

[0049] The external output message transmission FIFO 144 transmits the standard trace messages input from the external output message generation unit 143 to the outside of the LSI 100. In particular, the external output message transmission FIFO 144 temporarily stores the standard trace messages input from the external output message generation unit 143 in a FIFO (First-In First-Out) and transmits the standard trace messages in the order they were input.

[0050] Internal RAM message generator 145 generates a data-amount-reduced trace message using information input from trace information controller 142. In particular, internal RAM message generator 145 generates a data-amount-reduced trace message from which privileged mode information has been deleted, as compared with the standard trace message generated by external output message generator 143. Internal RAM message generator 145 may further perform data compression on the generated data-amount-reduced trace message.

[0051] The internal RAM message generator 145 may use a process based on a known technique to convert trace data into text. For example, the internal RAM message generator 145 may perform a known process that is performed when converting trace data into a trace message in RISC-V. The internal RAM message generator 145 outputs the generated data amount reduced trace message to the internal RAM message transmission FIFO 146 .

[0052] The internal RAM message transmission FIFO 146 outputs the data volume reduced trace messages input from the internal RAM message generation unit 145 to the internal RAM 150. In particular, the internal RAM message transmission FIFO 146 temporarily stores the standard trace messages input from the internal RAM message generation unit 145 in the FIFO, and outputs the data volume reduced trace messages in the order they were input. The internal RAM 150 stores the reduced data trace message input from the internal RAM message transmit FIFO 146 .

[0053] The combination of filter control unit 141, trace information control unit 142, and external output message generation unit 143 corresponds to an example of a standard trace data acquisition means. The combination of filter control unit 141, trace information control unit 142, and external output message generation unit 143 generates a standard trace message.

[0054] The combination of the filter control unit 141, the trace information control unit 142, and the internal RAM message generation unit 145 corresponds to an example of a data amount reduced trace data acquisition means, and the combination of the filter control unit 141, the trace information control unit 142, and the internal RAM message generation unit 145 generates a data amount reduced trace message.

[0055] The external output message transmission FIFO 144 corresponds to an example of a transmission means, and transmits the standard trace message to the outside of the LSI 100. The internal RAM message send FIFO 146 corresponds to an example of a memory writing means, and stores the data amount reduced trace message in the internal RAM 150.

[0056] In addition, even if the privileged mode is changed after executing multiple instructions, the trace encoder 140 may generate a reduced data trace message in which the privileged mode information has been removed and store it in the internal RAM 150.

[0057] Fig. 10 is a diagram showing an example of a case where the privileged mode is changed after executing multiple instructions. In the example of Fig. 6, the privileged mode is changed every time the CPU 120 executes one instruction, whereas in the example of Fig. 10, the privileged mode is changed after the CPU 120 executes multiple instructions. In this way, even when the privileged mode is changed after the execution of multiple instructions, the trace encoder 140 can reduce the amount of data stored in the internal RAM 150 by generating a data-reduced trace message in which the privileged mode information has been removed.

[0058] As described above, the standard trace data acquisition means, which is a combination of the filter control unit 141, the trace information control unit 142, and the external output message generation unit 143, acquires standard trace data, which is trace data of the operation of the CPU 120, including data indicating the privileged mode of the CPU 120. The data volume reduced trace data acquisition means, which is a combination of a filter control unit 141, a trace information control unit 142, and an internal RAM message generation unit 145, acquires data volume reduced trace data, which is trace data in which information indicating the privileged mode of the CPU 120 has been deleted from the standard trace data. The external output message send FIFO 144 sends standard trace messages. The internal RAM message transmit FIFO 146 stores reduced trace messages in the internal RAM 150 .

[0059] LSI 100 can provide a relatively large amount of information and can relatively reduce the amount of data in trace messages stored in memory. In particular, LSI 100 can provide a relatively large amount of information by transmitting standard trace messages, which are trace messages that include information indicating the privileged mode of CPU 120, to the outside of LSI 100. Furthermore, LSI 100 can store data-reduced trace messages, which are standard trace messages with the information indicating the privileged mode of CPU 120 deleted, in internal RAM 150, thereby relatively reducing the amount of data in trace messages stored in internal RAM 150.

[0060] In addition, the data volume reduced trace data acquisition means, which is a combination of the filter control unit 141, the trace information control unit 142, and the internal RAM message generation unit 145, generates data volume reduced trace messages in a single step mode in which the privilege mode is switched each time the CPU 120 executes an instruction.

[0061] According to LSI100, in single-step mode in which the privilege mode is changed each time CPU120 executes an instruction, the effect of reducing the amount of data stored in internal RAM150 is expected to be particularly significant in that data volume reduction trace messages are stored in internal RAM150.

[0062] As LSI circuits become more complex, it is conceivable to equip LSIs with on-chip debug circuits to improve the efficiency of debugging LSI hardware and the programs they run. By using on-chip debug circuits to collect information such as instructions and processing time generated when the CPU executes a program, information such as which instructions the CPU is executing, how long it is taking, and the core utilization rate can be collected, and this information can be used to analyze hardware and software bugs and to speed up and optimize programs.

[0063] When an LSI is equipped with an on-chip debug circuit, it is possible to store debug information (e.g., trace messages) in the LSI's internal memory. In this case, the memory capacity of the LSI is limited, and it is possible that debug information can only be stored in memory for a portion of the CPU's program execution time. For example, if a ring buffer is used to store debug information, any debug information that exceeds the memory capacity will be overwritten by subsequent data and lost. Since debug information can only be stored in memory for a portion of the program's execution time, the information you want to check may not be stored in memory, making debugging and other tasks difficult.

[0064] In this regard, the inventors of the present application discovered that when checking the operation of a program in single-step mode, trace messages notifying privileged mode (trace messages notifying changes in privileged mode) account for a large proportion of the data stored in memory. Based on this, the inventors of the present application discovered that the amount of data could be reduced by deleting the privileged mode information from trace messages in single-step mode. For example, by reducing the trace messages that notify privileged mode, the amount of data can be reduced by more than half, and it was estimated that data for more than twice as long can be stored in memory as if no data reduction was performed.

[0065] Therefore, as described above, internal RAM message generator 145 generates trace messages with reduced data volume, in which privileged mode information is deleted compared to standard trace messages. This allows data for a relatively long period of time to be stored in internal RAM 150, which is expected to improve the efficiency of debugging, etc. In particular, in single-step mode, it is expected that the effect of reducing the amount of data will be significant by the internal RAM message generator 145 generating a data-reduced trace message in which privileged mode information has been deleted.

[0066] On the other hand, the external output message generation unit 143 generates a standard trace message including a trace message notifying the privileged mode, and transmits the standard trace message to the outside of the LSI 100 via the external output message transmission FIFO 144 . According to LSI100, a relatively large amount of information can be provided as external output with high real-time performance, and the amount of debug information stored in memory (e.g., the amount of data for the entire execution of the program) can be relatively reduced.

[0067] Second Embodiment 11 is a diagram illustrating an example of the configuration of a trace data acquisition device according to at least one embodiment. In the configuration illustrated in FIG. 11, a trace data acquisition device 610 includes a standard trace data acquisition unit 611, a data amount reduced trace data acquisition unit 612, a transmission unit 613, and a memory writing unit 614.

[0068] With this configuration, the standard trace data acquisition unit 611 acquires standard trace data, which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU. The data amount reduced trace data acquisition unit 612 acquires data amount reduced trace data, which is trace data in which information indicating the privileged mode of the CPU has been deleted from the standard trace data. The transmitter 613 transmits the standard trace data. The memory writing unit 614 stores the reduced trace data in memory.

[0069] The standard trace data acquisition unit 611 corresponds to an example of standard trace data acquisition means. The data amount reduced trace data acquisition unit 612 corresponds to an example of data amount reduced trace data acquisition means. The transmission unit 613 corresponds to an example of transmission means. The memory writing unit 614 corresponds to an example of memory writing means.

[0070] The trace data acquisition device 610 can provide a relatively large amount of information while relatively reducing the amount of trace data stored in memory. In particular, the trace data acquisition device 610 can provide a relatively large amount of information by transmitting a standard trace message, which is a trace message including information indicating the privileged mode of the CPU. Furthermore, the trace data acquisition device 610 can store a data-amount-reduced trace message, which is a standard trace message from which the information indicating the privileged mode of the CPU has been deleted, thereby relatively reducing the amount of data of the trace message stored in memory.

[0071] Third Embodiment 12 is a diagram illustrating an example of the configuration of an integrated circuit according to at least one embodiment. In the configuration shown in FIG. 12, an integrated circuit 620 includes a CPU 621, a standard trace data acquisition unit 622, a data volume reduced trace data acquisition unit 623, a transmitter 624, and a memory writer 625.

[0072] With this configuration, the standard trace data acquisition unit 622 acquires standard trace data, which is trace data of the operation of the CPU 621 and includes data indicating the privileged mode of the CPU 621 . The data amount reduced trace data acquisition unit 623 acquires data amount reduced trace data, which is trace data in which information indicating the privileged mode of the CPU 621 has been deleted from the standard trace data. The transmitter 624 transmits the standard trace data. The memory writing unit 625 stores the trace data with reduced data volume in memory.

[0073] The standard trace data acquisition unit 622 corresponds to an example of standard trace data acquisition means. The data amount reduced trace data acquisition unit 623 corresponds to an example of data amount reduced trace data acquisition means. The transmission unit 624 corresponds to an example of transmission means. The memory writing unit 625 corresponds to an example of memory writing means.

[0074] The integrated circuit 620 can provide a relatively large amount of information and can store a relatively small amount of trace data in memory. In particular, the integrated circuit 620 can provide a relatively large amount of information by transmitting a standard trace message, which is a trace message including information indicating the privileged mode of the CPU 621. Furthermore, the integrated circuit 620 can store a data-size-reduced trace message, which is a standard trace message from which the information indicating the privileged mode of the CPU 621 has been deleted, and can store a relatively small amount of data in the trace message to be stored in memory.

[0075] <Fourth embodiment> 13 is a diagram illustrating an example of a processing procedure in a trace data acquisition method according to at least one embodiment. The trace data acquisition method illustrated in FIG. 13 includes acquiring standard trace data (step S611), acquiring reduced trace data (step S612), transmitting the data (step S613), and writing the data to memory (step S614).

[0076] In acquiring standard trace data (step S611), the trace data acquisition device acquires standard trace data, which is trace data of the operation of the CPU, including data indicating the privileged mode of the CPU. In acquiring data volume reduced trace data (step S612), the trace data acquisition device acquires data volume reduced trace data, which is trace data in which information indicating the privileged mode of the CPU has been deleted from the standard trace data. In transmitting data (step S613), the trace data acquisition device transmits standard trace data. In writing data to memory (step S614), the trace data acquisition device stores the trace data with reduced data volume in memory.

[0077] The trace data acquisition method shown in Fig. 13 can provide a relatively large amount of information and can relatively reduce the amount of trace data stored in memory. In particular, the trace data acquisition method shown in Fig. 13 can provide a relatively large amount of information by transmitting a standard trace message, which is a trace message that includes information indicating the privileged mode of the CPU. Furthermore, the trace data acquisition method shown in Fig. 13 can relatively reduce the amount of data of the trace message stored in memory by storing a data-amount-reduced trace message, which is a trace message obtained by deleting the information indicating the privileged mode of the CPU from the standard trace message.

[0078] Note that a program for executing all or part of the processing performed by the trace encoder 140, the trace data acquisition device 610, the standard trace data acquisition unit 622, the data volume reduced trace data acquisition unit 623, the transmission unit 624, and the memory writing unit 625 may be recorded on a computer-readable recording medium, and the processing of each unit may be performed by executing the program recorded on the recording medium. For example, these functions or part of them may be realized by firmware. Alternatively, these functions or part of them may be performed by a CPU executing the program. The term "computer-readable recording medium" as used herein refers to portable media such as flexible disks, optical magnetic disks, ROMs (Read Only Memory), and CD-ROMs (Compact Disc Read Only Memory), as well as storage devices such as hard disks built into computer systems. It may also be a medium that can realize the above-mentioned functions in combination with a program already stored in the computer system.

[0079] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs that do not deviate from the gist of the present invention. Furthermore, the above-described embodiments can be combined with other embodiments as appropriate.

[0080] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0081] (Appendix 1) standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU, including data indicating a privileged mode of the CPU; a data amount reduced trace data acquisition means for acquiring data amount reduced trace data, which is trace data obtained by deleting information indicating the privileged mode of the CPU from the standard trace data; a transmitting means for transmitting the standard trace data; a memory writing means for storing the data amount reduced trace data in a memory; Equipped with a trace data acquisition device.

[0082] (Appendix 2) the standard trace data acquisition means generates the standard trace message in a single step mode in which the privileged mode is switched every time the CPU executes an instruction, the reduced-data-volume trace data acquisition means generates the reduced-data-volume trace message in the single-step mode; Trace data acquisition equipment as described in Appendix 1.

[0083] (Appendix 3) the reduced-data-amount trace data acquisition means generates the reduced-data-amount trace message when the privileged mode is changed after the CPU executes a plurality of instructions; Trace data acquisition equipment as described in Appendix 1.

[0084] (Appendix 4) CPU and standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU, including data indicating a privileged mode of the CPU; a data amount reduced trace data acquisition means for acquiring data amount reduced trace data, which is trace data obtained by deleting information indicating the privileged mode of the CPU from the standard trace data; a transmitting means for transmitting the standard trace data; a memory writing means for storing the data amount reduced trace data in a memory; 1. An integrated circuit comprising:

[0085] (Appendix 5) the standard trace data acquisition means generates the standard trace message in a single step mode in which the privileged mode is switched every time the CPU executes an instruction, the reduced-data-volume trace data acquisition means generates the reduced-data-volume trace message in the single-step mode; 1. The integrated circuit described in Appendix 4.

[0086] (Appendix 6) the reduced-data-amount trace data acquisition means generates the reduced-data-amount trace message when the privileged mode is changed after the CPU executes a plurality of instructions; 1. The integrated circuit described in Appendix 4.

[0087] (Appendix 7) Trace data acquisition device, acquiring standard trace data, the standard trace data being trace data of the operation of the CPU, including data indicating a privileged mode of the CPU; acquiring reduced-data trace data, which is trace data in which information indicating a privileged mode of the CPU has been deleted from the standard trace data; said transmitting standard trace data; storing said data volume reduced trace data in a memory; Trace data acquisition methods, including:

[0088] (Appendix 8) Acquiring the standard trace data includes generating the standard trace message in a single-step mode in which the privileged mode is switched as the CPU executes each instruction; obtaining the reduced-data trace data includes generating the reduced-data trace message in the single-step mode; Trace data acquisition method described in Appendix 7.

[0089] (Appendix 9) generating the reduced-data trace message if the privileged mode is changed after the CPU executes a plurality of instructions, Trace data acquisition method described in Appendix 7.

[0090] (Appendix 10) Integrated circuits including CPUs acquiring standard trace data that is trace data of the operation of the CPU, the standard trace data including data indicating a privileged mode of the CPU; acquiring reduced-data-volume trace data, which is trace data obtained by deleting information indicating a privileged mode of the CPU from the standard trace data; transmitting said standard trace data; storing the reduced trace data in a memory; A program that executes the following.

[0091] (Appendix 11) acquiring the standard trace data includes causing the integrated circuit to generate the standard trace messages in a single step mode in which the privileged mode is switched for each instruction executed by the CPU; obtaining the reduced-data trace data includes causing the integrated circuit to generate the reduced-data trace message in the single-step mode; 10. The program described in Appendix 10.

[0092] (Appendix 12) obtaining the reduced-data trace data includes causing the integrated circuit to generate the reduced-data trace message if the privileged mode is changed after the CPU executes a plurality of instructions; 10. The program described in Appendix 10. [Explanation of symbols]

[0093] 100 LSI 110 Debugging target circuit 120,621 CPU 130 On-chip debug circuit 140 Trace Encoder 141 Filter control section 142 Trace information control section 143 External output message generation unit 144 External output message transmission FIFO 145 Internal RAM message generator 146 Message transmit FIFO for internal RAM 150 internal RAM 610 Trace data acquisition device 611, 622 Standard trace data acquisition unit 612, 623 Data volume reduction trace data acquisition section 613, 624 Transmitting unit 614, 625 Memory writing unit 620 Integrated Circuits

Claims

1. standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU, including data indicating a privileged mode of the CPU; a data amount reduced trace data acquisition means for acquiring data amount reduced trace data, which is trace data obtained by deleting information indicating the privileged mode of the CPU from the standard trace data; a transmitting means for transmitting the standard trace data; a memory writing means for storing the reduced trace data in a memory; A trace data acquisition device comprising:

2. the data amount reduced trace data acquisition means generates the data amount reduced trace message in a single step mode in which the privileged mode is switched every time the CPU executes one instruction.

2. The trace data acquisition device according to claim 1.

3. the reduced-data-amount trace data acquisition means generates the reduced-data-amount trace message when the privileged mode is changed after the CPU executes a plurality of instructions; 2. The trace data acquisition device according to claim 1.

4. A CPU and standard trace data acquisition means for acquiring standard trace data, which is trace data of the operation of the CPU, including data indicating a privileged mode of the CPU; a data amount reduced trace data acquisition means for acquiring data amount reduced trace data, which is trace data obtained by deleting information indicating the privileged mode of the CPU from the standard trace data; a transmitting means for transmitting the standard trace data; a memory writing means for storing the reduced trace data in a memory; 1. An integrated circuit comprising:

5. A trace data acquisition device acquiring standard trace data that is trace data of the operation of the CPU, including data indicating a privileged mode of the CPU; acquiring reduced-data-volume trace data, which is trace data obtained by deleting information indicating the privileged mode of the CPU from the standard trace data; transmitting said standard trace data; storing the reduced trace data in a memory; A trace data acquisition method comprising:

6. In an integrated circuit including a CPU, acquiring standard trace data that is trace data of the operation of the CPU, including data indicating a privileged mode of the CPU; acquiring reduced-data-volume trace data, which is trace data obtained by deleting information indicating a privileged mode of the CPU from the standard trace data; transmitting said standard trace data; storing the reduced trace data in a memory; A program that executes the following.

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