Semi-active magnetic shielding for qubit unit components of quantum computing devices

Abstract

1. A computer-implemented method for reducing the effects of stray magnetic fields on components of a quantum computing chip, comprising: applying a first current signal to a first component of a quantum computing chip, whereby the first component generates a stray magnetic field that affects the operation of a second component of the quantum computing chip; and applying a compensation current signal to a shielding circuit of the quantum computing chip to magnetically shield the second component from the stray magnetic field generated by the first component, the compensation current signal being generated according to a predetermined function of the first signal. A computer-implemented method comprising:

Description

[Technical Field]

[0001] The present invention relates generally to quantum processing devices and methods of operating such devices, and more particularly to a method of operating a quantum processing device, wherein a compensation current signal is applied to a shielding circuit to magnetically shield a given component of a qubit chip from stray magnetic fields generated by adjacent components on the qubit chip. [Background technology]

[0002] Recent advances in quantum-enhanced sensing and quantum computing make these technologies increasingly relevant for industrial applications. Both quantum sensing and quantum computing directly exploit quantum mechanical phenomena such as superposition and entanglement. Quantum sensing aims to increase the accuracy of measurement devices, while quantum computers perform operations on entangled data. Superconducting circuits are relatively easy to fabricate using current technology and are therefore promising candidates for further expanding quantum information technology. Quantum computers with superconducting qubits that have limited or no error correction are already available. Such quantum computers are capable of simulating systems that are intractable to classical computers. Summary of the Invention

[0003] According to one embodiment of the present invention, a computer-implemented method for reducing the effects of stray magnetic fields on a component of a quantum computing chip is disclosed. The computer-implemented method includes applying a first current signal to a first component of the quantum computing chip, whereby the first component generates a stray magnetic field that affects the operation of a second component of the quantum computing chip. The computer-implemented method further includes applying a compensation current signal to a shielding circuit of the quantum computing chip to magnetically shield the second component from the stray magnetic field generated by the first component, the compensation current signal being generated according to a predetermined function of the first signal.

[0004] According to another embodiment of the present invention, a computer system for reducing the effects of stray magnetic fields on components of a quantum computing chip is disclosed. The computer system includes one or more computer processors, one or more computer-readable storage media, and computer program instructions stored on the one or more computer-readable storage media for execution by the one or more computer processors. The program instructions include instructions for applying a first current signal to a first component of a quantum computing chip to operate the first component, whereby operation of the first component generates a stray magnetic field that affects operation of a second component of the quantum computing chip. The program instructions further include instructions for applying a compensation current signal to a shielding circuit of the quantum computing chip to magnetically shield the second component from the stray magnetic field generated by the first component, the compensation current signal being generated according to a predetermined function of the first signal.

[0005] According to another embodiment of the present invention, a quantum computing device for reducing the effects of stray magnetic fields on components of a quantum computing chip is disclosed. The quantum computing device includes a qubit unit having a shielding circuit, a first component, and a second component. The quantum computing device further includes a control unit operatively connected to each of the first component and the shielding circuit to (i) apply a first current signal to the first component of the quantum computing chip to operate the first component, whereby operation of the first component generates a stray magnetic field that affects operation of a second component of the quantum computing chip, and (ii) apply a compensation current signal to the shielding circuit of the quantum computing chip to magnetically shield the second component from the stray magnetic field generated by the first component, the compensation current signal being generated according to a predetermined function of the first signal.

[0006] Apparatus and methods embodying the present invention will now be described, by way of non-limiting example, and with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0007] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of this specification. The invention, both as to organization and method of operation, together with its objects, features, and advantages, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

[0008] In the drawings, where like reference characters refer to identical or functionally similar elements throughout the separate views, the accompanying drawings, which together with the following detailed description are incorporated in or form a part of this specification, further illustrate various embodiments and serve to explain various principles and advantages of the present disclosure in its entirety.

[0009] [Figure 1]FIG. 1 illustrates selected components of a quantum processing device in accordance with at least one embodiment of the present invention.

[0010] [Figure 2]

[0013] Figure 2 illustrates selected components of a quantum processing device in accordance with at least one embodiment of the present invention. Figure 2 is similar to Figure 1, except that it further includes a shielding circuit including a compensation loop surrounding a component of the qubit unit to shield this component from stray magnetic fields generated by adjacent components.

[0011] [Figure 3A] 3 is a contour plot obtained by simulating a qubit chip including two adjacent components in a configuration similar to that shown in FIG. 2, in accordance with at least one embodiment of the present invention. [Figure 3B] 3A-3B are contour plots obtained by simulating a qubit chip including two adjacent components in a configuration similar to that shown in FIG. 2 , in accordance with at least one embodiment of the present invention. The plots represent contour lines of the strength of the stray magnetic field generated by the left-hand side (LHS) component in a plane perpendicular to the major plane of the qubit chip. While FIG. 3A shows the contours of the magnetic field strength in the absence of any magnetic shielding, FIG. 3B shows the contours of the magnetic field strength when the stray field generated by the LHS component is locally shielded at the level of the right-hand side (RHS) component by applying a compensating current signal to a loop of shielding circuitry surrounding the RHS component.

[0012] [Figure 4] 10A-10C schematically illustrate a compensation circuit loop surrounding a circuit portion for a first component (located on the LHS) of a qubit unit for shielding a second component (located on the RHS) from stray magnetic fields generated by the first component, in accordance with at least one embodiment of the present invention.

[0013] [Figure 5A] 1 illustrates various shielding circuit configurations according to various embodiments of the present invention, where the shielding circuit includes both a compensation circuit and a shaping circuit. [Figure 5B] 1 illustrates various shielding circuit configurations according to various embodiments of the present invention, where the shielding circuit includes both a compensation circuit and a shaping circuit. [Figure 5C] 1 illustrates various shielding circuit configurations according to various embodiments of the present invention, where the shielding circuit includes both a compensation circuit and a shaping circuit. [Figure 5D] Figures 5A-5D show various shielding circuit configurations according to various embodiments of the present invention, where the shielding circuit includes both a compensation circuit and a shaping circuit. The compensation circuit, as seen in the embodiment, includes a loop surrounding an additional loop of the shaping circuit, which in turn surrounds the field-emitting component of the qubit chip. Figure 5A shows a configuration in which the compensation circuit loop and the additional loop are all connected in parallel with the first circuit of the field-emitting component. In Figure 5B, the additional loop of the shaping circuit is connected in series with the first circuit, while the compensation circuit loop is connected in parallel with the first circuit. Figures 5C-5D show variations in which the loops are all connected in series with the first circuit of the field-emitting component.

[0014] [Figure 6] FIG. 1 illustrates selected components of a quantum processing device in accordance with at least one embodiment of the present invention, in which a control unit is connected to both a shielding circuit and a field emission component via a coupler (capacitive voltage divider or transmission line coupler).

[0015] [Figure 7A] FIG. 1 is a diagram of the layout of an actual superconducting qubit chip according to various embodiments of the present invention, in which two transmon-type, computation qubits are coupled via a tunable coupler, such that the computation qubits may be subject to stray magnetic fields emitted by the tunable coupler during operation. [Figure 7B]7A-7B are diagrams of layouts of actual superconducting qubit chips according to various embodiments of the present invention, where two transmon-type, computation qubits are coupled via tunable couplers, whereby the computation qubits may be subject to stray magnetic fields emitted by the tunable couplers during operation. Figure 7A shows a qubit chip including shielding circuitry coiled around each of the computation qubits, while Figure 7B shows shielding circuitry coiled around only one tunable coupler. In both cases, the shielding circuitry shields the computation qubits from stray magnetic fields generated by the tunable couplers, according to embodiments of the present invention.

[0016] [Figure 8] 1 is a flowchart illustrating high-level steps in a method of operating a quantum processing device in accordance with at least one embodiment of the present invention.

[0017] [Figure 9] 9 is a block diagram illustrating components of a computer suitable for performing operations to reduce the effects of stray magnetic fields on components of a quantum computing chip in accordance with at least one embodiment of the present invention, generally designated 900. For example, computer 900 may be representative of various computing components that implement various processes, such as those included in FIGS. 1, 2, and 6 and described with respect to FIG. 8, in accordance with various embodiments of the present invention.

[0018] The accompanying drawings show simplified representations of devices or parts as included in the embodiments. The technical features depicted in the drawings are not necessarily drawn to scale. In particular, the layouts of the qubits and tunable couplers shown in Figures 7A and 7B are not drawn to scale. Similar or functionally similar elements in the figures are assigned the same reference numerals unless otherwise specified. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention relates generally to quantum processing devices and methods of operating such devices, and in particular to a method of operating a quantum processing device, where a compensation current signal is applied to a shielding circuit to magnetically shield a given component of a qubit chip from stray magnetic fields generated by adjacent components on the qubit chip.

[0020] Embodiments of the present invention recognize that qubits are highly sensitive to external magnetic fields. This is particularly true for superconducting qubits, especially where direct current (DC) magnetic fields are used to tune the frequency of individual computation qubits and / or alternating current (AC) fields are used to adjust tunable couplers. Embodiments of the present invention further recognize that stray magnetic fields and crosstalk from neighboring qubits or transmission lines can also affect the qubits, which is undesirable. Typically, with higher integration levels, the numerical value is expected to move to lower limits.

[0021] Magnetic shielding solutions have been developed for quantum computers. Such solutions rely on static magnetic shielding or active shielding of external stray fields, i.e., they aim to protect the entire quantum processing mechanism.

[0022] Embodiments of the present invention use active magnetic shielding to minimize the magnetic field outside of the required region or to locally minimize the magnetic field on neighboring qubits. Embodiments of the present invention recognize that flux tunability is an advantage in constructing dynamic couplers. Such couplers can be used between charge or flux qubits to enhance gate speeds. Embodiments of the present invention recognize that flux-tunable elements create stray magnetic fields that interact with other and / or neighboring SQUIDs. Significantly, flux-tunable elements would be attractive if the stray fields could be controlled. Embodiments of the present invention produce a significant localized reduction in stray magnetic fields.

[0023] Embodiments of the present invention ameliorate the aforementioned deficiencies by making the stray fields scale linearly with the current applied to the intended magnetic field. As a result, no feedback loop is required, and scaled compensation currents are used to minimize undesired stray fields. Embodiments of the present invention further ameliorate the aforementioned deficiencies by simplifying compensation. Embodiments of the present invention have all qubits and coils in one plane, resulting in fields on the chip surface all being in the z-direction. Embodiments of the present invention are integrated on-chip without the need for additional materials. Embodiments of the present invention use local crosstalk compensation to result in fewer frequency crowding effects. Embodiments of the present invention also use local shielding of stray fields, such as those of neighboring qubits. Embodiments of the present invention use frequency-selective shielding. Embodiments of the present invention use signals that generate known magnetic fields of aggressors. In these embodiments of the present invention, compensation coils can derive the current or shape to shield the victim, and no sensors or control loops are required. In embodiments of the present invention, the magnetic field scales the current linearly, resulting in a compensation current that is proportional to the aggressor current. In embodiments of the present invention, fine grain size resolution enables compensation for effects at small dimensions, such as microns.

[0024] Embodiments of the present invention include one or more combinations of local magnetic shielding, magnetic shielding outside the coil, scaled currents for field cancellation, and field cancellation by identical currents, geometric scaling.

[0025] The present invention may be a system, method, and / or computer program product integrated at any possible level of technical detail. The computer program product may include a computer-readable storage medium or media having computer-readable program instructions for causing a processor to carry out aspects of the present invention.

[0026] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may include the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves with instructions recorded on them, and any suitable combination of the foregoing. Computer-readable storage medium, as used herein, should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted through a wire.

[0027] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may comprise copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0028] Computer-readable program instructions for carrying out operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the present invention.

[0029] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0030] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to create a machine, whereby the instructions executing on the processor of the computer or other programmable data processing apparatus generate means for implementing the function(s) / act(s) specified in the block(s) of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, whereby the computer-readable storage medium having the instructions stored thereon has an article of manufacture including instructions that implement aspects of the function(s) / act(s) specified in the block(s) of the flowcharts and / or block diagrams.

[0031] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a sequence of operations to be executed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device implement the function / operation specified in the block or blocks of the flowcharts and / or block diagrams.

[0032] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of special-purpose hardware and computer instructions.

[0033] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications of, or technical improvements to, the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0034] The following description is structured as follows: First, general embodiments and advanced variants are described in Section 1. Section 2 addresses more specific embodiments and technical implementation details, including a detailed description of the accompanying drawings. Note that the method and its variants are collectively referred to as "the method." Similarly, the apparatus and its variants are collectively referred to as "the apparatus." All references Sn (e.g., S5, S10, etc.) refer to steps in the method of the flowchart of FIG. 8, while the reference numbers relate to physical parts or components of the apparatus shown, for example, in FIGS. 1, 2, and 6.

[0035] 1. General embodiments and advanced variations 2 through 7B, an aspect of the present invention will first be described relating to a method of operating a quantum processing device, such as quantum processing device 1 and 1a, which may be a quantum computer or a quantum sensing device. The following describes essential features of this method.

[0036] Quantum processing devices 1 and 1a are assumed to have a qubit unit, e.g., a qubit chip. The qubit unit is generally designated by reference numeral 20 in the accompanying drawings. References 20p, 20, 20a, 20b, and 20c indicate possible variations of such a qubit unit, as seen in FIGS. 1, 2, 6, 7A, and 7B. The qubit unit includes, among other things, two components 21, 22: a first component 21 and a second component 22. For example, the first component 21 may be a tunable coupler, while the second component 22 may be a computation qubit. In one embodiment, the tunable coupler is used to apply the gate sequence. Further examples are described in detail below with reference to other aspects of the invention.

[0037] Furthermore, qubit unit 20 includes shielding circuits 31-33s, or at least a portion of such shielding circuits. Shielding circuits may, for example, include one or more loops (i.e., spirals or coils) that at least partially surround one or both of components 21, 22. Such loops may also be referred to herein as "compensation loops." Compensation loops are generally designated by reference numeral 31 in the accompanying drawings. References 31, 31p, 31s, 31c, 31v, and 31a indicate possible variations in the configuration of such compensation loops, as can be seen in FIGS. 2 through 7B. As will be explained later with reference to FIGS. 5A-5D, shielding circuits may optionally include shaping circuits, where the latter include additional loops intended to shape stray fields.

[0038] 2 and 6, the shielding circuitry 31, 31c includes a compensation loop that partially surrounds the second component 22 in the plane (x, y) of the qubit chip 20, 20a. Further examples are described in detail below, in which the shielding circuitry includes a compensation loop that surrounds the first component 21 instead of the second component 22.

[0039] The method comprises applying a first current signal to a first component 21. Furthermore, a second signal (current or voltage) may typically be applied to a second component 22, as envisaged below. The applied signal is typically intended to operate the two components 21, 22 in a quantum process (see steps S10 and S20 in the flow of FIG. 8). In practice, such signals are repeatedly applied, for example to drive couplers and / or qubits.

[0040] In one embodiment, first component 21 is assumed to generate a stray magnetic field as a result of the applied first signal. The resulting stray magnetic field is further assumed to affect the operation of second component 22 during operation of a quantum processing device, such as quantum computing devices 1 and 1a. For this reason, first component 21 is sometimes referred to as the "aggressor," while second component 22 is sometimes referred to herein as the "victim."

[0041] To address this issue, the method further comprises applying (at step S30) a compensation current signal to the shielding circuit 31-33s to magnetically shield the second component 22 from the stray magnetic field generated by the first component 21. Note that the signals applied at steps S10 and S20 may be applied simultaneously or non-simultaneously, depending on the desired operation of the components 21, 22. However, steps S10 and S30 are typically performed simultaneously to achieve the desired shielding effect. The compensation current signal applied at step S30 may possibly be obtained as a result of the step of applying the first signal (step S10) due to a preferred configuration of the shielding circuit, as will be described in detail later with reference to another aspect of the present invention. In that case, steps S10 and S30 are not only simultaneous but also synchronous.

[0042] The compensation current signal applied in step S30 is a signal generated according to a predetermined function of the first signal. The predetermined function is fixed due to the configuration of the shielding circuit and the means by which the compensation signal is generated by the signal generator 14. This predetermined function is at least partially effected by the shielding circuits 31-33s. The predetermined function can also be considered a binary relationship (in a mathematical sense). However, the predetermined function is a manifestation of the shielding circuit and, if necessary, other components of the device. In other words, the shielding circuit and, if necessary, other components of the device (for generating the compensation signal) are jointly configured to ensure a specific correspondence between the first current signal and the compensation current signal.

[0043] The first signal is typically generated by signal generator 14 of control unit 12, 14 and applied to first component 21 via a first circuit. The shielding circuit may optionally be separate from this first circuit, as envisioned in FIG. 2 , where shielding circuit 31 is separate from circuit 20c connecting qubit unit 20. However, in variants, the shielding circuit is connected in parallel or in series to first circuit 21c, as shown in FIGS. 4 to 7 . In all cases, the proposed configuration of the shielding circuit results in a very simple circuit layout. Furthermore, connecting the shielding circuit to the first circuit, e.g., directly at the qubit unit, allows for a reduction in the number of connectors and wires required from signal generator 14, e.g., to save footprint on the qubit chip.

[0044] Due to the predetermined function enabled by the shielding circuit, the applied compensation signal locally shields the stray magnetic field, thereby making it possible to protect the second component without the need for any sensors or feedback loops as required in previous active solutions. It should be noted that although the above method is described with reference to a single pair of components (aggressor and victim), it will be clear to those skilled in the art that the method can be applied to multiple aggressor-victim pairs (simultaneously or not).

[0045] Since the first current signal generating the stray magnetic field has been identified by the control units 12, 14, the compensation current applied to the shielding circuit and / or the shape of the shielding circuit (e.g., including the compensation loop) can be optimized to reduce or cancel the residual magnetic field at the level of the second component (victim) without the need for any sensors or control loops. Indeed, the magnetic field strength scales linearly with the current, and therefore the compensation current can be set proportional to or equal to the first current to achieve the desired shielding effect. Furthermore, as mentioned above, the shielding circuit typically includes one or more loops, the shape of which can be optimized to reduce or cancel the stray field at the level of the victim 22. Furthermore, the resolution (submicron level) that can be achieved for the loops allows stray fields to be compensated on a small scale (e.g., a few microns).

[0046] Methods of operating quantum processing devices typically rely on (i) static magnetic shielding; or (ii) active shielding of the entire quantum device from external stray fields using Helmholtz coils and field sensors in close proximity to the qubit unit. In contrast, the present solution is local, i.e., it acts locally around the victim component. It is not a static solution insofar as the locally applied compensation signal depends on the signal applied to the aggressor 21. Nor is it an active solution insofar as it does not require sensors and feedback loops. Rather, embodiments of the present invention can be considered a semi-active solution, aimed at protecting a victim component 22 (e.g., a computation qubit) by locally shielding stray magnetic fields arising from neighboring components 21 (e.g., a computation qubit or tunable coupler).

[0047] It should be noted that the proposed approach is primarily aimed at shielding stray fields generated at the level of qubit unit 20 (e.g., on the qubit chip), rather than stray fields generated outside the qubit unit. However, the shielding circuitry could potentially be designed to additionally compensate for fixed stray fields generated outside qubit unit 20, if required.

[0048] Embodiments of the present invention can be integrated with qubit chips without requiring additional (e.g., incompatible) materials or substantial modifications to the fabrication methods used to fabricate the qubit chips. A compensation circuit is required (compare FIGS. 1 and 2), which is preferably realized using the same processing techniques used to obtain qubit unit 20p of FIG. 1. That is, the same type of conductor (or superconductor) used for the rest of the qubit unit (e.g., qubit chip) can be relied upon to obtain shielding circuits 31-33s. In particular, shielding circuits can be fabricated using the same lithography masks used to fabricate other conductors and structures required on the qubit chip. Typical dimensions of such conductors are on the micrometer scale, with sub-micrometer resolution.

[0049] Interestingly, this approach can also be used to achieve local crosstalk compensation, which results in a reduction of the frequency crowding effect at the level of the victim, i.e., the second component 22. Nevertheless, the proposed solution does not affect the frequency of the victim component.

[0050] Additional features of the method are implicitly addressed in the remainder of the description which concerns another aspect of the invention, namely the quantum processing device 1, 1a, which is now described in detail with reference to Figures 2 to 6.

[0051] As described above, the apparatus comprises a qubit unit 20 having shielding circuits 31-33s and two components 21, 22: a first component 21 (aggressor) and a second component 22 (victim). Consistent with the present method, the apparatus further comprises control units 12, 14 operably connected to first component 21 and shielding circuits 31-33s, respectively, so as to be able to apply current signals S10, S30 to them. The control units may, if desired, be further connected to second component 22 so as to be able to apply signals to operate this component as envisaged below.

[0052] During operation, the first current signal and the second signal (current and voltage) are applied to the first component 21 and the second component 22, respectively, to operate the two components 21, 22. This causes the first component 21 to generate a stray magnetic field that affects the operation of the second component 22 during operation of the device. To address this issue, the device is further configured to apply a compensation current signal to the shielding circuitry 31-33s so as to magnetically shield the second component 22 from the stray magnetic field generated by the first component 21. The compensation current signal is generated according to a predetermined function of the first signal, where, as explained above, this function is developed by the shielding circuitry and possibly other components of the device (e.g., components of the control units 12, 14).

[0053] The control units 12, 14 may comprise, inter alia, a controller 12 and one or more signal generators 14. The controller 12 is connected to the signal generators 14, where the latter is connected on the one hand to the shielding circuitry and on the other hand to the components 21, 22 of the qubit unit via respective circuits. In the example of Figure 2, a single signal generator 14 is used, which is connected to the shielding circuitry 31 and to the components 21, 22 (via circuit 20c).

[0054] The apparatus of the present invention is generally described for simplicity with reference to only two components 21, 22, namely, an aggressor and a victim. However, qubit unit 20 may have 10 or 100 components, or more, and the present principles may optionally be applied to any number of potential aggressors and victims in a qubit unit. In one embodiment, shielding circuitry may be configured to shield some components, or several shielding circuits may be provided to achieve this.

[0055] Each of the two components 21, 22 can be, for example, a fixed frequency superconducting qubit (for example of the transmon type), a tunable coupler (for coupling fixed frequency transmon qubits), or indeed just a Josephson junction.

[0056] In one embodiment, the potential victims are fixed-frequency quantum circuits 22, 23, i.e., circuits configured as computational qubits in the device. Each of the quantum circuits 22, 23 may be further coupled to a tunable coupler 21. The frequency of the tunable coupler 21 can be adjusted, for example, to drive selectively addressable energy transitions in the quantum processing device. The tunable coupling element may be embodied, for example, as a frequency-tunable superconducting qubit, i.e., involving a SQUID loop. Each of the quantum circuits 22, 23 is typically a nonlinear quantum circuit, which may be used as a computational qubit. "Nonlinear" means that the quantum circuit is capable of addressing at least two distinct energy levels (i.e., of different energies). However, the fixed-frequency quantum circuit may also be a harmonic oscillator in a variant. The tunable coupler 21, acting as a frequency-tunable coupling element, may also generate unwanted stray fields, thus potentially creating a disadvantage to the proposed solution.

[0057] It should be noted that a “superconducting” element is an element that can potentially become superconducting under certain conditions. Accordingly, a component (e.g., a superconducting qubit, channel, circuit, etc.) referred to herein as a superconducting component is a component that includes one or more potentially superconducting materials. That is, such materials may include, for example, aluminum (Al) or titanium nitride (TiN), which can become superconducting under certain conditions of temperature and magnetic field. Accordingly, if a qubit unit is a superconducting unit (e.g., a chip including a superconductor), the qubit unit may include a first circuit (e.g., circuit 21c) connected to the aggressor 21, a second circuit (e.g., circuit 22c) connected to the victim, and at least a portion of the shielding circuits 31-33s, where such circuit portions can potentially become superconducting.

[0058] However, beyond transmons, other types of superconducting qubits, including exmon and gatemon qubits, may potentially benefit from this approach. It will be apparent to those skilled in the art that in addition to superconducting qubit units, this approach may be suitably applied to other solid-state qubit architectures, including spin-based quantum circuits (or spin qubits for shorts) and topological qubits.

[0059] As shown in Figures 4-7B, a first current signal is typically applied S10 to a first component 21 via a first circuit 21c. A terminal portion of this circuit 21c may typically be considered to actually form part of the first component 21, as in Figures 6, 7A, and 7B, where the terminal portion of the flux line 21c can be considered to form part of the tunable coupler 21. In one embodiment, the central loop 21c seen in Figures 5A-5D forms part of a tunable coupler or Josephson junction.

[0060] In one embodiment, the shielding circuits 31-33s are connected to the first circuit 21c to enable the device to implement the predetermined functions described above. For example, the shielding circuit may include a loop connected in series with the circuit portion 21c, see, for example, loop 31s in FIGS. 5C and 5D. In a variant, the shielding circuit may include a loop connected in parallel with the circuit portion 21c, see, for example, loops 31p, 31c, 31v, and 31a in FIGS. 4, 5A, 5B, 6, 7A, and 7B. The parallel connection results in the same current being applied in the circuit portion 21c and in the compensation loops 31p, 31c, 31v, and 31a with respect to the superconducting circuit. The series connection ensures the same current in the two circuits, regardless of their respective resistances.

[0061] More generally, several configurations can be contemplated for the shielding circuit that result in the compensation current signal applied at S30 having the same amplitude as the first current signal applied at S10. In a variant, the shielding circuit can be designed to ensure that the compensation current signal applied at S30 has an amplitude that is scaled with respect to the amplitude of the first current signal applied at S10. This may be achieved, inter alia, using the arrangement shown in FIG. 2, for example, where the shielding circuit is separate from the circuit 20c connecting the qubit unit 20 to the control units 12, 14. In both cases, the shielding circuit can be configured to further ensure that the compensation current signal and the first current signal have synchronized frequencies and phases to ensure cancellation of stray fields.

[0062] In addition to the first circuit connecting to the first component 21, the quantum processing device 1, 1a may include one or more second circuits 22c connecting the components 22, 23 of the qubit unit 20, 20a, as shown in FIGS. 6, 7A, and 7B. In the context of a superconducting qubit chip, the circuits 21c and 22c optionally include channels configured as couplers / resonators. Similar to the circuit 20c in FIG. 2, the circuits 21c and 22c are used to apply first and second signals to the first component 21 and the second component 22, 23 during operation. Separate signals are typically applied to the second components 22, 23, e.g., qubits. The signals applied to the qubits via the circuits 20c, 22c may typically result in signals transmitted along a transmission line that couples one qubit 23 to another qubit 22 via a tunable coupler 21, as seen in the examples of FIGS. 6, 7A, and 7B.

[0063] 6, the control units 12, 14 are connected to a first component 21 via a first circuit 21c and further connected to a second component 22, 23 via a second circuit 22c. The shielding circuit 31c and the first circuit 21c are connected in parallel to the control units 12, 14 to effect a predetermined function. Since the first circuit 21c and the shielding circuit 31c are superconducting circuits in this example, the parallel connection ensures identical currents in each circuit path.

[0064] In one embodiment, the control units 12, 14 include a single signal generator 14 connected to each of the shielding circuit 31c, the first circuit 21c, and the second circuit 22c. In one embodiment, the signal generator 14 is connected to each of the shielding circuit 31c and the first component 21c via a coupler 40, which may be, for example, a capacitive voltage divider or a transmission line coupler, to effect a predetermined function. Capacitive voltage dividers and transmission line couplers are known to those skilled in the art. However, the physics of the coupling mechanism vary despite the depiction used in FIG. 6.

[0065] It should be understood that other parallel configurations may be contemplated, such as those shown in Figures 4, 5A, and 5B, in which the shielding circuit essentially has a loop 31p surrounding the first circuit 21c. In such instances, the loop 31p simply connects in parallel from the first circuit 21c or from a conductor leading to the first circuit 21c.

[0066] Besides parallel configurations, a simple series configuration may be contemplated, in which compensation loop 31s is connected in series with the conductor connecting to first circuit 21c, as shown in Figures 5C and 5D. Note that in the circuit layouts shown in Figures 4-5D, signal generator 14 is connected directly or indirectly to first circuit 21c, while the loops of shielding circuits 31-33s connect (in parallel and / or in series) to first circuit 21c within the qubit unit (e.g., on the qubit chip).

[0067] 4-7B, first component 21 and second component 22 are disposed in essentially the same plane (x,y) of qubit unit 20, i.e., the main plane of the qubit chip. In each of FIGS. 4, 5A-5D, 6, and 7B, the shielding circuitry has an outer loop that surrounds first component 21 (the aggressor) in the plane (x,y). In a variant, some or all of the loops of the shielding circuitry may be formed on another layer or another side of the chip, i.e., in a plane that is separate from, but still parallel to, and close to, the plane (x,y) in which components 21, 22, and 23 are disposed.

[0068] In contrast, in Figures 2, 3A, 3B, and 7A, the loop of the shielding circuit surrounds the second component 22, 23, i.e., the victim. The shielding circuit includes a single loop in Figures 2-6. More generally, the shielding circuit may include one or more compensation loops that surround one or each of the components 21, 22, 23, respectively, in the plane (x,y), or in a plane parallel to but very close to the plane (x,y), e.g., with reference to Figure 7A. However, due to circuit layout constraints, such loops may not completely surround each of those components as envisioned in the accompanying drawings. Also, as shown in Figure 7A, the compensation circuit may also include several loops that are coiled to surround two or more of the potential victims 22, 23, respectively.

[0069] 5A-5D, the shielding circuits 31-33s include both compensation circuits and shaping circuits 32p-33s. The compensation circuits include outer loops 31p, 31s surrounding an inner loop. The inner loop may include, among other things, two or more additional loops 32p-33s of the shaping circuit, where each of the additional loops 32p-33s surrounds the first component 21 (including its loop 21c) in the plane of the chip. In such an example, the additional loops are coiled around the aggressor 21 to shape the stray field emitted by the latter.

[0070] The shaping circuit loops 32p-33s are preferably located in the same plane as the compensation circuit loops 31p, 31s. The resulting loops 31p, 31s, 32p, 32s, 33p, 33s may all be concentric, with the outer compensation loop 31p, 31s surrounding two or more additional loops 32p-33s in the plane of the chip. In one embodiment, the geometries of these loops are jointly optimized (e.g., by trial and error using simulation, as performed in FIGS. 3A and 3B) to minimize stray field strength at the victim location.

[0071] As further shown in FIG. 4, the current direction in the compensation loop 31p is typically opposite to that in the inner loop 21c included in the aggressor. Similarly, in FIGS. 5A-5D, the shielding circuit is designed so that the applied current signal circulates according to the same rotational direction in the shaping circuit loops, while the currents flowing in the outer loops 31p, 31s have opposite rotational directions. Further designs may be obtained, for example, by providing alternating rotational directions for current flow to appropriately modify the residual magnetic field strength at the victim level. In an embodiment, some loops may surround the aggressor to shape the magnetic field, while the compensation loop surrounds the victim (not shown).

[0072] In one embodiment, the compensation signal applied to the shielding circuit may be equal (in amplitude) to the first current or scaled with respect to the first current. To that end, the shielding circuit may be connected in parallel or in series to the first circuit. Thus, the first current signal and the compensation current signal may each possibly be applied as one and the same initial current signal. Furthermore, this initial signal ultimately reaches separate components 21, 22, 23, which, among other things, result in the first current (applied to the aggressor) and the compensation current (applied to the compensation loop).

[0073] The above embodiments have been briefly described with reference to the accompanying drawings and may include numerous variations. Several combinations of the above-described features may be contemplated. Examples are given in the following sections.

[0074] 2. Detailed description of specific embodiments, technical implementation details, and drawings 2.1 Description of a preferred quantum circuit Preferably, the quantum circuits 22, 23 (i.e., potential "victim" qubits) are embodied as superconducting quantum circuits and form the fundamental computational elements. The devices 1, 1a are typically designed to operate in the radio frequency spectrum and must be cooled, typically using a dilution refrigerator, down to temperatures below 100 mK. Nevertheless, the components of the device can be accommodated with conventional electronics. In one embodiment, the quantum processing device 1, 1a comprises a large number of solid-state qubits, typically in the range of 50-400 qubits. In one embodiment, the quantum device may include fewer or larger numbers of qubits, particularly when several physically redundant qubits are required to form logical error-correcting qubits.

[0075] In particular, the quantum circuit is preferably realized as a fixed-frequency transmon-type quantum circuit, i.e., as a single Josephson junction superconducting qubit. In this way, the processing device can exploit the coherence time of the fixed-frequency transmon. In one embodiment, the qubits 22, 23 are coupled via a tunable coupler 21 and are potentially victims of residual stray fields from the coupler 21. In one embodiment, the couplers 21 may each be realized as a transmon, although the latter do not form part of the basic computational element.

[0076] In one embodiment, the tunable coupler 21 is capacitively coupled to one or more quantum circuits 22, 23. For example, as shown in FIG. 6, a chip 20a may include two fixed-frequency, single-Josephson junction superconducting qubits 22, 23 and a tunable coupler 21. In this example, the tunable coupler 21 is laid out as a transmon-type qubit and an anharmonic oscillator circuit. Additionally, the coupler 21 may be provided with an extra degree of freedom by an additional Josephson junction (not shown), which forms a superconducting quantum interference device (SQUID) loop, as known to those skilled in the art. The SQUID loop may then be used to tune the frequency of the coupler. Similar chip architectures are envisioned in FIGS. 7A and 7B.

[0077] Superconducting quantum circuits of the transmon type are controlled by radio frequency (RF) techniques and are operated at temperatures of only a few mK. The RF signal is usually fed to the cryostat by a coaxial cable. Two channels are usually sufficient to control the qubits. Attenuators (not shown) are usually placed on the intermediate temperature platform to thermalize the signal on each of the upward and downward paths. In a variant, the qubits are configured as spin-based quantum circuits, or spin qubits for shorting. In another variant, the qubits are topological qubits. In all cases, the platform on which the qubits are located is usually intended to be operated at very low temperatures.

[0078] 2.2 Detailed description of the drawings 2.2.1 Figure 1 FIG. 1 is not in itself in accordance with the present invention. However, FIG. 1 illustrates components of a quantum processing device that may typically be involved in an embodiment. Indeed, in an embodiment, and as shown in FIG. 1, a quantum processing device may comprise (at least) three platforms. These include a first platform on which qubits are located. The first platform contains one or more qubit chips 20p and is designed to be cooled to a cryogenic temperature T1 (e.g., 20 mK). A second platform is provided that is designed to be cooled to a second temperature T2 higher than T1. The temperature T2 is typically between 2 K and 6 K, e.g., 3 K or 4 K. A third platform is operated at a third temperature T3 higher than T2 (e.g., room temperature, 300 K).

[0079] The signal generator 14p (which generates the required current and / or voltage signals) is connected to control electronics 12p (which performs, among other things, the sequencing) which is itself connected to a computer 11 to interface the quantum processing device with the outside world.

[0080] 2.2.2 Figure 2 2 shows only three platforms for simplicity. However, as is customary in the art, one or more additional intermediate platforms may be provided. For example, a first platform may be operated at 20 mK and a second platform at 3 K, and a further intermediate platform, for example operated at 50 K, may be provided below the room temperature platform.

[0081] Figure 2 shows an arrangement essentially similar to that of Figure 1, except that it further includes a shielding circuit 31 connected to generator 14, where shielding circuit 31 has a compensation loop that partially surrounds component 22 of qubit chip 20 and magnetically shields component 22 from stray fields generated by adjacent component 21. The signals intended to be applied to components 21, 22 are first aligned at the level of control electronics 12, and corresponding signals are generated by signal generator 14 and passed to qubit chip 20 via circuit 20c. In one embodiment, the compensation signal applied to compensation loop 31 is scaled with respect to the current applied to component 21 in this example.

[0082] 2.2.3 Figure 3 3A and 3B show contour plots obtained by simulation in a configuration similar to that of Fig. 2, in the absence of compensation (Fig. 3A) or with semi-active compensation (Fig. 3B), i.e., the compensation coil 31 surrounds the victim 22, which is centered at a point mapped by the vector r, i.e., at a distance r = |r| of the aggressor 21.

[0083] 3A and 3B show selected contour lines of the total magnetic field strength in the plane (x,z) corresponding to the main plane of the qubit chip on which components 21 and 22 are located. The contour values ​​are 0.1, 0.5, 1, 2, 10, 20, 100, and 200. All contour values ​​(except the value 200) are shown in the vicinity of their respective contours. The figures show how the stray field generated by aggressor 21 can be locally shielded at the level of victim 22 by applying a compensation current signal to loop 31 of the shielding circuit surrounding victim 22.

[0084] It should be noted that the plot is not perfectly symmetrical about the horizontal plane (at y=0) due to the difference between the compositions of the materials on either side of the interface. The material below the plane y=0 is assumed to be silicon in this example, which is exposed to air, and therefore a slight asymmetry is observed. The permeability is approximately the same for silicon and air, but the permittivity is approximately 10 times lower for air (11.9 vs. 1.0). The silicon material is assumed to be lossless, without any free carriers.

[0085] The diameter of the coil is assumed to be equal to 120 microns, the distance between the centers of the two components 21, 22 is 250 microns, the width of the wire forming the coil is 2 microns, and its height is 1 micron. The aggressor current is 10 mA, while the compensation current is 0.111 mA. The magnetic (H) field strength is 0.82 A / m at the level of the second component 22 without applying a compensation current (Figure 3A). It should be noted that the compensation coil already reduces the stray field somewhat. The magnetic (H) field strength is reduced to 0.015 A / m when applying a compensation current (Figure 3B).

[0086] 2.2.4 Figure 4 FIG. 4 shows how the outer compensation loop 31p can be connected in parallel with the inner circuit 21c, which is part of the aggressor 21 located at the origin. The victim 22 is also centered on r, i.e., at a distance r = |r| of the aggressor 21. The compensation coil 31p surrounds the coil 21c. The dashed lines indicate the conductors (e.g., though including bias) used to ensure the parallel connection, i.e., the circuit parts implemented out of plane to ensure a safe connection, without including shorts. Using only a single outer compensation loop 31p centered on the aggressor 21 (without any shaping loops) usually results in overcompensation of stray fields at the level of the victim 22.

[0087] Therefore, it is preferable to use an additional loop of shaping circuitry as seen in FIGS. 5A-5D, or to place a compensation loop at the level of the victim as shown in FIG.

[0088] 2.2.5 Figures 5A to 5D 5A-5D also show the outer compensation loops 31p and 31s surrounding the inner coil 21c and two additional coils 32p, 33p; 32s, 33s. The victim is not shown. In FIGS. 5A and 5B, the outer loop 31p is connected in parallel with the inner coil 21c. In FIG. 5A, the shaping coils 32p and 33p are also connected in parallel with the inner coil 21c, while in FIG. 5B, the coils 32s and 33s are connected in series with the inner coil 21c. In FIGS. 5C and 5D, all coils are connected in series for a separate circuit design. Also, dashed lines represent circuit portions implemented out of plane to ensure short-free connections.

[0089] 2.2.6 Figure 6 In the example of FIG. 6, components 21-23 of quantum computing device 1a are connected to control units 12 and 14 as described in Section 1. Aggressor 21 is connected to the control unit via first circuit 21c, and shielding circuit 31c connects from circuit 21c via coupler 40. Qubit unit 20a is assumed to be a superconducting qubit unit having two superconducting computation qubits (transmons) 22 and 23. First component 21 is a tunable coupler, and first circuit 21c is a flux line in this case. Transmons 22 and 23 are connected to the coupler via transmission lines. A first current signal is applied via circuit 21c to drive coupler 21, while an additional current signal is applied via second circuit 22c to drive transmons 22 and 23.

[0090] In one embodiment, a separate shielding circuit (not shown) may be used to generally protect the second qubit 23 .

[0091] 2.2.7 Figures 7A and 7B 7A and 7B show superconducting qubit chip layouts 20b and 20c in which two transmon-type computation qubits 22 and 23 are coupled via a tunable coupler 21. As a result, the computation qubits 22 and 23 may be subject to stray magnetic fields emitted by the tunable coupler 21 during operation. The qubits 22 and 23 are connected to a circuit 22c. A transmission line connects each qubit 22 and 23 to the tunable coupler 21.

[0092] More precisely, the qubits are fixed-frequency transmons 22, 23 that are capacitively coupled to a flux-tunable transmon that acts as a tunable coupler 21, similar to Figure 6. The tunable coupler 21 is controlled by a flux line 21c that provides a current I(t) and a resulting flux Φ(t) that passes through the superconducting quantum interference device (SQUID) loop of the coupler 21. Each of the fixed-frequency qubits 22, 23 is coupled to a respective readout resonator R1, R2.

[0093] 7A further shows shielding circuits (dashed lines) 31v coiled around each of the computation qubits, branching off from flux line 21c in parallel.

[0094] 7B shows a shielding circuit (dashed line) 31a coiled around only one tunable coupler 21. In both cases, according to an embodiment, the shielding circuit shields the computation qubit from stray magnetic fields generated by the tunable coupler.

[0095] 2.2.8 Figure 8 Figure 8 is a high-level flow of operations performed using an apparatus such as that depicted in Figure 2 or Figure 6. In step S5, input signals are synthesized by a signal generator synthesizer (not shown), itself controlled by a controller, to simultaneously apply a first current signal to the aggressor and a compensation signal to the shielding circuit S10, S30. Another signal is applied to the victim component as appropriate, as needed, S20. The output signal is formally collected, for example, by a controller S40. Such steps are repeated as needed to perform quantum computations.

[0096] While the present invention has been described with reference to a limited number of embodiments, variations, and accompanying drawings, it will be apparent to those skilled in the art that various modifications may be made and equivalents may be substituted without departing from the scope of the invention. In particular, features (such as devices or methods) described in a given embodiment, variation, or illustrated in a drawing may be combined with or substituted for other features in other embodiments, variations, or drawings without departing from the scope of the invention. Accordingly, various combinations of features described in connection with any of the above embodiments or variations may be contemplated that remain within the scope of the appended claims. Furthermore, many minor modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is understood that the invention is not limited to the particular embodiments disclosed, but that the invention is intended to include all embodiments falling within the scope of the appended claims. Moreover, many other modifications besides those expressly mentioned above may be contemplated.

[0097] 2.2.9 Figure 9 9 is a block diagram illustrating components of a computing device, generally designated 900, suitable for performing operations to reduce the effects of stray magnetic fields on components of a quantum computing chip, in accordance with at least one embodiment of the present invention. Computing device 900 includes one or more processors 904 (having one or more computer processors), a communications fabric 902, memory 906 including RAM 916 and cache 918, persistent storage 908, a communications unit 912, an I / O interface 914, a display 922, and external devices 920. It should be understood that FIG. 9 is merely illustrative of one embodiment and is not intended to suggest any limitation with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.

[0098] As shown, computing device 900 operates with a communications fabric 902 that provides communications between a computer processor 904, memory 906, persistent storage 908, a communications unit 912, and an input / output (I / O) interface 914. Communications fabric 902 may be implemented with any architecture suitable for passing data or control information between processor 904 (e.g., a microprocessor, communications processor, and network processor), memory 906, external devices 920, and any other hardware components in the system. For example, communications fabric 902 may be implemented using one or more buses.

[0099] Memory 906 and persistent storage 908 are computer-readable storage media. In the illustrated embodiment, memory 906 includes random access memory (RAM) 916 and cache 918. In general, memory 906 may include any suitable volatile or non-volatile computer-readable storage medium or media.

[0100] Program instructions for reducing the effects of stray magnetic fields on components of a quantum computing chip according to embodiments of the present invention may be stored in persistent storage 908, or more generally, any computer-readable storage medium, for execution by one or more of the respective computer processors 904 via one or more memories of memory 806. Persistent storage 908 may be a magnetic hard disk drive, a solid-state disk drive, a semiconductor storage device, a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0101] The media used by persistent storage 908 may also be removable. For example, a removable hard drive may be used for persistent storage 908. Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive for transfer to another computer-readable storage medium that is also part of persistent storage 908.

[0102] Communications unit 912, in these examples, provides for communication with other data processing systems or devices. In these examples, communications unit 912 may include one or more network interface cards. Communications unit 912 may provide communication using either or both physical and wireless communication links. In the context of some embodiments of the present invention, sources of various input data may be physically remote from computing device 900, such that input data may be received and output may likewise be transmitted via communications unit 912.

[0103] The I / O interface 914 allows for the input and output of data with other devices that may operate in conjunction with the computing device 900. For example, the I / O interface 914 may provide a connection to an external device 920, which may be a keyboard, keypad, touchscreen, or other suitable input device. The external device 920 may also include portable computer-readable storage media, such as thumb drives, portable optical or magnetic disks, and memory cards. Software and data used to implement embodiments of the present invention may be stored on such portable computer-readable storage media and loaded into persistent storage 908 via the I / O interface 914. The I / O interface 914 may also be similarly connected to a display 922. The display 922 provides a mechanism for displaying data to a user and may be, for example, a computer monitor.

Claims

1. 1. A computer-implemented method for reducing the effects of stray magnetic fields on components of a quantum computing chip, comprising: applying a first current signal to a first component of a quantum computing chip, whereby the first component generates a stray magnetic field that affects the operation of a second component of the quantum computing chip; and applying a compensation current signal to a shielding circuit of the quantum computing chip to magnetically shield the second component from the stray magnetic field generated by the first component, the compensation current signal being generated according to a predetermined function of the first current signal; Equipped with The shielding circuit includes one or more loops at least partially surrounding one or both of the first component and the second component, and a current direction of the compensation current signal flowing through the one or more loops is opposite to a current direction of the first current signal. Computer-implemented methods.

2. the amplitude of the compensation current signal applied to the shielding circuit is equal to the amplitude of the first current signal applied to the first component of the quantum computing chip; The computer-implemented method of claim 1 .

3. the amplitude of the compensation current signal applied to the shielding circuit has an amplitude that is scaled relative to the amplitude of the first current signal applied to the first component of the quantum computing chip. The computer-implemented method of claim 1 .

4. the frequency and phase of the compensation current signal applied to the shielding circuit is synchronized with the frequency and phase of the first current signal applied to the first component of the quantum computing chip; A computer-implemented method according to any one of claims 1 to 3.

5. the first component is one of a superconducting computational qubit and a tunable coupler; 10. The computer-implemented method of claim 1, further comprising applying a first current signal to the first component of the quantum computing chip to drive the first component. A computer-implemented method according to any one of claims 1 to 4.

6. the second component is a superconducting computational qubit; 10. The computer-implemented method of claim 1, further comprising applying a second signal to the second component of the quantum computing chip to drive the second component.

6. A computer-implemented method according to any one of claims 1 to 5.

7. one or more computer processors; one or more computer-readable storage media; and computer program instructions stored on said one or more computer readable storage media for execution by said one or more computer processors; 1. A computer system for reducing the effects of stray magnetic fields on components of a quantum computing chip, comprising: applying a first current signal to a first component of a quantum computing chip to operate the first component, whereby operation of the first component generates a stray magnetic field that affects operation of a second component of the quantum computing chip; and applying a compensation current signal to a shielding circuit of the quantum computing chip to magnetically shield the second component from the stray magnetic field generated by the first component, wherein the compensation current signal is generated according to a predetermined function of the first current signal; has instructions for The shielding circuit includes one or more loops at least partially surrounding one or both of the first component and the second component, and a current direction of the compensation current signal flowing through the one or more loops is opposite to a current direction of the first current signal. Computer system.

8. a qubit unit having a shielding circuit, a first component, and a second component; and applying a first current signal to a first component of the quantum computing chip to operate the first component, whereby operation of the first component generates a stray magnetic field that affects operation of a second component of the quantum computing chip; and applying a compensation current signal to a shielding circuit of the quantum computing chip, the compensation current signal being generated according to a predetermined function of the first current signal, to magnetically shield the second component from the stray magnetic field generated by the first component; a control unit operatively connected to each of the first component and the shielding circuit for Equipped with The shielding circuit includes one or more loops at least partially surrounding one or both of the first component and the second component, and a current direction of the compensation current signal flowing through the one or more loops is opposite to a current direction of the first current signal. Quantum computing device.

9. the quantum computing chip further comprises a first circuit and a second circuit; the control unit is connected to the first component and the second component via the first circuit and the second circuit, respectively, and is configured to apply the first current signal to the first component via the first circuit; the shielding circuit is connected to the first circuit to effect a predetermined function of the first current signal; 9. The quantum computing device of claim 8.

10. the qubit unit is a superconducting qubit unit having the first circuit, the second circuit, and the shielding circuit; the control unit includes a signal generator connected to each of the shielding circuit and the first component, the signal generator being connected to the first component via the first circuit; 10. The quantum computing device of claim 9.

11. the shielding circuit and the first circuit are connected in parallel to the signal generator; 11. The quantum computing device of claim 10.

12. the signal generator is connected to the first circuit in the qubit unit, and the shielding circuit is connected in series thereto; 11. The quantum computing device of claim 10.

13. the quantum computing device further comprising one of a capacitive voltage divider or a transmission line coupler; the signal generator is connected to each of the shielding circuit and the first component via the capacitive voltage divider or the transmission line coupler to effect a predetermined function of the first current signal; 13. A quantum computing device according to any one of claims 10 to 12.

14. the amplitude of the compensation current signal applied to the shielding circuit is equal to the amplitude of the first current signal applied to the first component of the quantum computing chip; 14. A quantum computing device according to any one of claims 8 to 13.

15. each of the first component and the second component comprises at least one component selected from the group consisting of a superconducting qubit, a tunable coupler, and a Josephson junction; 15. A quantum computing device according to any one of claims 8 to 14.

16. the first component has a transmon type fixed frequency superconducting qubit, and the second component has a tunable coupler coupled to the transmon type superconducting qubit; 16. A quantum computing device according to any one of claims 8 to 15.

17. the first component and the second component are disposed on the same plane in the qubit unit; the one or more loops each surround at least one of the first component and the second component in a given plane in the qubit unit; the given plane is coincident with or juxtaposed to the same plane; 17. A quantum computing device according to any one of claims 8 to 16.

18. at least one of the one or more loops of the shielding circuit surrounds the second component in the given plane; 18. The quantum computing device of claim 17.

19. the shielding circuit includes both a compensation circuit and a shaping circuit connected in series; the compensation circuit includes the one or more loops; the shaping circuit includes two or more additional loops, each surrounding the inner loop of the first component in the given plane; the one or more loops surround the two or more additional loops in the given plane; a current direction of the compensation current signal flowing in the one or more loops is opposite to a current direction of the first current signal flowing in the inner loop; The direction of current flowing in the two or more additional loops is the same as the direction of current flowing in the first current signal in the inner loop.

19. A quantum computing device according to any one of claims 17 to 18.

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