A method for fast detection and automatic gain adjustment in ADC-based signals

Abstract

To provide an analog-to-digital converter (ADC) having input amplifiers with automatic gain adjustment.SOLUTION: A method by an ADC includes: amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream and selectively adjusting the gain of an amplifier based on the first filtered data stream; filtering the digital data stream with a second digital filter to generate a second filtered data stream, and generating output digital values corresponding to the analog input signal based on the second filtered data stream.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates generally to analog-to-digital converters (ADCs), and more particularly to ADCs having input amplifiers with automatic gain adjustment. [Background technology]

[0002] Many analog-to-digital converters (ADCs) can include a programmable gain amplifier (PGA) that accommodates a wide range of analog input voltages. Automatic gain control (AGC) can be used to automatically vary the gain of the amplifier in response to the amplifier's output signal.

[0003] FIG. 14 is a block diagram of a conventional ADC system 1401. In the conventional ADC system 1401, an analog input signal can be amplified using a PGA 1403. A sigma-delta (also referred to as delta-sigma) modulator 1407 with adjustable gain 1405 can sample the amplified output to generate a digital data stream that reflects the magnitude of the analog input signal. The digital data stream can be digitally filtered and sampled in a filter / decimator 1409. The digital filter can be a third-order sinc filter and decimator with an oversampling ratio (OSR) of 64. The output of the filter / decimator 1409 can be summed / accumulated to generate the final conversion result.

[0004] 14, in AGC operation, an analog input value may be applied to a comparator 1411. If the analog input value exceeds the range limits of the comparator 1411, the comparator 1411 may generate an interrupt signal. In response to the interrupt, a processor 1413 may generate gain values ​​for the PGA 1403, the modulator gain value 1405, and new range values ​​for the comparator 1411 according to predetermined instructions.

[0005] A drawback of the conventional ADC 1401 can be its power consumption. The processor 1413 may draw an excessive amount of current for some applications, including applications requiring low power consumption, such as battery monitoring. Another drawback is the amount of noise generated by the analog comparator.

[0006] FIG. 15 shows a block diagram of another conventional ADC system 1501. The conventional ADC system 1501 can have a general conversion path similar to that shown in FIG. 14, including a PGA 1503, a modulator gain stage 1505, a sigma-delta modulator 1507, and a filter / decimator 1509. Unlike FIG. 14, the AGC can be provided with logic 1515, which can detect amplitude variations based on the conversion result output from the filter / decimator 1509. The logic 1515 can determine and input the magnitude, or a variation in magnitude, and can adjust the gain values ​​of the PGA 1503 and the modulator gain stage 1505 in response.

[0007] A drawback of the conventional ADC 1501 can be the delay between the analog input signal change and the output from the filter / decimator 1509. In some applications, the delay between the analog signal change and the gain adjustment provided by the logic 1515 may be too large to meet system requirements. Summary of the Invention [Problem to be solved by the invention]

[0008] It would be desirable to have a technique for providing analog to digital conversion that overcomes the shortcomings of conventional approaches. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of an analog-to-digital converter (ADC) according to one embodiment. [Figure 2]FIG. 10 is a block diagram of an ADC according to another embodiment. [Figure 3] FIG. 10 is a block diagram of an ADC according to a further embodiment. [Figure 4A] FIG. 2 is a detailed block diagram of an ADC and corresponding operation according to an embodiment. [Figure 4B] FIG. 2 is a detailed block diagram of an ADC and corresponding operation according to an embodiment. [Figure 4C] FIG. 2 is a detailed block diagram of an ADC and corresponding operation according to an embodiment. [Figure 4D] FIG. 2 is a detailed block diagram of an ADC and corresponding operation according to an embodiment. [Figure 5] FIG. 4B is a timing diagram illustrating delays that may be included in the embodiment of FIG. 4A. [Figure 6A] 4B is a waveform illustrating the operation of the ADC shown in FIG. 4A. [Figure 6B] 4B is a waveform illustrating the operation of the ADC shown in FIG. 4A. [Figure 6C] 4B is a waveform illustrating the operation of the ADC shown in FIG. 4A. [Figure 6D] 4B is a waveform illustrating the operation of the ADC shown in FIG. 4A. [Figure 6E] 4B is a waveform illustrating the operation of the ADC shown in FIG. 4A. [Figure 7A] FIG. 2 is a block diagram of a masking circuit according to an embodiment. [Figure 7B] FIG. 2 is a block diagram of a masking circuit according to an embodiment. [Figure 7C] FIG. 2 is a block diagram of a masking circuit according to an embodiment. [Figure 7D] FIG. 2 is a block diagram of a masking circuit according to an embodiment. [Figure 8] FIG. 1 is a flow diagram of a method according to one embodiment. [Figure 9] FIG. 4 is a flow diagram of a method according to another embodiment. [Figure 10] FIG. 10 is a flow diagram of a method according to a further embodiment. [Figure 11] FIG. 4 is a flow diagram of a method according to another embodiment. [Figure 12] FIG. 1 is a block diagram of a system according to one embodiment. [Figure 13] FIG. 1 is a diagram of a system according to another embodiment. [Figure 14] FIG. 1 is a block diagram of a conventional ADC. [Figure 15] FIG. 1 is a block diagram of another conventional ADC. DETAILED DESCRIPTION OF THE INVENTION

[0010] According to embodiments, an analog-to-digital converter (ADC) can provide high-speed automatic gain control (AGC) without an analog comparator by using a high-speed digital detection loop that can detect variations in the analog input signal with digital circuitry. The high-speed digital detection loop can operate in parallel with (and faster than) the conversion path that produces the final digital output value corresponding to the analog input signal.

[0011] In some embodiments, the high-speed digital detection loop may include a filter / decimator that produces output values ​​faster (albeit at lower resolution) than the filter / decimator in the conversion path.

[0012] In some embodiments, the ADC can also include a masking section that can mask the sigma-delta modulator output stream corresponding to the gain excursion event to suppress transients that may be caused by the gain excursion. In some embodiments, the masking section can include a memory element that can output a previous digital data stream instead of the digital data stream corresponding to the gain excursion event.

[0013] In some embodiments, the high-speed digital detection loop may include a first sinc filter, while the conversion path includes a sinc filter of a higher order than the sinc filter of the high-speed digital detection loop.

[0014] In the various embodiments below, similar components are referred to by the same reference numerals, with the leading digits corresponding to the figure numbers.

[0015] FIG. 1 is a block diagram of an ADC 100 according to one embodiment. The ADC 100 may include a conversion path 102 and an AGC loop 104. The conversion path 102 may receive an analog input signal 106 and generate a digital output value 108 representing the analog input signal 106. The conversion path 102 may include an amplifier 110, a sigma-delta modulator 112 (hereinafter referred to as the "modulator"), a filter / decimator 114, and a result section 116. The amplifier 110 may amplify the analog input signal 106 according to a gain value 118. The amplified analog input signal may be provided to the modulator 112, which may generate a stream of digital values ​​120 at a sampling rate (i.e., frequency Fs). The stream of digital values ​​120 may be single-bit or multi-bit. The filter / decimator 114 may digitally filter and downsample the data stream 120. In some embodiments, the filter / decimator 114 may include a sinc filter for filtering higher frequency components. The result section 116 may provide the final digital conversion value 108.

[0016] It will be appreciated that the conversion path 102 may include any other suitable processing sections, including, but not limited to, analog filters, buffers, and / or additional digital filters.

[0017] The AGC loop 104 may receive a stream of digital values ​​120 from the modulator 112 and selectively vary the gain value 118 of the amplifier 110 based on such values. In some embodiments, the AGC loop 104 may operate at a lower resolution than the filter / decimator of the conversion path 102. The AGC loop 104 may include a “fast” filter / decimator 122 and an automatic gain circuit 124. The “fast” filter / decimator 122 may perform digital filtering and downsampling of the data stream 120 and may run at a faster speed compared to the filter / decimator 114 of the conversion path 102. In some embodiments, both the fast filter / decimator 122 and the filter / decimator 114 of the conversion path may include sinc filters, although the fast filter / decimator 122 of the AGC loop 104 may be a lower-order sinc filter than the filter / decimator 114 of the conversion path 102.

[0018] The automatic gain circuit 124 can determine the response of the analog input signal 106 from the filtered / downsampled data values ​​output from the fast filter / decimator 122 and increase, decrease, or maintain the gain value 118 of the amplifier 110 accordingly. In the illustrated embodiment, the automatic gain circuit 124 can include a range comparison circuit 124-0 and a gain control circuit 124-1. The range comparison circuit 124-0 can determine from the filtered / downsampled digital values ​​whether the analog input signal 106 is within one or more ranges. Based on this determination, the gain control circuit 124-1 can generate appropriate gain values, as needed. As will be appreciated, such operations include determining when the analog input signal 106 is above a lower limit of a range and responsively increasing a gain value, and determining when the analog input signal 106 is below an upper limit of a range and responsively decreasing a gain value.

[0019] The AGC loop 104 can perform amplifier gain discrimination faster than the conversion path 102 can reach the digital output value 108. The AGC loop 104 consumes very little power because it does not need to include any processor circuitry, which may be circuitry that performs operations in response to a series of instructions.

[0020] 2 is a block diagram of an ADC 200 according to another embodiment. The ADC may include a conversion path 202 and a gain adjustment loop 226. The conversion path 202 may include components as shown in FIG. 1, such as a modulator 212, a filter / decimator 214, and a result section 216. The conversion path 202 may operate in a manner similar to that described for FIG. 1. Unlike FIG. 1, the amplifier in the conversion path 202 may be a programmable gain amplifier (PGA) and may include a masking circuit 228.

[0021] The masking circuit (228 and / or 228′) can mask portions of the data stream 220 output from the modulator 212 in response to mask instructions 230 provided by the gain adjustment loop 226. In some embodiments, the masking circuit 228 can include one or more memory circuits that can store a running portion of the data stream 220 and then output the stored data stream values ​​in place of the current data stream in response to an active mask instruction 230. However, the masking can take any suitable form, as described in more detail herein.

[0022] The masking circuit (228 and / or 228') can be located at various locations within the conversion path. As illustrated by masking circuit 228, masking circuit 228 can mask the data values ​​as they are output from modulator 212. However, as illustrated by masking circuit 228', in other embodiments, masking can be performed at the "back end" of the conversion path, where the data values ​​are masked following digital processing steps including, but not limited to, digital filtering and / or decimation.

[0023] The gain adjustment loop 226 may change the gain value 218 of the PGA 210 in response to the data stream 220 output from the modulator 212. Additionally, the gain adjustment loop 226 may activate a mask instruction 230 when a variation occurs in the gain value 218. Such an operation may mask the portion of the data stream 220 corresponding to the PGA gain variation, which may include transient and other undesirable effects. The gain adjustment loop 226 need not include any processor circuitry.

[0024] During operation, the ADC 200 may receive an analog input signal 206. The conversion path 202 may generate an output digital value 208 that reflects the analog input signal 206. At the same time, if the magnitude of the analog input signal 206 rises or falls by a predetermined amount, the gain adjustment loop 226 may decrease or increase the gain value 218. When such a gain value change occurs, the gain adjustment loop 226 may activate a mask instruction 230, causing a masking circuit 228 to modify the data stream output from the modulator 212. It will be appreciated that the gain adjustment loop 226 may delay activation of the mask instruction 230 to determine when masking of the data stream occurs. In some embodiments, the masking period (e.g., the number of data values ​​masked) may be determined by the masking circuit 228. Additionally or alternatively, the masking period may be determined by the mask instruction 230. The masking period may be static or dynamic (e.g., programmable, varies with gain variation, etc.).

[0025] FIG. 3 is a block diagram of an ADC 300 according to a further embodiment. In some embodiments, the ADC 300 may be one of the implementations shown in FIG. 1 and / or FIG. 2. The ADC 300 may include a conversion path 302 and an AGC loop 304. The conversion path 302 may include a PGA 310, an anti-aliasing filter (AAF) 332, a buffer 334, a modulator gain adjuster 312-0, a modulator 312, a masking circuit 328, a scaler 336, a filter / decimator 314, and a result section 316. The PGA 310 may amplify the analog input signal 306 according to a PGA gain value 318, as described herein and equivalents. The AAF 332 may limit the bandwidth of the signal output from the PGA according to, for example, the sampling rate of the ADC 300. The buffer 334 may buffer the resulting analog signal output from the AAF 332. The modulator gain adjuster 312-0 may adjust the gain of the modulator 312 according to a modulator gain value 338. In some embodiments, the modulator gain value 338 may select values ​​for the input capacitance and the reference capacitance of the modulator 312. The modulator 312 may sample the analog signal output from the buffer 334 to generate a digital data stream 320. The digital data stream 320 may be multi-bit or single-bit.

[0026] The masking circuit 328 may include a memory 328-0 and a multiplexer (MUX) 328-1. The memory 328-0 may store a predetermined amount of data stream values ​​320. The MUX 328-1 may selectively connect the data stream output from the modulator 312 or the value stored by the memory 328-0 in response to a mask instruction 330. The scaler 336 may digitally amplify the data stream value output from the MUX 328-1 according to a digital gain value 340. The filter / decimator 314 and the result section 316 may operate in a manner similar to that described with respect to FIG. 1. As a result, a downsampled and filtered digital output signal 308 may be provided.

[0027] The AGC loop 304 may include a fast filter / decimator 322, a range comparison section 324-0, and a gain lookup section 324-1. The fast filter / decimator 322 may operate similarly to that described in 122 for FIG. 1. In response to the value provided by the fast filter / decimator 322, the range comparison section 324-0 may increase, decrease (or maintain) the gain setting of the ADC 300. Based on the increase or decrease instruction from the range comparison section 324-0, the gain lookup section 324-1 may generate the PGA gain value 318, the modulator gain value 338, the digital gain value 340, and the mask instruction 330. Additionally, the gain lookup section 324-1 may provide new comparison thresholds for the range comparison section 324-0. In some embodiments, the gain lookup section 324-1 may include one or more lookup tables (LUTs) for fast generation of values. The AGC loop 304 may not include any processor circuitry.

[0028] In operation, the analog input signal 306 may be amplified, filtered, and modulated to generate a data stream 320. The data stream 320 may be provided to a filter / decimator 314, which may generate an ADC conversion result 316. At the same time, the AGC loop 304 may process the data stream 320 from the modulator 312 to determine whether the analog input signal 306 is at the upper or lower limit of a range.

[0029] If the analog input signal 306 exceeds or falls below a range limit, the range comparison section 324-0 can signal a gain increase or decrease. In response, the gain lookup section 324-1 can provide a new PGA gain value 318 and, if appropriate, a new modulator gain value 338 and / or digital gain value 340. Additionally, a mask instruction 330 can be activated.

[0030] Fluctuations in PGA gain value 318 can result in undesirable effects (e.g., transient settling, step response artifacts) at the output of PGA 318. Such undesirable effects may be sampled by modulator 312 and reflected in the resulting data stream 320. Activation of mask instruction 330 can be timed to coincide with that portion of data stream 320. Thus, while such potentially undesirable values ​​are being output from modulator 312, MUX 328-1 can output the value stored in memory 328-0. Once the PGA transition period has passed (i.e., once the adverse effects of the gain variation are no longer expected), mask instruction 330 can be deactivated and MUX 328-1 can return to providing data stream 320 output by modulator 312.

[0031] 4A-4D are block diagrams of an ADC 400 according to another embodiment. The ADC 400 may be any one of the implementations shown in FIGS. 1-3. The ADC 400 may include a conversion path 402 and an AGC loop 404. The conversion path 402 may have components as shown in FIG. 3, including a PGA 410, an AAF 432, a buffer 434, a modulator gain adjuster 412-0, a modulator 412, a masking circuit 428, a scaler 436, a filter / decimator 414-0 / 1, and a result section 416. Such components may operate in the same or similar manner as the corresponding components in FIG. 3.

[0032] FIG. 4A may differ from FIG. 3 in that the AAF 432 may include switch elements sw1-sw4. The operation of the switch elements of the AAF 432 will be described in more detail with reference to FIGS. 4B-0-4B-2. The modulator 412 may be a 16-bit sigma-delta modulator that may output a converted value as a stream of 4-bit values. The operation of the masking circuit 428, the scaler 436, and the decimator 414-0 will be described with reference to FIG. 4C. The output from the filter / decimator 414-0 / 1 may be provided to a finite impulse response (FIR) filter 444 to arrive at a 32-bit result. A 32-bit accumulator 446 may sum the samples, which may further smooth the output result and / or reduce the effects of noise. The AGC loop 404 may include a filter / decimator 422, a range comparison section 424-0, and a gain lookup section 424-1.

[0033] The ADC 400 may include various delays 450-0 through 450-2. The delays (450-0 through 450-2) allow the timing of the corresponding circuit sections to be set by PGA gain change events, which may cause undesirable effects such as transients due to PGA gain changes. Delay 450-0 may trigger a switch setting within the AAF 432, and the output of the PGA 410 is controlled by modulator gain 412-0, which is placed just before or during the PGA gain change. The function of delays 450-0 / 1 is further described with reference to FIG. 4C.

[0034] 4B-0-4B-2 are a series of diagrams illustrating various configurations of the AAF 432 according to one embodiment. Figures 4B-0-4B-2 show a portion of the ADC 400' including the PGA 410, the AAF 432, the buffer 434, and the delay 450-0.

[0035] 4B-0 shows AAF 432 while PGA gain 418 is constant. Within AAF 432, switch element sw1 can be closed while sw2 and sw3 are open, applying the output of PGA 410 to analog filter element 432-0.

[0036] 4B-1 shows the AAF 432 while the PGA gain 418' is varying. The switch control signal enables the switch element sw1 in the AAF 432 to open and the switch element sw2 to close, bypassing the filter resistor. This configuration allows the analog signal to stabilize faster.

[0037] 4B-2 shows the AAF 432 while the input signal source 406' is fluctuating. Fluctuations in the input signal source 406' can occur when the ADC is used to process different signals. Within the AAF 432, switch element sw3 can be closed (while switch elements sw1 and sw2 are open), bypassing all filter elements. Such a configuration can enable very rapid switching of the analog signal from the previous signal (i.e., S1) level to the new input signal (i.e., S2) level.

[0038] FIG. 4C illustrates a portion of the ADC 400′ including a masking circuit, a scaler 436, and filter / decimators 414-0 / 1. The masking circuit 428 may include a circular buffer 428-0 that stores a set amount of 4-bit (×4) values ​​output from the modulator 412. The size of the circular buffer 428-0 may be static or programmable. Stored data stream values ​​from the circular buffer 428-0 are output via a MUX 428-1, but the circular buffer 428-0 may not store new data. In this manner, the operation of the circular buffer 428-0 and the MUX 428-1 isolates the (potentially corrupting) data stream from the modulator from the filter / decimators 414-0 / 1. The duration of such operation may be determined by a delay 450-1 (delay_Y). The masking circuit may take any suitable form. Examples of other possible masking circuits are described with reference to FIGS. 7A-7D.

[0039] 4C , the scaler 436 may implement a digital gain (i.e., a left shift) that can vary from 0:9 based on the digital gain value 440 and provide a 13-bit output value. The filter / decimator 414-0 / 1 may include a first stage 414-0 with a third-order sinc (sinc3) filter with an oversampling ratio (OSR) of 64 and a second stage 414-1 with a sinc3 filter with an OSR of 6. The filter / decimator 414-0 / 1 may provide a 32-bit value. The delay 450-1 may control how long the circular buffer 428-0 is activated (i.e., outputs a stream of stored data values) with respect to the PGA gain variation. The delay 450-2 may control when the scaler 436 increases the digital gain value.

[0040] FIG. 4D shows the AGC loop 404 in more detail. The AGC 404 may include a filter / decimator 422, a range comparison section 424-0, and a gain lookup section 424-1. The filter / decimator 422 may include a first-order (sinc1) filter 422 and may have an OSR of 16 to 32. In the illustrated embodiment, the filter / decimator 422 may provide an output value of 8 to 10 bits. Note that the filter / decimator 422 may arrive at a value faster than the filters / decimators 414-0 / 1 of the conversion path 402, allowing the AGC loop 404 to respond to the modulator data stream 420 faster than the conversion path 402. The range comparison section 424-0 may generate an indication of range increase or decrease. Within the gain lookup section 424-1, logic 452 may generate a lookup value based on the increase / decrease indication. The LUT can output a PGA gain value 418, as well as other corresponding ADC configuration values ​​(e.g., filter control 442, modulator gain 438, buffer control 448, MUX control 450, and digital gain 440). The AGC loop 404 may not include any processor circuitry.

[0041] FIG. 5 is a timing diagram showing an example of the operation of an ADC such as that shown in FIGS. 4A to 4D. The following waveforms are included in FIG. 5: s " may be a sampling clock that may indicate the frequency at which sigma-delta conversion is generated by the modulator. "AGC Decision" may transition high when the AGC loop begins PGA gain variation. "Data Stream Mask" may transition high to mask the modulator data stream and prevent unwanted artifacts (e.g., the current data stream is replaced by the previously stored data stream). "SW1 / SW2" may transition to a bypass resistor for the AAF. "Digital Gain" may transition high to change the digital gain of the scaler after a predetermined delay (e.g., delay_Z).

[0042] In some embodiments, the duration of the "Data Stream Mask" and "SW1 / SW2" can be controlled by delay values ​​(e.g., delay_Y and delay_X). The various delay values ​​(delay_X, delay_Y, delay_Z) are programmable.

[0043] 6A to 6E are timing diagrams showing simulation results of an ADC such as that shown in FIGS. 4A to 4D.

[0044] FIG. 6A shows a test analog input signal (eg, 406) being fed to a PGA (410).

[0045] FIG. 6B shows a representation of the corresponding sampled data stream (eg, 420) output from the modulator (412).

[0046] 6C shows a representation of the values ​​produced by the "fast" filter / decimator (422), which, while not having the resolution of the higher order filter / decimators (414-0 / 1), are sufficient to determine the required gain variation.

[0047] FIG. 6D shows the gain variations (eg, 418) produced by the AGC loop (404) to the PGA (410) in response to a test analog signal.

[0048] FIG. 6E shows a representation of the digital output value produced by conversion path (402).

[0049] The AGC loop (e.g., 404) described herein can provide fast detection of variations in the analog input signal using digital circuitry, allowing automatic gain adjustment to be performed at low power. Additionally, a fast filter / decimator can provide fast response with low noise.

[0050] The masking circuits (e.g., 428) described herein may enable dynamic adjustment of the gain of the ADC conversion path with little or no corruption of the data output by preventing slow transient responses from propagating through the ADC conversion path.

[0051] 7A to 7C are diagrams showing other masking circuits that may be included in the embodiment.

[0052] 7A illustrates a portion of an ADC 700A in which a mask circuit 728A may include a data MUX 728-1, a delay stage 728-2, and an interpolator 728-3. While the corresponding chopping circuit is inactive, the data MUX 728-1 outputs the data stream received at input “0.” Simultaneously, the interpolator 728-3 may generate a stream of interpolated data values ​​generated from the current data stream and stored by the delay stage 728-2. When the corresponding chopping circuit is active, the data MUX 728-1 may output the interpolated data stream values. In some embodiments, the delay value of the delay stage 728-2 is programmable and / or can be varied on-the-fly.

[0053] FIG. 7B illustrates a portion of an ADC 700B in which a mask circuit 728B may include a data MUX 728-1, a first delay element 728-4, and a second delay element 728-5. The delay element 728-5 may have the same delay as 728-4. However, in alternative embodiments, such delays may be different. While the corresponding chopping circuit is inactive, the data MUX 728-1 outputs the data stream received at input “0” delayed by the first delay element 728-4. When the corresponding chopping circuit is active, the data MUX 728-1 may output the data stream received at input “1” delayed by the second delay element 728-5. In some embodiments, the delay values ​​of the second delay elements 728-5 and / or 728-4 may be programmable and / or may be varied on the fly.

[0054] FIG. 7C illustrates a portion of an ADC 700C in which a mask circuit 728C may include a combiner circuit 728-6. The combiner circuit 728-6 may combine data stream values ​​in response to a gain excursion event instead of the data values ​​output from the modulator 712. In the absence of a gain excursion event, the combiner circuit 728-6 may output the data stream from the modulator 712. In some embodiments, the combined data stream values ​​may be generated using gain excursion data. The gain excursion data may include a gain before the gain excursion, a gain after the gain excursion, an input signal level before the gain excursion, or an input signal level after the gain excursion. In some embodiments, the combiner circuit 728-6 may include a lookup table or the like that generates the combined data stream values ​​in response to the gain excursion data and / or data stream values ​​output from the modulator 712.

[0055] 7D illustrates a portion of an ADC 700D in which a mask circuit 728D may include a machine learning (ML) engine 728-7 and a MUX 728-1. The ML engine 728-7 may include a machine learning inference engine trained to generate masked (e.g., corrected) data stream values ​​from data stream values ​​that include undesired effects, such as effects from gain excursions. In some embodiments, the ML engine 728-7 may also receive gain excursion data as an input. In the absence of a gain excursion event, the data MUX 728-1 outputs the data stream received at input “0” (i.e., the output of the modulator 712). In the event of a gain excursion event, the data MUX 728-1 may output the data stream value from the ML engine 728-7.

[0056] The ML engine 728-7 may take any suitable form. FIG. 7D illustrates an example of an ML engine 728-7′ that may be included in an embodiment. The ML engine 728-7′ is shown in a training configuration. When trained, the ML engine 728-7′ may include an encoder 728-7a, a latent space 728-7b, a decoder 728-7c, and a training agent 728-7d. Data stream values ​​output from an amplifier undergoing gain variation (data stream (training)) may be applied to the encoder 728-7a, which may encode such values ​​into the latent space 728-7b. The values ​​in the latent space 728-7b may be decoded by the decoder 728-7c to generate inferred data stream values. The training agent 728-7d may compare the inferred data stream values ​​to desired data stream values ​​(e.g., an amplifier response without undesired errors / artifacts). Based on such comparison, the training agent 728-7d may revise the encoder 728-7a and / or the decoder 728-7c. In some embodiments, the encoder 728-7a and / or the decoder 728-7c may include an artificial neural network with neural weights adjusted by the training agent 728-7d.

[0057] While the embodiments of Figures 1-7D illustrate various ADCs and corresponding methods, additional methods will now be described.

[0058] FIG. 8 is a flow diagram of a method 860 according to one embodiment. Method 860 may include receiving an analog input signal at the input of a PGA (860-0). The PGA output may be sigma-delta converted to a digital stream (860-2). Such an operation may include any suitable conversion operation and may result in an output data stream at the sampling rate. The data stream may be multi-bit or as small as a 1-bit data stream. The data stream may be filtered with a “fast” digital filter (860-4). Such an operation may include any suitable digital filter, and in some embodiments, may include a sinc-type filter. The gain of the PGA may be selectively adjusted (860-6) in response to the output of the fast digital filter. Thus, for some filter output values, the gain may be increased, decreased, or not changed.

[0059] Continuing with reference to FIG. 8, while a data stream is being filtered with a fast digital filter, the same data stream may be filtered with a "slow" digital filter (860-8). The slow digital filter may produce a filtered result slower than the fast digital filter (860-6). In some embodiments, the slow digital filter may provide a higher resolution result than the fast digital filter. A digital value corresponding to the analog signal may be generated from the output of the slow digital filter (860-10).

[0060] 9 is a flow diagram of a method 960 according to another embodiment. The method 960 may include receiving an analog signal at an input of a PGA (960-0). The output of the PGA may be sigma-delta converted to a digital stream (960-2). Such operations may include any of those described for 860-2 and equivalents. The PGA gain may be dynamically adjusted in a digital control loop (960-4) in response to the digital stream. The digital control loop may include only digital circuitry.

[0061] In response to the PGA gain adjustment, the digital stream can be masked (960-6). Such operations can include replacing or modifying the digital stream generated by the sigma-delta modulator during the gain change. This can include portions of the data stream before and / or after the gain change. Substituting the data stream can include substituting alternative data stream values ​​for data stream values ​​generated during the gain change. The alternative data stream values ​​can include previously stored values. The previously stored values ​​can be data stream values ​​immediately prior to the gain change. Modifying the data stream can include performing arithmetic or logical operations on the data stream values. As two examples among many possible examples, the data stream values ​​corresponding to the gain change can be averaged with previous data stream values ​​and / or subjected to interpolation operations with respect to other data stream values, such as previously stored data stream values.

[0062] A digital value corresponding to the analog signal may be generated from the digital stream including the masked portion of the digital stream (960-8).

[0063] 10 is a flow diagram of a method 1060 according to a further embodiment. The method 1060 may include receiving an analog signal at an input of a PGA (1060-0). The PGA output may be filtered with an analog filter (1060-2). In some embodiments, the analog filter may include an AAF. The output of the analog filter may be sigma-delta converted to a digital stream (1060-4). Such operations may include any of those described for 860-2 and equivalents. The PGA gain may be dynamically adjusted with a digital control loop in response to the digital stream (1060-6).

[0064] The analog filter element can be reconfigured 1060-8 in response to a PGA gain adjustment. Such action can include activating a switch or equivalent within the analog filter. In some embodiments, such action can include bypassing all or a portion of the input resistor to enable faster settling of the analog signal.

[0065] A digital value corresponding to the analog signal can be generated from the digital stream (1060-10).

[0066] 11 is a flow diagram of a method 1160 according to another embodiment. The method 1160 may include receiving an analog signal at a PGA input (1160-0). The PGA output may be filtered with an AAF (1160-2). The analog signal from the AAF may be sigma-delta converted to a digital stream (1160-4). Such operations may include any of the operations described for 860-2 and equivalents. The digital stream may be filtered with a low-order sinc filter (1160-6). The digital stream may be compared to one or more range values ​​(1160-8). Such operations may indicate whether a PGA gain setting for the conversion path should be varied.

[0067] When the PGA gain is varied (Y in 1160-10), the modulator gain can be adjusted (1160-12). In some embodiments, such an operation may include varying one or more input capacitances to the sigma-delta converter. A filter element of the AAF filter can be bypassed for a predetermined delay (Delay 1) (1160-14). The digital stream can also be masked for a predetermined delay (Delay 2) (1160-16). Such an operation may include any of the digital stream masking approaches described herein or equivalents. After a predetermined delay (Delay 3), the digital gain can also be adjusted (1160-18). The various delays (Delay 1, 2, 3) may be programmable and may be different from one another or the same.

[0068] A digital gain may be applied to the digital stream (1160-20). Such operations may include processing the data stream with a scaler circuit or the like. The digital stream may be filtered with a high-order sinc filter (1160-22). Such operations may include using a higher-order sinc filter over a lower-order sinc filter. A digital value corresponding to the analog signal may be generated from the digital stream output from the high-order sinc filter (1160-24).

[0069] Embodiments may include ADC circuits, ADC systems and ADC methods, but may also include other systems.

[0070] 12 is a block diagram of a battery monitoring system 1270 according to one embodiment. The system 1270 may include a battery 1272, a control unit 1274, a current sampler 1280, and an ADC system 1200. A power source 1276 may be provided from (i.e., the battery is discharging) and / or to (i.e., the battery is charging) the battery 1272. The battery 1272 may include one or more temperature sensors 1278.

[0071] The ADC system 1200 can take the form of any of those described herein or equivalents and can perform accurate conversions with high speed, low power, and low noise automatic gain control. In the embodiment shown, the ADC system 1200 can generate digital values ​​corresponding to the analog signal provided by the current sampler 1280. Additionally or alternatively, the ADC 1200 can generate digital values ​​corresponding to analog temperature readings from the temperature sensor 1278 as well as voltage readings (e.g., terminal voltage) of the battery 1272. In some embodiments, the ADC 1200 can include an input MUX 1282 for selectively connecting different analog input signals to the ADC 1200.

[0072] The digital values ​​generated by the ADC system 1200 may be transmitted to a control unit 1274 via a bus system 1278. It should be noted that the control unit 1274 may include a processor or the like, but such a processor is not used by the ADC 1200 for analog-to-digital conversion.

[0073] 13 is a diagram of an automotive system 1380 according to one embodiment. The system 1380 may include a battery 1372 and an intelligent battery sensor 1382. The intelligent battery sensor 1382 may include an ADC system 1300. The ADC system 1300 may take the form of any of those described herein or an equivalent and may generate digital signals corresponding to the operation of the battery 1372, including, but not limited to, terminal voltage, charge current, and / or discharge current.

[0074] It should be understood that references throughout this specification to "one embodiment" or "embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. As such, it is emphasized and should be understood that two or more references to "embodiment" or "one embodiment" or "alternative embodiment" in various parts of this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined as appropriate in one or more embodiments of the present invention.

[0075] Similarly, in the foregoing description of exemplary embodiments of the invention, it should be understood that various features of the invention may be grouped together in a single embodiment, drawing, or description for the purpose of presenting a more understandable disclosure of one or more of the various inventive aspects. However, this distribution should not be interpreted as reflecting an intention that the claims require more features than are expressly recited in each claim. Rather, inventive aspects may lie in fewer than all features of a single disclosed embodiment described above. Thus, the claims following the detailed description are expressly incorporated into that detailed description, with each claim standing on its own as a separate embodiment of the invention.

Claims

1. 1. A method comprising: amplifying the analog input signal by operating an amplifier to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream by operation of a sigma-delta modulator; The digital gain control loop operates as follows: filtering the digital data stream with a first digital filter to generate a first filtered data stream; selectively varying a gain of the amplifier in response to the first filtered data stream; While the digital data stream is being filtered by the first digital filter, filtering the digital data stream with a second digital filter to generate a second filtered data stream; generating an output digital value corresponding to the analog input signal in response to the second filtered data stream; Including, The method comprises: filtering the output of the amplifier with an anti-aliasing filter (AAF); changing a configuration of the AAF in response to varying the gain of the amplifier; further comprising the first digital filter filters the digital data stream faster than the second digital filter; method.

2. the first digital filter includes a first sinc filter; the second digital filter includes a second sinc filter of a higher order than the first sinc filter; The method of claim 1.

3. Selectively varying the gain of the amplifier comprises: determining an amplitude from the first filtered data stream; Varying the gain of the amplifier when the amplitude exceeds a predetermined range; Including, The method of claim 2.

4. The method further includes varying a gain of the sigma-delta modulator in response to varying a gain of the amplifier. The method of claim 1.

5. the method further comprising, in response to varying a gain of the amplifier, masking a portion of the second filtered data stream corresponding to a variation in gain. The method of claim 1.

6. the masking portion of the second filtered data stream includes a repeated portion of the second filtered data stream preceding a gain variation. The method of claim 5.

7. An analog-to-digital converter (ADC), comprising: an amplifier coupled to receive the analog input signal; a sigma-delta modulator coupled to an output of the amplifier and configured to generate a digital data stream in response to an analog output from the amplifier; a digital gain control loop coupled to an output of the sigma-delta modulator, a first digital filter coupled to receive the digital data stream from the sigma-delta modulator; a gain control circuit configured to vary the gain of the amplifier in response to an output of the first digital filter; a digital gain control loop including: a second digital filter coupled to receive the digital data stream; and a results section configured to generate a digital value corresponding to the analog input signal from the output of the second digital filter; an anti-aliasing filter (AAF) coupled between the output of the amplifier and the input to the sigma-delta modulator, the AAF configured to change a configuration of analog filter elements in response to variations in gain of the amplifier; Including, the first digital filter filters the digital data stream faster than the second digital filter; Analog-to-Digital Converter (ADC).

8. the ADC further comprising a data masking section configured to mask a portion of the digital data stream corresponding to variations in gain of the amplifier. The ADC of claim 7.

9. The data masking section comprises: a memory circuit configured to receive and delay the digital data stream; a multiplexer configured to selectively switch the digital data stream or the delayed digital data stream output from the memory circuit as an input to the second digital filter; Including, The ADC of claim 8.

10. the ADC further includes a scaler circuit configured to digitally amplify the digital data stream with a digital gain value, the scaler circuit configured to selectively vary the digital gain value in response to variations in the gain of the amplifier. The ADC of claim 7.

11. the first digital filter includes a first sinc filter; the second digital filter includes a second sinc filter of a higher order than the first sinc filter; The ADC of claim 7.

12. the digital gain control loop includes at least a look-up table configured to output a gain value for the amplifier; The ADC of claim 7.

13. 1. A system including an analog-to-digital converter (ADC) configured to generate a digital output signal corresponding to samples of at least one analog input signal, the ADC comprising: an amplifier coupled to receive the at least one analog input signal; a sigma-delta modulator configured to generate a digital data stream in response to the analog output of the amplifier; a digital control loop configured to automatically adjust the gain of the amplifier in response to the digital data stream, a first digital filter coupled to receive the digital data stream; a gain control circuit configured to provide a gain value to the amplifier in response to an output of the first digital filter; a digital control loop including: an evaluation section configured to generate the digital output signal from the digital data stream, the evaluation section including a second digital filter coupled to receive the digital data stream; an anti-aliasing filter (AAF) coupled between the output of the amplifier and the input to the sigma-delta modulator, the AAF configured to change a configuration of analog filter elements in response to variations in gain of the amplifier; Including, the first digital filter filters the digital data stream faster than the second digital filter; system.

14. the ADC further includes a data masking section coupled between the sigma-delta modulator and the second digital filter and configured to mask a portion of the digital data stream corresponding to variations in gain of the amplifier. The system of claim 13.

15. The system further includes an input multiplexer (MUX) configured to selectively connect different analog input signals to the inputs of the amplifier. The system of claim 13.

16. the system further includes at least one battery sensor coupled to a battery and configured to generate the at least one analog input signal. The system of claim 13.

17. the system further includes at least one vehicle control system coupled to receive the digital output signal from the ADC.

17. The system of claim 16.

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