Compilation device, generation method, program, and system

Abstract

To properly represent an arrangement of each element of a tensor for multiple memories connected by a tree structure topology.SOLUTION: A compiler, for generating a machine code to be executed in a chip including a plurality of distributed memories connected by a tree structure topology, includes at least one memory and at least one processor. The at least one processor is configured to associate each element of a tensor to be processed with an address in the plurality of memories included in the chip, based on a stride and the number of divisions in a predetermined layer of the tree structure with respect to the tensor to be processed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a compilation device, a generation method, and a program. and Regarding the system. [Background technology]

[0002] When writing source code, the user can specify the location in memory where each element of a tensor is to be placed.

[0003] On the other hand, for example, accelerator chips for deep learning may have multiple memories (Static Random Access Memory: SRAM) connected in a tree topology and operate using a Single Instruction / Multiple Data (SIMD) architecture. Therefore, when processing each element of a tensor using such an accelerator chip, it is important to determine the location of each element of the tensor in which of the multiple memories. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Special Publication No. 2020-517006 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-242017 [Patent Document 3] Japanese Patent Application Publication No. 06-208501 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure makes it possible to appropriately represent the arrangement of each element of a tensor in a plurality of memories connected by a tree-structure topology. [Means for solving the problem]

[0006] A compiling device according to an aspect of the present disclosure has, for example, the following configuration: A compilation device that generates machine code to be executed on a chip having at least a first tier and a second tier, the second layer is higher than the first layer, and the first layer has a plurality of first blocks; The compiling device at least One memory and at least One a processor; The at least One The processor is Obtaining a tensor to be processed on the chip; executes a process of associating each element of the tensor with any one of the plurality of first blocks included in the chip, based on at least the number of divisions in the first layer of the chip; generating the machine code to be executed on the chip based on the associating process; The first layer used in the association process corresponds to the hardware configuration of the chip. . [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 illustrates an example of a system configuration of a data processing system and a hardware configuration of each device. [Figure 2] FIG. 1 is a first diagram illustrating an example of the functional configuration of each device in a data processing system. [Figure 3] FIG. 2 is a diagram illustrating an example of a hardware configuration of an accelerator chip. [Figure 4] FIG. 1 is a diagram showing a specific example of a plurality of memories connected by a tree-structure topology. [Figure 5] FIG. 10 is a diagram showing a description method for a layout. [Figure 6] FIG. 10 is a first diagram showing a specific example of a description regarding layout and processing by an allocation unit. [Figure 7] FIG. 10 is a second diagram showing a specific example of a description regarding layout and processing by the allocation unit. [Figure 8] FIG. 10 is a first diagram showing a specific example of processing by a writing unit. [Figure 9] FIG. 2 is a second diagram showing a specific example of processing by the writing unit. [Figure 10]FIG. 10 is a first diagram showing a specific example of processing by an element value reading unit. [Figure 11] FIG. 10 is a second diagram showing a specific example of processing by the element value reading unit. [Figure 12] 10 is a flowchart showing the flow of a source code generation process. [Figure 13] 10 is a flowchart showing the flow of a machine code generation process. [Figure 14] 10 is a flowchart illustrating the flow of a machine code execution process. [Figure 15] FIG. 2 is a second diagram illustrating an example of the functional configuration of each device in the data processing system. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, each embodiment will be described with reference to the accompanying drawings. In this specification and drawings, devices having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0009] [First embodiment] <System configuration of data processing system and hardware configuration of each device> First, the overall system configuration of a data processing system having a server device according to the first embodiment and the hardware configuration of each device constituting the data processing system will be described.

[0010] 1, the data processing system 100 includes a server device 110 and an external device 160. Also, as shown in FIG.

[0011] The compiling device 120 includes, for example, a processor 121, a main storage device 122 (memory), an auxiliary storage device 123 (memory), a network interface 124, and a device interface 125. The compiling device 120 may be realized as a computer in which these devices are connected via a bus 130.

[0012] The processor 121 may be an electronic circuit (processing circuit, processing circuitry, CPU, GPU, FPGA, ASIC, etc.). The processor 121 may also be a semiconductor device including a dedicated processing circuit. The processor 121 is not limited to an electronic circuit using electronic logic elements, and may be realized by an optical circuit using optical logic elements. The processor 121 may also include an arithmetic function based on quantum computing.

[0013] The processor 121 performs various calculations based on various data and commands input from each device, etc., in the internal configuration of the compiling device 120, and outputs the calculation results and control signals to each device, etc. The processor 121 may control each device included in the compiling device 120 by executing an OS (Operating System), an application, etc.

[0014] Furthermore, processor 121 may refer to one or more electronic circuits arranged on one chip, or to one or more electronic circuits arranged on two or more chips or two or more devices. When multiple electronic circuits are used, the respective electronic circuits may communicate with each other via wires or wirelessly.

[0015] The main memory device 122 is a memory device that stores instructions to be executed by the processor 121 and various data, and the various data stored in the main memory device 122 is read by the processor 121. The auxiliary memory device 123 is a memory device other than the main memory device 122. Note that these memory devices refer to any electronic component that can store various data, and may be semiconductor memory. The semiconductor memory may be either volatile memory or non-volatile memory. The memory device for storing various data in the compiling device 120 may be realized by the main memory device 122 or the auxiliary memory device 123, or may be realized by an internal memory built into the processor 121.

[0016] The network interface 124 is an interface for connecting to the communication network 150 wirelessly or via a wire. An appropriate interface, such as one conforming to an existing communication standard, is used for the network interface 124. The communication network 150 may be any one of a WAN (Wide Area Network), a LAN (Local Area Network), a PAN (Personal Area Network), etc., or a combination thereof. An example of a WAN is the Internet, an example of a LAN is IEEE802.11 or Ethernet, and an example of a PAN is Bluetooth (registered trademark) or NFC (Near Field Communication), etc.

[0017] The device interface 125 is an interface such as a USB that directly connects to an external device 160 .

[0018] The external device 160 is a device connected to a computer. For example, the external device 160 may be an input device. The input device is an operation device 161 such as a keyboard, a mouse, or a touch panel, and provides acquired information to the computer.

[0019] Furthermore, the external device 160 may be, for example, an output device, which may be a display device 162 such as an LCD (Liquid Crystal Display), a CRT (Cathode Ray Tube), a PDP (Plasma Display Panel), or an organic EL (Electro Luminescence) panel.

[0020] The data processing device 140 has a plurality of boards (boards 140_1 to 140_4) as each device. The boards 140_1 to 140_4 are equipped with a plurality of accelerator chips (for example, chips 170_1 to 170_n).

[0021] 1, each device of the compiling device 120 and each device of the data processing device 140 are connected via a bus 130. Note that, although the example of Fig. 1 shows a case where the data processing device 140 has four boards 140_1 to 140_4, the number of boards that the data processing device 140 has is arbitrary.

[0022] The chips 170_1 to 170_n are dedicated chips specialized for the learning phase of deep learning, for example. Details of the chips 170_1 to 170_n will be described later.

[0023] <Functional configuration of each device in the data processing system> Next, a description will be given of the functional configuration of each device (here, server device 110, display device 162) of data processing system 100. Fig. 2 is a first diagram showing an example of the functional configuration of each device of the data processing system.

[0024] A generation program for generating source code and a compiler for generating machine code are installed in the compiling device 120. By executing these programs, the compiling device 120: ·Source code description section 211, ·Generation unit 212, Compilation unit 213, It functions as:

[0025] A user of the compiling device 120 starts writing source code by activating the source code writing unit 211. In FIG. 2, source code 230 is an example of source code being written and displayed on the display device 162. In this embodiment, the source code 230 includes a description related to tensors, a description related to layouts, a description related to indexes, etc. The written source code 230 is notified to the generating unit 212.

[0026] The generation unit 212 generates a computation graph based on the source code 230. A computation graph refers to a graph that represents the flow of computations from an input tensor to generating an output tensor, or a graph that represents the flow of computations that update the values ​​of tensors. For example, if the source code 230 is written in Python (registered trademark) code, the computation graph is generated by executing the source code 230 and converting it into the ONNX representation format. ONNX is an abbreviation for Open Neural Network Exchange.

[0027] Furthermore, the generation unit 212 generates a layout instruction based on the source code 230. The layout instruction is information for executing a process of assigning an address to each element of a tensor, which is generated based on a description related to the layout included in the source code 230. Here, the "process of assigning an address to each element of a tensor" is an example of the "process of associating each element of a tensor with an address." The "process of associating each element of a tensor with an address" includes at least either the "process of assigning an address to each element of a tensor" or the "process of assigning each element of a tensor to an address."

[0028] The calculation graph and layout instruction generated by the generating unit 212 (hereinafter referred to as the calculation graph, etc.) are notified to the compiling unit 213.

[0029] The compiling unit 213 performs a compilation process by receiving the computation graph and the like notified by the generating unit 212, and generates a machine code. At this time, the compiling unit 213 functions as an allocating unit. Specifically, the compiling unit 213 allocates an address of one of the memories (which may be SRAM, for example) in the chips 170_1 to 170_n to each element of the tensor, based on, for example, a layout instruction generated based on a description related to the layout.

[0030] The generated machine code is input to the data processing device 140 together with the data stored in the data storage unit 214 .

[0031] The boards 140_1 to 140_4 of the data processing device 140 function as an execution unit 220 that executes the machine code generated by the compilation unit 213 and processes the data stored in the data storage unit 214.

[0032] At this time, the execution unit 220 functions as a writing unit 251. The writing unit 251 writes the value of each element of the tensor (data stored in the data storage unit 214) to the address of the memory in the chips 170_1 to 170_n allocated by the allocation unit 241, for example, based on the description related to the tensor.

[0033] The execution unit 220 also functions as an element value reading unit 252. The element value reading unit 252 reads the value of a specific element of a tensor written in the memory in the chips 170_1 to 170_n, for example, based on a description related to an index.

[0034] Furthermore, the execution unit 220 functions as an auxiliary write unit 253. The auxiliary write unit 253 complements the values ​​of each element of a tensor based on, for example, a description related to the layout. Specifically, the auxiliary write unit 253 performs padding processing to complement the values ​​of missing elements so as to adjust the size of the tensor according to the memory to which it is written. Furthermore, when performing an operation on each element of tensors whose array shapes do not match, the auxiliary write unit 253 performs broadcast processing to match the shapes.

[0035] <Hardware configuration of accelerator chip> Next, a description will be given of the hardware configuration of the accelerator chips (for example, chips 170_1 to 170_n) mounted on the boards 140_1 to 140_4 etc. Fig. 3 is a diagram showing an example of the hardware configuration of the accelerator chip.

[0036] The chip 170_1 (chips 170_1 to 170_n all have the same hardware configuration, and therefore only the chip 170_1 will be described here) operates, for example, according to a SIMD architecture. SIMD stands for Single Instruction / Multiple Data, and refers to a method of applying one instruction to multiple pieces of data simultaneously and processing them in parallel. However, the chip 170_1 may operate according to an architecture other than the SIMD architecture.

[0037] 3, the chip 170_1 has four third-level blocks. Each third-level block has four second-level blocks. Each second-level block has multiple first-level blocks and one second-level block memory.

[0038] Each first-level block has one arithmetic unit and four arithmetic units, which supply data to the arithmetic unit.

[0039] In this way, chip 170_1 has multiple first-level blocks distributed among four second-level blocks and four third-level blocks, which are connected by a tree-structure topology. Therefore, within chip 170_1, the communication cost between memories included in multiple first-level blocks is not uniform. For example, communication between memories that are close to each other is low cost, whereas communication between memories that require going back up the tree-structure hierarchy is high cost.

[0040] <Tree structure topology> Next, a specific example of a plurality of memories connected by a tree-structure topology will be described. Fig. 4 is a diagram showing a specific example of a plurality of memories connected by a tree-structure topology.

[0041] As shown in the example of Figure 4, the four third-level blocks belong to Level A of the tree structure and are connected to each other. The four second-level blocks included in each third-level block all belong to Level B of the tree structure and are each connected to the corresponding third-level block at Level A of the tree structure.

[0042] Furthermore, the four first-level blocks contained in each second-level block belonging to the hierarchy at Level B of the tree structure all belong to the hierarchy at Level C of the tree structure and are each connected to the corresponding second-level block at the hierarchy at Level B of the tree structure.

[0043] Here, for example, The value written in the memory 411 included in the first hierarchical block of Level C indicated by the reference numeral 401 is In the memory 412 included in the first hierarchical block of Level C shown by the reference numeral 402, Consider the case of moving.

[0044] In this case, chip 170_1 is ·Traverse the tree structure from Level C → Level B → Level A, -Across different blocks within Level A, - Proceed through the tree structure from Level A to Level B to Level C. On the other hand, in order to reduce the communication cost, it is effective to write the value to a memory near the memory 412 instead of writing the value to the memory 411.

[0045] In other words, in the case of chip 170_1 in which multiple memories connected by a tree-structure topology are distributed, it is important to appropriately assign memory addresses to each element of a tensor so that the value of each element of the tensor is written to memory taking into account the hierarchy of the tree structure.

[0046] In this embodiment, in the data processing system 100, a source code description unit 211 that performs a "layout description" using a description method that can appropriately assign a memory address to each element of a tensor; A compilation unit 213 that assigns an address to each element of the tensor according to the description method; An execution unit 220 that writes the value of each element of the tensor (the data stored in the data storage unit 214) to the assigned address; to provide.

[0047] <How to write layout descriptions> Next, a description method for the layout description will be explained with reference to Fig. 5, which shows a description method for the layout description.

[0048] As shown in FIG. 5, the description regarding the layout includes, in parentheses, a description regarding the vertical arrangement and a description regarding the horizontal arrangement, which are separated by a comma.

[0049] 5, the description regarding the vertical arrangement includes a description regarding the first hierarchical level, a description regarding the second hierarchical level, etc., and further includes a description regarding the memory of the lowest hierarchical level. Note that the description regarding the first hierarchical level is, for example, a description regarding Level A in FIG. 4, and the description regarding the second hierarchical level is, for example, a description regarding Level B in FIG. 4. Furthermore, the description regarding the memory of the lowest hierarchical level is, for example, a description regarding the memory included in the first hierarchical block of Level C in FIG. 4.

[0050] Also, as shown in Figure 5, the description of the Level at the Nth hierarchical level (N is an integer greater than or equal to 1) is "number of divisions_Level name: stride", and the description of the memory at the lowest level is "number of divisions_memory address: stride".

[0051] The "stride" here refers to information indicating how many block names (addresses in the case of the lowest layer) advance when one block (tensor element in the case of the lowest layer) advances vertically in each layer (one element in the case of the lowest layer). However, the block names may also be identifiers (numbers, names, etc.) that can identify each block.

[0052] For example, suppose the block names of the four third-level blocks in Level A are "A0" to "A3". Also, suppose the third-level blocks are arranged in the order of "A0" and "A1" from the left on the first row, and "A2" and "A3" from the left on the second row. In this case, when the third-level block with block name = "A0" is moved vertically by one block, the block name moves by two blocks ("A0" → "A2", "A1" → "A3"). Therefore, in this arrangement direction, the stride is "2".

[0053] Also, for example, suppose that in the Level C hierarchy, the addresses of memory 411 allocated to the elements of the first row of a tensor are "0" to "24", and the addresses of memory 411 allocated to the elements of the second row are "25" to "49", etc. In this case, when the tensor element is advanced by one in the vertical direction, the address advances by 25 ("0" → "25" → ...). Therefore, for such memory, the stride is "25". Note that the above explanation of the stride is just an example, and the stride may be expressed in other formats as long as it is information indicating a change in block name in the vertical direction at each hierarchy.

[0054] Similarly, as shown in FIG. 5, the description regarding horizontal placement includes a description regarding the first level, a description regarding the second level, . . . , and further includes a description regarding the memory of the lowest level.

[0055] Also, as shown in Figure 5, the description of the Level at the Nth hierarchical level (N is an integer greater than or equal to 1) is "number of divisions_Level name: stride", and the description of the memory at the lowest level is "number of divisions_memory address: stride".

[0056] The "stride" here refers to information that indicates how many blocks the block name (or address in the case of the lowest layer) advances when one block (or tensor element in the case of the lowest layer) advances horizontally in each layer.

[0057] For example, suppose the block names of the four third-level blocks in Level A are "A0" to "A3". Also, suppose the third-level blocks are arranged in the order "A0" and "A1" from the left on the first row, and "A2" and "A3" from the left on the second row. In this case, when the third-level block with block name "A0" is moved one block horizontally, the block name moves one block ("A0" → "A1", "A2" → "A3"). Therefore, in this arrangement direction, the stride is "1".

[0058] Also, for example, suppose that in the Level C hierarchy, the addresses of memory 411 allocated to the elements of the first row of a tensor are "0" to "24", and the addresses of memory 411 allocated to the elements of the second row are "25" to "49", etc. In this case, when the tensor element is advanced by one in the vertical direction, the address advances by one ("0" → "1" → ...). Therefore, for such memory, the stride is "1". Note that the above explanation of the stride is just an example, and the stride may be expressed in other formats as long as it is information indicating the change in block name in the horizontal direction at each hierarchy.

[0059] In this way, by dividing the description into one about vertical placement and one about horizontal placement, and by specifying the number of divisions and stride for each layer, A highly expressive description method can be realized, and the placement of each element of a tensor in multiple memories can be appropriately expressed even when multiple memories are connected by a complex tree-structure topology. This allows appropriate addresses to be assigned to each element of the tensor, and the chip 170_1 can reduce communication costs between memories. - A highly expressive description method can be realized, and the constraints imposed on each operation can be accommodated. - Users can intuitively understand the placement of each element of a tensor across multiple memories, allowing them to optimize operations taking into account the placement of each element of a tensor, and to place each element of a tensor taking into account the characteristics of SIMD. - The arrangement of each element can be aligned between tensors, which is advantageous for operation on SIMD architectures. There are other advantages, such as:

[0060] <Specific examples of layout descriptions and processing by the allocation unit> (1) Example 1 Next, a specific example of a description related to a layout will be described. Fig. 6 is a first diagram showing a specific example of a description related to a layout. In the example of Fig. 6, for the sake of simplicity, the number of layers is set to "2" (first layer = Level A, second layer = lowest layer = Level B).

[0061] As shown in FIG. 6(b), when each element of a tensor X with 100 rows and 100 columns is allocated to a memory included in a block of Level B in the lowest layer of the chip 600 in FIG. 6(a), the description regarding the layout is, for example, ((2_A:2,2_B:2,25_Addr:25),(2_A:1,2_B:1,25_Addr:1)) This becomes:

[0062] Here, among the descriptions regarding vertical placement, 2_A:2 is At Level A, divide 100 elements vertically into two groups of 50 elements. In Level A, when you move one block vertically, the block name moves two blocks ("A0" → "A2" or "A1" → "A3"). represents.

[0063] In addition, among the descriptions regarding vertical placement, 2_B:2 is In Level B, divide the 50 vertical elements into two groups of 25 elements. In Level B, when you move one block vertically, the block name moves two blocks ("B0" → "B2" or "B1" → "B3"). represents.

[0064] Also, among the descriptions regarding vertical placement, 25_Addr:25 is In the memory contained in the Level B block, divide the 25 elements vertically into 25. In the memory contained in the Level B block, moving one tensor element vertically advances the address by 25 (for example, address "0" → "25", "1" → "26", etc.). represents.

[0065] On the other hand, among the descriptions regarding horizontal placement, 2_A:1 is At Level A, divide the 100 horizontal elements into two groups of 50 elements. In Level A, when you move one block horizontally, the block name moves forward by one ("A0" → "A1" or "A2" → "A3"). represents.

[0066] In addition, among the descriptions regarding horizontal placement, 2_B:1 is In Level B, divide the 50 horizontal elements into two groups of 25 elements. In Level B, when you move one block horizontally, the block name moves forward by one ("B0" → "B1" or "B2" → "B3"). represents.

[0067] Also, among the descriptions regarding horizontal placement, 25_Addr:1 is In the memory contained in the Level B block, divide the 25 horizontal elements into 25. In the memory contained in the Level B block, moving one tensor element horizontally advances the address by one (for example, address "0" → "1", "1" → "2", etc.). represents.

[0068] In this way, based on the above description of the layout, the allocation unit 241 can allocate a memory address included in the Level B block of the chip 600 to each element of 100 rows x 100 columns.

[0069] (2) Example 2 Next, another specific example of a description regarding a layout will be described. Fig. 7 is a second diagram showing a specific example of a description regarding a layout. In the example of Fig. 7, the number of layers is also set to "2" for the sake of simplicity (first layer = Level A, second layer = lowest layer = Level B). However, in the example of Fig. 7, the way blocks are divided is different from the example of Fig. 6 (see Fig. 7(a)).

[0070] As shown in FIG. 7(b), when each element of a tensor X with 100 rows and 100 columns is allocated to a memory included in a block of Level B in the lowest layer of the chip 700 in FIG. 7(a), the description regarding the layout is, for example, ((4_A:1,25_Addr:25),(4_B:1,25_Addr:1)) This becomes:

[0071] Here, among the descriptions regarding vertical placement, 4_A:1 is At Level A, divide the 100 vertical elements into 4 groups of 25 elements. In Level A, when you move one block vertically, the block name moves one block ("A0" → "A1", "A1" → "A2", "A2" → "A3"). represents.

[0072] Also, among the descriptions regarding vertical placement, 25_Addr:25 is In the memory contained in the Level B block, divide the 25 elements vertically into 25. In the memory contained in the Level B block, moving one tensor element vertically advances the address by 25 (for example, address "0" → "25", "1" → "26", etc.). represents.

[0073] On the other hand, among the descriptions regarding horizontal placement, 4_B:1 is In Level B, divide the 100 horizontal elements into 4 groups of 25 elements. In Level B, when you move one block horizontally, the block name moves forward by one ("B0" → "B1", "B1" → "B2", "B2" → "B3"). represents.

[0074] Also, among the descriptions regarding horizontal placement, 25_Addr:1 is In the memory contained in the Level B block, divide the 25 horizontal elements into 25. In the memory contained in the Level B block, moving one tensor element horizontally advances the address by one (for example, address "0" → "1", "1" → "2", etc.). represents.

[0075] In this way, based on the above description of the layout, the allocation unit 241 can allocate a memory address included in the Level B block of the chip 700 to each element of 100 rows x 100 columns.

[0076] <Specific example of processing by the writing unit> (1) Example 1 Next, a specific example of processing will be described in which the value of each element of tensor X is written to the corresponding memory in accordance with the address (FIG. 6) assigned by the assignment unit 241. FIG. 8 is a first diagram showing a specific example of processing by the writing unit.

[0077] 8, reference numeral 800 indicates a specific example of the values ​​of each element of tensor X of 100 rows and 100 columns (data stored in data storage unit 214). Also in FIG. 8, reference numeral 600′ indicates a state in which the values ​​of each element of tensor X are written to memory included in the Level B block of chip 600.

[0078] For example, in the block with block name="A0", the memory contained in the block with block name="B0" is: Addresses "0" to "24" contain x 1_1 ~x 1_25 is written, Addresses "25" to "49" have x 2_1 ~x 2_25 is written, ... Addresses "600" to "624" include x 25_1 ~x 25_25 is written.

[0079] Also, in the block with block name="A0", the memory contained in the block with block name="B1" is Addresses "0" to "24" contain x 1_26 ~x 1_50 is written, Addresses "25" to "49" have x 2_26 ~x 2_50 is written, ... Addresses "600" to "624" include x 25_26 ~x 25_50 is written.

[0080] Also, in the block with block name="A0", the memory included in the block with block name="B2" is Addresses "0" to "24" contain x 26_1 ~x 26_25 is written, Addresses "25" to "49" have x 27_1 ~x 27_25 is written, ... Addresses "600" to "624" include x 50_1 ~x 50_25 is written.

[0081] Also, in the block with block name="A0", the memory contained in the block with block name="B3" is Addresses "0" to "24" contain x 26_26 ~x 26_50 is written, Addresses "25" to "49" have x 27_26 ~x 27_50 is written, ... Addresses "600" to "624" include x 50_26 ~x 50_50 is written.

[0082] Thereafter, the value of each element of tensor X is similarly written to the memory included in the block of Level B.

[0083] In this way, the writing unit 251 can write each element of 100 rows x 100 columns into the memory included in the Level B block of the chip 600.

[0084] (2) Example 2 Next, a specific example of processing will be described in which the value of each element of tensor X is written to the corresponding memory in accordance with the address (FIG. 7) assigned by assignment unit 241. FIG. 9 is a second diagram showing a specific example of processing by the writing unit.

[0085] 9, reference numeral 800 indicates a specific example of the values ​​of each element of tensor X of 100 rows and 100 columns (data stored in the data storage unit 214). Also, in FIG. 9, reference numeral 700′ indicates a state in which the values ​​of each element of tensor X are written to a memory included in a Level B block of the chip 700.

[0086] For example, in the block with block name="A0", the memory contained in the block with block name="B0" is: Addresses "0" to "24" contain x 1_1 ~x 1_25 is written, Addresses "25" to "49" have x 2_1 ~x 2_25 is written, ... Addresses "600" to "624" include x 25_1 ~x 25_25 is written.

[0087] Also, in the block with block name="A0", the memory contained in the block with block name="B1" is Addresses "0" to "24" contain x 1_26 ~x 1_50 is written, Addresses "25" to "49" have x 2_26 ~x 2_50 is written, ... Addresses "600" to "624" include x 25_26 ~x 25_50 is written.

[0088] Also, in the block with block name="A0", the memory included in the block with block name="B2" is Addresses "0" to "24" contain x 1_51 ~x 1_75 is written, Addresses "25" to "49" have x 2_51 ~x 2_75 is written, ... Addresses "600" to "624" include x 25_51 ~x 25_75 is written.

[0089] Also, in the block with block name="A0", the memory contained in the block with block name="B3" is Addresses "0" to "24" contain x 1_76 ~x 1_100 is written, Addresses "25" to "49" have x 2_76 ~x 2_100 is written, ... Addresses "600" to "624" include x 25_76 ~x 25_100 is written.

[0090] Thereafter, the value of each element of tensor X is similarly written to the memory included in the block of Level B.

[0091] In this way, the writing unit 251 can write each element of 100 rows x 100 columns into the memory included in the Level B block of the chip 700.

[0092] <Specific example of processing by the element value reading unit> Next, we will explain a specific example of processing by the element value reading unit 252. As described above, the element value reading unit 252 reads the value of a specific element of a tensor written to memory, based on a description related to an index included in the source code 230.

[0093] (1) Example 1 Fig. 10 is a first diagram showing a specific example of processing by the element value reading unit. The example in Fig. 10 shows how the value of index (91, 36) is read out when the values ​​of the elements of tensor X shown by reference numeral 800 in Fig. 8 are written to chip 600 (see reference numeral 600') based on the "layout description" in Fig. 6(b).

[0094] As shown in Figure 10, the element value reading unit 252 identifies the vertical block of Level A based on the quotient obtained by dividing the value (="91") for identifying the vertical address by the number of vertical elements per block of Level A (="50").

[0095] In the example of FIG. 10, the quotient value is "1", so the element value reading unit 252 identifies the vertical block of Level A as the first block (block name="A2" or "A3").

[0096] Next, the element value reading unit 252 identifies the vertical blocks of Level B based on the quotient obtained by dividing the remainder value (="41") by the number of vertical elements per block of Level B (="25").

[0097] In the example of FIG. 10, the quotient value is "1", so the element value reading unit 252 identifies the vertical block of Level B as the first block (block name="B2" or "B3").

[0098] Next, the element value reading unit 252 identifies the vertical position of the tensor as the 16th row from the remainder value (="16").

[0099] Similarly, the element value reading unit 252 identifies the horizontal blocks of Level A based on the quotient obtained by dividing the value (="36") for identifying the horizontal address by the number of horizontal elements per block of Level A (="50").

[0100] In the example of FIG. 10, the quotient value is "0", so the element value reading unit 252 identifies the horizontal block of Level A as the 0th block (block name="A0" or "A2").

[0101] Next, the element value reading unit 252 identifies the horizontal blocks of Level B based on the quotient obtained by dividing the remainder value (="36") by the number of horizontal elements per block of Level B (="25").

[0102] In the example of FIG. 10, the quotient value is "1", so the element value reading unit 252 identifies the horizontal block of Level B as the first block (block name="B1" or "B3").

[0103] Next, the element value reading unit 252 identifies the horizontal position of the tensor as the 11th column from the remainder value (="11").

[0104] As a result, the element value reading unit 252 The block on Level A has the block name ="A2", The block on Level B has the block name = "B3", The memory address is 16th row x 25 + 11th column = "411th address" (see code 1000), Identify that.

[0105] As a result, the element value reading unit 252 can read the value written to the address specified based on the description related to the index.

[0106] In this way, the index (91,36) is decomposed into ((1,1,16), (0,1,11)), respectively. For the Level A block, 1 × stride(="2") + 0 × stride(="1") = 2, For the Level B block, 1 × stride (="2") + 1 × stride (="1") = 3, · As the memory address, 16 × stride (="25") + 11 × stride (="1") = 411, By performing the calculation, it is possible to identify the block name="A2" as the block of Level A, the block name="B3" as the block of Level B, and the "411th address" as the memory address.

[0107] As described above, in this embodiment, the ((1,1,16), (0,1,11)) obtained by the element value reading unit 252 decomposing the index (91,36) is referred to as, for example, a "decomposed index." Also, as described above, the block name="A2", block name="B3", and memory address="411th address" identified by the element value reading unit 252 from the index (91,36) are referred to as, for example, an "index for each layer."

[0108] Expressions such as "decomposed index" ((1,1,16), (0,1,11)) and "indexes for each hierarchy" ("A2", "B3", "411th address") may be used in the process of generating machine code by the compilation unit 213. For example, they may be used as a method of identifying each element of a tensor when generating machine code that changes the layout of the same tensor.

[0109] When the values ​​of each element of tensor X indicated by reference numeral 800 in FIG. 8 are written to chip 600, a reduction in communication costs can be achieved when tensor X is calculated in units of, for example, a 3×3 matrix or a 5×5 matrix. This is because the number of times different blocks are crossed at Level A can be reduced when calculations are performed in units of a 3×3 matrix or a 5×5 matrix. Calculations performed in units of a 3×3 matrix or a 5×5 matrix include, for example, convolution processing and pooling processing.

[0110] (2) Example 2 Fig. 11 is a second diagram showing a specific example of processing by the element value reading unit. The example in Fig. 11 shows how the value of index (91, 36) is read out when the values ​​of each element of tensor X indicated by reference numeral 900 in Fig. 9 are written to chip 700 (see reference numeral 700') based on the "layout description" in Fig. 7(b).

[0111] As shown in FIG. 11, the element value reading unit 252 identifies the vertical block of Level A based on the quotient obtained by dividing the value (="91") for identifying the vertical address by the number of vertical elements per block of Level A (="25").

[0112] In the example of FIG. 11, the quotient value is "3", so the element value reading unit 252 identifies the block in the vertical direction of Level A as the third block (block name="A3").

[0113] Next, the element value reading unit 252 identifies the vertical position of the tensor as the 16th row from the remainder value (="16").

[0114] Similarly, the element value reading unit 252 identifies the horizontal block of Level B based on the quotient obtained by dividing the value (="36") for identifying the horizontal address by the number of horizontal elements per block of Level B (="25").

[0115] In the example of FIG. 11, the quotient value is "1", so the element value reading unit 252 identifies the horizontal block of Level B as the first block (block name="B1").

[0116] Next, the element value reading unit 252 identifies the horizontal position of the tensor as the 11th column from the remainder value (="11").

[0117] As a result, the element value reading unit 252 The block on Level A has the block name="A3", The block on Level B has the block name = "B1", The memory address is 16th row x 25 + 11th column = "411th address" (see code 1100), Identify that.

[0118] As a result, the element value reading unit 252 can read the value written to the address specified based on the description related to the index.

[0119] In this way, the index (91,36) is decomposed into ((3,16), (1,11)), respectively. For the Level A block, 3 x stride (="1") = 3, ·For the LevelB block, 1 × stride(="1") = 1, · As the memory address, 16 × stride (="25") + 11 × stride (="1") = 411, By performing the calculation, it is possible to identify the block name="A3" as the block of Level A, the block name="B1" as the block of Level B, and the "411th address" as the memory address.

[0120] 9 is written to the chip 700, communication costs can be reduced when calculating the statistical values ​​for each row of the tensor X. This is because there is no need to cross different blocks at Level A when calculating the statistical values ​​for each row of the tensor X.

[0121] <Data processing flow by the data processing system> Next, we will explain the flow of data processing by the data processing system 100. Here, we will explain the source code generation process by the source code description unit 211 and the generation unit 212, the machine code generation process by the compilation unit 213, and the machine code execution process by the execution unit 220 separately.

[0122] (1) Source code generation process First, a description will be given of the flow of source code generation processing by the source code description unit 211 and the generation unit 212. Fig. 12 is a flowchart showing the flow of source code generation processing. The source code generation processing shown in Fig. 12 starts when the user starts the source code description unit 211.

[0123] In step S1201, the user starts writing source code, which causes the source code writing unit 211 to accept the source code written by the user.

[0124] In step S1202, the user determines whether or not a description related to a tensor has been made, and if it is determined that a description related to a tensor has been made (YES in step S1202), the process proceeds to step S1203, whereby the source code description unit 211 accepts a description related to a tensor made by the user.

[0125] In step S1203, the user writes a description about the layout, and the process proceeds to step S1204, whereby the source code description unit 211 accepts the description about the layout by the user.

[0126] On the other hand, if it is determined in step S1202 that there is no description related to a tensor (NO in step S1202), the process proceeds directly to step S1204.

[0127] In step S1204, the user determines whether or not to end the description of the source code. If it is determined in step S1204 that the description of the source code is not to end (NO in step S1204), the process returns to step S1202, and the description of the source code continues.

[0128] On the other hand, if it is determined in step S1204 that the description of the source code has been completed (YES in step S1204), the process proceeds to step S1205.

[0129] In step S1205, the user starts the generation unit 212 and instructs it to generate a computation graph, etc. As a result, the generation unit 212 obtains the source code from the source code description unit 211 and generates a computation graph, etc. In addition, the generation unit 212 notifies the compilation unit 213 of the generated computation graph, etc.

[0130] (2) Machine code generation process Next, a description will be given of the flow of machine code generation processing by the compiling unit 213. Fig. 13 is a flowchart showing the flow of machine code generation processing. When the user starts the compiling unit 213 of the compiling device 120, the compiling unit 213 starts the machine code generation processing shown in Fig. 13.

[0131] In step S1301, the compiling unit 213 starts the compiling process based on the computation graph and the like.

[0132] In step S1302, the compiler 213 determines whether or not there is a description related to layout. If it is determined in step S1302 that there is a description related to layout (YES in step S1302), the process proceeds to step S1303.

[0133] In step S1303, the compilation unit 213 assigns a memory address to each element of the tensor based on the description regarding the layout, and proceeds to step S1304.

[0134] On the other hand, if it is determined in step S1302 that there is no description regarding layout (NO in step S1302), the process proceeds directly to step S1304.

[0135] In step S1304, it is determined whether or not the compilation process has been completed for the computation graph, etc. In step S1304, if it is determined that the compilation process has not been completed (NO in step S1304), the process returns to step S1302, and the compilation process continues.

[0136] On the other hand, if it is determined in step S1304 that the compilation process for the computation graph etc. has been completed (YES in step S1304), the machine code generation process is terminated.

[0137] (3) Machine code execution process Next, we will explain the flow of machine code execution processing by the execution unit 220. Fig. 14 is a flowchart showing the flow of machine code execution processing. When a user specifies data to be processed that is stored in the data storage unit 214 and inputs an execution instruction to the execution unit 220 of the server device 110, the execution unit 220 starts the machine code execution processing shown in Fig. 14.

[0138] In step S1401, the execution unit 220 starts the operation of the machine code.

[0139] In step S1402, the execution unit 220 writes the value of each element of the tensor (the data to be processed stored in the data storage unit 214) to the address of the allocated memory.

[0140] In step S1403, the execution unit 220 sequentially executes various processes included in the machine code 1410. For example, the execution unit 220 performs padding in accordance with a code indicating padding, and updates the allocated memory with the values ​​of each element of the tensor after the processing. Also, the execution unit 220 performs broadcasting in accordance with a code indicating broadcasting, and updates the allocated memory with the values ​​of each element of the tensor after the processing.

[0141] When all of the various processes included in the machine code 1410 have been executed, or when a predetermined termination condition is met, the execution unit 220 terminates the machine code execution process.

[0142] <Summary> As is clear from the above description, the compiling device 120 according to the first embodiment: Generate machine code that runs on an accelerator chip with multiple distributed memories connected by a tree topology. Based on the number of divisions per layer and stride (vertical or horizontal) for the tensor to be processed, addresses are assigned to each element of the tensor to be processed within multiple memories of the accelerator chip.

[0143] As a result, according to the first embodiment, it becomes possible to appropriately represent the arrangement of each element of a tensor with respect to a plurality of memories connected by a tree-structure topology.

[0144] [Second embodiment] In the above first embodiment, the compiling device 120 has been described as being arranged within the server device 110, but the compiling device 120 may be configured separately from the server device 110. Furthermore, in the above first embodiment, the compiling unit 213 has been described as being realized by the compiling device 120, but the compiling unit 213 may be realized, for example, in a terminal device (not shown). Alternatively, the compiling unit 213 may be realized in an external device other than a terminal (for example, another server device).

[0145] In the above first embodiment, the source code description unit 211, the generation unit 212, and the compilation unit 213 are described as being realized by the compiling device 120. However, the source code description unit 211 may be realized by a terminal device connected to the server device 110, in which the compiling device 120 is arranged, via a network. Alternatively, the source code description unit 211 and the generation unit 212 may be realized by a terminal device connected to the server device 110, in which the compiling device 120 is arranged, via a communication network 150.

[0146] Fig. 15 is a second diagram showing an example of the functional configuration of each device in the data processing system. The example of Fig. 15 shows a state in which the source code description unit 211 and the generation unit 212 are realized by a terminal device 1510, and the source code 230 is displayed on a display device 1520 connected to the terminal device 1510. In the example of Fig. 15, the computation graph etc. generated by the terminal device 1510 is transmitted to the compiling device 120.

[0147] In addition, in the above first embodiment, the computation graph is described as being generated by executing the source code 230 and converting it into the ONNX representation format, but the method for generating the computation graph is not limited to this, and the computation graph may be generated by other methods.

[0148] In the first embodiment, the generation unit 212 generates a layout instruction based on a layout description input by a user, and the compilation unit 213 assigns an address to each element of a tensor in accordance with the layout instruction. However, the method of assigning addresses is not limited to this, and for example, the compilation unit 213 may select a layout and assign an address to each element of a tensor in accordance with the selected layout.

[0149] In the first embodiment, for example, the chip 170_1 has four third-level blocks in the hierarchy of Level A and four second-level blocks in the hierarchy of Level B (FIG. 3). However, the number of blocks (memories) in each hierarchy and the number of hierarchies (depth) are not limited to this and are arbitrary.

[0150] In addition, in the first embodiment, Level A: 3rd level block, Level B: Second-level blocks, Level C: 1st level block, However, the definition of each layer is not limited to this. For example, Level A hierarchy: chip, Level B: 3rd level block, Level C: Second-level blocks, Level D hierarchy: 1st hierarchy block, Or you can say, Level A: chips and third-level blocks, Level B: Second-level blocks, Level C: 1st level block, It may also be possible to use the following.

[0151] In addition, in the case of "Level A hierarchy: chips and third-level blocks," for example, if one board is equipped with four chips, each of which has four third-level blocks, the layout for Level A hierarchy can be described as if there were 16 third-level blocks.

[0152] The layer to which the memory belongs is not limited to the lowest layer, and may be changed to another layer. Also, the first and second embodiments may be applied by defining layers such as a structure bundling top-level memories (e.g., chips), a structure bundling chips (e.g., nodes), and a structure bundling nodes.

[0153] [Other embodiments] In this specification (including the claims), when the expression "at least one of a, b, and c" or "at least one of a, b, or c" (including similar expressions) is used, it includes any of a, b, c, ab, ac, bc, or abc. It may also include multiple instances of any element, such as aa, abb, aabbcc, etc. Furthermore, it also includes the addition of elements other than the enumerated elements (a, b, and c), such as having d, as in abcd.

[0154] Furthermore, in this specification (including claims), when expressions such as "using data as input / based on / according to / in response to" (including similar expressions) are used, unless otherwise specified, this includes cases where various data itself is used as input, or where various data that has been processed in some way (e.g., noise-added, normalized, intermediate representation of various data, etc.) is used as input. Furthermore, when it is stated that a result is obtained "based on / according to / in response to data," this includes cases where the result is obtained based solely on the data in question, as well as cases where the result is obtained as a result of being influenced by other data, causes, conditions, and / or states other than the data in question. Furthermore, when it is stated that "data is output," unless otherwise specified, this includes cases where various data itself is used as output, or where various data that has been processed in some way (e.g., noise-added, normalized, intermediate representation of various data, etc.) is output.

[0155] Furthermore, when the terms "connected" and "coupled" are used in this specification (including the claims), they are intended as open-ended terms that include any of direct connection / coupling, indirect connection / coupling, electrically connection / coupling, communicatively connection / coupling, functionally connection / coupling, and physically connection / coupling. These terms should be interpreted appropriately depending on the context in which they are used, but any form of connection / coupling that is not intentionally or naturally excluded should be interpreted as being included in these terms without any restrictions.

[0156] Furthermore, in this specification (including the claims), when the expression "A configured to B" is used, it may include the physical structure of element A having a configuration capable of performing operation B, and the permanent or temporary setting / configuration of element A being configured / set to actually perform operation B. For example, if element A is a general-purpose processor, it is sufficient that the processor has a hardware configuration capable of performing operation B, and is configured to actually perform operation B by setting a permanent or temporary program (instruction). Furthermore, if element A is a dedicated processor or dedicated arithmetic circuit, it is sufficient that the circuit structure of the processor is implemented to actually perform operation B, regardless of whether control instructions and data are actually attached.

[0157] Furthermore, when words implying containing or possessing (such as "comprising / including" and "having") are used in this specification (including the claims), they are intended to be open-ended terms that include cases where things other than the object indicated by the object of the term are contained or possessed. When the object of such words implying containing or possessing does not specify a quantity or suggests a singular number (such as an expression using the article "a" or "an"), the expression should be construed as not being limited to a specific number.

[0158] Furthermore, in this specification (including the claims), even if expressions such as "one or more" or "at least one" are used in some places and expressions that do not specify a quantity or suggest a singular number (expressions using the articles "a" or "an") are used in other places, the latter expressions are not intended to mean "one." In general, expressions that do not specify a quantity or suggest a singular number (expressions using the articles "a" or "an") should be interpreted as not necessarily being limited to a specific number.

[0159] Furthermore, if a particular advantage / result is described in this specification as being obtained from a particular configuration of an embodiment, it should be understood that the same advantage / result can also be obtained from one or more other embodiments having the same configuration, unless otherwise stated. However, it should be understood that the presence or absence of the effect generally depends on various causes, conditions, and / or states, etc., and that the effect is not necessarily obtained by the configuration. The effect is merely obtained by the configuration described in the embodiment when various causes, conditions, and / or states, etc. are satisfied, and the effect does not necessarily occur in a claimed invention that defines the same or a similar configuration.

[0160] When the term "optimize" or "optimization" is used in this specification (including the claims), it should be interpreted appropriately according to the context in which the term is used, including determining a global optimum, determining an approximation of a global optimum, determining a local optimum, and determining an approximation of a local optimum. It also includes determining an approximation of these optimum values ​​probabilistically or heuristically.

[0161] Furthermore, in this specification (including claims), when multiple pieces of hardware perform a predetermined process, the pieces of hardware may cooperate to perform the predetermined process, or some of the hardware may perform all of the predetermined process. Furthermore, some of the hardware may perform part of the predetermined process, and other hardware may perform the rest of the predetermined process. In this specification (including claims), when an expression such as "one or more pieces of hardware perform a first process, and the one or more pieces of hardware perform a second process" is used, the hardware performing the first process and the hardware performing the second process may be the same or different. In other words, it is sufficient that the hardware performing the first process and the hardware performing the second process are included in the one or more pieces of hardware. Note that hardware may include an electronic circuit, a device including an electronic circuit, or the like.

[0162] Furthermore, in this specification (including the claims), when multiple storage devices (memories) store data, each of the multiple storage devices (memories) may store only a portion of the data, or may store the entire data.

[0163] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the individual embodiments described above. Various additions, modifications, substitutions, partial deletions, etc. are possible within the scope of the conceptual idea and spirit of the present invention derived from the content defined in the claims and their equivalents. For example, in all of the above-described embodiments, when numerical values ​​or formulas are used in the explanation, they are shown as examples and are not limited to these. Furthermore, the order of each operation in the embodiments is shown as an example and is not limited to these.

Claims

1. 1. A compiling device for generating machine code to be executed on a chip having at least a first tier and a second tier, comprising: the second layer is higher than the first layer, and the first layer has a plurality of first blocks; The compiling device at least one memory; at least one processor; The at least one processor Obtaining a tensor to be processed on the chip; executes a process of associating each element of the tensor with any one of the plurality of first blocks included in the chip, based on at least the number of divisions in the first layer of the chip; generating the machine code to be executed on the chip based on the associating process; the first layer used in the association process corresponds to a hardware configuration of the chip; Compilation device.

2. the at least one processor executes the associating process based on at least the number of divisions in the first layer and the stride in the first layer. The compiling device according to claim 1 .

3. each of the plurality of first blocks includes at least one memory among a plurality of memories included in the chip; As the associating process, the at least one processor executes a process of associating each element of the tensor with an address of the plurality of memories included in the chip, based on at least the number of divisions in the first layer.

3. The compiling device according to claim 1.

4. the number of divisions in the first layer includes at least the number of divisions in the vertical direction and the number of divisions in the horizontal direction in the first layer; The compiling device according to any one of claims 1 to 3.

5. the stride in the first hierarchical layer includes at least a stride in a vertical direction and a stride in a horizontal direction in the first hierarchical layer; The compiling device according to claim 2 .

6. the second hierarchical level includes a plurality of second blocks, each of which includes the plurality of first blocks; The associating process includes: the at least one processor includes another process of associating each element of the tensor with any one second block among the plurality of second blocks included in the chip, based on at least the number of divisions in the second layer of the chip; the second layer used in the other process of associating corresponds to a hardware configuration of the chip; The compiling device according to any one of claims 1 to 5.

7. the at least one processor executes the other associating process based on at least the number of divisions in the second hierarchical layer and the stride in the second hierarchical layer. The compiling device according to claim 6.

8. the number of divisions in the first hierarchy and the number of divisions in the second hierarchy are different from each other; 8. The compiling device according to claim 6 or 7.

9. The at least one processor further obtains a computation graph to be processed on the chip, and the tensor is a tensor used in the computation graph. The compiling device according to any one of claims 1 to 8.

10. The at least one processor further generates the computation graph based on source code. The compiling device according to claim 9 .

11. the number of divisions in the first hierarchy is described in the source code; The compiling device according to claim 10.

12. The at least one processor included in the compiling device according to any one of claims 1 to 11 generates the machine code. Generation method.

13. The generating method according to claim 12 is executed by at least one processor included in a compiling device. program.

14. a compilation device having at least one memory and at least one processor; a chip having at least a first tier and a second tier, the second layer is higher than the first layer, and the first layer has a plurality of first blocks; The at least one processor Obtaining a tensor to be processed on the chip; executes a process of associating each element of the tensor with any one of the plurality of first blocks included in the chip, based on at least the number of divisions in the first layer of the chip; generating machine code to be executed on the chip based on the mapping process; The chip is By executing the machine code generated by the compiling device performing the associating process, at least one of a process of writing values ​​of each element of the tensor to the first block associated with each element of the tensor, or a process of reading values ​​of each element of the tensor from the first block associated with each element of the tensor is performed; the first layer used in the association process corresponds to a hardware configuration of the chip; system.

15. When executing a process of writing values ​​of each element of the tensor to the first block associated with each element of the tensor, the chip executes a padding process of adjusting a size according to a memory of a write destination. The system of claim 14.

16. The chip further performs broadcast processing when performing an operation between tensors whose array shapes do not match.

16. A system according to claim 14 or claim 15.

17. the at least one processor executes the associating process based at least on the number of divisions in the first layer and the stride in the first layer.

17. A system according to any one of claims 14 to 16.

18. the chip further comprises a plurality of memories, and each of the plurality of first blocks includes at least one memory of the plurality of memories; As the associating process, the at least one processor executes a process of associating each element of the tensor with an address of the plurality of memories included in the chip, based on at least the number of divisions in the first layer.

18. A system according to any one of claims 14 to 17.

19. the plurality of memories included in the chip are connected in a tree structure; 20. The system of claim 18.

20. the second layer of the chip includes a plurality of second blocks, each of the second blocks including the plurality of first blocks; The associating process includes: the at least one processor includes another process of associating each element of the tensor with any one second block among the plurality of second blocks included in the chip, based on at least the number of divisions in the second layer of the chip; the second layer used in the other process of associating corresponds to a hardware configuration of the chip; 20. A system according to any one of claims 14 to 19.

21. each of the plurality of first blocks includes at least one arithmetic unit; 21. A system according to any one of claims 14 to 20.

22. The chip operates according to a SIMD architecture.

22. A system according to any one of claims 14 to 21.

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