Power supply device

Abstract

To suppress an in-rush current.SOLUTION: In a power supply device, a first capacitance element is electrically connected between a first input node and a first node. A second capacitance element is electrically connected between a second input node and the first node. A first switching element is electrically connected between the first input node and the second node. A second switching element is electrically connected between the first node and the second node. A third switches element is electrically connected between the first node and a third node. A fourth switching element is electrically connected between the second input node and the third node. A third capacitance element is electrically connected between the second node and the third node. A first inductive element is electrically connected between the second node and the first output node. A second inductive element is electrically connected to the third capacitance element in series between the second node and the third node.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power supply device. [Background technology]

[0002] Power supply devices are sometimes configured using switched capacitor circuits (see, for example, Patent Document 1). In these power supply devices, the switched capacitor circuit is provided with a plurality of sets of switching elements and capacitors. In the switched capacitor circuit, even-numbered switching elements and odd-numbered switching elements are alternately turned on to equalize the voltages of the plurality of capacitors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-158334 Summary of the Invention [Problem to be solved by the invention]

[0004] In a power supply device, when even-numbered switching elements and odd-numbered switching elements in a switched capacitor circuit are alternately turned on, a large transient inrush current may occur in the capacitor. When a large inrush current occurs, elements such as the switching elements are more likely to deteriorate.

[0005] The present disclosure provides a power supply device that can suppress inrush current. [Means for solving the problem]

[0006] The power supply device according to the present disclosure includes a first capacitive element, a second capacitive element, a first switching element, a second switching element, a third switching element, a fourth switching element, a third capacitive element, a first inductive element, and a second inductive element. A fourth capacitance element and a resistance element The first capacitance element has Ground potentialThe second capacitance element is electrically connected between the first input node and the first node. The absolute value of the potential is higher than that of the ground potential The first switching element is electrically connected between the second input node and the first node. The first switching element is electrically connected between the first input node and the second node. The second switching element is electrically connected between the first node and the second node. The third switching element is electrically connected between the first node and the third node. The fourth switching element is electrically connected between the second input node and the third node. The third capacitive element is electrically connected between the second node and the third node. The first inductive element is connected between the second node and the first output node. One end The second inductive element is electrically connected in series with the third capacitive element between the second node and a third node. The fourth capacitive element is electrically connected between the first input node and the other end of the first inductive element. The resistive element is electrically connected in parallel with the fourth capacitive element between the first input node and the other end of the first inductive element. A circuit including the first capacitive element, the second capacitive element, the first switching element, the second switching element, the third switching element, and the fourth switching element functions as a switched capacitor circuit. A circuit including the first switching element, the first inductive element, the fourth capacitive element, and the resistive element functions as a step-down chopper circuit. The power supply device is capable of generating a resonant current in a first loop. The first loop includes a first capacitive element, a third capacitive element, and a second inductive element. The power supply device is capable of generating a resonant current in a second loop. The second loop includes a second capacitive element, a third capacitive element, and a second inductive element. The resonant frequency of the first loop and the resonant frequency of the second loop are all lower than the switching frequencies of the first switching element, the second switching element, the third switching element, and the fourth switching element. [Effects of the Invention]

[0007] The power supply device according to the present disclosure can suppress inrush current. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing the configuration of a power supply device according to an embodiment. [Figure 2] FIG. 3 is a waveform diagram showing the operation of the power supply device according to the embodiment. [Figure 3] FIG. 3 is a waveform diagram showing the operation of the power supply device according to the embodiment. [Figure 4] 5A to 5C are waveform diagrams showing operation in a plurality of modes in the embodiment. [Figure 5] FIG. 3 is a circuit diagram illustrating operation in multiple modes in an embodiment. [Figure 6] FIG. 10 is a circuit diagram showing the configuration of a power supply device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of a power supply device according to the present disclosure will be described with reference to the drawings. (Embodiment) The power supply device according to the embodiment is configured by connecting a step-down chopper circuit to a switched capacitor circuit, and further includes an inrush current suppression circuit. The inrush current suppression circuit is a circuit for suppressing inrush current in the switched capacitor circuit. For example, the power supply device 1 may be configured as shown in FIG. 1. FIG. 1 is a circuit diagram showing the configuration of the power supply device according to the embodiment.

[0010] The power supply device 1 is electrically connected between an external power supply Vin and a load circuit LD. The power supply device 1 is connected to the power supply Vin via input nodes Nin1 and Nin2, and to the load circuit LD via output nodes Nout1 and Nout2. The input node Nin1 is connected to ground potential and the positive side of the power supply Vin. The input node Nin1 is connected to the negative side of the power supply Vin. In other words, the power supply device 1 is a power supply device that operates on a negative power supply voltage Vin. The power supply device 1 receives a power supply voltage Vin from the power supply Vin and generates a power supply voltage Vout for the load circuit LD in accordance with the power supply voltage Vin. The power supply device 1 supplies the power supply voltage Vout to the load circuit LD. The power supply device 1 includes a switched capacitor circuit 2, a step-down chopper circuit 3, and an inrush current suppression circuit 4. The switched capacitor circuit 2 is electrically connected between the input nodes Nin1 and Nin2 and the step-down chopper circuit 3. The step-down chopper circuit 3 is electrically connected between the switched capacitor circuit 2 and output nodes Nout1 and Nout2. The inrush current suppression circuit 4 is electrically connected to the switched capacitor circuit 2 and the step-down chopper circuit 3, respectively.

[0011] The switched capacitor circuit 2 is a circuit that can boost, lower, and invert voltage polarity without using magnetic components. The switched capacitor circuit 2 is provided with multiple sets of switching elements and capacitors. The switched capacitor circuit 2 has a capacitance element Cin1, a capacitance element Cin2, a switching element Q1, a switching element Q2, a switching element Q3, and a switching element Q4. The capacitance element Cin1 corresponds to the switching elements Q1 and Q2 and forms one set. The capacitance element Cin2 corresponds to the switching elements Q3 and Q4 and forms one set. The capacitance element Cin1 is electrically connected between the input node Nin1 and the node N1. One end of the capacitance element Cin1 is connected to the input node Nin1 and the other end is connected to the node N1. The capacitance element Cin2 is electrically connected between the input node Nin2 and the node N1. One end of the capacitance element Cin2 is connected to the input node Nin2 and the other end is connected to the node N1.

[0012] The switching element Q1 is electrically connected between the input node Nin1 and the node N2. The switching element Q1 includes, for example, a transistor NM1 and a diode D1. The transistor NM1 is, for example, an NMOS transistor, and has a gate connected to an external control circuit CTR, a source connected to the node N2, and a drain connected to the input node Nin1 and the output node Nout1. The diode D1 is, for example, a parasitic diode of an NMOS transistor, and has a cathode connected to the input node Nin1 and an anode connected to the node N2. The switching element Q2 is electrically connected between the nodes N1 and N2. The switching element Q2 includes, for example, a transistor NM2 and a diode D2. The transistor NM2 is, for example, an NMOS transistor, and has a gate connected to the external control circuit CTR, a source connected to the node N1, and a drain connected to the node N2. The diode D2 is, for example, a parasitic diode of an NMOS transistor, and has a cathode connected to the node N2 and an anode connected to the node N1. The switching element Q3 is electrically connected between the nodes N1 and N3. The switching element Q3 includes, for example, a transistor NM3 and a diode D3. The transistor NM3 is, for example, an NMOS transistor, and has a gate connected to an external control circuit CTR, a source connected to node N3, and a drain connected to node N1. The diode D3 is, for example, a parasitic diode of an NMOS transistor, and has a cathode connected to node N1 and an anode connected to node N3. The switching element Q4 is electrically connected between the input node Nin2 and node N3. The switching element Q4 includes, for example, a transistor NM4 and a diode D4. The transistor NM4 is, for example, an NMOS transistor, and has a gate connected to the external control circuit CTR, a source connected to the input node Nin2, and a drain connected to node N3. The diode D4 is, for example, a parasitic diode of an NMOS transistor, and has a cathode connected to node N3 and an anode connected to the input node Nin2.

[0013] The switched capacitor circuit 2 does not have the function of regulating the magnitude of the power supply voltage Vout to be output from the power supply device 1. For this reason, a step-down chopper circuit 3 is connected in the subsequent stage of the switched capacitor circuit 2. The step-down chopper circuit 3 can regulate the magnitude of the power supply voltage Vout according to the switching duty ratio (i.e., the ratio of on / off times).

[0014] The step-down chopper circuit 3 has a switching element Q1, a capacitance element Co, an inductance element Lo, and a resistance element Ro. The step-down chopper circuit 3 shares the switching element Q1 with the switched capacitor circuit 2. The capacitance element Co is electrically connected between output nodes Nout1 and Nout2. One end of the capacitance element Co is connected to the output node Nout1, and the other end is connected to the output node Nout2. The inductance element Lo is electrically connected between node N2 and the output node Nout2. One end of the inductance element Lo is connected to node N2, and the other end is connected to the output node Nout2. The resistance element Ro is electrically connected between the output nodes Nout1 and Nout2. One end of the resistance element Ro is connected to the output node Nout1, and the other end is connected to the output node Nout2.

[0015] The switched capacitor circuit 2 is a circuit that includes multiple sets of switching elements and capacitors (Q1, Q2, Cin1), (Q3, Q4, Cin2), so there is a possibility that an excessive inrush current will flow under high load and high voltage conditions, resulting in increased switch loss. For this reason, the inrush current suppression circuit 4 is electrically connected to the switched capacitor circuit 2. The inrush current suppression circuit 4 can suppress the inrush current by delaying the phase of the current using resonance.

[0016] The inrush current suppression circuit 4 includes a capacitance element Cfly and an inductance element Lr. The resonant frequency of the loop including capacitance element Cin1, capacitance element Cfly, and inductance element Lr is lower than the switching frequency of switching element Q1, switching element Q2, switching element Q3, and switching element Q4. This allows the phase of the current flowing through the loop including capacitance element Cin1, capacitance element Cfly, and inductance element Lr to be delayed during switching. The resonant frequency of the loop including capacitance element Cin2, capacitance element Cfly, and inductance element Lr is lower than the switching frequency of switching element Q1, switching element Q2, switching element Q3, and switching element Q4. This allows the phase of the current flowing through the loop including capacitance element Cin2, capacitance element Cfly, and inductance element Lr to be delayed during switching. Note that the resonant frequency of the loop including capacitance element Cin1, capacitance element Cfly, and inductance element Lr may be the same as or different from the resonant frequency of the loop including capacitance element Cin2, capacitance element Cfly, and inductance element Lr. The capacitive element Cfly is electrically connected between the node N2 and the node N3. One end of the capacitive element Cfly is connected to the node N2, and the other end is connected to the node N3. The capacitive element Cfly can be in a floating state during switching, and is therefore also called a floating capacitor. The inductive element Lr is electrically connected in series with the capacitive element Cfly between the node N2 and the node N3. The inductive element Lr may be electrically connected between the node N2 and the capacitive element Cfly, or may be electrically connected between the capacitive element Cfly and the node N3. In FIG. 1, the inductive element Lr has one end connected to the node N2, and the other end connected to the capacitive element Cfly.

[0017] In the inrush current suppression circuit 4, an inductive element Lr is inserted in series with the capacitive element Cfly, which allows a resonant current to be generated in a loop including the inrush current suppression circuit 4. By designing the resonant frequency to be lower than the switching frequency, soft switching operation is possible when the switching elements (Q1, Q3, Q4) are turned on, reducing switch loss. This allows for highly efficient circuit operation.

[0018] Soft switching refers to switching operation in which the locus on the voltage-current characteristic plane of a switching element during the switching process moves within the triangular region connecting the maximum voltage point, maximum current point, and origin (a region that can be considered a gradual change). If the entire locus when the switching element is turned on and off falls within the triangular region, soft switching is successful; if it strays even slightly outside the triangular region, soft switching fails and hard switching occurs. For example, if the change in current and / or voltage accompanying the switching operation is within the transition time of the switching element's gate signal, it will fall outside the triangular region and the switching operation will often be hard switching. If the change in current and / or voltage accompanying the switching operation exceeds the transition time, it will fall within the triangular region and the switching operation will often be soft switching, but if a surge voltage occurs, it will momentarily leave the triangular region and become hard switching.

[0019] For example, the power supply 1 may operate as shown in FIGS. 2 and 3. FIGS. 2 and 3 are waveform diagrams illustrating the operation of the power supply 1, respectively. FIG. 2 shows the results of a simulation of the operation of switching elements Q1 and Q2, and FIG. 3 shows the results of a simulation of the operation of switching elements Q3 and Q4. The simulations for both FIGS. 2 and 3 were performed under the following conditions: the input voltage Vin from the power supply Vin is 1500 V; the capacitance value Cin1 of the capacitive element Cin1 is 12 μF; the capacitance value Cin2 of the capacitive element Cin2 is 12 μF; the capacitance value Cin3 of the capacitive element Cin3 is 12 μF; the inductance value Lr of the inductive element Lr is 500 nH; the inductance value Lo of the inductive element Lo is 100 μH; the capacitance value Co of the capacitive element Co is 12 μF; and the resistance value Ro of the resistive element Ro is 16.66 Ω. The switching frequency is 100 kHz. The duty ratio is (on period of switching element Q2) / (switching cycle). The duty ratio is 50%. The interval (dead time) between the on period of switching element Q1 and the on period of switching element Q2 is 120 ns. Switching elements Q1 and Q3 are turned on and off simultaneously. Switching elements Q2 and Q4 are turned on and off simultaneously. Under these conditions, the resonant frequency of the loop including capacitance element Cin1, capacitance element Cfly, and inductance element Lr is 91.9 kHz, which is lower than the switching frequency of 100 kHz. The resonant frequency of the loop including capacitance element Cin2, capacitance element Cfly, and inductance element Lr is 91.9 kHz, which is lower than the switching frequency of 100 kHz.

[0020] Figures 2(d) and 2(f) show waveform diagrams in which the portion enclosed by the dashed-dotted line in Figures 2(a) to 2(c) is enlarged in the time direction. Figures 2(g) to 2(i) show waveform diagrams in which the portion enclosed by the dashed-dotted line in Figures 2(a) to 2(c) is enlarged in the time direction. In Figures 2(a), 2(d), and 2(g), the gate signal of switching element Q1 is indicated by a solid line, and the gate signal of switching element Q2 is indicated by a dotted line. In Figures 2(b), 2(e), and 2(h), the voltage across switching element Q1 is indicated by a solid line, and the current flowing through switching element Q1 is indicated by a dotted line. In Figures 2(c), 2(f), and 2(i), the voltage across switching element Q2 is indicated by a solid line, and the current flowing through switching element Q2 is indicated by a dotted line. As shown in FIG. 2(a), switching element Q1 is turned on at time t1, turned off at time t2, turned on at time t5, and turned off at time t6. Switching element Q2 is turned on at time t3, turned off at time t4, and turned on at time t7. The periods from t2 to t3, t4 to t5, and t6 to t7 are dead times during which switching element Q1 and switching element Q2 are both off. As shown in FIGS. 2(a) and 2(d), when switching element Q1 is turned off at time t2, a substantially constant negative current flows through switching element Q1, as shown in FIGS. 2(b) and 2(e). That is, as shown by the dotted line in FIG. 2(e), when switching element Q1 is off, current flows through parasitic diode D1, and the current changes gradually in response to changes in the gate signal voltage, resulting in soft switching. As shown in Figures 2(a) and 2(g), when switching element Q1 is turned on at time t5, a substantially constant negative current flows through switching element Q1, as shown in Figures 2(b) and 2(h). That is, as shown by the dotted line in Figure 2(h), when switching element Q1 is on, current flows through parasitic diode D1, and the current changes gradually in response to changes in gate signal voltage, resulting in soft switching. As shown in Figures 2(a) and 2(g), when switching element Q2 is turned on at time t3, a surge current flows through switching element Q2, as shown in Figures 2(c) and 2(f).That is, as shown by the dashed line in FIG. 2(f), the current in the switching element Q2 changes suddenly in response to a change in the voltage of the gate signal when the element is turned on, resulting in a hard switch operation.

[0021] However, by utilizing the resonance characteristics of the loop including the inrush current suppression circuit 4, part of the current that flows when switching element Q2 flows through the loop including the inrush current suppression circuit 4. As a result, the current that flows through switching element Q2 is reduced compared to when the inrush current suppression circuit 4 is not provided. Therefore, the loss level, expressed as voltage x current, is reduced compared to conventional cases.

[0022] As shown in Figures 2(a) and 2(d), when switching element Q2 is turned off at timing t4, the positive current flowing through switching element Q2 changes to zero, just like the gate signal, as shown in Figures 2(c) and 2(i). In other words, as shown in Figures 2(g) and 2(i), the transition time of the gate signal for switching element Q2 and the transition time of the current are approximately equal, resulting in operation at the boundary conditions between soft and hard switching.

[0023] Figures 3(d) and 3(f) show waveform diagrams in which the portions enclosed by the dashed-dotted lines in Figures 3(a) to 3(c) are enlarged in the time direction. Figures 3(g) to 3(i) show waveform diagrams in which the portions enclosed by the dashed-dotted lines in Figures 3(a) to 3(c) are enlarged in the time direction. In Figures 3(a), 3(d), and 3(g), the gate signal for switching element Q3 is indicated by a solid line, and the gate signal for switching element Q4 is indicated by a dotted line. In Figures 3(b), 3(e), and 3(h), the voltage across switching element Q3 is indicated by a solid line, and the current flowing through switching element Q3 is indicated by a dotted line. In Figures 3(c), 3(f), and 3(i), the voltage across switching element Q4 is indicated by a solid line, and the current flowing through switching element Q4 is indicated by a dotted line. As shown in FIG. 3(a), switching element Q3 is turned on at time t1, turned off at time t2, turned on at time t5, and turned off at time t6. Switching element Q4 is turned on at time t3, turned off at time t4, and turned on at time t7. The periods from t2 to t3, t4 to t5, and t6 to t7 are dead times during which switching elements Q3 and Q4 are both off. As shown in FIGS. 3(a) and 3(d), when switching element Q3 is turned off at time t2, the voltage across switching element Q3 changes at a gradual rate, as shown in FIGS. 3(b) and 3(e), and a small, substantially constant negative current flows. That is, as shown by the dotted line in FIG. 3(e), when switching element Q3 is off, current flows through parasitic diode D1, and the voltage changes gradually in response to changes in the gate signal voltage, resulting in soft switching. As shown in Figures 3(a) and 3(d), when switching element Q3 is turned on at time t5, a substantially constant negative current flows through switching element Q3, as shown in Figures 3(b) and 3(h). That is, as shown by the dotted line in Figure 2(h), when switching element Q3 is on, current flows through parasitic diode D1, and the current changes gradually in response to changes in gate signal voltage, resulting in soft switching. As shown in Figures 3(a) and 3(d), when switching element Q4 is turned on at time t3, a surge current flows through switching element Q4, as shown in Figures 3(c) and 3(f).That is, as shown by the dashed-dotted line in Figure 3(f), when switching element Q4 is on, the current changes abruptly in response to changes in the gate signal voltage, resulting in hard switching. As shown in Figures 3(a) and 3(d), when switching element Q4 is turned off at timing t4, the positive current flowing through switching element Q4 changes to zero, just like the gate signal, as shown in Figures 3(c) and 3(i). That is, as shown in Figures 3(g) and 3(i), the transition time of the gate signal and the current transition time of switching element Q4 are approximately equal, resulting in operation at the boundary conditions between soft and hard switching.

[0024] Next, the change over time of the current path in the power supply device 1 will be described using Figures 4 and 5. The change over time of the current path can be classified into multiple modes. Figure 4 is a waveform diagram showing operation in multiple modes. Figures 4(a), 4(b), 4(c), 4(d), and 4(e) show the change over time of the current flowing through the capacitance element Cfly, switching element Q1, switching element Q2, switching element Q3, and switching element Q4, respectively. Figure 5 is a circuit diagram showing operation in multiple modes. The multiple modes include, for example, mode (1), mode (2), mode (3), and mode (4).

[0025] Timings t2 and t3 shown in FIGS. 2 and 3 correspond to timing t11, timings t4 and t5 correspond to timing t12, timing t6 corresponds to timing t14, and timing t7 corresponds to timing t15.

[0026] 4, operation in mode (1) is performed during the period from timing t11 to t12. Operation in mode (2) is performed during the period from timing t12 to t13. Operation in mode (3) is performed during the period from timing t13 to t14. Operation in mode (4) is performed during the period from timing t14 to t15.

[0027] Just before timing t11, switching element Q2 remains off, but charge accumulates in the parasitic capacitance Coss between the source and drain. Therefore, at timing t11, switching element Q2 turns on. However, at this time, there is a sudden change in current due to the parasitic capacitance Coss, and switching element Q2 turns on in a hard-switched state. In other words, in mode (1), as shown by the solid arrow in Figure 5(a), switching element Q2 takes over the current that was flowing through switching element Q1. This causes current to flow from one end of capacitance element Cin1 to capacitance element Co and resistance element Ro to inductance element Lo to switching element Q2 to the other end of capacitance element Cin1. However, if the current flowing through inductance element Lo is smaller than the current flowing through inductance element Lr, the initial current value will be 0 A.

[0028] Similarly, just before timing t11, switching element Q4 remains off, but charge accumulates in the parasitic capacitance Coss between its source and drain. Therefore, at timing t11, switching element Q4 turns on. However, a sudden change in current occurs due to the parasitic capacitance Coss, resulting in hard switching. In other words, in mode (1), as shown by the solid arrow in Figure 5(a), switching element Q4 takes over the current that was flowing through switching element Q3. This causes current to flow from one end of capacitance element Cin2 to switching element Q2 to inductance element Lr to capacitance element Cfly to switching element Q4 to the other end of capacitance element Cin2. However, the initial value of the current is approximately equal to the current flowing through inductance element Lr just before timing t11.

[0029] When switching elements Q2 and Q4 are turned off at timing t12, current flows in the ratio of the parasitic capacitances of switching elements Q2 and Q4, as shown by the dashed-dotted line in Fig. 5(b). That is, in mode (2), the ratio of the current value in the path from one end of capacitance element Cin1 to capacitance element Co and resistance element Ro to inductance element Lo to switching element Q2 to the other end of capacitance element Cin1 to the current value in the path from one end of capacitance element Cin2 to switching element Q2 to inductance element Lr to capacitance element Cfly to switching element Q4 to the other end of capacitance element Cin2 is the parasitic capacitance ratio of switching elements Q2 and Q4.

[0030] After that, switching elements Q1 and Q3 turn on. At this time, the resonant frequency of the resonant operation of the loop of capacitive element Cin1, inductive element Lr, and capacitive element Cfly is lower than the switching frequency of switching elements Q1 to Q4. Therefore, the resonant operation of the loop of capacitive element Cin2, inductive element Lr, and capacitive element Cfly causes the voltage to change gradually, and the on operation of switching elements Q1 and Q3 becomes a soft switch operation.

[0031] At timing t13, the source-drain voltage of switching elements Q2 and Q4 rises to Vin / 2, causing diodes D of switching elements Q1 and Q3 to become forward biased, and as shown in Figure 5(c), forward current flows through diodes D of switching elements Q1 and Q3. That is, in mode (3), two currents flow: a first current from node N2 to diode D of switching element Q1 to capacitance element Co and resistance element Ro to inductance element Lo; and a second current from one end of capacitance element Cin1 to switching element Q1 to node N2 to inductance element Lr to capacitance element Cfly to the diode of switching element Q3 to the other end of capacitance element Cin1. This second current flows in the reverse direction due to the resonant action of the resonant circuit formed by the loop of capacitance element Cin1, inductance element Lr, and capacitance element Cfly. A current (third current) flows through the path of the other end of the capacitance element Cin1 → switching element Q3 → capacitance element Cfly → inductive element Lr → node N2 → diode of the switching element Q1 → capacitance element Cin2. The second current and the third current flow alternately.

[0032] At timing t14, switching elements Q1 and Q3 are turned off. At this time, the resonant frequency of the resonant operation of the loop of capacitance element Cin1, inductive element Lr, and capacitance element Cfly is lower than the switching frequency of switching elements Q1 to Q4. Therefore, the resonant operation of the loop of capacitance element Cin1, inductive element Lr, and capacitance element Cfly causes the voltage to change gradually, and the turning off of switching elements Q1 and Q3 becomes a soft switching operation.

[0033] For example, in mode (4), as shown by the dashed-dotted arrow in Fig. 5(d), half-wave resonance occurs between the parasitic capacitance Coss of switching element Q3 and inductance element Lr, causing a current (third current) to flow through the path: the other end of capacitance element Cin1 → switching element Q3 → capacitance element Cfly → inductance element Lr → node N2 → diode of switching element Q1 → capacitance element Cin2. After that, as shown by the dotted-line arrow in Fig. 5(d), the current switches to a forward current through diode D of switching element Q3, and a current (second current) flows through the path: one end of capacitance element Cin1 → switching element Q1 → node N2 → inductance element Lr → capacitance element Cfly → diode of switching element Q3 → other end of capacitance element Cin1.

[0034] At timing t14, the switching elements Q2 and Q4 are turned on, and the mode returns to mode (1). The turning on operation of the switching elements Q2 and Q4 becomes a hard switch operation.

[0035] As described above, in the embodiment, the power supply device 1 includes the inrush current suppression circuit 4 in addition to the switched capacitor circuit 2 and the step-down chopper circuit 3. The inrush current suppression circuit 4 is connected between the switched capacitor circuit 2 and the step-down chopper circuit 3, and includes a series connection of a capacitance element Cfly and an inductance element Lr. This allows the inrush current suppression circuit 4 to transiently form a resonant circuit with the switched capacitor circuit 2. For example, the resonant frequency of the transiently formed resonant circuit can be set lower than the switching frequency of the switching element in the switched capacitor circuit 2, and the phase of the current can be delayed by utilizing the resonance, thereby suppressing the inrush current during switching operation.

[0036] Therefore, the advantages of switched capacitors include mitigating the voltage applied to the elements and soft switching using resonance, which suppresses inrush current and reduces switch stress, resulting in a highly efficient circuit. Furthermore, by using resonance for the step-down chopper switches, which would normally operate as hard switches, it is possible to suppress conduction loss and switching loss, thereby reducing stress on semiconductor components while maintaining regulation. This prevents component costs from increasing and reduces loss, making it easier to miniaturize the entire power supply unit 1.

[0037] The power supply device 1i may be configured to receive a positive power supply voltage Vin, as shown in FIG. 6. FIG. 6 is a circuit diagram showing the configuration of a power supply device according to a modified example of the embodiment. The power supply device 1i is a power supply device in which the input node Nin2 is connected to ground potential instead of the input node Nin1 and operates on the positive power supply voltage Vin. It has a circuit configuration symmetrical to that of the power supply device 1 (see FIG. 1). The power supply device 1i has a step-down chopper circuit 3i and an inrush current suppression circuit 4i instead of the step-down chopper circuit 3 and the inrush current suppression circuit 4 (see FIG. 1). The step-down chopper circuit 3i has a switching element Q4 instead of the switching element Q1. The step-down chopper circuit 3i shares the switching element Q4 with the switched capacitor circuit 2.

[0038] The step-down chopper circuit 3i has a circuit configuration symmetrical to that of the step-down chopper circuit 3. The inductive element Lo is electrically connected between the node N2i and the output node Nout1. One end of the inductive element Lo is connected to the node N2i, and the other end is connected to the output node Nout1.

[0039] The inrush current suppression circuit 4i has a circuit configuration symmetrical to that of the inrush current suppression circuit 4. The capacitive element Cfly is electrically connected between the node N2i and the node N3i. One end of the capacitive element Cfly is connected to the node N2i and the other end is connected to the node N3i. The node N2i is connected to one end of the inductive element Lo, one end of the capacitive element Cfly, the source of the switching element Q3, and the drain of the switching element Q4. The node N3i is connected to the source of the switching element Q1 and the drain of the switching element Q2.

[0040] Even with this configuration, the inrush current suppression circuit 4i can transiently form a resonant circuit between itself and the switched capacitor circuit 2. For example, the resonant frequency of the transiently formed resonant circuit can be set lower than the switching frequency of the switching element in the switched capacitor circuit 2, and the phase of the current can be delayed by utilizing the resonance, thereby suppressing the inrush current during the switching operation.

[0041] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0042] 1,1i power supply 2 Switched Capacitor Circuits 3,3i Step-down chopper circuit 4,4i Inrush current suppression circuit Cfly,Cin1,Cin2,Co Capacitance element Lo, Lr inductive element Q1~Q4 switching elements

Claims

1. A first capacitance element electrically connected between a first input node at ground potential and a first node; a second capacitance element electrically connected between a second input node having a potential higher in absolute value than the ground potential and the first node; a first switching element electrically connected between the first input node and a second node; a second switching element electrically connected between the first node and the second node; a third switching element electrically connected between the first node and a third node; a fourth switching element electrically connected between the second input node and the third node; a third capacitance element electrically connected between the second node and the third node; a first inductive element having one end electrically connected between the second node and an output node; a second inductive element electrically connected in series with the third capacitive element between the second node and the third node; a fourth capacitive element electrically connected between the first input node and the other end of the first inductive element; a resistive element electrically connected in parallel with the fourth capacitive element between the first input node and the other end of the first inductive element; Equipped with a circuit including the first capacitance element, the second capacitance element, the first switching element, the second switching element, the third switching element, and the fourth switching element functions as a switched capacitor circuit; a circuit including the first switching element, the first inductive element, the fourth capacitive element, and the resistive element functions as a step-down chopper circuit, A resonant current can be generated in a first loop including the first capacitive element, the third capacitive element, and the second inductive element; A resonant current can be generated in a second loop including the second capacitive element, the third capacitive element, and the second inductive element; The resonant frequency of the first loop and the resonant frequency of the second loop are all lower than the switching frequencies of the first switching element, the second switching element, the third switching element, and the fourth switching element. power supply.

2. the third capacitive element has one end electrically connected to the third node and the other end electrically connected to the second inductive element; The second inductive element has one end electrically connected to the second node and the other end electrically connected to the third capacitive element. The power supply device of claim 1 .

3. the third capacitance element has one end electrically connected to the second inductive element and the other end electrically connected to the second node; The second inductive element has one end electrically connected to the third capacitive element and the other end electrically connected to the third node. The power supply device of claim 1 .

4. The first switching element and the third switching element are maintained in an on state during a first period, and the second switching element and the fourth switching element are maintained in an on state during a second period. The power supply device according to any one of claims 1 to 3.

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