Process flow for fabricating an integrated photonics optical gyroscope

Abstract

Aspects of the present disclosure are directed to the construction of compact, ultra-low-loss integrated photonics-based waveguides for optical gyroscope applications and methods for fabricating these waveguides to facilitate large-scale manufacturing. Four main process flows are described: (1) a process flow based on repeated oxide deposition and annealing sequences; (2) a chemical-mechanical polishing (CMP)-based process flow followed by wafer bonding; (3) a damascene process flow followed by oxide deposition and annealing or wafer bonding; and (4) a CMP-based process flow followed by oxide deposition. Any combination of these process flows can be employed to achieve the ultimate goal of fabricating optical gyroscope waveguides in one or more layers on a silicon substrate using standard silicon fabrication techniques.

Description

[Technical Field]

[0001] The present disclosure relates to various manufacturing processes for integrated photonics-based optical gyroscopes, including fabrication processes, some of which involve chemical mechanical polishing (CMP). [Background technology]

[0002] A gyroscope (also called gyro for short) is a device that can sense angular velocity. Applications of gyroscopes include, but are not limited to, military applications, aircraft navigation, robotics, autonomous vehicles, virtual reality, augmented reality, and gaming. Gyroscopes can be mechanical or optical and vary in accuracy, performance, cost, and size. Optical gyroscopes have no moving parts and are therefore more resistant to shock, vibration, and temperature changes than mechanical gyroscopes. The most common optical gyroscope is the fiber optic gyroscope (FOG), which operates based on interferometric measurement of optical phase shift due to the Sagnac effect (a phenomenon encountered in rotation-induced interferometry). FOG configurations typically include a coil containing several turns of polarization-maintaining (PM) fiber. Laser light is launched into both ends of the PM fiber coil so that two light beams travel in opposite directions. When the fiber coil is moving, the opposing light beams experience different optical path lengths. By setting up an interferometric system, we can measure small path length differences proportional to the area of ​​the loop enclosed by the turns of the fiber coil and the angular velocity of the rotating fiber coil, which are expressed as phase signals.

[0003] The phase signal of the optical gyro is proportional to the Sagnac effect multiplied by the rotation angular velocity, as shown in the following equation. ΔΦ=(8πNA / λc)Ω Where N = number of turns of the gyro A = enclosed area Ω=angular velocity of rotation ΔΦ=optical phase difference signal λ = wavelength of light c=speed of light Summary of the Invention [Problem to be solved by the invention]

[0004] Fiber-based gyroscopes can offer extremely high accuracy, but they also have a large footprint, are very expensive, and are difficult to assemble because the devices are built on separate optical components that must be precisely aligned. Manual alignment is often complex and difficult to scale up for mass production. [Means for solving the problem]

[0005] We propose to replace fibers with waveguide-based integrated photonics components for cost-effective and easy integration on semiconductor platforms, which is much more promising for mass production of gyroscopes. This application describes various process flows for fabricating silicon nitride (SiN) waveguide cores in silicon fabs using repeated deposition and annealing steps and / or chemical mechanical polishing (CMP) techniques, as detailed below.

[0006] The present disclosure will become more fully understood from the detailed description given below and from the accompanying drawings of various implementations of the present disclosure. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram of a substrate having a pre-grown oxide layer with an ultra-low hydrogen absorption peak at a selected wavelength, according to one embodiment of the present disclosure. [Figure 2] FIG. 1 is a schematic diagram of a silicon nitride (SiN) waveguide core patterned on a pre-grown oxide that serves as a lower cladding, according to one embodiment of the present disclosure. [Figure 3]1A-1C are schematic diagrams of SiN waveguide cores patterned onto different types of oxide layers as starting materials to serve as undercladding, according to an embodiment of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of a SiN waveguide core with a silicon oxide upper cladding according to one embodiment of the present disclosure. [Figure 5] FIG. 2 is a schematic diagram illustrating the individual layers of a silicon oxide upper cladding according to one embodiment of the present disclosure. [Figure 6] 1 is a transmission electron microscope (TEM) photograph of a cross section of a SiN waveguide core with upper and lower claddings fabricated by an exemplary process of the present disclosure. [Figure 7] FIG. 10 is a schematic diagram of a second SiN waveguide core patterned at a vertical distance away from a previously formed SiN waveguide core, according to one embodiment of the present disclosure. [Figure 8] FIG. 1 is a schematic diagram of two vertically separated SiN waveguide cores with silicon oxide upper and lower claddings for the top layer of the SiN waveguide core, and a silicon oxide upper cladding and pre-grown oxide lower cladding for the bottom layer of the SiN waveguide core, according to one embodiment of the present disclosure. [Figure 9] FIG. 1 is a first schematic diagram of chemical mechanical polishing (CMP) of a silicon oxide layer for a subsequent wafer bonding process according to one embodiment of the present disclosure. [Figure 10] FIG. 12 is a second schematic diagram of chemical mechanical polishing (CMP) of a silicon oxide layer for a subsequent wafer bonding process according to one embodiment of the present disclosure. [Figure 11] FIG. 1 is a schematic diagram of a wafer bonded onto a SiN waveguide core in a CMP-based process flow according to one embodiment of the present disclosure. [Figure 12] 1 is a schematic diagram of starting materials for a damascene process flow according to one embodiment of the present disclosure. [Figure 13] 1A-1C are schematic diagrams of trenches etched for SiN waveguide cores in a damascene process flow according to one embodiment of the present disclosure. [Figure 14]1A-1C are schematic diagrams of trenches filled with SiN to form SiN waveguide cores in a damascene process flow according to one embodiment of the present disclosure. [Figure 15] 1A-1C are schematic diagrams of a SiN waveguide core polished to a flat surface in a damascene process flow according to one embodiment of the present disclosure. [Figure 16] 1A-1C are schematic diagrams of a silicon oxide layer deposited on a SiN waveguide core in a damascene process flow according to one embodiment of the present disclosure. [Figure 17] FIG. 1 is a schematic diagram of a SiN waveguide core in an “all-glass” (fused silica upper and lower cladding) configuration, according to one embodiment of the present disclosure. [Figure 18] FIG. 1 is a schematic diagram of a SiN waveguide core with a lower cladding of fused silica and an upper cladding of silicon oxide, according to one embodiment of the present disclosure. [Figure 19] FIG. 1 is a schematic diagram of a process flow that uses a thick oxide wafer as a starting material, followed by deposition and patterning of a SiN waveguide core on top, according to one embodiment of the present disclosure. [Figure 20] FIG. 1 is a schematic diagram of a process flow that uses a thick oxide wafer as a starting material, followed by deposition and patterning of a SiN waveguide core on top, according to one embodiment of the present disclosure. [Figure 21] FIG. 1 is a schematic diagram of a process flow that uses a thick oxide wafer as a starting material, followed by deposition and patterning of a SiN waveguide core on top, according to one embodiment of the present disclosure. [Figure 22] 1 illustrates one possible CMP flow for creating a SiN waveguide core in an oxide undercladding layer according to one embodiment of the present disclosure. [Figure 23] 1 illustrates one possible CMP flow for creating a SiN waveguide core in an oxide undercladding layer according to one embodiment of the present disclosure. [Figure 24] 1 illustrates one possible CMP flow for creating a SiN waveguide core in an oxide undercladding layer according to one embodiment of the present disclosure. [Figure 25]1 illustrates an alternative CMP flow for creating a SiN waveguide core according to one embodiment of the present disclosure. [Figure 26] 1 illustrates an alternative CMP flow for creating a SiN waveguide core according to one embodiment of the present disclosure. [Figure 27] 1 illustrates a final cross section of a single layer gyroscope sensing chip with a waveguide core in one layer according to one embodiment of the present disclosure. [Figure 28] 1 illustrates a final cross section of a multi-layer gyroscope sensing chip with waveguide cores in two layers, according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Aspects of the present disclosure are directed to the construction of compact, ultra-low-loss integrated photonics-based waveguides for optical gyroscope applications and methods for fabricating these waveguides for ease of large-scale manufacturing. Four main process flows are described: (1) a process flow based on repeated oxide deposition and annealing sequences; (2) a chemical-mechanical polishing (CMP)-based process flow followed by wafer bonding; (3) a damascene process flow followed by oxide deposition and annealing or wafer bonding; and (4) a CMP-based process flow followed by oxide deposition. Any combination of these process flows can be employed to achieve the ultimate goal of fabricating optical gyroscope waveguides in one or more layers on a silicon substrate using standard silicon fabrication techniques. In this particular application, the CMP-based process flow achieves at least two objectives: obtaining precise layer thicknesses without precise control of deposition parameters, and obtaining the desired surface roughness of the CMP-processed top surface of the SiN core, since surface roughness significantly impacts waveguide loss. It should be noted that CMP may be used even before depositing the SiN layer to further reduce the roughness of the deposited SiN layer.

[0009] The key to the high performance of fiber-based optical gyroscopes is the length of high-quality, low-loss optical fiber used to measure the Sagnac effect. The inventors recognize that with the advent of integrated silicon photonics suitable for wafer-scale processing, there is an opportunity to replace FOGs with smaller, integrated photonic chip solutions without sacrificing performance. Photonics-based optical gyros have the potential to offer performance comparable to FOGs, while being reduced in size, weight, power, and cost, yet still be mass-producible, vibration-resistant, and capable of operating at a high level of performance.

[0010] One of the key elements of this integrated photonics solution is the production of very low-loss waveguides that can be fabricated using wafer-scale processes and used to replace long PM optical fibers in optical gyros. The technology platform used for this integrated photonics-based optical gyro is based on a silicon nitride (Si3N4) waveguide core surrounded by an oxide or fused silica cladding. The entire waveguide structure is sometimes referred to as a SiN waveguide for simplicity.

[0011] Disclosed herein is SiPhOG TMThis paper presents a composition and method for producing very low-loss SiN waveguides that can be used as integrated components for small-footprint integrated optical gyroscopes, often referred to as silicon photonic optical gyroscopes (SPGs). The propagation loss in SiN waveguides fabricated by the process flow described herein can be well below 0.1 dB / meter. This represents a significant improvement over current state-of-the-art SiN processes, which have propagation losses in the 0.1 dB / centimeter range. The key to reducing loss while using standard silicon fab processes and equipment is to use high-quality fused silica (sometimes called "glass") wafers or wafers with pre-grown oxide as the lower cladding, and then deposit a silicon oxide layer of the required thickness as the upper cladding by repeated deposition / annealing steps. The repeated deposition / annealing steps ensure precise control of the thickness of the upper cladding layer and eliminate trapped hydrogen from the deposited layer.

[0012] The inventors have recognized that distributing the SiN waveguide coils (or spirals) and / or rings into different vertically separated layers (e.g., two or more layers) can lead to lower values ​​of gyro sensitivity without increasing the form factor. Details of stacked multilayer gyro configurations are covered in co-pending and commonly owned provisional application 62 / 858,599, entitled "Integrated Silicon Photonics Optical Gyroscope on Fused Silica Platform," filed June 7, 2019. Subsequent application 62 / 896,365, entitled "Single-layer and Multi-layer Structures for Integrated Silicon Photonics Optical Gyroscopes," filed September 5, 2019, describes additional embodiments. These applications are incorporated herein by reference. Additionally, system-level integration of silicon photonics-based front-end chips and SiN waveguide chips is covered in co-pending and commonly owned provisional applications 62 / 872,640, titled "System Architecture for Silicon Photonics Optical Gyroscopes," filed July 10, 2019, and 62 / 904,443, titled "System Architecture for Silicon Photonics Optical Gyroscopes with Mode-Selective Waveguides," filed September 23, 2019, both of which are incorporated herein by reference.

[0013] Figures 1-8 show an exemplary process flow for fabricating a SiN waveguide core (one or two layers) on a conventional silicon substrate with an asymmetric upper cladding (tetraethyl orthosilicate (TEOS)) and lower cladding (grown oxide) around the SiN waveguide core. Specifically, Figure 1 shows a wafer having a substrate 102 with a pre-grown oxide layer 104. The substrate 102 can be a silicon substrate, and the pre-grown oxide layer can be a crystalline layer, e.g., 10-15 μm in dimension. A key feature of layer 104 is that it has a low absorption peak at the wavelength of interest (e.g., around 1550 nm, but not necessarily exactly 1550 nm, as waveguide propagation loss can be optimized for wavelengths slightly different from 1550 nm). The wafer can be double-sided polished.

[0014] FIG. 2 shows that a SiN layer is deposited to form a layer above and adjacent to the pre-grown oxide layer 104 and patterned to create the waveguide core 106. Non-limiting exemplary dimensions of the SiN waveguide core 106 are a height (i.e., the thickness of the waveguide layer, "h") of 60-100 nm and a lateral width of 2-10 μm. Those skilled in the art will appreciate that these exemplary dimensional values ​​described herein do not limit the scope of the disclosure. The SiN layer may be deposited using a low-pressure chemical vapor deposition (LPCVD) process or other process. The bottom SiN layer 108 may be left intact, and the top SiN layer is photolithographically or otherwise patterned on the pre-grown oxide layer 104 to form the SiN waveguide core 106. Some post-etching processing may be required to reduce line edge roughness in the SiN waveguide core 106. For example, a blanket argon (Ar) sputter step after the photoresist and lithography-assist layer (e.g., BARC) can be removed to smooth the top and side surfaces of the SiN waveguide core 106. Alternatively, a blanket dip in hot phosphoric acid, which has very high selectivity between SiN (high etch rate) and the pre-grown oxide 104, can be performed. Post-etch cleans can include piranha cleans (e.g., hot sulfuric acid mixed with peroxide), SC1 (diluted hot ammonium hydroxide and peroxide mixture), or SC2 (hydrochloric acid mixed with peroxide). Finally, a post-etch high-temperature anneal can be performed to drive off residual hydrogen or other impurities from the SiN layer. Figure 3 shows that in an alternative embodiment, other types of oxide starting materials 103 can also be used as the lower cladding instead of the crystalline pre-grown oxide layer 104, examples of which are amorphous fused silica ("glass") or quartz.

[0015] Continuing the process flow of the pre-grown oxide layer 104, as shown in Figure 4, a silicon oxide layer (also referred to as a TEOS layer) 110 is grown to cover the SiN waveguide core 106. The silicon oxide layer 110 can have a total thickness of 2-3 μm. Hydrogen in the TEOS layer should be minimal, and the growth rate is adjusted accordingly. Optionally, a pre-deposition anneal can be performed (e.g., at 1150-1200 °C for 2 hours or more). The final total thickness of the TEOS layer can be achieved in several rounds, with each round producing a layer with a thickness of 0.1-0.2 μm. Note that the structure shown in Figure 4 has asymmetric cladding around the waveguide core 106, since the upper cladding is TEOS (layer 110) and the lower cladding is grown oxide (layer 104). Waveguide loss is highly dependent on the quality of the TEOS layer serving as the upper cladding.

[0016] As shown in Figure 5, the oxide layer 110 comprises individual layers of deposited TEOS, each followed by an annealing step to drive off hydrogen. While only five layers are shown in the figure, any number of layers can be selected depending on the deposition rate and annealing time. For example, if the total thickness of layer 110 is 2 μm, 10 layers, each 0.2 μm thick, can be deposited. A high-temperature LPCVD method is typically used for TEOS deposition. This method can begin with a pre-deposition anneal. Then, a deposition-anneal-deposition-anneal sequence is repeated multiple times. For each anneal, the temperature can be 1150-1200 °C, and the duration can be 2 hours. Note that instead of TEOS as a precursor gas, a chlorinated or deuterated source can be used for silicon oxide deposition.

[0017] 6 is a transmission electron micrograph (TEM) of a cross section of a SiN waveguide core with upper and lower claddings fabricated by an exemplary process of the present disclosure, which shows that the deposited upper cladding oxide layer 110 has properties as good as the lower cladding pre-grown oxide layer 104.

[0018] 7 and 8 illustrate the formation of another waveguide core 112 for implementing a multilayer optical gyroscope. While only two waveguide core layers are shown for illustrative purposes, it should be noted that more than two waveguide core layers can be created using the process flow discussed herein. Specifically, FIG. 7 illustrates that a deposited silicon oxide layer 110 is polished, and then an upper SiN waveguide core 112 is patterned on top of the layer 110 using the same process used to form the lower SiN waveguide core 106 discussed above. FIG. 8 illustrates that the deposition-anneal-deposition-anneal sequence is repeated to embed the upper SiN waveguide core 112 under the upper cladding. In other words, the oxide layer 110 of FIG. 7 is extended over the waveguide core 112 to create the total thickness of the oxide layer 114 of FIG. 8. The final annealing step may be longer (e.g., 6 hours to prevent hydrogen from diffusing downward).

[0019] Figures 9-11 illustrate an alternative process flow for creating the upper cladding, including chemical-mechanical polishing (CMP) and wafer bonding. Specifically, Figure 9 illustrates the formation of a silicon oxide layer 110 on the SiN waveguide core 106 as described above. This process may include a pre-deposition cleaning step with sulfuric acid and SC1 or SC2. Additionally, a pre-deposition annealing step may be performed. The use of high-temperature LPCVD minimizes the possibility of air gaps at the SiN-oxide interface. Figure 10 illustrates that the initial thickness of the oxide layer 110 is reduced by CMP to be approximately flush with or extend slightly above the SiN waveguide core 106. Dummy structures may be added to ensure CMP uniformity and process control. Figure 11 illustrates that a fused silica wafer 120 may be bonded on top of the CMP-thinned oxide layer 110, with the wafer 120 serving as the upper cladding.

[0020] Figures 12-16 illustrate yet another alternative process flow involving a damascene process. As shown in Figure 12, in a damascene process, the oxide starting material 103 can be a pre-grown oxide (such as 104 illustrated in Figure 1). Figure 13 shows that a trench (or notch) 122 is created in the oxide starting material 103 by a timed etch. The dimensions of the trench 122 are the same as the dimensions of the SiN waveguide core 106 (e.g., a desired waveguide core height of 97.5 nm can be an example of the depth of the trench 122, and the lateral width of the trench matches the width of the waveguide (e.g., 2.5-4.5 μm)). The sidewalls of the trench 122 should have vertical sidewalls, as controlled by the timed etch parameters.

[0021] FIG. 14 shows that a silicon nitride layer 107 is deposited on top of the oxide starting material 103, conforming to the notch 122. Simultaneously, a SiN layer 108 is also formed on the backside of the substrate. At least the top SiN layer 107 should be as contaminant-free as possible. LPCVD is preferred for SiN deposition. Annealing is also performed to drive contaminants (including hydrogen) out of the SiN layer 107. FIG. 15 shows that the SiN layer 107 is polished down to the oxide layer 103, so that the SiN remaining in the trench 122 creates the SiN waveguide core 106. After polishing, a cleaning step is performed, followed by an anneal (e.g., at 1150-1200°C for 2-6 hours).

[0022] Figure 16 illustrates the formation of an upper cladding, which may include a deposited silicon oxide layer 110 as described above. The TEOS oxide layer 110 may be formed by repeating a deposition and annealing sequence until a desired thickness of 2-3 μm is reached. The length of the anneal may vary, with the overall length of the anneal being up to 20 hours to drive off contaminants.

[0023] It should be noted that the wafer bonding described above can be used to create the upper cladding in a damascene process.

[0024] 17 shows an example in which the starting wafer (e.g., with notch 122) and the bonded wafer are both fused silica, and therefore have an "all-glass" configuration 250. Alternatively, a silicon substrate with a pre-grown oxide (as shown in FIG. 1) can be used as the starting wafer, and another such wafer (upside down with the pre-grown oxide layer facing the SiN waveguide core 106) can be bonded from above to create the upper cladding.

[0025] Figure 18 shows an alternative example where the starting wafer is a fused silica wafer 250 on which a SiN waveguide core 106 is formed and the upper cladding is formed from TEOS (or other alternative sources such as chlorinated or deuterated sources). The length of the anneal can be multiple times at 1200°C for 6-10 hours to drive off contaminants.

[0026] 19-21 are schematic diagrams of a process flow for using a thick oxide wafer as a starting material, followed by deposition and patterning of a SiN waveguide core on top, according to one embodiment of the present disclosure. The thermally oxidized wafer may be 14.5 μm thick and may have thick oxide layers 204 and 205 on either side of the substrate 204, as shown in FIG. 19. FIG. 20 shows that the SiN waveguide core 106 is deposited and patterned on top of layer 204. FIG. 21 shows that an upper cladding 206 is formed surrounding the waveguide core 106. Layer 206 may be deposited using a TEOS oxide source, as described above.

[0027] The sensitivity of an interferometric fiber-based optical gyro is determined by the phase difference between the two counter-rotating beams and is known to be expressed by the equation: Δφ = 2πLD / λc, where L is the length of the fiber and D is the diameter of each loop. The same analogy applies to planar devices such as SiPhOGs, in which the fiber is replaced by a planar waveguide. To design a highly sensitive system, it is necessary to obtain longer lengths and maximize the product (L*D). However, a limitation of such systems is the propagation loss of the SiN waveguide. We have developed several methods to reduce the propagation loss, such as the deposition-annealing sequence described above. From the measured data, we determined that the loss reduction approaches the limit of loss due to bulk material properties and that the loss is largely dependent on scattering caused by imperfections in the fabrication process. Because the waveguide core is thin and wide (e.g., 60–100 nm thick and 2–3 μm wide), the propagation loss is very low dependent on the roughness of the sidewalls of the waveguide core and highly dependent on the roughness of the bottom and top of the waveguide core. Waveguide-based gyroscope sensing coils with multiple turns can be tens of meters long, and it has been experimentally confirmed that the excess loss in SiN chips can be attributed to scattering losses. To improve scattering losses, we have demonstrated that chemical-mechanical polishing (CMP) can be used to reduce the roughness of the top and bottom surfaces of the waveguide core. The resulting loss levels after CMP are comparable to those of polished new silicon wafers.

[0028] 22-24 illustrate one possible CMP flow for creating a SiN waveguide core in an oxide lower cladding layer according to one embodiment of the present disclosure. In this process flow, as shown in FIG. 22, a thicker layer of SiN is deposited and patterned (106A) on a silicon dioxide lower cladding layer 104. The thickness "h1" can be larger (e.g., twice the final desired thickness), i.e., precise thickness control of the SiN layer is not required at this step. Next, as shown in FIG. 23, an upper oxide layer 110 is deposited surrounding the waveguide core 106A, which is thicker than the final desired thickness "h2." Finally, the upper oxide layer 110 and a portion of the SiN layer 106A are polished using a CMP process so that the final thickness of the waveguide core 106 is the desired thickness "h2," and the top surface of the waveguide core 106 is automatically flush with the top surface of the lower cladding oxide layer 104, as shown in FIG. 24.

[0029] 25-26 illustrate an alternative CMP flow for creating a SiN waveguide core according to one embodiment of the present disclosure. In this process flow, as shown in FIG. 25, a thicker layer of SiN 106B is deposited on a silicon dioxide lower cladding layer 104. The thickness "h1" can be larger (e.g., twice the final desired thickness), i.e., precise thickness control of the SiN layer is not necessary at this step. Next, a CMP process can be used to polish the SiN layer 106B down to the desired thickness "h2" (layer 106C). In one example, h1 can be in the 200 nm range, while h2 can be in the 100 nm or less range. The thinned layer 106C can then be patterned to create the waveguide core 106.

[0030] FIG. 27 shows the final cross-section of a single-layer gyroscope sensing chip having a waveguide core in one layer according to one embodiment of the present disclosure. Each of the waveguide cores 106-1 and 106-2 (having a thickness h2 and a width w) can be envisioned as adjacent turns of a multi-turn sensing coil of an optical gyroscope. The cores can be formed on the lower cladding layer 104 using one of the CMP flows (or other manufacturing flows) described above. After CMP, the upper cladding layer 110-1 is deposited. Note that if the lower cladding layer 104 (with a thickness H1), the SiN layer 106, and the upper cladding layer 110-1 (with a thickness H2) are formed on one side of the silicon substrate 102, the corresponding oxide layer 104-1 (with a thickness H1), the SiN layer 108-1, and the oxide layer 110-2 are also formed on the opposite side of the substrate 102. Discontinuity 101 is shown in the middle of silicon substrate 102 to convey the idea that the thickness of silicon substrate 102 is orders of magnitude greater than the other device layers.

[0031] 28 illustrates the final cross-section of a multilayer gyroscope sensing chip with waveguide cores in two layers according to one embodiment of the present disclosure. Here, the deposition and CMP processes of oxide layers (110-1 and 110-3) and SiN layers (106-1, 106-2, 106-3, 106-4) are repeated to create the final multilayer structure. The first layer of waveguide cores 106-1 and 106-2 is vertically separated from the second layer of waveguide cores 106-3 and 106-4 by a distance “S” (the thickness of oxide layer 110-1). Corresponding oxide layers 104-1, 110-2, and 110-4, as well as SiN layers 108-1 and 108-2, are automatically formed on the opposite side of the silicon substrate 102, but these layers may not be used for waveguiding purposes.

[0032] Those skilled in the art will appreciate that various metrology steps (including but not limited to wafer bow inspection at various stages, refractive index measurements at specific wavelengths of interest, line edge roughness measurements, etc.) can be incorporated to monitor the effectiveness of the process flow and determine adjustments to process parameters.

[0033] Furthermore, those skilled in the art will understand that different generations of SiPhOGs can be based on interferometric waveguide coils or ring resonators, but both configurations rely on low-loss waveguide core and cladding structures, such as those described in the figures of this disclosure.

[0034] In the foregoing specification, implementations of the present disclosure have been described with reference to specific exemplary implementations thereof. It will be apparent that various changes may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense. Furthermore, directional terms, such as "upper," "lower," etc., do not limit the scope of the present disclosure to fixed directions but encompass various permutations and combinations of directions. [Explanation of symbols]

[0035] 102 Circuit Board 103 Oxide starting materials 104 Pre-grown oxide layer 106 Waveguide Core 107 Silicon nitride layer 108 SiN layer 110 oxide layer 112 Waveguide core 114 Oxide layer 120 wafers 122 Trench 204 Oxide layer 205 Oxide layer 206 Upper Cladding 250 fused silica wafer

Claims

1. 1. A method for fabricating an integrated photonics optical gyroscope, comprising: providing a silicon substrate having a first oxide layer thereon, said first oxide layer acting as a lower cladding for a waveguide; forming a patterned silicon nitride (SiN) layer on the first oxide layer, the patterned SiN layer serving as a core of the waveguide; forming a second oxide layer on the patterned SiN layer, the second oxide layer comprising: depositing a first sublayer of a second oxide to a predetermined thickness; annealing the deposited first sublayer of said second oxide at a predetermined temperature for a predetermined time to drive out impurities; depositing a subsequent sublayer of the second oxide to the predetermined thickness; and after depositing each subsequent sub-layer of the second oxide, annealing the deposited sub-layer at the predetermined temperature for the predetermined time to drive out impurities. Including, the second oxide layer is polished to a reduced thickness by chemical mechanical polishing (CMP) so that the polished top surface of the second oxide layer is substantially flush with the top surface of the waveguide core; A method in which a wafer is bonded onto the second oxide layer that has been polished to the reduced thickness by CMP, the wafer being in direct contact with the entire top surface of the waveguide core.

2. The method of claim 1 , wherein the second oxide layer comprises an oxide deposited using a precursor gas selected from TEOS, a chlorinated source, or a deuterated source.

3. The method of claim 2 wherein the impurities displaced from the second oxide layer include hydrogen.

4. 3. The method of claim 2, wherein the predetermined temperature for annealing is in the range of 1100 to 1300°C.

5. The method of claim 2 , wherein the predetermined time for annealing depends on the thickness of each sub-layer.

6. The method of claim 2, wherein each sublayer is 0.1 to 0.2 μm thick.

7. The method of claim 2, wherein the total thickness of the second oxide layer is 2 to 3 μm.

8. The method of claim 1 , wherein the second oxide layer serves as an upper cladding for the waveguide.

9. The method of claim 1 , wherein the CMP achieves a desired surface roughness of the SiN core of the waveguide.

10. The method of claim 1 , wherein the wafer bonded onto the second oxide layer comprises a fused silica wafer.

11. The method of claim 1 , wherein the wafer bonded onto the second oxide layer serves as an upper cladding for the waveguide.

12. forming a patterned silicon nitride (SiN) layer on the first oxide layer; depositing a SiN layer to a first thickness greater than a desired thickness of the waveguide core; reducing the first thickness of the SiN layer to a second thickness by CMP, the second thickness being the desired thickness of the waveguide core; The method of claim 1 , comprising:

13. The method of claim 12 , wherein the second oxide layer is deposited after the waveguide core has attained the desired thickness by CMP.

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