Indication device

Abstract

The purpose of the present invention is to provide a display device excellent in downsizing, reduction in power consumption, or flexibility of the placement of a computing device. This display device has a pixel circuit, a driving circuit, and a functional circuit. The driving circuit has a function of outputting an image signal for performing display in the pixel circuit. The functional circuit has a CPU provided with a CPU core having a flip-flop electrically connected to a backup circuit. The display device has a first layer and a second layer. The first layer has the driving circuit and the CPU. The second layer has the pixel circuit and the backup circuit. The first layer has a semiconductor layer having silicon in a channel forming region. The second layer has a semiconductor layer having a metallic oxide in the channel forming region. The CPU has a function of correcting the image signal according to the amount of an electric current flowing through the pixel circuit.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device and a display correction system.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, etc. may be referred to as semiconductor devices. Alternatively, they may be referred to as including semiconductor devices. [Background technology]

[0004] Wearable electronic devices and stationary electronic devices are becoming popular as electronic devices equipped with display devices for Augmented Reality (AR) or Virtual Reality (VR). Examples of wearable electronic devices include head-mounted displays (HMDs) and eyeglass-type electronic devices. Examples of stationary electronic devices include head-up displays (HUDs).

[0005] In electronic devices such as HMDs, where the display unit is close to the user, the user can easily see the pixels, which can cause a strong sense of graininess, which can diminish the immersive and realistic feel of AR or VR. For this reason, it is preferable to provide an HMD with a display device that has fine pixels so that the pixels are not visible to the user. Patent Document 1 discloses a method for realizing an HMD with fine pixels by using transistors that can be driven at high speed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-2856 Summary of the Invention [Problem to be solved by the invention]

[0007] By making the pixels of a display device finer, the pixel density can be increased. This allows for more pixels to be provided on the display device, resulting in a high sense of immersion or realism. To achieve a greater sense of immersion or realism, it is preferable to have fewer pixel defects (bright spots, dark spots, etc.).

[0008] To eliminate pixel defects, a configuration in which pixel defects are corrected using a calculation device such as a CPU is effective. However, if the calculation device such as a CPU and the display device are provided separately, there is a risk that the electronic device including the device will become larger. Alternatively, if a calculation device such as a CPU performs calculation processing to correct pixel defects, there is a risk that the function of the display device will be impaired due to heat generation from the calculation device. Alternatively, if the calculation device and the display device are integrated, there is a risk that the degree of freedom in arranging the calculation device will be reduced depending on the shape of the display device, etc.

[0009] An object of one embodiment of the present invention is to provide a display device, a display correction system, or the like having a novel structure.Another object of one embodiment of the present invention is to provide a display device, a display correction system, or the like that can be miniaturized.Another object of one embodiment of the present invention is to provide a display device, a display correction system, or the like that can consume less power.Another object of one embodiment of the present invention is to provide a display device, a display correction system, or the like in which the degree of freedom in the arrangement of a computing device is increased.

[0010] The description of multiple problems does not preclude the existence of each other. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than those listed will become apparent from the description in the specification, drawings, claims, etc., and these problems may also be problems of one embodiment of the present invention. [Means for solving the problem]

[0011] One embodiment of the present invention is a display device including a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting a signal for displaying in the pixel circuit. The functional circuit has a CPU including a CPU core having a flip-flop electrically connected to a backup circuit. The display device includes a first layer and a second layer. The first layer includes the driver circuit and the CPU. The second layer includes the pixel circuit and the backup circuit. The first layer and the second layer are provided in different layers.

[0012] One embodiment of the present invention is a display device including a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting an image signal for displaying in the pixel circuit. The functional circuit has a CPU including a CPU core having a flip-flop electrically connected to a backup circuit. The display device includes a first layer and a second layer. The first layer has the driver circuit and the CPU. The second layer has the pixel circuit and the backup circuit. The first layer and the second layer are provided in different layers. The CPU has a function of correcting the image signal in accordance with an amount of current flowing through the pixel circuit.

[0013] One embodiment of the present invention is a display device including a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting an image signal for displaying in the pixel circuit. The functional circuit has a CPU including a CPU core having a flip-flop electrically connected to a backup circuit. The display device includes a first layer and a second layer. The first layer has the driver circuit and the CPU. The second layer has the pixel circuit and the backup circuit. The first layer has a first transistor having a semiconductor layer including silicon in a channel formation region. The second layer has a second transistor having a semiconductor layer including a metal oxide in a channel formation region. The CPU has a function of correcting an image signal in accordance with an amount of current flowing through the pixel circuit.

[0014] In one embodiment of the present invention, the metal oxide preferably includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.

[0015] In one embodiment of the present invention, the backup circuit preferably has a function of holding data held in a flip-flop while the CPU is not operating, in a state where the supply of power supply voltage is stopped.

[0016] In one embodiment of the present invention, the display device preferably includes an accelerator, and the accelerator is a circuit that performs a product-sum operation.

[0017] In one embodiment of the present invention, the pixel circuit preferably has an organic EL device, and the organic EL device is a light-emitting device processed by a photolithography method.

[0018] In one embodiment of the present invention, the backup circuit preferably includes a first transistor provided in a first layer and a capacitor electrically connected to the first transistor, and the capacitor is provided in the first layer.

[0019] One embodiment of the present invention is a display correction system including a pixel circuit, a driver circuit, and a functional circuit. The driver circuit has a function of outputting an image signal for displaying in the pixel circuit. The functional circuit has a CPU including a CPU core having a flip-flop electrically connected to a backup circuit. The display correction system includes a first layer and a second layer. The first layer has the driver circuit and the CPU. The second layer has the pixel circuit and the backup circuit. The backup circuit has a function of retaining data stored in the flip-flop by turning off a first transistor having a semiconductor layer having silicon in a channel formation region when the CPU is not operating. The CPU has a function of correcting an image signal by estimating a defective pixel according to an amount of current flowing through the pixel circuit. The correction corrects the amount of current flowing through a pixel circuit of a pixel adjacent to the defective pixel.

[0020] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0021] One embodiment of the present invention can provide a display device, a display correction system, or the like having a novel configuration. Alternatively, one embodiment of the present invention can provide a display device, a display correction system, or the like that can be miniaturized. Alternatively, one embodiment of the present invention can provide a display device, a display correction system, or the like that can reduce power consumption. Alternatively, one embodiment of the present invention can provide a display device, a display correction system, or the like in which the degree of freedom in arranging a computing device is increased.

[0022] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0023] FIG. 1 is a block diagram showing an example of the configuration of a display device. FIG. 2 is a block diagram showing an example of the configuration of the display device. FIG. 3 is a block diagram showing an example of the configuration of the display device. 4A and 4B are block diagrams showing configuration examples of the display device. FIG. 5 is a block diagram showing an example of the configuration of the display device. FIG. 6 is a block diagram showing an example of the configuration of a display device. 7A and 7B are circuit diagrams showing examples of the configuration of a display device. 8A and 8B are circuit diagrams showing examples of the configuration of a display device. FIG. 9 is a block diagram showing an example of the configuration of a display device. 10A and 10B are circuit diagrams showing configuration examples of a display device. FIG. 11 is a timing chart showing an example of a method for driving a display device. 12A to 12C are circuit diagrams and schematic diagrams showing configuration examples of a display device. FIG. 13 is a block diagram showing an example of the configuration of a display device. 14A and 14B are circuit diagrams showing configuration examples of a display device. 15A and 15B are circuit diagrams showing configuration examples of a display device. FIG. 16 is a circuit diagram showing an example of the configuration of a display device. FIG. 17 is a circuit diagram showing an example of the configuration of a display device. FIG. 18 is a circuit diagram showing an example of the configuration of a display device. FIG. 19 is a circuit diagram showing an example of the configuration of a display device. 20A and 20B are circuit diagrams showing configuration examples of a display device. 21A and 21B are circuit diagrams showing configuration examples of a display device. 22A and 22B are circuit diagrams showing configuration examples of a display device. 23A and 23B are circuit diagrams showing configuration examples of a display device. 24A and 24B are circuit diagrams showing configuration examples of a display device. 25A and 25B are circuit diagrams showing configuration examples of a display device. 26A and 26B are circuit diagrams showing configuration examples of a display device. 27A and 27B are block diagrams showing configuration examples of a display device. FIG. 28 is a cross-sectional view showing an example of the configuration of a display device. FIG. 29 is a cross-sectional view showing an example of the configuration of a display device. Fig. 30A is a block diagram showing an example of the configuration of a display device, and Fig. 30B is a cross-sectional view showing an example of the configuration of a display device. FIG. 31 is a cross-sectional view showing an example of the configuration of a display device. FIG. 32 is a cross-sectional view showing an example of the configuration of a display device. FIG. 33 is a cross-sectional view showing an example of the configuration of a display device. FIG. 34 is a cross-sectional view showing an example of the configuration of a display device. 35A is a top view illustrating an example of the structure of a transistor, and FIGS. 35B and 35C are cross-sectional views illustrating an example of the structure of a transistor. 36A to 36C are diagrams showing configuration examples of a display device. 37A to 37C are diagrams showing configuration examples of a display device. 38A to 38C are diagrams showing configuration examples of a display device. Fig. 39A is a diagram explaining the classification of IGZO crystal structures, Fig. 39B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Fig. 39C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. 40A and 40B are diagrams showing an example of a display IC. 41A to 41D are diagrams showing an example of an electronic device. 42A and 42B are diagrams showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0025] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0026] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or a cut-off state) when a voltage V between the gate and the source of an n-channel transistor is applied. gs is the threshold voltage V th (For p-channel transistors, V th This refers to a state of being (higher than)

[0027] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including an oxide or an oxide semiconductor.

[0028] (Embodiment 1) In this embodiment, a display device and a display correction system according to one embodiment of the present invention will be described.

[0029] <Example of display device configuration> 1 is a block diagram schematically illustrating a configuration example of a display device 10, which is a display device of one embodiment of the present invention. The display device 10 includes a layer 20 and a layer 30, and the layer 30 can be stacked, for example, above the layer 20. An interlayer insulator, a conductor for electrical connection between different layers, and the like can be provided between the layer 20 and the layer 30.

[0030] The transistors provided in the layer 20 can be, for example, transistors having silicon in their channel formation regions (also referred to as Si transistors), such as transistors having single crystal silicon in their channel formation regions. In particular, when transistors having single crystal silicon in their channel formation regions are used as the transistors provided in the layer 20, the on-state current of the transistors can be increased. Therefore, it is preferable that the circuits included in the layer 20 be driven at high speed. In addition, Si transistors can be formed by microfabrication to have a channel length of 3 nm to 10 nm, and therefore can be used in the display device 10 provided with an accelerator such as a CPU or a GPU, an application processor, or the like.

[0031] The transistor provided in the layer 30 can be, for example, an OS transistor. In particular, it is preferable to use a transistor having an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region as the OS transistor. Such an OS transistor has a characteristic of having a very low off-state current. Therefore, it is preferable to use an OS transistor as a transistor provided in a pixel circuit in a display portion, because analog data written in the pixel circuit can be retained for a long period of time.

[0032] The layer 20 is provided with a driving circuit 40 and a functional circuit 50. The Si transistors in the layer 20 can increase the on-current of the transistors, so that each circuit can be driven at high speed.

[0033] The layer 30 includes a display unit 60 having a plurality of pixels 61. Each pixel 61 includes pixel circuits 62R, 62G, and 62B that control red, green, and blue light emission. The pixel circuits 62R, 62G, and 62B function as subpixels of the pixel 61. The pixel circuits 62R, 62G, and 62B include OS transistors, allowing analog data written to the pixel circuits to be retained for a long period of time. Each pixel 61 in the layer 30 is also provided with a backup circuit 82. The backup circuit may also be called a storage circuit or a memory circuit.

[0034] The driving circuit 40 includes a gate line driving circuit, a source line driving circuit, and the like for driving the pixel circuits 62R, 62G, and 62B. For example, the driving circuit 40 includes a gate line driving circuit and a source line driving circuit for driving the pixels 61 of the display unit 60. By arranging the driving circuit 40 on a layer 20 different from the layer 30 on which the display is provided, the area occupied by the display unit in the layer 30 can be increased. The driving circuit 40 may also include an LVDS (Low Voltage Differential Signaling) circuit or a D / A (Digital to Analog) conversion circuit, which functions as an interface for receiving data such as image data from outside the display device 10. The Si transistors in the layer 20 can increase their on-state current. The channel length or channel width of the Si transistors may be varied depending on the operating speed of each circuit.

[0035] The functional circuit 50 has a CPU used for arithmetic processing of data. The CPU has multiple CPU cores. Each CPU core has a flip-flop. The flip-flop has multiple scan flip-flops. The flip-flop 80 inputs and outputs data (backup data) from the scan flip-flop to and from a backup circuit 82. In FIG. 1, backup data BD is illustrated as a data signal held in the backup circuit 82.

[0036] The backup circuit 82 is preferably a memory having an OS transistor, for example. A backup circuit configured with an OS transistor has advantages such as being able to suppress a voltage drop corresponding to the data to be backed up and consuming almost no power to retain the data, due to the characteristic of the OS transistor being extremely small off-current. The backup circuit 82 having an OS transistor can be provided in the display unit 60 in which a plurality of pixels 61 are arranged. FIG. 1 illustrates a state in which a backup circuit 82 is provided for each pixel 61.

[0037] The backup circuit 82, which is made up of OS transistors, can be stacked on the layer 20 having Si transistors. The backup circuits 82 may be arranged in a matrix, like the sub-pixels in the pixel 61, or may be arranged for each set of pixels. In other words, the backup circuits 82 can be arranged in the layer 30 without being restricted by the arrangement of the pixels 61. This increases the degree of freedom in the display unit / circuit layout, allows for arrangement without increasing the circuit area, and allows for an increase in the storage capacity of the backup circuit 82 required for arithmetic processing.

[0038] <Configuration example of pixel circuit and backup circuit> 2 to 4, an example of the arrangement of the backup circuit 82 and the pixel circuits 62R, 62G, and 62B, which are sub-pixels, in the display unit 60 will be described.

[0039] 2 illustrates a configuration in which a plurality of pixels 61 are arranged in a matrix in a display unit 60. In addition to pixel circuits 62R, 62G, and 62B, each pixel 61 has a backup circuit 82. As described above, the backup circuit 82 and the pixel circuits 62R, 62G, and 62B can all be configured using OS transistors, and therefore can be arranged within the same pixel.

[0040] 3 illustrates a configuration in which a plurality of pixels 61 are arranged in a matrix in a display unit 60, and in FIG. 3, two rows and two columns of pixels 61 are illustrated as a unit pixel 61UNI. The pixels 61 have pixel circuits 62R, 62G, and 62B. The unit pixel 61UNI has a backup circuit 82 located in a position surrounded by four pixels 61. As described above, the backup circuit 82 and the pixel 61 can both be configured using OS transistors, and therefore can be arranged within the same unit pixel 61UNI.

[0041] 4A illustrates a configuration in which a pixel 61PEN employing a Pentile array is arranged in a display unit. As an example, the pixel 61PEN includes pixel circuits 62R and 62G or pixel circuits 62B and 62G, as well as a backup circuit 82. As described above, the backup circuit 82 and the pixel circuits 62R and 62G or pixel circuits 62B and 62G can all be configured using OS transistors, and therefore can be arranged within the same pixel.

[0042] 4B illustrates a configuration in which pixels 61PEN are arranged in a matrix in the display unit 60, with two rows and two columns of pixels 61PEN illustrated as a unit pixel 61UNI. Each pixel 61PEN has pixel circuits 62R and 62G or pixel circuits 62B and 62G. Each unit pixel 61UNI has a backup circuit 82 located at a position surrounded by four pixels 61PEN. As described above, both the backup circuit 82 and the pixel 61PEN can be configured using OS transistors, and therefore can be arranged within the same unit pixel 61UNI.

[0043] <Block diagram of display device> 5 shows a block diagram for explaining each component of the display device 10. The display device has a drive circuit 40, a functional circuit 50, and a display unit 60.

[0044] The drive circuit 40 includes, for example, a gate driver 41 and a source driver 42. The gate driver 41 drives wirings GL that function as gate lines for outputting signals to the pixel circuits 62R, 62G, and 62B. The source driver 42 drives a plurality of wirings SL that function as source lines for outputting signals to the pixel circuits 62R, 62G, and 62B. The drive circuit 40 also supplies voltages for displaying images in the pixel circuits 62R, 62G, and 62B to the pixel circuits 62R, 62G, and 62B via the plurality of wirings.

[0045] The functional circuit 50 has a CPU 51. The CPU 51 has a CPU core 53. The CPU core 53 has a flip-flop 80 for temporarily holding data used in arithmetic processing. The flip-flop 80 has a plurality of scan flip-flops 81, and each scan flip-flop 81 is electrically connected to a backup circuit 82 provided in the display unit 60.

[0046] The display unit 60 has a plurality of pixels 61, each of which is provided with pixel circuits 62R, 62G, and 62B, and a backup circuit 82. As described with reference to Figures 2 to 4, the backup circuit 82 does not necessarily have to be arranged within the pixel 61, which is the repeating unit. The backup circuit 82 can be arranged freely depending on the shape of the display unit 60, the shapes of the pixel circuits 62R, 62G, and 62B, etc.

[0047] 6 is a schematic diagram illustrating the positional relationship between the layer 30 provided on the layer 20 and the light-emitting element 70. FIG. 6 corresponds to an example of a schematic cross-sectional view of the display device 10 shown in FIG.

[0048] 6, functional circuits 50A and 50B are shown on layer 20 as examples of the drive circuit 40 and the functional circuit 50. The drive circuit 40 and the functional circuits 50A and 50B have Si transistors. The functional circuits 50A and 50B have different functions.

[0049] 6, the layer 30 has pixel circuits 62R, 62G, and 62B provided at positions overlapping with the drive circuit 40 and the functional circuits 50A and 50B, and a backup circuit 82. Fig. 6 shows an example configuration in which a backup circuit is provided for each pixel circuit.

[0050] 6, the light-emitting element 70 has light-emitting elements 70R, 70G, and 70B connected to pixel circuits 62R, 62G, and 62B, respectively. For example, the light-emitting element 70R, the pixel circuit 62R, the backup circuit 82, and the drive circuit 40 are provided so as to overlap in a region 71.

[0051] 6, functional circuits 50A and 50B are connected to different backup circuits 82 via wiring 72 and 73. Also, as shown in FIG. 6, pixel circuits 62R, 62G, and 62B are connected to light-emitting elements 70R, 70G, and 70B via wiring 74, respectively.

[0052] As shown in FIG. 6, the backup circuit 82 can be provided in the layer 30 where the OS transistors are provided, and can therefore be stacked with the layer 20 having the Si transistors. The backup circuit 82 can be provided in the layer 30 without being restricted by the arrangement of the pixels 61. This increases the degree of freedom in the display unit / circuit layout, and allows the backup circuit 82 to be arranged without increasing the circuit area, thereby increasing the storage capacity of the backup circuit 82 required for arithmetic processing. As a result, the functional circuits 50A and 50B can be operated intermittently, thereby contributing to power savings.

[0053] <Pixel circuit configuration example> 7A and 7B show a configuration example of a pixel circuit 62 applicable to pixel circuits 62R, 62G, and 62B, and a light-emitting element 70 connected to pixel circuit 62. Fig. 7A is a diagram showing the connection of each element, and Fig. 7B is a diagram schematically showing the hierarchical relationship between drive circuit 40, pixel circuit 62, and light-emitting element 70.

[0054] In this specification and the like, the term “element” may be replaced with “device” in some cases. For example, a display element, a light-emitting element, and a liquid crystal element may be replaced with a display device, a light-emitting device, and a liquid crystal device, for example.

[0055] 7A and 7B includes a pixel circuit 62 including a switch SW21, a switch SW22, a transistor M21, and a capacitor C21. The switches SW21 and SW22 may be transistors. The switches SW21 and SW22 may also be transistors. The switches SW21, SW22, and transistor M21 may be OS transistors. Each of the OS transistors SW21, SW22, and transistor M21 preferably includes a back gate electrode. In this case, the back gate electrode may be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode.

[0056] The transistor M21 includes a gate electrode electrically connected to the switch SW21, a first electrode electrically connected to the light-emitting element 70, and a second electrode electrically connected to a wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting element 70.

[0057] The switch SW21 has a first terminal electrically connected to the gate electrode of the transistor M21 and a second terminal electrically connected to the wiring SL that functions as a source line, and has the function of controlling the conductive state or non-conductive state based on the potential of the wiring GLA that functions as a gate line.

[0058] The switch SW22 has a first terminal electrically connected to the wiring V0 and a second terminal electrically connected to the light-emitting element 70, and has a function of controlling the conductive state or non-conductive state based on the potential of the wiring GLB functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 62 to the drive circuit 40 or the functional circuit 50.

[0059] The capacitor C21 includes a conductive film electrically connected to the gate electrode of the transistor M21 and a conductive film electrically connected to the second terminal of the switch SW22.

[0060] The light emitting element 70 includes a first electrode electrically connected to the first electrode of the transistor M21 and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light emitting element 70.

[0061] This allows the intensity of light emitted by the light-emitting element 70 to be controlled in accordance with an image signal applied to the gate electrode of the transistor M21. The amount of current flowing through the light-emitting element 70 can also be controlled by the reference potential of the wiring V0 applied via the switch SW22. Furthermore, by monitoring the amount of current flowing through the wiring V0 with an external circuit, the amount of current flowing through the light-emitting element can be estimated. This allows pixel defects and the like to be detected.

[0062] Note that the light-emitting element described in one embodiment of the present invention refers to a self-luminous display element such as an organic light-emitting diode (OLED). Note that the light-emitting element electrically connected to the pixel circuit can be a self-luminous light-emitting element such as an LED (light-emitting diode), a micro LED, a QLED (quantum-dot light-emitting diode), or a semiconductor laser. Alternatively, a liquid crystal element or the like can be used as the display element.

[0063] In the configuration shown in FIG. 7B as an example, the wiring electrically connecting the pixel circuits 62 and the driver circuit 40 can be shortened, thereby reducing the wiring resistance of the wiring. This allows data to be written at high speed, enabling the display device 10 to be driven at high speed. This allows the display device 10 to have a large number of pixels 61, ensuring a sufficient frame period, thereby increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 increases the resolution of images displayed by the display device 10. For example, the pixel density of the display device 10 can be 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, for example, and is suitable for use in electronic devices such as HMDs, where the display unit is close to the user.

[0064] Although FIG. 7B illustrates a diagram in which the wirings GLA, GLB, ANO, VCOM, V0, and SL are supplied via wirings from the driver circuit 40 below the pixel circuit 62, one embodiment of the present invention is not limited thereto. For example, wirings for supplying signals and voltages from the driver circuit 40 may be routed to the periphery of the display unit 60 and electrically connected to the pixel circuits 62 arranged in a matrix on the layer 30. In this case, it is effective to provide the gate driver 41 of the driver circuit 40 on the layer 30. That is, it is effective to use OS transistors as the transistors of the gate driver 41. It is also effective to provide part of the function of the source driver 42 of the driver circuit 40 on the layer 30. For example, it is effective to provide a demultiplexer on the layer 30 that distributes signals output by the source driver 42 to each source line. It is effective to use OS transistors as the transistors of the demultiplexer.

[0065] 7A and 7B show an example of the pixel circuit 62 including three transistors in total, two transistors functioning as switches and one transistor functioning as a driving transistor, but one embodiment of the present invention is not limited to this. For example, the pixel circuit 62A shown in FIG. 8A or the pixel circuit 62B shown in FIG. 8A may also be used.

[0066] The pixel circuit 62A shown in FIG. 8A is a pixel circuit having two transistors, a switch SW21 and a transistor M21. The capacitor C21 in FIGS. 7A and 7B can be omitted by using the gate capacitance of the transistor M21. The pixel circuit 62B shown in FIG. 8B is a pixel circuit similar to the pixel circuit 62 shown in FIGS. 7A and 7B, but having a switch SW23 between the transistor M21 and the line ANO, the gate electrode of which is electrically connected to the line GLC. In other words, the pixel circuit 62B shown in FIG. 8B is a pixel circuit having four transistors. The number of transistors is not limited to the examples of the pixel circuits 62A and 62B shown, and pixel circuits with other circuit configurations can also be used for the pixel circuit 62.

[0067] 7A to 8B, the pixel circuits are illustrated with the wiring connected to the back gate electrode being different from the wiring connected to the gate electrode, and different potentials are applied to them. However, other configurations are also possible. For example, the back gate electrode and the gate electrode may be mutually connected. Alternatively, the transistor functioning as a switch and the drive transistor controlling the current flowing through the light-emitting element 70 may have different connection configurations. For example, in the transistor functioning as a switch, the back gate electrode and the gate electrode may be mutually connected, and in the drive transistor, the back gate electrode may be connected to the source side of the transistor (for example, the wiring side connected to the light-emitting element 70).

[0068] <Example of functional circuit configuration> As an example of a circuit included in a functional circuit, a CPU having a CPU core capable of power gating will be described.

[0069] 9 shows an example of the configuration of a CPU 51 included in the functional circuit 50. The CPU 51 includes a CPU core 53, an L1 (level 1) cache memory device (L1 Cache) 54, an L2 cache memory device (L2 Cache) 55, a bus interface unit (Bus I / F) 56, power switches 57A to 57C, and a level shifter (LS) 58. The CPU core 53 includes a flip-flop 80.

[0070] The CPU core 53, the L1 cache memory device 54, and the L2 cache memory device 55 are interconnected by a bus interface unit 56.

[0071] The PMU 59 generates a clock signal GCLK1 and various PG (power gating) control signals in response to externally input interrupt signals (Interrupts) and signals such as the SLEEP1 signal emitted by the CPU 51. The clock signal GCLK1 and the PG control signals are input to the CPU 51. The PG control signals control the power switches 57A to 57C and the flip-flop 80.

[0072] Power switches 57A and 57B respectively control the supply of voltages VDDD and VDD1 to a virtual power line V_VDD (hereinafter referred to as a V_VDD line). Power switch 57C controls the supply of voltage VDDH to a virtual power line V_VDH (hereinafter referred to as a V_VDH line). Voltage VSSS is input to the CPU 51 and PMU 59 without passing through a power switch. Voltage VDDD is input to PMU 59 without passing through a power switch.

[0073] The voltages VDDD and VDD1 are drive voltages for the CMOS circuit. The voltage VDD1 is lower than the voltage VDDD and is the drive voltage in the sleep state. The voltage VDDH is the drive voltage for the OS transistors and is higher than the voltage VDDD.

[0074] Each of the L1 cache memory device 54, the L2 cache memory device 55, and the bus interface unit 56 has at least one power domain that can be power-gated. Each power domain that can be power-gated has one or more power switches. These power switches are controlled by a PG control signal.

[0075] The flip-flop 80 is used as a register. A backup circuit is provided in the flip-flop 80. The flip-flop 80 will be described below.

[0076] 10A shows an example of the circuit configuration of a flip-flop 80. The flip-flop 80 has a scan flip-flop 81 and a backup circuit 82.

[0077] The scan flip-flop 81 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 81A.

[0078] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 81A. The analog switch of scan flip-flop 81 is connected to nodes CK1 and CKB1 of clock buffer circuit 81A. Node RT is an input node for a reset signal.

[0079] A signal SCE is a scan enable signal and is generated by the PMU 59. The PMU 59 generates signals BK and RC. A level shifter 58 level-shifts the signals BK and RC to generate signals BKH and RCH. The signals BK and RC are a backup signal and a recovery signal.

[0080] The circuit configuration of the scan flip-flop 81 is not limited to that shown in Fig. 10A, and any flip-flop available in a standard circuit library can be applied.

[0081] The backup circuit 82 includes nodes SD_IN and SN11, transistors M11 to M13, and a capacitor C11.

[0082] The node SD_IN is an input node for scan test data and is connected to the node Q1 of the scan flip-flop 81. The node SN11 is a holding node of the backup circuit 82. The capacitor C11 is a holding capacitor for holding the voltage of the node SN11.

[0083] The transistor M11 controls the conduction state between the node Q1 and the node SN11. The transistor M12 controls the conduction state between the node SN11 and the node SD. The transistor M13 controls the conduction state between the node SD_IN and the node SD. The on / off of the transistors M11 and M13 is controlled by a signal BKH, and the on / off of the transistor M12 is controlled by a signal RCH.

[0084] The transistors M11 to M13 are OS transistors, similar to the transistors included in the pixel circuit 62. The transistors M11 to M13 are illustrated as having back gates. In this example, the back gates of the transistors M11 to M13 are connected to a power supply line that supplies a voltage VBG1.

[0085] At least the transistors M11 and M12 are preferably OS transistors. OS transistors have an extremely small off-state current, which prevents the voltage drop at the node SN11. Furthermore, the backup circuit 82 consumes almost no power to retain data, making it nonvolatile. Because data is rewritten by charging and discharging the capacitor C11, the backup circuit 82 is theoretically capable of writing and reading data without any restrictions on the number of times it can be rewritten, and it can write and read data with low energy.

[0086] It is highly preferable that all transistors in the backup circuit 82 are OS transistors. As shown in Fig. 10B, the backup circuit 82 can be stacked on a scan flip-flop 81 made up of a silicon CMOS circuit.

[0087] Since the backup circuit 82 has an extremely small number of elements compared to the scan flip-flop 81, stacking the backup circuit 82 does not require changing the circuit configuration or layout of the scan flip-flop 81. In other words, the backup circuit 82 is a highly versatile backup circuit. Furthermore, since the backup circuit 82 can be provided so as to overlap the area where the scan flip-flop 81 is formed, even if the backup circuit 82 is incorporated, the area overhead of the flip-flop 80 can be reduced to zero. Therefore, providing the backup circuit 82 in the flip-flop 80 enables power gating of the CPU core 53. Because little energy is required for power gating, power gating of the CPU core 53 can be performed with high efficiency.

[0088] By providing backup circuit 82, a parasitic capacitance due to transistor M11 is added to node Q1, but since this is small compared to the parasitic capacitance due to the logic circuit connected to node Q1, it does not affect the operation of scan flip-flop 81. In other words, even if backup circuit 82 is provided, the performance of flip-flop 80 does not substantially deteriorate.

[0089] For example, a clock gating state, a power gating state, or a sleep state can be set as the low power consumption state (non-operating state) of the CPU core 53. The PMU 59 selects the low power consumption mode of the CPU core 53 based on an interrupt signal, the signal SLEEP1, etc. For example, when transitioning from the normal operating state to the clock gating state, the PMU 59 stops generating the clock signal GCLK1.

[0090] For example, when transitioning from a normal operating state to a hibernation state, the PMU 59 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU 59 turns off the power switch 57A and turns on the power switch 57B to input the voltage VDD1 to the CPU core 53. The voltage VDD1 is a voltage that does not cause the data in the scan flip-flop 81 to be lost. When performing frequency scaling, the PMU 59 reduces the frequency of the clock signal GCLK1.

[0091] When the CPU core 53 is transitioned from the normal operation state to the power gating state, an operation is performed to back up the data in the scan flip-flop 81 to the backup circuit 82. When the CPU core 53 is returned from the power gating state to the normal operation state, a recovery operation is performed to write the data in the backup circuit 82 back to the scan flip-flop 81.

[0092] 11 shows an example of a power gating sequence for the CPU core 53. In FIG. 11, t1 to t7 represent time. Signals PSE0 to PSE2 are control signals for the power switches 57A to 57C and are generated by the PMU 59. When the signal PSE0 is "H" / "L", the power switches 57A to 57C are on / off. The same applies to the signals PSE1 and PSE2.

[0093] Before time t1, the state is normal operation. The power switch 57A is on, and the voltage VDDD is input to the CPU core 53. The scan flip-flop 81 performs normal operation. At this time, the level shifter 58 does not need to operate, so the power switch 57C is off, and the signals SCE, BK, and RC are "L." Since the node SE is "L," the scan flip-flop 81 stores the data at the node D1. In the example of FIG. 11, at time t1, the node SN11 of the backup circuit 82 is "L."

[0094] The operation during backup will be described. At operation time t1, the PMU 59 stops the clock signal GCLK1 and sets the signals PSE2 and BK to "H." The level shifter 58 becomes active and outputs the signal BKH at "H" to the backup circuit 82.

[0095] The transistor M11 of the backup circuit 82 turns on, and the data at the node Q1 of the scan flip-flop 81 is written to the node SN11 of the backup circuit 82. If the node Q1 of the scan flip-flop 81 is "L", the node SN11 remains "L", and if the node Q1 is "H", the node SN11 becomes "H".

[0096] The PMU 59 sets the signals PSE2 and BK to "L" at time t2, and sets the signal PSE0 to "L" at time t3. At time t3, the state of the CPU core 53 transitions to the power gating state. Note that the signal PSE0 may also fall at the same timing as the falling edge of the signal BK.

[0097] The operation during power gating will be described. When the signal PSE0 goes to "L", the voltage of the V_VDD line drops, and the data at node Q1 is lost. Node SN11 continues to hold the data at node Q1 at time t3.

[0098] The operation during recovery will be explained below. At time t4, the PMU 59 sets the signal PSE0 to "H", transitioning from the power gating state to the recovery state. Charging of the V_VDD line begins, and when the voltage on the V_VDD line reaches VDDD (time t5), the PMU 59 sets the signals PSE2, RC, and SCE to "H".

[0099] Transistor M12 turns on, and the charge of capacitor C11 is distributed between node SN11 and node SD. If node SN11 is "H," the voltage of node SD rises. Since node SE is "H," the data of node SD is written to the input latch circuit of scan flip-flop 81. When clock signal GCLK1 is input to node CK at time t6, the data of the input latch circuit is written to node Q1. In other words, the data of node SN11 has been written to node Q1.

[0100] At time t7, the PMU 59 sets the signals PSE2, SCE, and RC to "L," completing the recovery operation.

[0101] The backup circuit 82 using OS transistors is highly suitable for normally-off computing because it consumes low power both dynamically and statically. Even if the flip-flop 80 is installed, it can be ensured that there is almost no degradation in performance of the CPU core 53 or an increase in dynamic power consumption.

[0102] The CPU core 53 may have multiple power domains that can be power-gated. Each of the multiple power domains is provided with one or more power switches for controlling voltage input. The CPU core 53 may also have one or more power domains in which power gating is not performed. For example, a power domain in which power gating is not performed may be provided with a power gating control circuit for controlling the flip-flop 80 and the power switches 57A to 57C.

[0103] The application of the flip-flop 80 is not limited to the CPU 51. In a computing device, the flip-flop 80 can be applied to a register provided in a power domain that is capable of power gating.

[0104] <Example of display correction system configuration> In the display correction system according to one embodiment of the present invention, the current I ELBy correcting the above, it is possible to reduce display defects caused by defective pixels such as bright spots or dark spots.

[0105] The circuit diagram shown in Figure 12A illustrates a portion of the pixel circuit 62 shown in Figure 5. The current I EL In the case of a defective pixel that causes a bright spot or a dark spot, the current flowing through the defective pixel becomes extremely large or small compared to the current flowing through a pixel with a normal display.

[0106] The CPU51 monitors the current I that flows through the switch SW23. MONI The data of the monitor current I MONI The amount of current is converted into digital data that can be handled by the CPU 51, and the CPU 51 performs calculations using the digital data. The calculations in the CPU 51 estimate defective pixels, and the CPU 51 performs corrections to make display defects caused by defective pixels less visible. For example, when pixel 61D shown in FIG. 12B is a defective pixel, the current I flowing through the light-emitting element 70 of the adjacent pixel 61N is EL Correct the following.

[0107] The correction can be estimated by performing operations based on artificial neural networks such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs).

[0108] As shown in FIG. 12C, the current I EL current I EL_C By correcting the pixel 61N as described above, the defective pixel and the pixel 61G can be combined to produce a display. As a result, display defects caused by defective pixels, such as bright spots or dark spots, become less visible, and a normal display can be achieved.

[0109] The calculations performed by the display correction system to correct the current flowing through pixels can be continuously stored as backup data in the CPU 51 described above. This is particularly effective when performing massive calculations, such as calculations based on artificial neural networks. By using the CPU 51 as an application processor, it is possible to reduce display defects and power consumption by combining it with a drive that allows the frame frequency to be varied.

[0110] <Modifications of the display device> 13 to 27 show modified examples of the respective components of the display device 10 described above.

[0111] The block diagram of the display device 10A shown in FIG. 13 corresponds to a configuration in which an accelerator 52 is added to the functional circuit 50 in the display device 10 of FIG.

[0112] When the display correction system described above performs calculations based on an artificial neural network, it is configured to repeatedly perform product-sum calculations. The accelerator 52 functions as a dedicated calculation circuit for the product-sum calculation process of the artificial neural network NN. Calculations using the accelerator 52 can perform corrections due to the above-mentioned display defects or processes to correct the contours of images by up-converting the display data. Power gating of the CPU 51 can be configured to reduce power consumption while the accelerator 52 is performing calculations.

[0113] The circuit diagrams shown in Figures 14A and 14B are diagrams combining the pixel circuit 62 shown in Figure 7A and the backup circuit 82 shown in Figure 10A. Figure 14A illustrates a configuration in which one electrode of the capacitance C11 of the backup circuit 82 is connected to the wiring VCOM. Figure 14B illustrates a configuration in which one electrode of the capacitance C11 of the backup circuit 82 is connected to the wiring ANO. As shown in Figures 14A and 14B, by sharing wiring between the pixel circuit 62 and the backup circuit 82, which have different circuit configurations, on the layer 30, it is possible to reduce the number of wirings.

[0114] 14A and 14B, it is also possible to omit the transistors M12 and M13. Such a configuration is shown in FIGS. 15A and 15B, respectively. The memory circuit 82B shown in FIGS. 15A and 15B can be used as a highly versatile memory circuit, not limited to backing up data in the flip-flop 80. For example, the memory circuit 82B can be used as a memory circuit for the functional circuit 50.

[0115] 15A and 15B show a configuration in which one electrode of the capacitor C11 in the memory circuit 82B is connected to the wiring VCOM or the wiring ANO, but other configurations are also possible, such as a configuration in which one electrode is connected to the wiring V0 or the wiring GL.

[0116] The circuit diagram shown in FIG. 16 illustrates an example of pixel circuits and memory circuits arranged across multiple rows. In FIG. 16, pixel circuits 62_1R, 62_1G, and 62_1B are illustrated as pixel circuits functioning as subpixels in the first row. In FIG. 16, light-emitting elements 70R_1, 70G_1, and 70B_1 are illustrated as light-emitting elements in the first row. In FIG. 16, memory circuit 82B_1 is illustrated as a memory circuit in the first row. In FIG. 16, pixel circuits 62_2R, 62_2G, and 62_2B are illustrated as pixel circuits functioning as subpixels in the second row. In FIG. 16, light-emitting elements 70R_2, 70G_2, and 70B_2 are illustrated as light-emitting elements in the second row. In FIG. 16, memory circuit 82B_2 is illustrated as a memory circuit in the second row. The memory circuits 82B_1 and 82B_2 are connected to nodes that hold data in the functional circuits 50_1 and 50_2. The functional circuits 50_1 and 50_2 correspond to different terminals in the functional circuit 50.

[0117] 16 illustrates a wiring GL_1 that functions as the wiring GL in the first row and a wiring GL_2 that functions as the wiring GL in the second row. Also illustrated in Fig. 16 are wirings SL_R, SL_G, and SL_B, a wiring ANO, and a wiring VCOM that function as source lines. Also illustrated in Fig. 16 are a wiring ML_1 that supplies a signal BKH for controlling the memory circuit 82B_1 and a wiring ML_2 that supplies a signal BKH for controlling the memory circuit 82B_2.

[0118] In the following description, when describing the same elements such as pixel circuit 62_1R, pixel circuit 62_1G, and pixel circuit 62_1B, the description may refer to parts that share a common reference symbol, such as pixel circuit 62_1. Furthermore, when describing multiple elements using the same reference symbol, and particularly when it is necessary to distinguish between them, the reference symbol may be accompanied by a reference symbol for identifying a row number, such as "_1" or "_2," or a reference symbol for identifying each color controlled by a sub-pixel, such as "R," "G," or "B."

[0119] Note that the pixel circuits 62_1 and 62_2 shown in Fig. 16 are the example of the configuration in Fig. 8A that includes a switch SW21 and a transistor M21. The memory circuits 82B_1 and 82B_2 shown in Fig. 16 are the example of the configuration in Fig. 15A that includes a transistor M11 and a capacitor C11. Note that the memory circuit 82B may be configured to be disposed between a set of pixel circuits (pixel circuits 62_1R, 62_1G, and 62_1B) that control RGB.

[0120] In addition, although connections of the back gate electrodes of the transistors in the pixel circuits 62_1 and 62_2 and the memory circuits 82B_1 and 82B_2 are omitted in FIG. 16, they may be connected to each other. Alternatively, the back gate electrodes of the transistors in the pixel circuit 62 and the memory circuit 82B in the same row may be connected to each other. Alternatively, the back gate electrodes of the transistors in the pixel circuit 62 may be connected to each other, and the back gate electrodes of the transistors in the memory circuit 82B may be connected to each other separately. In other words, it is preferable that the wiring connecting the back gate electrodes of the transistors in the pixel circuit 62 and the wiring connecting the back gate electrodes of the transistors in the memory circuit 82B are separate wirings.

[0121] 16 , memory circuits 82B provided together with pixel circuits 62 can be provided corresponding to RGB subpixels. The memory circuits 82B can retain data of circuits provided in layer 20, such as the functional circuits 50 or the CPU 51, by using OS transistors. The memory circuits 82B provided in layer 30, in which OS transistors are provided, can be uniformly arranged in layer 30. This makes it easier to electrically connect the memory circuits 82B to the functional circuits 50 or the CPU 51, unlike when the memory circuits 82B are locally arranged.

[0122] FIG. 17 illustrates an example of pixel circuits and memory circuits arranged across multiple rows, which is different from the configuration illustrated in FIG. 16 . While FIG. 16 illustrates a configuration in which a memory circuit 82B is provided corresponding to a pair of pixel circuits 62_1 and 62_2 that control RGB, FIG. 17 illustrates a configuration in which a memory circuit 82B is provided for each pair of pixel circuits that control RGB. Note that functional circuits 50_11, 50_12, 50_13, 50_21, 50_22, and 50_23 correspond to different terminals of the functional circuit 50. The configuration illustrated in FIG. 17 allows more memory circuits 82B to be provided in the layer 30 where the OS transistors are provided than in the configuration illustrated in FIG. 16 . In addition, because the memory circuits 82B can be uniformly arranged in the layer 30, unlike when the memory circuits 82B are arranged locally, electrical connection between the memory circuits 82B and the functional circuit 50 or the CPU 51 can be easily established regardless of the circuit arrangement of the functional circuit 50 or the CPU 51.

[0123] FIG. 18 illustrates an example of pixel circuits and memory circuits arranged across multiple rows, which is different from the configurations illustrated in FIGS. 16 and 17. In FIG. 18, the wiring ML_1 and the wiring ML_2 are configured as a common wiring ML. The wiring ML is a wiring for supplying a signal BKH for controlling the memory circuits 82B_1 and 82B_2. The wiring ML is configured to connect wirings arranged in different rows via wirings arranged parallel to the wirings arranged in the column direction. The wiring ML_COL arranged parallel to the wirings arranged in the column direction can be disposed, for example, between the pixel circuits of the subpixels to reduce the influence of noise between the pixel circuits.

[0124] Fig. 19 shows an example of pixel circuits and memory circuits provided across multiple rows, with a configuration different from those shown in Figs. 16 to 18. In Fig. 19, a memory circuit 82B_1 in the first row and a memory circuit 82B_2 in the second row are connected to the same node that holds data in the functional circuit 50. The memory circuits 82B_1 and 82B_2 can control the transistor M11 with different signals at different timings, so that data at the nodes in the functional circuit 50 can be acquired and held at multiple timings.

[0125] FIG. 20A shows a modified example of the memory circuit 82B that can be applied to the memory circuit 82B_1 in the first row and / or the memory circuit 82B_2 in the second row shown in FIGS. 16 to 19. FIG. 20A illustrates a configuration in which the terminal of the capacitor C11 connected to the wiring ANO is connected to a node in the functional circuit 50 on the layer 20 side to which a fixed potential is applied. As another configuration, FIG. 20B illustrates a configuration in which the terminal of the capacitor C11 connected to the wiring ANO is connected to a node in the functional circuit 50 on the layer 20 side to which a fixed potential is applied, the wiring ML connected to the gate electrode of the transistor M11 is omitted, and a control signal is applied from the functional circuit 50 on the layer 20 side. Note that the functional circuits 50_1A, 50_1B, and 50_1C represent different terminals in the functional circuit 50. This configuration can reduce the configuration of the memory circuit 82B in the layer 30 and increase the area occupied by the pixel circuit 62.

[0126] 20A and 20B, Fig. 21A shows a modified example of the memory circuit 82B. Fig. 21A illustrates a configuration in which the capacitor C11 in the memory circuit 82B is provided in the functional circuit 50 on the layer 20 side. As another configuration, Fig. 21B illustrates a configuration in which the capacitor C11 in the memory circuit 82B is provided in the functional circuit 50 on the layer 20 side, the wiring ML connected to the gate electrode of the transistor M11 is omitted, and a control signal is provided from the functional circuit 50 on the layer 20 side. With this configuration, the configuration of the memory circuit 82B on the layer 30 can be reduced, and the area occupied by the pixel circuit 62 can be increased.

[0127] The circuit diagram shown in FIG. 22A illustrates a modified example in which the backup circuit 82 described in FIG. 14B is applied instead of the memory circuit 82B described in FIGS. 16 to 20. FIG. 22A illustrates a configuration in which a terminal of a capacitor C11 in the backup circuit 82 is connected to a wiring ANO. FIG. 22B illustrates a configuration in which a terminal of the capacitor C11 in the backup circuit 82 is connected to a transistor M12. Note that scan flip-flops 81_A, 81_B, and 81_C represent different terminals of the scan flip-flop 81. This configuration also makes it possible for the capacitor C11 to hold node data in the functional circuit 50.

[0128] 22A and 22B, FIG. 23A shows a modified example of the backup circuit 82. FIG. 23A illustrates a configuration in which the capacitor C11 in the backup circuit 82 is provided on the layer 20 side where the scan flip-flop 81 is located. As another configuration, FIG. 23B illustrates a configuration in which the capacitor C11 in the backup circuit 82 is provided on the layer 20 side where the scan flip-flop 81 is located, the wiring connected to the gate electrode of the transistor M11 and the wiring connected to the gate of the transistor M12 are omitted, and the control signals BUH and RCH are provided from the functional circuit 50 on the layer 20 side. With this configuration, the configuration of the backup circuit 82 in the layer 30 can be reduced, and the area occupied by the pixel circuit 62 can be increased.

[0129] 22A to 23B, the connection of the back gate electrodes of the transistors in the pixel circuit 62 and the backup circuit 82 is omitted from the illustration, but they may be connected to each other. Alternatively, the back gate electrodes of the transistors in the pixel circuit 62 and the backup circuit 82 in the same row may be connected to each other. Alternatively, the back gate electrodes of the transistors in the pixel circuit 62 may be connected to each other, and the back gate electrodes of the transistors in the backup circuit 82 may be connected to each other separately. In other words, it is preferable that the wiring that connects the back gate electrodes of the transistors in the pixel circuit 62 and the wiring that connects the back gate electrodes of the transistors in the backup circuit 82 are separate wirings.

[0130] 24A shows an example of a circuit configuration provided in the layer 30 that is different from the memory circuit 82B and the backup circuit 82 described above. The arithmetic circuit 82C shown in FIG. 24A is an example of a circuit that performs a product-sum operation and an activation function operation. The arithmetic circuit 82C shown in FIG. 24A is a circuit that performs a product-sum operation on first data and second data. It is preferable to provide a plurality of arithmetic circuits 82C in order to perform a product-sum operation using a plurality of data.

[0131] The arithmetic circuit 82C includes a transistor M31, a transistor M32, and a capacitor CP. The transistor M31 is preferably an OS transistor. Using an OS transistor as the transistor M31 can reduce the leakage current of the transistor M31. This allows data required for calculation to be held as charge at the node NM for a long period of time, thereby realizing a product-sum calculation circuit with high calculation accuracy. This reduces the number of refresh operations of the potential of the node NM, thereby reducing the power consumption of the product-sum calculation circuit.

[0132] Furthermore, by using an OS transistor for the transistor M32, the transistor M32 can be manufactured at the same time as the transistor M31, thereby shortening the manufacturing process of the product-sum circuit.

[0133] In the arithmetic circuit 82C, a first terminal of the transistor M31 is electrically connected to the gate of the transistor M32. R The first terminal of the capacitor CP is electrically connected to the gate of the transistor M32.

[0134] In the arithmetic circuit 82C, a second terminal of the transistor M31 is electrically connected to the wiring BW, and a gate of the transistor M31 is electrically connected to the wiring WW. Y The second terminal of the capacitor CP is electrically connected to the wiring V X In FIG. 24A, the wiring V Y The current flowing from the second terminal of transistor M32 to I AM Let's say.

[0135] In the arithmetic circuit 82C, a charge corresponding to the data is held in the node NM, and the wiring V X By changing the potential of the gate of the electrically floating transistor M32, the potential of the gate of the transistor M32 is changed, and the current I AM Then, the current I flowing through the plurality of arithmetic circuits 82C can be calculated. AM By adding these, it is possible to perform a multiply-and-accumulate operation that corresponds to the sum of the multiplication results.

[0136] The circuit diagram in FIG. 24B shows a modified example in which the arithmetic circuit 82C described in FIG. 24A is used instead of the memory circuit 82B or the backup circuit 82 described in FIGS. 16 to 23. FIG. 25A also shows a configuration in which the capacitance CP in the arithmetic circuit 82C is provided on the layer 30 side. The OS transistors provided on the layer 30 may be configured to have different transistor characteristics. For example, the transistor M31 is required to suppress leakage current in order to retain charge, and the transistor M32 is required to suppress leakage current I AMIn this case, the atomic ratio of the In-Ga-Zn-O metal oxide in the semiconductor layer of the transistor M31 may be, for example, In:Ga:Zn=1:3:4 or 1:1:0.5, and the atomic ratio of the In-Ga-Zn-O metal oxide in the semiconductor layer of the transistor M32 may be, for example, In:Ga:Zn=4:2:3 or 3:1:2.

[0137] As another configuration, in FIG. 25B, the capacitance CP in the arithmetic circuit 82C is provided on the layer 20 side, and the wiring connected to the gate electrode of the transistor M31 and the wiring connected to the transistor M32 are omitted, and only wirings BW, WWL, and wiring V for control from the functional circuit 50 on the layer 20 side are provided. R , V Y , V X 25B, transistor M31 is illustrated as an OS transistor provided in layer 30, and transistor M32 is illustrated as a Si transistor provided in layer 20. With this configuration, the configuration of arithmetic circuit 82C in layer 30 can be reduced, and the area occupied by pixel circuit 62 can be increased.

[0138] 24B to 25B, the connection of the back gate electrodes of the transistors in the pixel circuit 62 and the arithmetic circuit 82C is omitted, but they may be connected to each other. Alternatively, the back gate electrodes of the transistors in the pixel circuit 62 and the arithmetic circuit 82C in the same row may be connected to each other. Alternatively, the back gate electrodes of the transistors in the pixel circuit 62 may be connected to each other, and the back gate electrodes of the transistors in the arithmetic circuit 82C may be connected to each other separately. In other words, it is preferable that the wiring connecting the back gate electrodes of the transistors in the pixel circuit 62 and the wiring connecting the back gate electrodes of the transistors in the arithmetic circuit 82C are separate wirings.

[0139] 26A shows an example of a circuit configuration provided in layer 30 that is different from the memory circuit 82B and backup circuit 82 described above. A block circuit 82D shown in FIG. 26A represents a sequential circuit or a combinational circuit such as a flip-flop, an inverter, or a shift register. It is preferable that a plurality of block circuits 82D are provided in combination.

[0140] The block circuit 82D is provided between the wirings that provide the power supply potential (VDD-VSS). As shown in FIG. 26A, the block circuit 82D is also connected to a transistor M41. The transistor M41 is preferably an OS transistor. A period during which the transistor M41 is turned off can be set by a control signal PSW. By turning off the transistor M41, the node V VDD Since the potential of can be made smaller than VDD, it is possible to suppress leakage current flowing between the wiring that supplies the power supply potential (VDD-VSS) via the block circuit 82D. Therefore, by turning off the transistor M41 during the period when the block circuit 82D is not operating, it is possible to reduce power consumption.

[0141] The circuit diagram in Fig. 26B shows a modified example in which the block circuit 82D described in Fig. 26A is applied instead of the memory circuit 82B or the backup circuit 82 described in Fig. 16 to Fig. 23. Fig. 26A also shows a configuration in which the block circuit 82D is provided on the layer 20 side, and the transistor M41 is provided on the layer 30 side. With this configuration, the transistor M41 can be arranged overlapping the block circuit 82D, thereby achieving a configuration in which power consumption can be reduced without increasing the area occupied by the block circuit 82D.

[0142] 27A shows an example of a configuration in which the transistors of the gate driver 41 included in the drive circuit 40 in FIG. 1 are OS transistors, and the gate driver 41 (illustrated as gate driver 41L and gate driver 41R on both sides of the display unit 60 in the figure) is provided on layer 30. With this configuration, the number of wires from the drive circuit 40 on layer 20 to the display unit 60 on layer 30 can be reduced.

[0143] 27B shows an example of a configuration in which part of the functions of the source driver 42 of the drive circuit 40 in FIG. 27A is provided on the layer 30. In FIG. 27B, the transistors of the demultiplexer that distributes the signals output by the source driver 42 to each source line are OS transistors, and this is provided on the layer 30 as a demultiplexer 42DEM. With this configuration, the number of wires from the drive circuit 40 on the layer 20 to the display unit 60 on the layer 30 can be further reduced.

[0144] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0145] (Embodiment 2) In this embodiment, a cross-sectional structure example of a display device 10 according to one embodiment of the present invention will be described.

[0146] 28 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 has a substrate 701 and a substrate 705, and the substrates 701 and 705 are bonded together with a sealant 712.

[0147] A single crystal semiconductor substrate such as a single crystal silicon substrate can be used as the substrate 701. Note that the substrate 701 may be a semiconductor substrate other than a single crystal semiconductor substrate.

[0148] The transistor 441 and the transistor 601 are provided over a substrate 701. The transistor 441 and the transistor 601 can be the transistors provided in the layer 20 described in Embodiment 1.

[0149] The transistor 441 includes a conductor 443 functioning as a gate electrode, an insulator 445 functioning as a gate insulator, and a part of the substrate 701, and includes a semiconductor region 447 including a channel formation region, a low-resistance region 449a functioning as one of a source region and a drain region, and a low-resistance region 449b functioning as the other of the source region and the drain region. The transistor 441 may be either a p-channel type or an n-channel type.

[0150] The transistor 441 is electrically isolated from other transistors by an element isolation layer 403. Fig. 28 shows a case where the transistor 441 and the transistor 601 are electrically isolated by the element isolation layer 403. The element isolation layer 403 can be formed by a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.

[0151] 28 has a convex semiconductor region 447. A conductor 443 is provided to cover the side surface and the top surface of the semiconductor region 447 with an insulator 445 interposed therebetween. Note that the conductor 443 covering the side surface of the semiconductor region 447 is not shown in FIG. A material that adjusts the work function can be used for the conductor 443.

[0152] A transistor having a convex semiconductor region, such as the transistor 441, can be called a fin transistor because it utilizes the convex portion of a semiconductor substrate. Note that an insulator that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Also, although FIG. 28 shows a configuration in which the convex portion is formed by processing a part of the substrate 701, a semiconductor having a convex portion may be formed by processing an SOI substrate.

[0153] 28 is just an example, and is not limited to this configuration, and may be an appropriate configuration depending on the circuit configuration, the operation method of the circuit, etc. For example, the transistor 441 may be a planar transistor.

[0154] The transistor 601 can have a structure similar to that of the transistor 441 .

[0155] In addition to the element isolation layer 403, the transistor 441, and the transistor 601, an insulator 405, an insulator 407, an insulator 409, and an insulator 411 are provided over the substrate 701. A conductor 451 is embedded in the insulator 405, the insulator 407, the insulator 409, and the insulator 411. Here, the height of the top surface of the conductor 451 and the height of the top surface of the insulator 411 can be made approximately the same.

[0156] An insulator 421 and an insulator 214 are provided on the conductor 451 and the insulator 411. A conductor 453 is embedded in the insulator 421 and the insulator 214. Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 can be made approximately the same.

[0157] An insulator 216 is provided on the conductor 453 and the insulator 214. A conductor 455 is embedded in the insulator 216. Here, the height of the top surface of the conductor 455 and the height of the top surface of the insulator 216 can be made approximately the same.

[0158] Insulators 222, 224, 254, 280, 274, and 281 are provided on conductor 455 and insulator 216. Conductor 305 is embedded in insulator 222, insulator 224, insulator 254, insulator 280, insulator 274, and insulator 281. Here, the height of the top surface of conductor 305 and the height of the top surface of insulator 281 can be made approximately the same.

[0159] An insulator 361 is provided on the conductor 305 and on the insulator 281. The conductor 317 and the conductor 337 are embedded in the insulator 361. Here, the height of the upper surface of the conductor 337 and the height of the upper surface of the insulator 361 can be made approximately the same.

[0160] An insulator 363 is provided on the conductor 337 and on the insulator 361. The conductors 347, 353, 355, and 357 are embedded in the insulator 363. Here, the height of the top surfaces of the conductors 353, 355, and 357 can be made approximately the same as the height of the top surface of the insulator 363.

[0161] Connection electrodes 760 are provided on the conductors 353, 355, 357, and insulator 363. An anisotropic conductor 780 is provided so as to be electrically connected to the connection electrodes 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 10 from outside the display device 10 via the FPC 716.

[0162] 28 , the low-resistance region 449b serving as the other of the source and drain regions of the transistor 441 is electrically connected to the FPC 716 through the conductor 451, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780. Here, although FIG. 28 shows three conductors, the conductor 353, the conductor 355, and the conductor 357, as conductors each having a function of electrically connecting the connection electrode 760 and the conductor 347, one embodiment of the present invention is not limited thereto. The number of conductors each having a function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, or four or more. By providing a plurality of conductors each having a function of electrically connecting the connection electrode 760 and the conductor 347, contact resistance can be reduced.

[0163] A transistor 750 is provided over the insulator 214. The transistor 750 can be the transistor provided in the layer 30 described in Embodiment 1. For example, the transistor 750 can be a transistor provided in the pixel circuit 62. An OS transistor can be suitably used as the transistor 750. An OS transistor has an extremely low off-state current. Therefore, the retention time of image data and the like can be extended, thereby reducing the frequency of refresh operations. Therefore, the power consumption of the display device 10 can be reduced.

[0164] The transistor 750 can be provided in the backup circuit 82. An OS transistor can be preferably used as the transistor 750. An OS transistor has an extremely low off-state current. Therefore, data stored in the flip-flop can be retained even during a period when the shared power supply voltage is stopped. This allows the CPU to operate normally (intermittently stop the power supply voltage). This reduces the power consumption of the display device 10.

[0165] Conductor 301a and conductor 301b are embedded in insulator 254, insulator 280, insulator 274, and insulator 281. Conductor 301a is electrically connected to one of the source and drain of transistor 750, and conductor 301b is electrically connected to the other of the source and drain of transistor 750. Here, the height of the top surfaces of conductor 301a and conductor 301b and the height of the top surface of insulator 281 can be made approximately the same.

[0166] The conductor 311, the conductor 313, the conductor 331, the capacitor 790, the conductor 333, and the conductor 335 are embedded in the insulator 361. The conductor 311 and the conductor 313 are electrically connected to the transistor 750 and function as wirings. The conductor 333 and the conductor 335 are electrically connected to the capacitor 790. Here, the height of the top surfaces of the conductor 331, the conductor 333, and the conductor 335 can be made approximately the same as the height of the top surface of the insulator 361.

[0167] Conductor 341, conductor 343, and conductor 351 are embedded in insulator 363. Here, the height of the top surface of conductor 351 and the height of the top surface of insulator 363 can be made approximately the same.

[0168] The insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 363 function as interlayer films and may also function as planarizing films that cover uneven shapes below them. For example, the top surface of the insulator 363 may be planarized by planarization treatment using chemical mechanical polishing (CMP) or the like to improve flatness.

[0169] 28, the capacitor 790 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. That is, the capacitor 790 has a layered structure in which the insulator 323, which functions as a dielectric, is sandwiched between a pair of electrodes. Note that while FIG. 28 shows an example in which the capacitor 790 is provided on the insulator 281, the capacitor 790 may also be provided on an insulator different from the insulator 281.

[0170] FIG. 28 shows an example in which conductors 301a, 301b, and 305 are formed in the same layer. It also shows an example in which conductors 311, 313, 317, and the lower electrode 321 are formed in the same layer. It also shows an example in which conductors 331, 333, 335, and 337 are formed in the same layer. It also shows an example in which conductors 341, 343, and 347 are formed in the same layer. It also shows an example in which conductors 351, 353, 355, and 357 are formed in the same layer. Forming multiple conductors in the same layer can simplify the manufacturing process of the display device 10, thereby reducing the manufacturing cost of the display device 10. These conductors may be formed in different layers and may be made of different types of materials.

[0171] 28 includes a light-emitting element 70. The light-emitting element 70 includes a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0172] Materials that can be used for the organic compounds include fluorescent materials and phosphorescent materials, etc. Materials that can be used for the quantum dots include colloidal quantum dot materials, alloy quantum dot materials, core-shell quantum dot materials, and core quantum dot materials.

[0173] The conductor 772 is electrically connected to the other of the source and the drain of the transistor 750 through the conductor 351, the conductor 341, the conductor 331, the conductor 313, and the conductor 301b. The conductor 772 is formed over the insulator 363 and functions as a pixel electrode.

[0174] A material that transmits or reflects visible light can be used for the conductor 772. For example, an oxide material containing indium, zinc, tin, or the like can be used as the light-transmitting material. For example, a material containing aluminum, silver, or the like can be used as the reflective material.

[0175] Although not shown in FIG. 28, the display device 10 can be provided with optical members (optical substrates) such as a polarizing member, a phase difference member, an anti-reflection member, and the like.

[0176] A light-shielding layer 738 and an insulator 734 in contact with the light-shielding layer 738 are provided on the substrate 705 side. The light-shielding layer 738 has a function of blocking light emitted from an adjacent region. Alternatively, the light-shielding layer 738 has a function of blocking external light from reaching the transistor 750 and the like.

[0177] 28, an insulator 730 is provided over an insulator 363. The insulator 730 can be configured to cover part of a conductor 772. The light-emitting element 70 includes a light-transmitting conductor 788 and can be a top-emission light-emitting element. The light-emitting element 70 may have a bottom-emission structure in which light is emitted to the conductor 772 side, or a dual-emission structure in which light is emitted to both the conductor 772 and the conductor 788.

[0178] The light-shielding layer 738 is provided to have a region overlapping with the insulator 730. The light-shielding layer 738 is covered with the insulator 734. The space between the light-emitting element 70 and the insulator 734 is filled with the sealing layer 732.

[0179] Furthermore, structure 778 is disposed between insulator 730 and EL layer 786. Structure 778 is also disposed between insulator 730 and insulator 734.

[0180] 29 is a cross-sectional view of the Si transistors of the drive circuit 40 included in the layer 20, the OS transistors (regions 40 and 62) of the pixel circuit 62 included in the layer 30, the Si transistors of the function circuit 50 included in the layer 20, and the OS transistors (regions 50 and 82) of the backup circuit 82 included in the layer 30, all of which are described in the first embodiment. The description of the cross-sectional view shown in FIG. 29 is the same as that of the cross-sectional view shown in FIG. 28.

[0181] 29, a Si transistor 91 of the drive circuit 40 and a Si transistor 94 of the function circuit 50 can be provided on the layer 20. Also, as shown in FIG. 29, an OS transistor 92 and a capacitor 93 of the pixel circuit 62, and an OS transistor 95 and a capacitor 96 of the backup circuit 82 can be provided on the layer 30. Furthermore, a light-emitting element 70 can be provided on the layer 30.

[0182] 30A is a diagram schematically illustrating how data is backed up in functional circuit 50 provided in layer 20 in the exemplary configuration of display device 10 described in Embodiment 1. Fig. 30A illustrates an exemplary configuration in which backup circuit 82 is provided in each pixel 61 in display unit 60 provided in layer 30.

[0183] 30A is arranged uniformly in the display unit 60, the flip-flops 80 for transmitting and receiving backup data BD are preferably arranged close to the backup circuits 82. In a configuration in which the backup circuits 82 can be arranged uniformly in the display unit 60, the flip-flops 80 can be arranged anywhere in the layer 20 to transmit and receive backup data to and from the backup circuit 82 located immediately above.

[0184] For example, the backup circuit 82M in FIG. 30A can be configured to transmit and receive backup data to and from a circuit (e.g., a flip-flop 80) included in the functional circuit 50 directly below, while the backup circuit 82F in FIG. 30A can be configured not to transmit and receive backup data to and from a circuit included in the functional circuit 50 directly below.

[0185] Fig. 30B shows a cross-sectional view corresponding to the configuration described in Fig. 30A. For example, between the circuitry of functional circuit 50 and backup circuit 82M that transmits and receives backup data, wiring 97 for electrical connection between layer 20 and layer 30 can be provided, thereby electrically connecting transistor 94M on layer 20 to transistor 95M and capacitor 96M on layer 30.

[0186] On the other hand, between the circuitry of the functional circuit 50 and the backup circuit 82F that transmits and receives backup data, no wiring 97 for electrically connecting between the layer 20 and the layer 30 is provided. With this configuration, the transistor 94M in the layer 20 is not electrically connected to the transistor 95M and the capacitor 96M in the layer 30. The backup circuit 82F that is not electrically connected to the circuitry of the functional circuit 50 may have each terminal in an electrically floating state, or may be configured to be connected to a wiring that is given a fixed potential.

[0187] As described in Figures 30A and 30B, by configuring the electrical connection between the circuitry of the functional circuit 50 in layer 20 and the backup circuit 82 in layer 30 to be selectable, even if the placement of the functional circuit 50 that processes data is changed within layer 20, the connection with the backup circuit that backs up data can be ensured simply by changing the layout of the wiring layer.

[0188] FIG. 31 shows a modified example of the display device 10 shown in FIG. 28. The display device 10 shown in FIG. 31 differs from the display device 10 shown in FIG. 28 in that a colored layer 736 is provided. The colored layer 736 is provided so as to have an area overlapping with the light-emitting element 70. By providing the colored layer 736, the color purity of the light extracted from the light-emitting element 70 can be improved. This allows the display device 10 to display a high-quality image. Furthermore, since all of the light-emitting elements 70 of the display device 10 can be light-emitting elements that emit white light, it is not necessary to form the EL layer 786 by different colors, and the display device 10 can have high definition.

[0189] The light emitting element 70 can have a micro-optical resonator (microcavity) structure. This allows light of a predetermined color (e.g., RGB) to be extracted without providing a colored layer, and the display device 10 can perform color display. By configuring the display device 10 without providing a colored layer, it is possible to suppress light absorption by the colored layer. This allows the display device 10 to display high-brightness images and reduce the power consumption of the display device 10. Note that even when the EL layer 786 is formed in an island shape for each pixel or in a striped shape for each pixel column, that is, formed by coloring, it is also possible to configure the display device 10 without providing a colored layer. Note that the luminance of the display device 10 can be, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 More than 10000cd / m 2 or less, more preferably 2000 cd / m 2 More than 5000cd / m 2 It can be as follows:

[0190] 28 and 31 show a structure in which the transistors 441 and 601 are provided so that channel formation regions are formed inside the substrate 701 and the OS transistors are stacked over the transistors 441 and 601, but one embodiment of the present invention is not limited to this. A modification of FIG. 31 is shown in FIG. 32. The display device 10 shown in FIG. 32 is mainly different from the display device 10 shown in FIG. 31 in that OS transistors 602 and 603 are provided instead of the transistors 441 and 601. Furthermore, an OS transistor can be used as the transistor 750. That is, the display device 10 shown in FIG. 32 has a stack of OS transistors.

[0191] An insulator 613 and an insulator 614 are provided over a substrate 701, and a transistor 602 and a transistor 603 are provided over the insulator 614. Note that a transistor or the like may be provided between the substrate 701 and the insulator 613. For example, a transistor having a structure similar to that of the transistor 441 and the transistor 601 shown in FIG. 31 may be provided between the substrate 701 and the insulator 613.

[0192] The transistor 602 and the transistor 603 can be the transistors provided in the layer 20 described in Embodiment 1.

[0193] The transistors 602 and 603 can have a structure similar to that of the transistor 750. Note that the transistors 602 and 603 may be OS transistors with a structure different from that of the transistor 750.

[0194] In addition to the transistor 602 and the transistor 603, insulators 616, 622, 624, 654, 680, 674, and 681 are provided over the insulator 614. The conductor 461 is embedded in the insulator 654, the insulator 680, the insulator 674, and the insulator 681. Here, the height of the top surface of the conductor 461 can be made approximately the same as the height of the top surface of the insulator 681.

[0195] An insulator 501 is provided on the conductor 461 and the insulator 681. The conductor 463 is embedded in the insulator 501. Here, the height of the top surface of the conductor 463 and the height of the top surface of the insulator 501 can be made approximately the same.

[0196] An insulator 421 and an insulator 214 are provided on the conductor 463 and the insulator 501. A conductor 453 is embedded in the insulator 421 and the insulator 214. Here, the height of the top surface of the conductor 453 and the height of the top surface of the insulator 214 can be made approximately the same.

[0197] As shown in Figure 32, one of the source and drain of transistor 602 is electrically connected to FPC 716 via conductor 461, conductor 463, conductor 453, conductor 455, conductor 305, conductor 317, conductor 337, conductor 347, conductor 353, conductor 355, conductor 357, connection electrode 760, and anisotropic conductor 780.

[0198] The insulators 613, 614, 680, 674, 681, and 501 function as interlayer films and may also function as planarizing films that cover the uneven shapes below them.

[0199] 32, the display device 10 can have a narrower frame and be smaller in size, and all of the transistors included in the display device 10 can be OS transistors. This allows, for example, the transistors provided in the layer 20 and the transistors provided in the layer 30 described in Embodiment 1 to be manufactured using the same device. Therefore, the manufacturing cost of the display device 10 can be reduced, and the display device 10 can be manufactured at a low price.

[0200] 33 is a cross-sectional view illustrating a configuration example of the display device 10. The display device 10 differs from the display device 10 illustrated in FIG. 31 mainly in that a layer including a transistor 800 is provided between a layer including a transistor 750 and a layer including a transistor 601 and a transistor 441.

[0201] 33, the layer 20 described in Embodiment 1 can be formed from a layer including the transistors 601 and 441 and a layer including the transistor 800. The transistor 750 can be the transistor provided in the layer 30 described in Embodiment 1.

[0202] An insulator 821 and an insulator 814 are provided on the conductor 451 and the insulator 411. A conductor 853 is embedded in the insulator 821 and the insulator 814. Here, the height of the top surface of the conductor 853 and the height of the top surface of the insulator 814 can be made approximately the same.

[0203] An insulator 816 is provided on the conductor 853 and the insulator 814. A conductor 855 is embedded in the insulator 816. Here, the height of the top surface of the conductor 855 and the height of the top surface of the insulator 816 can be made approximately the same.

[0204] Insulators 822, 824, 854, 880, 874, and 881 are provided on the conductor 855 and the insulator 816. The conductor 805 is embedded in the insulators 822, 824, 854, 880, 874, and 881. Here, the height of the top surface of the conductor 805 and the height of the top surface of the insulator 881 can be made approximately the same.

[0205] An insulator 421 and an insulator 214 are provided over the conductor 817 and the insulator 881 .

[0206] As shown in Figure 33, the low resistance region 449b, which functions as the other of the source region or drain region of the transistor 441, is electrically connected to the FPC 716 via conductor 451, conductor 853, conductor 855, conductor 805, conductor 817, conductor 453, conductor 455, conductor 305, conductor 317, conductor 337, conductor 347, conductor 353, conductor 355, conductor 357, connection electrode 760, and anisotropic conductor 780.

[0207] A transistor 800 is provided over the insulator 814. The transistor 800 can be the transistor provided in the layer 20 described in Embodiment 1. The transistor 800 is preferably an OS transistor. For example, the transistor 800 can be a transistor provided in the backup circuit 82.

[0208] Conductors 801a and 801b are embedded in the insulators 854, 880, 874, and 881. The conductor 801a is electrically connected to one of the source and the drain of the transistor 800, and the conductor 801b is electrically connected to the other of the source and the drain of the transistor 800. Here, the height of the top surfaces of the conductors 801a and 801b can be made approximately the same as the height of the top surface of the insulator 881.

[0209] The transistor 750 can be the transistor provided in the layer 30 described in Embodiment 1. For example, the transistor 750 can be a transistor provided in the pixel circuit 62. The transistor 750 is preferably an OS transistor.

[0210] Insulator 405, insulator 407, insulator 409, insulator 411, insulator 821, insulator 814, insulator 880, insulator 874, insulator 881, insulator 421, insulator 214, insulator 280, insulator 274, insulator 281, insulator 361, and insulator 363 function as interlayer films and may also function as planarizing films that cover the uneven shapes below each other.

[0211] 33 shows an example in which a conductor 801a, a conductor 801b, and a conductor 805 are formed in the same layer. Also shown is an example in which a conductor 811, a conductor 813, and a conductor 817 are formed in the same layer.

[0212] 34 is a cross-sectional view showing a configuration example of the display device 10. It differs from the display device 10 shown in FIG. 31 mainly in that the layer including the transistor 750 is omitted in the illustration.

[0213] 34, a Si transistor in the layer 20 described in Embodiment 1, such as the transistor 601, can be used as a transistor corresponding to the OS transistor 750. The transistor 601 preferably has a longer channel length than the transistor 441 because it has a small off-state current.

[0214] 34 does not include a layer including the OS transistor 750 and layers including conductors functioning as wirings. A plurality of layers including conductors functioning as wirings may be provided between a layer including Si transistors such as the transistor 601 and the transistor 441 and a layer including the light-emitting element 70. This configuration increases the flexibility in the layout of the display unit and elements such as transistors below the display unit.

[0215] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0216] (Embodiment 3) In this embodiment, a transistor and a light-emitting element (light-emitting device) that can be used in a display device that is one embodiment of the present invention will be described.

[0217] <Transistor configuration example> 35A, 35B, and 35C are a top view and a cross-sectional view of a transistor 200A that can be used in a display device of one embodiment of the present invention and the periphery of the transistor 200A. The transistor 200A can be used in the display device of one embodiment of the present invention.

[0218] FIG. 35A is a top view of transistor 200A. FIGS. 35B and 35C are cross-sectional views of transistor 200A. FIG. 35B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 35A, and is also a cross-sectional view of transistor 200A in the channel length direction. FIG. 35C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 35A, and is also a cross-sectional view of transistor 200A in the channel width direction. Note that some elements are omitted from the top view of FIG. 35A for clarity.

[0219] As shown in FIG. 35, the transistor 200A has a metal oxide 230a arranged on a substrate (not shown), a metal oxide 230b arranged on the metal oxide 230a, a conductor 242a and a conductor 242b arranged spaced apart from each other on the metal oxide 230b, an insulator 280 arranged on the conductors 242a and 242b and having an opening formed between the conductors 242a and 242b, a conductor 260 arranged in the opening, an insulator 250 arranged among the metal oxide 230b, the conductors 242a, 242b, and the insulator 280, and the conductor 260, and a metal oxide 230c arranged among the metal oxide 230b, the conductors 242a, 242b, the insulator 280, and the insulator 250. 35B and 35C, it is preferable that the top surface of the conductor 260 substantially coincides with the top surfaces of the insulators 250, 254, metal oxide 230c, and 280. Note that, hereinafter, the metal oxides 230a, 230b, and 230c may be collectively referred to as metal oxides 230. Furthermore, the conductors 242a and 242b may be collectively referred to as conductors 242.

[0220] In the transistor 200A shown in Fig. 35, the side surfaces of the conductor 242a and the conductor 242b facing the conductor 260 have a substantially vertical shape. Note that the transistor 200A shown in Fig. 35 is not limited to this, and the angle formed between the side surface and the bottom surface of the conductor 242a and the conductor 242b may be 10° or more and 80° or less, preferably 30° or more and 60° or less. Furthermore, the opposing side surfaces of the conductor 242a and the conductor 242b may have multiple surfaces.

[0221] 35, it is preferable that an insulator 254 be disposed between the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductor 242a, the conductor 242b, and the metal oxide 230c and the insulator 280. Here, it is preferable that the insulator 254 be in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224, as shown in FIGS.

[0222] Although the transistor 200A has been described as having a three-layer structure of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c in and around a region where a channel is formed (hereinafter also referred to as a channel formation region), the present invention is not limited to this. For example, a two-layer structure of the metal oxide 230b and the metal oxide 230c or a stacked structure of four or more layers may be provided. Furthermore, the transistor 200A has been described as having a two-layer structure of the conductor 260, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may have a stacked structure of two or more layers.

[0223] For example, when metal oxide 230c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of metal oxide 230b, and the second metal oxide has a composition similar to that of metal oxide 230a.

[0224] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source and drain electrodes, respectively. As described above, the conductor 260 is formed so as to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260, 242a, and 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 200A, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 260 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 200A. This allows for a high-resolution display device. Furthermore, the display device can have a narrow frame.

[0225] As shown in FIG. 35, the conductor 260 preferably has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0226] The transistor 200A preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. A metal oxide 230a is preferably disposed on the insulator 224.

[0227] An insulator 274 functioning as an interlayer film and an insulator 281 are preferably disposed over the transistor 200A. Here, the insulator 274 is preferably disposed in contact with the top surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280.

[0228] It is preferable that the insulators 222, 254, and 274 have a function of suppressing the diffusion of at least one of hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that the insulators 222, 254, and 274 have lower hydrogen permeability than the insulators 224, 250, and 280. It is also preferable that the insulators 222 and 254 have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, it is preferable that the insulators 222 and 254 have lower oxygen permeability than the insulators 224, 250, and 280.

[0229] Here, the insulator 224, the metal oxide 230, and the insulator 250 are separated by the insulators 280 and 281, and the insulators 254 and 274. Therefore, impurities such as hydrogen contained in the insulators 280 and 281, or excess oxygen, can be prevented from being mixed into the insulators 224, the metal oxide 230a, the metal oxide 230b, and the insulator 250.

[0230] It is preferable that a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 200A and functioning as a plug is provided. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 functioning as a plug. That is, the insulator 241 is provided in contact with the inner wall of the opening of the insulators 254, 280, 274, and 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inward. Here, the height of the top surface of the conductor 240 and the height of the insulator 281 can be made approximately the same. Note that, in the transistor 200A, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown, but the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, it may be distinguished by assigning an ordinal number to the order of formation.

[0231] In the transistor 200A, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 230 (metal oxide 230a, metal oxide 230b, and metal oxide 230c) including the channel formation region. For example, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more, is preferably used for the channel formation region of the metal oxide 230.

[0232] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition to these, it is preferable that it contains element M. As element M, one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and cobalt (Co) can be used. In particular, element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), and tin (Sn). Furthermore, it is more preferable that element M contains either or both of Ga and Sn.

[0233] 35B, the film thickness of the metal oxide 230b in the region that does not overlap with the conductor 242 may be thinner than the film thickness of the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is formed on the upper surface of the metal oxide 230b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent a channel from being formed in that region.

[0234] According to one embodiment of the present invention, a display device having high definition and a small transistor can be provided. Alternatively, a display device having high luminance and a transistor with high on-state current can be provided. Alternatively, a display device having high-speed operation and a transistor with stable electrical characteristics can be provided. Alternatively, a display device having low power consumption and a transistor with low off-state current can be provided.

[0235] The detailed structure of the transistor 200A that can be used in the display device of one embodiment of the present invention will be described.

[0236] The conductor 205 is disposed so as to have an overlapping region with the metal oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216.

[0237] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 216. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0238] The conductors 205a and 205c are preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0239] By using a conductive material that can reduce hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the metal oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0240] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0241] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed independently of the potential applied to the conductor 260, thereby controlling the V th In particular, applying a negative potential to conductor 205 can control the V th It is possible to make the off-state current smaller by making the potential greater than 0 V. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.

[0242] The conductor 205 is preferably provided to be larger than the channel formation region of the metal oxide 230. In particular, as shown in Fig. 35C, the conductor 205 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 230. In other words, outside the side surface of the metal oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator.

[0243] With the above structure, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260 that functions as a first gate electrode and the electric field of the conductor 205 that functions as a second gate electrode.

[0244] 35C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor that functions as wiring may be provided below the conductor 205.

[0245] The insulator 214 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200A from the substrate side. Therefore, the insulator 214 is preferably made of an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., the impurities are less likely to permeate through the material). Alternatively, the insulator 214 is preferably made of an insulating material that has a function of preventing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through the material).

[0246] For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 214 to the transistor 200A side. Alternatively, it can prevent oxygen contained in the insulator 224, etc. from diffusing from the insulator 214 to the substrate side.

[0247] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 216, 280, and 281.

[0248] The insulators 222 and 224 function as gate insulators.

[0249] Here, the insulator 224 in contact with the metal oxide 230 preferably releases oxygen upon heating. In this specification, oxygen released upon heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like, as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced, and the reliability of the transistor 200A can be improved.

[0250] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0251] 35C, the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 230b may be thinner than the thickness of the other region. It is preferable that the thickness of the region of insulator 224 that does not overlap with insulator 254 and metal oxide 230b is a thickness that allows sufficient diffusion of the oxygen.

[0252] Similar to the insulator 214, etc., the insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200A from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, the insulator 250, etc. with the insulators 222, 254, and 274, it is possible to prevent impurities such as water or hydrogen from entering the transistor 200A from the outside.

[0253] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. The insulator 222 preferably has a function of suppressing the diffusion of oxygen or impurities, which can reduce the diffusion of oxygen contained in the metal oxide 230 toward the substrate side. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the metal oxide 230.

[0254] The insulator 222 may be an insulator containing an oxide of one or both of insulating materials, aluminum and hafnium. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing an oxide of one or both of aluminum and hafnium. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the metal oxide 230 or the intrusion of impurities such as hydrogen into the metal oxide 230 from the periphery of the transistor 200A.

[0255] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0256] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning of the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0257] The insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to the stacked structure made of the same material, and may be a stacked structure made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

[0258] The metal oxide 230 includes a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. By providing the metal oxide 230a below the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b. Furthermore, by providing the metal oxide 230c on the metal oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the metal oxide 230c to the metal oxide 230b.

[0259] The metal oxide 230 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. For example, when the metal oxide 230 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 230a to the number of atoms of all elements constituting the metal oxide 230a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. Furthermore, the atomic ratio of the element M contained in the metal oxide 230a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 230b to In. Here, the metal oxide 230c can be any metal oxide that can be used for the metal oxide 230a or the metal oxide 230b.

[0260] The energy of the conduction band minimum of the metal oxide 230a and the metal oxide 230c is preferably higher than the energy of the conduction band minimum of the metal oxide 230b. In other words, the electron affinity of the metal oxide 230a and the metal oxide 230c is preferably lower than the electron affinity of the metal oxide 230b. In this case, the metal oxide 230c is preferably a metal oxide that can be used for the metal oxide 230a. Specifically, the ratio of the number of atoms of the element M contained in the metal oxide 230c to the number of atoms of all elements constituting the metal oxide 230c is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 230b to the number of atoms of all elements constituting the metal oxide 230b. Furthermore, the atomic ratio of the element M contained in the metal oxide 230c to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 230b to In.

[0261] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c. In other words, the energy level of the conduction band minimum at the junction between the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 230a and the metal oxide 230b and the interface between the metal oxide 230b and the metal oxide 230c.

[0262] Specifically, the metal oxide 230a and the metal oxide 230b, and the metal oxide 230b and the metal oxide 230c, may have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low density of defect states. For example, when the metal oxide 230b is an In-Ga-Zn oxide, the metal oxide 230a and the metal oxide 230c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like. The metal oxide 230c may also have a stacked structure. For example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide, may be used. In other words, the metal oxide 230c may have a stacked structure of an In-Ga-Zn oxide and an oxide that does not contain In.

[0263] Specifically, the metal oxide 230a may have an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The metal oxide 230b may have an atomic ratio of In:Ga:Zn=4:2:3 or 3:1:2. The metal oxide 230c may have an atomic ratio of In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the metal oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0264] In this case, the main carrier path is the metal oxide 230b. By configuring the metal oxide 230a and the metal oxide 230c as described above, the defect state density at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200A to achieve a high on-state current and high frequency characteristics. Note that, when the metal oxide 230c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the metal oxide 230b and the metal oxide 230c, it is expected that the diffusion of constituent elements of the metal oxide 230c toward the insulator 250 can be suppressed. More specifically, by configuring the metal oxide 230c as a stacked structure and positioning an oxide that does not contain In above the stacked structure, it is possible to suppress In diffusion toward the insulator 250. Because the insulator 250 functions as a gate insulator, the diffusion of In can cause poor transistor characteristics. Therefore, by forming the metal oxide 230c into a laminated structure, it is possible to provide a highly reliable display device.

[0265] Conductors 242 (conductors 242a and 242b) functioning as a source electrode and a drain electrode are provided on the metal oxide 230b. Conductor 242 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when they absorb oxygen.

[0266] By providing the conductor 242 so as to be in contact with the metal oxide 230, the oxygen concentration may decrease in the vicinity of the conductor 242 of the metal oxide 230. Furthermore, a metal compound layer containing the metal contained in the conductor 242 and components of the metal oxide 230 may be formed in the vicinity of the conductor 242 of the metal oxide 230. In such a case, the carrier density increases in the region of the metal oxide 230 in the vicinity of the conductor 242, and this region becomes a low-resistance region.

[0267] Here, the region between the conductor 242a and the conductor 242b is formed to overlap the opening of the insulator 280. This allows the conductor 260 to be arranged in a self-aligned manner between the conductor 242a and the conductor 242b.

[0268] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the metal oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0269] The insulator 250 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0270] A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. This makes it possible to suppress oxidation of the conductor 260 due to oxygen in the insulator 250.

[0271] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By forming the gate insulator into a stacked structure of the insulator 250 and the metal oxide, it is possible to achieve a stacked structure that is thermally stable and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0272] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0273] Although the conductor 260 is shown as having a two-layer structure in FIG. 35, it may have a single-layer structure or a laminated structure of three or more layers.

[0274] The conductor 260a is preferably made of a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0275] The conductor 260a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0276] The conductor 260b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Furthermore, the conductor 260b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0277] 35A and 35C, in a region of the metal oxide 230b that does not overlap with the conductor 242, in other words, in the channel formation region of the metal oxide 230, the conductor 260 is arranged to cover the side surface of the metal oxide 230. This makes it easier for the electric field of the conductor 260, which functions as the first gate electrode, to act on the side surface of the metal oxide 230. This increases the on-current of the transistor 200A and improves the frequency characteristics.

[0278] Like the insulator 214, the insulator 254 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200A from the insulator 280 side. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 35B and 35C , the insulator 254 preferably contacts the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and the metal oxide 230b, and the top surface of the insulator 224. This configuration prevents hydrogen contained in the insulator 280 from entering the metal oxide 230 from the top or side surfaces of the conductor 242a, the conductor 242b, the metal oxide 230a, the metal oxide 230b, and the insulator 224.

[0279] Furthermore, it is preferable that the insulator 254 has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0280] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 by sputtering in an oxygen-containing atmosphere, oxygen can be added to the insulator 224 near the region where the insulator 254 is in contact with the insulator 254. This allows oxygen to be supplied from this region to the metal oxide 230 through the insulator 224. The insulator 254 has a function of suppressing upward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 to the insulator 280. The insulator 222 has a function of suppressing downward oxygen diffusion, thereby preventing oxygen from diffusing from the metal oxide 230 toward the substrate. In this way, oxygen is supplied to the channel formation region of the metal oxide 230. This reduces oxygen vacancies in the metal oxide 230 and suppresses the transistor from becoming normally on.

[0281] For example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as the insulator 254. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

[0282] The insulator 224, the insulator 250, and the metal oxide 230 are covered with the insulator 254, which has a barrier property against hydrogen, and the insulator 280 is separated from the insulator 224, the metal oxide 230, and the insulator 250 by the insulator 254. This makes it possible to prevent impurities such as hydrogen from penetrating from the outside of the transistor 200A, thereby providing the transistor 200A with good electrical characteristics and reliability.

[0283] The insulator 280 is provided over the insulator 224, the metal oxide 230, and the conductor 242 with the insulator 254 interposed therebetween. For example, the insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0284] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 280. The top surface of the insulator 280 may be flattened.

[0285] Similar to the insulator 214, the insulator 274 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. may be used.

[0286] An insulator 281 functioning as an interlayer film is preferably provided over the insulator 274. Like the insulator 224 and the like, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen.

[0287] The conductor 240a and the conductor 240b are arranged in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductor 240a and the conductor 240b are arranged opposite each other with the conductor 260 interposed therebetween. The height of the upper surfaces of the conductor 240a and the conductor 240b may be flush with the upper surface of the insulator 281.

[0288] Note that insulator 241a is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240a is formed in contact with the side surface of insulator 241a. Conductor 242a is located on at least a portion of the bottom of the openings, and conductor 240a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the inner walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240b is formed in contact with the side surface of insulator 241b. Conductor 242b is located on at least a portion of the bottom of the openings, and conductor 240b is in contact with conductor 242b.

[0289] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0290] When the conductor 240 has a layered structure, it is preferable to use the above-mentioned conductors that have the function of suppressing the diffusion of impurities such as water or hydrogen for the conductors in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a layered structure. The use of such a conductive material can suppress the absorption of oxygen added to the insulator 280 by the conductors 240a and 240b. Furthermore, it can suppress the intrusion of impurities such as water or hydrogen from layers above the insulator 281 into the metal oxide 230 through the conductors 240a and 240b.

[0291] The insulators 241a and 241b may be, for example, insulators that can be used for the insulator 254. The insulators 241a and 241b are provided in contact with the insulator 254, and therefore can prevent impurities such as water or hydrogen from the insulator 280 from being mixed into the metal oxide 230 through the conductors 240a and 240b. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0292] Although not shown, a conductor functioning as wiring may be disposed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. The conductor functioning as wiring is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0293] <Transistor constituent materials> The constituent materials that can be used for the transistor will be described.

[0294] [substrate] The substrate on which the transistor 200A is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having metal nitrides and substrates having metal oxides. Other examples include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. These substrates may also be used with elements provided thereon. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0295] [Insulator] Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0296] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0297] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0298] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0299] The electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding it with an insulator (such as the insulator 214, the insulator 222, the insulator 254, or the insulator 274) that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, a single-layer or stacked insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0300] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be compensated for.

[0301] [conductor] As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0302] A plurality of conductors formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0303] When a metal oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure of a combination of a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0304] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0305] <Configuration example of light-emitting element 70> 36A, the EL layer 786 of the light-emitting element 70 can be composed of multiple layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer containing a substance with high electron injection properties (electron injection layer) and a layer containing a substance with high electron transport properties (electron transport layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with high hole injection properties (hole injection layer) and a layer containing a substance with high hole transport properties (hole transport layer).

[0306] A structure having the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 36A is referred to as a single structure in this specification.

[0307] As shown in FIG. 36B, a configuration in which a plurality of light-emitting layers (light-emitting layers 4411, 4412, 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0308] Furthermore, as shown in Figure 36C, a configuration in which multiple light-emitting units (EL layers 786a, 786b) are connected in series via an intermediate layer (charge generating layer) 4440 is referred to as a tandem structure in this specification. Note that, although the configuration shown in Figure 36C is referred to as a tandem structure in this specification, the present invention is not limited to this, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting element capable of emitting light with high brightness can be obtained.

[0309] The emitted light color of the light-emitting element 70 can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 786. Furthermore, the color purity can be further improved by providing the light-emitting element 70 with a microcavity structure.

[0310] A light-emitting element that emits white light preferably has a structure in which two or more light-emitting substances are contained in the light-emitting layer. To obtain white light emission, light-emitting substances are selected such that the respective emissions of the two or more light-emitting substances are in a complementary color relationship.

[0311] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0312] <Method of forming the light emitting element 70> A method for forming the light emitting element 70 provided on the pixel circuit 62 will be described below.

[0313] FIG. 37A is a schematic top view of a light-emitting element 70 according to one embodiment of the present invention. The light-emitting element 70 includes a plurality of light-emitting elements 70R that emit red light, a plurality of light-emitting elements 70G that emit green light, and a plurality of light-emitting elements 70B that emit blue light. In FIG. 37A, the light-emitting elements are labeled with R, G, and B within their light-emitting regions to easily distinguish them from one another. The structure of the light-emitting element 70 shown in FIG. 37A may be referred to as a side-by-side (SBS) structure. The structure shown in FIG. 37A illustrates a structure having three colors, red (R), green (G), and blue (B), but is not limited thereto. For example, a structure having four or more colors may also be used.

[0314] The light-emitting elements 70R, 70G, and 70B are arranged in a matrix. Fig. 37A shows a so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement of the light-emitting elements is not limited to this, and arrangements such as a delta arrangement or a zigzag arrangement may also be used, or a pentile arrangement may also be used.

[0315] The light-emitting elements 70R, 70G, and 70B are preferably organic EL devices such as organic light-emitting diodes (OLEDs) or quantum-dot light-emitting diodes (QLEDs). Examples of light-emitting materials included in the EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (TADF) materials. The TADF material may be a material that is in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in efficiency in the high-brightness region of the light-emitting element.

[0316] FIG. 37B is a schematic cross-sectional view corresponding to the dashed dotted line A1-A2 in FIG. 37A.

[0317] 37B shows cross sections of the light-emitting element 70R, the light-emitting element 70G, and the light-emitting element 70B. The light-emitting element 70R, the light-emitting element 70G, and the light-emitting element 70B are each provided over a substrate 251, and include a conductor 772 that functions as a pixel electrode and a conductor 788 that functions as a common electrode.

[0318] The light-emitting element 70R has an EL layer 786R between a conductor 772 functioning as a pixel electrode and a conductor 788 functioning as a common electrode. The EL layer 786R contains a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The EL layer 786G of the light-emitting element 70G contains a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The EL layer 786B of the light-emitting element 70B contains a light-emitting organic compound that emits light having a peak in at least the blue wavelength range.

[0319] The EL layer 786R, the EL layer 786G, and the EL layer 786B may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0320] The conductor 772 functioning as a pixel electrode is provided for each light-emitting element. The conductor 788 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductor 772 functioning as a pixel electrode or the conductor 788 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductor 772 functioning as a pixel electrode transparent and the conductor 788 functioning as a common electrode reflective, a bottom-emission display device can be obtained. Conversely, by making the conductor 772 functioning as a pixel electrode reflective and the conductor 788 functioning as a common electrode transparent, a top-emission display device can be obtained. By making both the conductor 772 functioning as a pixel electrode and the conductor 788 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0321] An insulating layer 272 is provided to cover an edge of a conductor 772 that functions as a pixel electrode. The edge of the insulating layer 272 is preferably tapered.

[0322] The EL layer 786R, the EL layer 786G, and the EL layer 786B each have a region in contact with the top surface of the conductor 772 that functions as a pixel electrode, and a region in contact with the surface of the insulating layer 272. Ends of the EL layer 786R, the EL layer 786G, and the EL layer 786B are located on the insulating layer 272.

[0323] As shown in Figure 37B, a gap is provided between two EL layers between light-emitting elements of different colors. In this way, it is preferable that the EL layer 786R, the EL layer 786G, and the EL layer 786G are provided so as not to be in contact with each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This allows for increased contrast and a display device with high display quality to be realized.

[0324] The EL layer 786R, the EL layer 786G, and the EL layer 786G can be separately formed by vacuum deposition using a shadow mask such as a metal mask. Alternatively, they may be separately formed by photolithography. By using photolithography, a high-definition display device can be realized, which is difficult to achieve when using a metal mask.

[0325] In addition, a protective layer 271 is provided over the conductor 788 functioning as a common electrode to cover the light-emitting elements 70R, 70G, and 70B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0326] The protective layer 271 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used for the protective layer 271. Note that the protective layer 271 may be formed by an ALD method, a CVD method, or a sputtering method. Note that, although the protective layer 271 includes an inorganic insulating film, this is not limiting. For example, the protective layer 271 may have a stacked structure including an inorganic insulating film and an organic insulating film.

[0327] FIG. 37C shows a different example from the above.

[0328] 37C includes a light-emitting element 70W that emits white light. The light-emitting element 70W includes an EL layer 786W that emits white light between a pixel electrode and a conductor 788 that functions as a common electrode.

[0329] The EL layer 786W may be configured by stacking two or more light-emitting layers selected so that the emitted colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.

[0330] FIG. 37C shows three light-emitting elements 70W lined up. A colored layer 264R is provided on the top of the left light-emitting element 70W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 70W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 70W. This allows the display device to display color images.

[0331] Here, the EL layer 786W and the conductor 788 functioning as a common electrode are separated between two adjacent light-emitting elements 70W. This effectively prevents current from flowing through the EL layer 786W between the two adjacent light-emitting elements 70W, which would otherwise cause unintended light emission. In particular, when a stacked EL element in which a charge-generating layer is provided between two light-emitting layers is used as the EL layer 786W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using such a configuration, a display device that combines high resolution and high contrast can be realized.

[0332] The EL layer 786W and the conductor 788 functioning as a common electrode are preferably separated by photolithography, which allows the distance between light-emitting elements to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0333] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductor 772 functioning as a pixel electrode and the substrate 251 .

[0334] FIG. 38A shows an example different from the above. Specifically, FIG. 38A shows a configuration in which an insulating layer 272 is not provided between the light-emitting elements 70R, 70G, and 70B. This configuration allows for a display device with a high aperture ratio. Furthermore, a protective layer 271 covers the side surfaces of the light-emitting elements 70R, 70G, and 70B. This configuration prevents impurities (typically, water) from entering through the side surfaces of the light-emitting elements 70R, 70G, and 70B. In the configuration shown in FIG. 38A, the top surfaces of the conductor 772, the EL layer 786R, and the conductor 788 are generally aligned. This structure can be formed collectively using a resist mask or the like after the conductor 772, the EL layer 786R, and the conductor 788 are formed. This process can also be called self-aligned patterning because the EL layer 786R and the conductor 788 are processed using the conductor 788 as a mask. Although the light emitting element 70R has been described here, the light emitting element 70G and the light emitting element 70B can also be configured in a similar manner.

[0335] 38A shows a structure in which a protective layer 758 is further provided on the protective layer 271. For example, the protective layer 271 is formed using an apparatus (typically, an ALD apparatus) capable of depositing a film with high coverage, and the protective layer 758 is formed using an apparatus (typically, a sputtering apparatus) capable of depositing a film with lower coverage than the protective layer 271, whereby a region 759 can be provided between the protective layer 271 and the protective layer 758. In other words, the region 759 is located between the light-emitting element 70R and the light-emitting element 70G, and between the light-emitting element 70G and the light-emitting element 70B.

[0336] The region 759 contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). The region 759 may also contain, for example, a gas used when forming the protective layer 758. For example, when the protective layer 758 is formed by sputtering, the region 759 may contain one or more of the above Group 18 elements. When the region 759 contains a gas, the gas can be identified by gas chromatography or the like. When the protective layer 758 is formed by sputtering, the gas used during sputtering may also be contained in the protective layer 758. In this case, when the protective layer 758 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like, elements such as argon may be detected.

[0337] Furthermore, when the refractive index of region 759 is lower than the refractive index of protective layer 271, light emitted from light-emitting element 70R, light-emitting element 70G, or light-emitting element 70B is reflected at the interface between protective layer 271 and region 759. This makes it possible to prevent light emitted from light-emitting element 70R, light-emitting element 70G, or light-emitting element 70B from entering adjacent pixels. This makes it possible to prevent light of different colors from mixing, thereby improving the image quality of the display device.

[0338] 38A, the area between light-emitting element 70R and light-emitting element 70G or the area between light-emitting element 70G and light-emitting element 70B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of light-emitting element 70R and the side surface of light-emitting element 70G or the distance between the side surface of light-emitting element 70G and the side surface of light-emitting element 70B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0339] Furthermore, for example, when the region 759 contains air, it is possible to isolate the light emitting elements while suppressing color mixing or crosstalk of light from the light emitting elements.

[0340] Region 759 may also include an insulating layer containing an organic material. For example, region 759 may be filled with acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins. Region 759 may also be filled with a photosensitive resin. Photoresist may be used as the photosensitive resin. The photosensitive resin may be a positive-type material or a negative-type material.

[0341] The region 759 may also include an insulating layer containing an inorganic material. Examples of the inorganic material that can be used include inorganic insulating films such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. The inorganic insulating film may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film.

[0342] It is also preferable that the region 759 contains both the inorganic material and the organic material described above. For example, the region 759 may have a stacked structure of an aluminum oxide film and a photoresist on the aluminum oxide film.

[0343] FIG. 38B shows a different example. Specifically, the configuration shown in FIG. 38B differs from the configuration shown in FIG. 38A in the configuration of the substrate 251. The substrate 251 has a recess formed by removing a portion of its upper surface during processing of the light-emitting elements 70R, 70G, and 70B. A protective layer 271 is formed in the recess. In other words, the substrate 251 has a region where the lower surface of the protective layer 271 is located lower than the lower surface of the conductor 772 in a cross-sectional view. By providing this region, impurities (typically, water, etc.) that may enter the light-emitting elements 70R, 70G, and 70B from below can be suitably suppressed. The recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements 70R, 70G, and 70B are removed by wet etching or the like during processing. After removing the residue, the side surfaces of the light-emitting elements are covered with the protective layer 271, resulting in a highly reliable display device.

[0344] FIG. 38C shows a different example. Specifically, the configuration shown in FIG. 38C includes an insulating layer 776 and a microlens array 777 in addition to the configuration shown in FIG. 38B. The insulating layer 776 functions as an adhesive layer. When the refractive index of the insulating layer 776 is lower than that of the microlens array 777, the microlens array 777 can condense light emitted from the light-emitting elements 70R, 70G, and 70B. This improves the light extraction efficiency of the display device. This is particularly advantageous because it allows a bright image to be viewed when a user views the display surface of the display device from directly in front of the display surface. The insulating layer 776 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet-curable adhesive), a reactive-curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0345] In this specification, a device that uses a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as an MM (metal mask) structure. In addition, in this specification, a device that does not use a metal mask or an FMM may be referred to as an MML (metal maskless) structure.

[0346] The above is the description of the light emitting element.

[0347] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0348] (Fourth embodiment) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0349] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 39A, which is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0350] As shown in Figure 39A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0351] The structure within the bold frame in Figure 39A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "Amorphous" or "Crystal."

[0352] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 39B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 39B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 39B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 39B is 500 nm.

[0353] As shown in Figure 39B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 39B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0354] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 39C. Figure 39C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 39C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In addition, electron diffraction is performed using a probe diameter of 1 nm in nanobeam electron diffraction.

[0355] As shown in Figure 39C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0356] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from those shown in FIG. 39A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0357] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0358] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. Considering an atomic arrangement as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0359] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0360] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0361] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0362] For example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0363] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries can be identified even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction or the change in interatomic bond distance caused by metal atom substitution.

[0364] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0365] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, because the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0366] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0367] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0368] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0369] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0370] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0371] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0372] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0373] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0374] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0375] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0376] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0377] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0378] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0379] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0380] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore, the density of trap states may also be low.

[0381] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0382] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0383] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0384] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by SIMS) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0385] When an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0386] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3Do the following:

[0387] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0388] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0389] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0390] (Embodiment 5) In this embodiment, an integrated circuit with a display unit (hereinafter also referred to as a display IC) and an electronic device including a display device according to one embodiment of the present invention will be described.

[0391] 40A shows a perspective view of a display IC 100 including a display device 10 according to one embodiment of the present invention. The display IC 100 illustrates the display device 10 and a plurality of pins 101. In addition to the pins 101, the display IC may also include a heat sink for heat dissipation. The pins 101 may be FPCs.

[0392] The display IC 100 can be configured to emit light (indicated by an arrow in the drawing) from a display unit 60 included in the display device 10, allowing an image to be viewed.

[0393] 40B is a perspective view schematically illustrating the configuration of layer 20, layer 30, and light-emitting element 70 of display device 10. Layer 30, in which OS transistors are provided, includes pixel circuits 62R, 62G, and 62B as well as backup circuit 82 in the region of pixel 61, as described in the first embodiment and the like.

[0394] 40B, backup circuits 82 provided together with pixel circuits 62R, 62G, and 62B can be provided corresponding to the RGB sub-pixels. The backup circuits 82 can retain data from circuits provided in layer 20, such as the functional circuit 50 or the CPU 51, by using OS transistors. The memory circuits 82B provided in layer 30, in which the OS transistors are provided, can be uniformly arranged in layer 30. This makes it possible to easily electrically connect the backup circuits 82 to the functional circuit 50 or the CPU 51, unlike when the backup circuits 82 are locally arranged.

[0395] Next, an electronic device equipped with the display IC will be described.

[0396] FIG. 41A is a diagram showing the appearance of the head mounted display 8200.

[0397] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0398] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 is equipped with a wireless receiver or the like, and can display an image corresponding to received image data or the like on a display portion 8204. In addition, a camera provided in the main body 8203 captures the movement of the user's eyeball or eyelid, and calculates the coordinates of the user's line of sight based on the information, thereby allowing the user's line of sight to be used as an input means.

[0399] The wearing unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 may have a function of recognizing the user's line of sight by detecting a current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 8203 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204. The wearing unit 8201 may also detect the movement of the user's head, etc., and change the image displayed on the display unit 8204 in accordance with the movement.

[0400] The display IC of one embodiment of the present invention can be applied to the display portion 8204. This reduces the power consumption of the head-mounted display 8200, allowing the head-mounted display 8200 to be used continuously for a long period of time. Furthermore, reducing the power consumption of the head-mounted display 8200 allows the battery 8206 to be made smaller and lighter, thereby enabling the head-mounted display 8200 to be made smaller and lighter. This reduces the burden on a user of the head-mounted display 8200, making it possible for the user to feel less fatigue.

[0401] 41B, 41C, and 41D are diagrams showing the external appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305. A battery 8306 is built into the housing 8301, and power can be supplied from the battery 8306 to the display portion 8302 and the like.

[0402] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner. By arranging the display portion 8302 in a curved manner, a user can feel a high sense of presence. Note that although the configuration in which one display portion 8302 is provided has been illustrated in this embodiment, the present invention is not limited thereto, and for example, a configuration in which two display portions 8302 are provided may be used. In this case, if one display portion is arranged at one eye of the user, three-dimensional display using parallax or the like can be performed.

[0403] Note that the above-described display IC can be applied to the display unit 8302. This allows the power consumption of the head mounted display 8300 to be reduced, allowing the head mounted display 8300 to be used continuously for a long period of time. Furthermore, by reducing the power consumption of the head mounted display 8300, the battery 8306 can be made smaller and lighter, and therefore the head mounted display 8300 can be made smaller and lighter. This reduces the burden on the user of the head mounted display 8300, making it possible for the user to feel less fatigue.

[0404] Next, an example of an electronic device different from the electronic device shown in FIGS. 41A to 41D is shown in FIGS. 42A and 42B.

[0405] The electronic device shown in Figures 42A and 42B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), and a battery 9009.

[0406] The electronic device shown in FIGS. 42A and 42B has various functions. For example, it may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to connect to various computer networks using the wireless communication function, a function to send or receive various data using the wireless communication function, a function to read programs or data recorded on a recording medium and display them on a display unit, etc. Note that the functions that the electronic device shown in FIGS. 42A and 42B can have are not limited to these, and it may have various other functions. Also, although not shown in FIGS. 42A and 42B, the electronic device may be configured to have multiple display units. Furthermore, the electronic device may be equipped with a camera or the like to have functions such as taking still images, taking videos, saving the captured images to a recording medium (external or built-in to the camera), and displaying the captured images on a display unit.

[0407] The electronic device shown in FIGS. 42A and 42B will be described in detail below.

[0408] FIG. 42A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information viewing device, and the like. Specifically, it can be used as a smartphone. The mobile information terminal 9101 can display text or images on multiple surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display unit 9001. Information 9051, indicated by a dashed rectangle, can be displayed on the other surface of the display unit 9001. Examples of the information 9051 include a display notifying an incoming email, SNS (social networking service), or phone call, the title of the email or SNS, the name of the sender of the email or SNS, the date and time, the remaining battery level, and the strength of the antenna reception. Alternatively, the operation buttons 9050, etc., can be displayed in place of the information 9051.

[0409] The above-described display IC can be applied to the portable information terminal 9101. This reduces the power consumption of the portable information terminal 9101, allowing the portable information terminal 9101 to be used continuously for a long period of time. Furthermore, by reducing the power consumption of the portable information terminal 9101, the battery 9009 can be made smaller and lighter, thereby making it possible to reduce the size and weight of the portable information terminal 9101. This improves the portability of the portable information terminal 9101.

[0410] FIG. 42B is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can execute various applications such as mobile phone calls, e-mail, document browsing and creation, music playback, internet communication, and computer games. The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. FIG. 42B shows an example in which time 9251, operation buttons 9252 (also referred to as operation icons or simply icons), and content 9253 are displayed on the display unit 9001. The content 9253 can be, for example, a video.

[0411] The mobile information terminal 9200 can also perform short-distance wireless communication according to a communication standard. For example, hands-free conversation is also possible by mutual communication with a wireless headset. The mobile information terminal 9200 also has a connection terminal 9006, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Note that charging may also be performed by wireless power supply without using the connection terminal 9006.

[0412] The above-described display IC can be applied to the portable information terminal 9200. This reduces the power consumption of the portable information terminal 9200, allowing the portable information terminal 9200 to be used continuously for a long period of time. Furthermore, by reducing the power consumption of the portable information terminal 9200, the battery 9009 can be made smaller and lighter, thereby enabling the portable information terminal 9200 to be made smaller and lighter. This improves the portability of the portable information terminal 9200.

[0413] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0414] <Additional notes regarding the present specification etc.> The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0415] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0416] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0417] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0418] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0419] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0420] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0421] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0422] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0423] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0424] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0425] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0426] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0427] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0428] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, transmission of an electrical signal between A and B is possible. [Explanation of symbols]

[0429] 10: display device, 20: layer, 30: layer, 40: drive circuit, 50: function circuit, 60: display unit, 61: pixel, 62R, 62G, 62B: pixel circuit, 80: flip-flop, 82: backup circuit, BD: backup data

Claims

1. a pixel circuit, a drive circuit, and a function circuit; the drive circuit has a function of outputting a signal for displaying in the pixel circuit, the functional circuit includes a CPU having a CPU core with a scan flip-flop electrically connected to a backup circuit; A first layer and a second layer, the first layer includes the drive circuit and the CPU; the second layer includes the pixel circuit and the backup circuit; the first layer and the second layer are provided on different layers, the backup circuit has a function of retaining the data held in the scan flip-flops in a state where the supply of a power supply voltage is stopped when the CPU is not operating; The pixel circuit includes a transistor SW21, a transistor SW22, a transistor M21, and a capacitor C21. The gate electrode of the transistor M21 is electrically connected to one of the source electrode and the drain electrode of the transistor SW21, One of the source electrode or the drain electrode of the transistor M21 is electrically connected to the first electrode of the light-emitting element, The other of the source electrode and the drain electrode of the transistor M21 is electrically connected to a wiring ANO that applies a potential for causing a current to flow to the light emitting element. The other of the source electrode and the drain electrode of the transistor SW21 is electrically connected to a wiring SL that functions as a source line. The transistor SW21 is controlled to be in a conductive state or a non-conductive state based on the potential of the wiring GLA that functions as a gate line. One of the source electrode and the drain electrode of the transistor SW22 is electrically connected to the wiring V0. The other of the source electrode and the drain electrode of the transistor SW22 is electrically connected to one electrode of the light-emitting element, The transistor SW22 is controlled to be in a conductive state or a non-conductive state based on the potential of the wiring GLB that functions as a gate line. the wiring V0 has a function of applying a reference potential and a function of outputting a current flowing through the pixel circuit to the drive circuit or the functional circuit, the capacitor C21 has a first conductive film electrically connected to the gate electrode of the transistor M21 and a second conductive film electrically connected to the other of the source electrode and the drain electrode of the transistor SW22; a second electrode of the light-emitting element electrically connected to a wiring VCOM; The wiring VCOM has a function of applying a potential for supplying a current to the light-emitting element, The backup circuit includes a transistor M11, a transistor M12, a transistor M13, and a capacitor C11. The gate of the transistor M13 is electrically connected to the gate of the transistor M11. scan test data is input to one of the source and drain of the transistor M13, and input to the scan flip-flop from the other of the source and drain of the transistor M13; The other of the source and the drain of the transistor M13 is electrically connected to one of the source and the drain of the transistor M12, The other of the source and the drain of the transistor M12 is electrically connected to one electrode of the capacitor C11, The other of the source and the drain of the transistor M12 is electrically connected to one of the source and the drain of the transistor M11, The other of the source and the drain of the transistor M11 is electrically connected to the data output node of the scan flip-flop, The on / off of the transistors M11 and M13 is controlled by a signal BKH. The on / off of the transistor M12 is controlled by a signal RCH. The other electrode of the capacitor C11 is electrically connected to the wiring VCOM or the wiring ANO.

2. a pixel circuit, a drive circuit, and a function circuit; the drive circuit has a function of outputting an image signal for displaying in the pixel circuit, the functional circuit includes a CPU having a CPU core with a scan flip-flop electrically connected to a backup circuit; A first layer and a second layer, the first layer includes the drive circuit and the CPU; the second layer includes the pixel circuit and the backup circuit; the first layer and the second layer are provided on different layers, the CPU has a function of correcting the image signal in accordance with the amount of current flowing through the pixel circuit; the backup circuit has a function of retaining the data held in the scan flip-flops in a state where the supply of a power supply voltage is stopped when the CPU is not operating; The pixel circuit includes a transistor SW21, a transistor SW22, a transistor M21, and a capacitor C21. The gate electrode of the transistor M21 is electrically connected to one of the source electrode and the drain electrode of the transistor SW21, One of the source electrode or the drain electrode of the transistor M21 is electrically connected to the first electrode of the light-emitting element, The other of the source electrode and the drain electrode of the transistor M21 is electrically connected to a wiring ANO that applies a potential for causing a current to flow to the light emitting element. The other of the source electrode and the drain electrode of the transistor SW21 is electrically connected to a wiring SL that functions as a source line. The transistor SW21 is controlled to be in a conductive state or a non-conductive state based on the potential of the wiring GLA that functions as a gate line. One of the source electrode and the drain electrode of the transistor SW22 is electrically connected to the wiring V0. The other of the source electrode and the drain electrode of the transistor SW22 is electrically connected to one electrode of the light-emitting element, The transistor SW22 is controlled to be in a conductive state or a non-conductive state based on the potential of the wiring GLB that functions as a gate line. the wiring V0 has a function of applying a reference potential and a function of outputting a current flowing through the pixel circuit to the drive circuit or the functional circuit, the capacitor C21 has a first conductive film electrically connected to the gate electrode of the transistor M21 and a second conductive film electrically connected to the other of the source electrode and the drain electrode of the transistor SW22; a second electrode of the light-emitting element electrically connected to a wiring VCOM; The wiring VCOM has a function of applying a potential for supplying a current to the light-emitting element, The backup circuit includes a transistor M11, a transistor M12, a transistor M13, and a capacitor C11. The gate of the transistor M13 is electrically connected to the gate of the transistor M11. scan test data is input to one of the source and drain of the transistor M13, and input to the scan flip-flop from the other of the source and drain of the transistor M13; The other of the source and the drain of the transistor M13 is electrically connected to one of the source and the drain of the transistor M12, The other of the source and the drain of the transistor M12 is electrically connected to one electrode of the capacitor C11, The other of the source and the drain of the transistor M12 is electrically connected to one of the source and the drain of the transistor M11, The other of the source and the drain of the transistor M11 is electrically connected to the data output node of the scan flip-flop, The on / off of the transistors M11 and M13 is controlled by a signal BKH. The on / off of the transistor M12 is controlled by a signal RCH. The other electrode of the capacitor C11 is electrically connected to the wiring VCOM or the wiring ANO.

3. a pixel circuit, a drive circuit, and a function circuit; the drive circuit has a function of outputting an image signal for displaying in the pixel circuit, the functional circuit includes a CPU having a CPU core with a scan flip-flop electrically connected to a backup circuit; A first layer and a second layer, the first layer includes the drive circuit and the CPU; the second layer includes the pixel circuit and the backup circuit; the transistor provided in the first layer has silicon in a channel formation region; the transistor provided in the second layer has a metal oxide in a channel formation region; the CPU has a function of correcting the image signal in accordance with the amount of current flowing through the pixel circuit; the backup circuit has a function of retaining the data held in the scan flip-flops in a state where the supply of a power supply voltage is stopped when the CPU is not operating; The pixel circuit includes a transistor SW21, a transistor SW22, a transistor M21, and a capacitor C21. The gate electrode of the transistor M21 is electrically connected to one of the source electrode and the drain electrode of the transistor SW21, One of the source electrode or the drain electrode of the transistor M21 is electrically connected to the first electrode of the light-emitting element, The other of the source electrode and the drain electrode of the transistor M21 is electrically connected to a wiring ANO that applies a potential for causing a current to flow to the light emitting element. The other of the source electrode and the drain electrode of the transistor SW21 is electrically connected to a wiring SL that functions as a source line. The transistor SW21 is controlled to be in a conductive state or a non-conductive state based on the potential of the wiring GLA that functions as a gate line. One of the source electrode and the drain electrode of the transistor SW22 is electrically connected to the wiring V0. The other of the source electrode and the drain electrode of the transistor SW22 is electrically connected to one electrode of the light-emitting element, The transistor SW22 is controlled to be in a conductive state or a non-conductive state based on the potential of the wiring GLB that functions as a gate line. the wiring V0 has a function of applying a reference potential and a function of outputting a current flowing through the pixel circuit to the drive circuit or the functional circuit, the capacitor C21 has a first conductive film electrically connected to the gate electrode of the transistor M21 and a second conductive film electrically connected to the other of the source electrode and the drain electrode of the transistor SW22; a second electrode of the light-emitting element electrically connected to a wiring VCOM; The wiring VCOM has a function of applying a potential for supplying a current to the light-emitting element, The backup circuit includes a transistor M11, a transistor M12, a transistor M13, and a capacitor C11. The gate of the transistor M13 is electrically connected to the gate of the transistor M11. scan test data is input to one of the source and drain of the transistor M13, and input to the scan flip-flop from the other of the source and drain of the transistor M13; The other of the source and the drain of the transistor M13 is electrically connected to one of the source and the drain of the transistor M12, The other of the source and the drain of the transistor M12 is electrically connected to one electrode of the capacitor C11, The other of the source and the drain of the transistor M12 is electrically connected to one of the source and the drain of the transistor M11, The other of the source and the drain of the transistor M11 is electrically connected to the data output node of the scan flip-flop, The on / off of the transistors M11 and M13 is controlled by a signal BKH. The on / off of the transistor M12 is controlled by a signal RCH. The other electrode of the capacitor C11 is electrically connected to the wiring VCOM or the wiring ANO.

4. In claim 3, The metal oxide comprises In, an element M (M is Al, Ga, Y, or Sn), and Zn.

5. In any one of claims 1 to 4, the functional circuit includes an accelerator; The display device, wherein the accelerator is a circuit that performs a multiply-accumulate operation.

6. In any one of claims 1 to 5, the light-emitting element has an organic EL device, The display device, wherein the organic EL device is a light-emitting device processed by a photolithography method.

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